Serdes PHY multiplexing method, apparatus, device and storage medium

Abstract

The application discloses a Serdes PHY multiplexing method and device, equipment and storage medium, and relates to the technical field of integrated circuits, which comprises the following steps: counting the number of target controllers required in multiple different application scenarios respectively, obtaining a plurality of corresponding controller numbers; determining the maximum value from the plurality of controller numbers, and determining a plurality of target Serdes PHYs with the same number of the maximum value; and setting a plurality of different working modes respectively, so as to match the target controllers and the plurality of target Serdes PHYs in the different application scenarios under the plurality of different working modes. The application sets a plurality of different working modes, and matches different controllers and Serdes PHYs under different modes, so that the Serdes PHY is flexibly multiplexed, the number of Serdes PHYs is reduced, the area of the chip is greatly reduced, the system integration is improved, and the cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a Serdes PHY multiplexing method, device, equipment and storage medium. BACKGROUND

[0002] In the current test scheme, a high-speed serial interface (HSSI) is composed of one controller corresponding to one Serdes PHY (Serializer / Deserializer Physical Layer). If multiple high-speed serial interfaces are integrated in a system, multiple controllers correspond to multiple Serdes PHYs. For example, when there are four controllers of PCIE0 (Peripheral Component Interconnect Express), PCIE1, SATA (Serial Advanced Technology Attachment) and EMAC (Ethernet Media Access Control), they correspond to four Serdes PHYs respectively, such as PCIE0 controller corresponding to Serdes PHY0, PCIE1 controller corresponding to Serdes PHY1, SATA controller corresponding to Serdes PHY2, and EMAC controller corresponding to Serdes PHY3.

[0003] However, in actual application scenarios, different applications usually require multiple controllers of different types or the same type. At this time, if the above test scheme of one controller corresponding to one Serdes PHY is used, a large number of Serdes PHYs are required, resulting in a large chip area and high cost.

[0004] Therefore, how to realize multiplexing of multiple Serdes PHYs in different application scenarios is a problem to be solved by those skilled in the art at present. SUMMARY

[0005] Therefore, how to realize multiplexing of multiple Serdes PHYs in different application scenarios is a problem to be solved by those skilled in the art at present.

[0006] In a first aspect, the present application discloses a Serdes PHY multiplexing method, comprising:

[0007] Count the number of target controllers required in various application scenarios to obtain the corresponding number of controllers;

[0008] Determine a maximum value from the plurality of controller quantities, and determine a plurality of target SerDes PHYs having the same number as the maximum value;

[0009] A plurality of different operating modes are respectively set so as to match the target controller and a plurality of target SerDes PHYs in the different application scenarios under the plurality of different operating modes.

[0010] Optionally, after counting the number of target controllers required in various application scenarios to obtain the corresponding number of controllers, the method further includes:

[0011] The types of all the target controllers required in the multiple different application scenarios are counted to obtain a first number of target controller types.

[0012] Optionally, a plurality of different working modes are set respectively, including:

[0013] A variety of working modes can be set by properly configuring the working mode registers through the central processing unit.

[0014] Optionally, matching the target controller and the plurality of target SerDes PHYs in the different application scenarios in the plurality of different operating modes includes:

[0015] Determine a plurality of target selectors having the same number as the maximum value through the working mode register;

[0016] Each of the target selectors is matched with a plurality of controllers having the same first number and type as the target controller, and the matched target selectors are matched one by one with a plurality of target SerDes PHYs.

[0017] Optionally, the SerDes PHY multiplexing method further includes:

[0018] When a new application scenario is detected, the number and type of controllers required in the new application scenario are counted to obtain the number of new application scenario controllers and the second number of new application scenario controller types;

[0019] Determine whether the new application scenario controller types all belong to the target controller types;

[0020] If the new application scenario controller types all belong to the types of the target controller types, determining whether the number of the new application scenario controllers exceeds the number of the plurality of target SerDes PHYs;

[0021] If the number of controllers in the new application scenario does not exceed the number of the multiple target SerDes PHYs, the target selector is used to match the controllers in the new application scenario with the multiple target SerDes PHYs.

[0022] Optionally, the using the target selector to match the controller in the new application scenario with the plurality of target SerDes PHYs includes:

[0023] The target selector is used to match a plurality of controllers of the same type as the second number and the new application scenario controllers one by one with a plurality of the target SerDes PHYs.

[0024] Optionally, the number of target controllers required in various application scenarios is counted to obtain the corresponding number of controllers, including

[0025] The numbers of PCIE controllers, SATA controllers, and EMAC controllers required in various application scenarios are counted respectively to obtain the corresponding numbers of PCIE controllers, SATA controllers, and EMAC controllers.

[0026] In a second aspect, the present application discloses a SerDes PHY multiplexing device, comprising:

[0027] A quantity statistics module is used to count the number of target controllers required in various application scenarios and obtain the corresponding number of multiple controllers;

[0028] a determination module, configured to determine a maximum value from the plurality of controller quantities, and determine a plurality of target SerDes PHYs having the same number as the maximum value;

[0029] The working mode setting module is used to respectively set a plurality of different working modes so as to match the target controller and the plurality of target SerDes PHYs in the different application scenarios under the plurality of different working modes.

[0030] In a third aspect, the present application discloses an electronic device, comprising a processor and a memory; wherein the processor implements the aforementioned Serdes PHY multiplexing method when executing a computer program stored in the memory.

[0031] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned Serdes PHY multiplexing method is implemented.

[0032] It can be seen that the present application first counts the number of target controllers required in a variety of different application scenarios to obtain the corresponding number of multiple controllers, then determines the maximum value from the multiple numbers of controllers, and determines a plurality of target Serdes PHYs with the same number as the maximum value, and then sets a plurality of different working modes, so as to match the target controllers and the multiple target Serdes PHYs in the different application scenarios under the multiple different working modes. By setting a plurality of different working modes and matching different controllers and Serdes PHYs in different modes, the present application enables flexible reuse of Serdes PHYs, thereby reducing the number of Serdes PHYs, greatly reducing the chip area, improving system integration, and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0034] Figure 1 This is a flow chart of a SerDes PHY multiplexing method disclosed in this application;

[0035] Figure 2 A schematic diagram of a specific SerDes PHY application scenario disclosed in this application;

[0036] Figure 3 A block diagram of a conventional SerDes PHY usage method disclosed in this application;

[0037] Figure 4 This is a block diagram of a specific SerDes PHY multiplexing method disclosed in this application;

[0038] Figure 5 This is a structural diagram of a Serdes PHY multiplexing device disclosed in this application;

[0039] Figure 6 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0041] The present application embodiment discloses a Serdes PHY multiplexing method, see Figure 1 As shown, the method includes:

[0042] Step S11: Counting the number of target controllers required in various application scenarios to obtain a corresponding number of controllers.

[0043] In this embodiment, it is first necessary to count the number of controllers required in various application scenarios to obtain a corresponding number of controllers, wherein the target controllers include but are not limited to PCIE controllers, SATA controllers, and EMAC controllers.

[0044] In a specific embodiment, the method of counting the number of target controllers required in various application scenarios to obtain the corresponding number of controllers may include counting the number of PCIE controllers, SATA controllers, and EMAC controllers required in various application scenarios to obtain the corresponding number of PCIE controllers, SATA controllers, and EMAC controllers. For example, see Figure 2 As shown, Figure 2 Shows five specific application scenarios of Serdes PHY chip, respectively Figure 2 The types and quantities of controllers used in the five application scenarios are statistically analyzed: Scenario 1 requires 4 PCIE controllers + 4 PHYs; Scenario 2 requires 4 SATA controllers + 4 PHYs; Scenario 3 requires 4 EMAC controllers + 4 PHYs; Scenario 4 requires 2 PCIE controllers and 2 SATA controllers + 4 PHYs; Scenario 5 requires 2 PCIE controllers, 1 SATA controller and 1 EMAC controller + 4 PHYs.

[0045] In this embodiment, after counting the number of target controllers required in various application scenarios and obtaining the corresponding number of controllers, the method may further include counting the types of all target controllers required in various application scenarios and obtaining the first number of target controller types. That is, it is necessary not only to count the number of controllers required in various application scenarios, but also to further count the types of all controllers and the corresponding number of types. Figure 2 It can be seen that the five specific application scenarios include three types of controllers: PCIE controller, SATA controller and EMAC controller.

[0046] Step S12: determining a maximum value from the plurality of controller quantities, and determining a plurality of target SerDes PHYs having the same number as the maximum value.

[0047] In this embodiment, after the number of target controllers required in various application scenarios is counted to obtain the corresponding number of controllers, the maximum value is further determined from the multiple numbers of controllers, and then multiple target Serdes PHYs with the same number as the maximum value are determined. Figure 2 From the analysis of the five specific application scenarios, we can see that scenario one, scenario two, scenario three, scenario four and scenario five all require four controllers. Therefore, the maximum number of controllers used in the five application scenarios is four. At this time, we need to determine the corresponding four SerDes PHY chips.

[0048] Step S13: setting a plurality of different operating modes respectively, so as to match the target controller and a plurality of target SerDes PHYs in the different application scenarios under the plurality of different operating modes.

[0049] In this embodiment, after determining the maximum value from the number of the multiple controllers and determining a plurality of target SerDes PHYs having the same number as the maximum value, a plurality of different operating modes can be set for each of the above-mentioned application scenarios, respectively, so as to match the target controllers and the plurality of target SerDes PHYs in the above-mentioned different application scenarios under the plurality of different operating modes, that is, to match the plurality of target controllers with the plurality of target SerDes PHYs one by one.

[0050] Specifically, the setting of the plurality of different operating modes may include setting the plurality of different operating modes by properly configuring the operating mode registers through the central processing unit. That is, the central processing unit (CPU) may configure the operating mode registers, and then set the plurality of different operating modes through the configured operating mode registers.

[0051] In the embodiment, the matching the target controller and the target Serdes PHY in the different application scenarios in the different working modes can specifically include: determining a same number of target selectors as the maximum value through the working mode register; matching each target selector with a same number of controllers of the first number and the target controller type, and matching the matched target selectors with the target Serdes PHY one by one. Specifically, refer to Figure 3 and Figure 4 , Figure 3 It is shown that when the above five specific application scenarios are realized at the same time, the number relationship and the corresponding relationship between the controller and the Serdes PHY chip are as follows: the four PCIE controllers in scenario one, i.e., PCIE0, PCIE1, PCIE2, and PCIE3, correspond to four Serdes PHY chips, i.e., Serdes PHY0, Serdes PHY1, Serdes PHY2, and Serdes PHY3, respectively; the four SATA controls in scenario two, i.e., SATA0, SATA1, SATA2, and SATA3, correspond to four Serdes PHY chips, i.e., Serdes PHY4, Serdes PHY5, Serdes PHY6, and Serdes PHY7, respectively; the four EMAC controls in scenario three, i.e., EMAC0, EMAC1, EMAC2, and EMAC3, correspond to four Serdes PHY chips, i.e., Serdes PHY8, Serdes PHY9, Serdes PHY10, and Serdes PHY11, respectively; the two PCIE controllers and the two SATA controls in scenario four, i.e., PCIE0, PCIE1, SATA2, and SATA3, correspond to four Serdes PHY chips, i.e., Serdes PHY0, Serdes PHY1, Serdes PHY6, and Serdes PHY7, respectively; the two PCIE controllers, the one SATA controller, and the one EMAC controller in scenario five, i.e., PCIE0, PCIE1, SATA2, and EMAC3, correspond to four Serdes PHY chips, i.e., Serdes PHY0, Serdes PHY1, Serdes PHY6, and Serdes PHY11, respectively. As can be seen from the above, a total of 12 Serdes PHY chips are needed for the above five specific application scenarios. Figure 4 A specific Serdes PHY multiplexing framework is proposed for the application, which is shown in Figure 4It can be seen that in order to realize the multiplexing of Serdes PHY, that is, to meet multiple application scenarios at the same time, the CPU can be used to reasonably configure the working mode register, and then the corresponding number of selectors can be allocated through the working mode register, wherein the number of selectors is the above maximum value, that is, the value with the largest number of controllers in all application scenarios. Further, the controller in each scenario is connected to the Serdes PHY chip through the selector, and finally five different working modes are realized. Specifically, when the working mode register is configured for scenario one: use PCIE0 controller + Serdes PHY0, PCIE1 controller + Serdes PHY1, PCIE2 controller + Serdes PHY2, PCIE3 controller + Serdes PHY3; when the working mode register is configured for scenario two: use SATA0 controller + Serdes PHY0, SATA1 controller + Serdes PHY1, SATA2 controller + Serdes PHY2, SATA3 controller + Serdes PHY3; when the working mode register is configured for scenario three: use EMAC0 controller + Serdes PHY0, EMAC1 controller + Serdes PHY1, EMAC2 controller + Serdes PHY2, EMAC3 controller + Serdes PHY3; when the working mode register is configured as scenario 4: use PCIE0 controller + Serdes PHY0, PCIE1 controller + Serdes PHY1, SATA2 controller + Serdes PHY2, SATA3 controller + Serdes PHY3; when the working mode register is configured as scenario 5: use PCIE0 controller + Serdes PHY0, PCIE1 controller + Serdes PHY1, SATA2 controller + Serdes PHY2, EMAC3 controller + Serdes PHY3. Figure 4 It can be seen that the above five specific application scenarios can be realized through 4 SerDes PHY chips, which greatly reduces the number of SerDes PHY chips compared to the traditional 12 SerDes PHY chips.

[0052] Furthermore, after matching the target controllers and multiple target Serdes PHYs in the different application scenarios under the multiple different working modes, it can also include: when a new application scenario is monitored, counting the number and type of controllers required in the new application scenario to obtain the number of new application scenario controllers and the second number of new application scenario controller types; judging whether the new application scenario controller types all belong to the types in the target controller types; if the new application scenario controller types all belong to the types in the target controller types, judging whether the number of new application scenario controllers exceeds the number of multiple target Serdes PHYs; if the number of new application scenario controllers does not exceed the number of multiple target Serdes PHYs, using the target selector to match the controller in the new application scenario with the multiple target Serdes PHYs. In this embodiment, if a new application scenario is monitored, the number and type of controllers required in the new application scenario can be counted first to obtain the number of controllers in the new application scenario and the type of controllers in the new application scenario, and then the number of controller types in the new application scenario, that is, the second number, can be further counted; then, it is determined whether all controller types existing in the above-mentioned new application scenario belong to the types in the above-mentioned target controller types; if all controller types existing in the above-mentioned new application scenario belong to the types in the above-mentioned target controller types, it is further determined whether the total number of controllers in the above-mentioned new application scenario exceeds the total number of multiple target Serdes PHYs; if the total number of controllers in the above-mentioned new application scenario does not exceed the number of multiple target Serdes PHYs, the above-mentioned target selector can be directly used to match the controller in the new application scenario with the multiple target Serdes PHYs. For example, when application scenario six (2 SATA controllers and 1 EMAC controller + 4 PHYs) is monitored, the total number of controllers required in scenario six is ​​first counted, that is, 3. Then, it is determined whether the number of all controllers in scenario six is ​​greater than the number of Serdes PHYs in the above five specific application scenarios, that is, whether 3 is greater than 4. Since 3 is less than 4, the CPU can be used to configure the working mode register to implement scenario six, such as using SATA0 controller + Serdes PHY0, SATA1 controller + Serdes PHY1, and EMAC2 controller + Serdes PHY2.

[0053] In this embodiment, using the target selector to match the controller in the new application scenario with the multiple target Serdes PHYs may specifically include: using the target selector to match multiple controllers of the same type as the second number and the new application scenario controllers one by one with the multiple target Serdes PHYs. That is, when a new application scenario needs to be configured, the number of all controllers and the number of controller types in the new application scenario are first counted, and then it is determined whether the controller types in the new application scenario completely belong to the controller types that have already been configured with Serdes PHY chips. If the controller types in the new application scenario completely belong to the controller types that have already been configured with Serdes PHY chips, it is further determined whether the number of all controllers in the new application scenario exceeds the total number of the multiple target Serdes PHYs. If not, the existing controllers and Serdes PHY chips can be directly reused, and the connection relationship between the corresponding controllers and Serdes PHY chips can be established using the selector. Specifically, the new controller type required for the new application scenario can be first determined, and then the new controller type can be matched one by one with the existing Serdes PHY chips using the selector.

[0054] It can be seen that the embodiment of the present application first counts the number of target controllers required in a variety of different application scenarios to obtain a corresponding number of multiple controllers, then determines the maximum value from the multiple numbers of controllers, and determines a plurality of target Serdes PHYs equal to the maximum value, and then sets a plurality of different operating modes, so as to match the target controllers and the plurality of target Serdes PHYs in the different application scenarios under the multiple different operating modes. The embodiment of the present application sets a plurality of different operating modes and matches different controllers and Serdes PHYs under different modes, so that Serdes PHYs are flexibly reused, thereby reducing the number of Serdes PHYs, greatly reducing the chip area, improving system integration, and reducing costs.

[0055] Correspondingly, the embodiment of the present application also discloses a Serdes PHY multiplexing device, see Figure 5 As shown, the device includes:

[0056] The quantity statistics module 11 is used to count the number of target controllers required in various application scenarios to obtain the corresponding number of controllers;

[0057] A determination module 12 is configured to determine a maximum value from the plurality of controller quantities, and determine a plurality of target SerDes PHYs having the same number as the maximum value;

[0058] The working mode setting module 13 is configured to set a plurality of different working modes respectively, so as to match the target controllers and the plurality of target Serdes PHYs in the different application scenarios under the plurality of different working modes.

[0059] The specific working procedures of the above modules can refer to the corresponding content disclosed in the foregoing embodiments, and will not be described here.

[0060] It can be seen that in the embodiments of the present application, the number of target controllers required in a plurality of different application scenarios is counted respectively to obtain a plurality of controller numbers, then the maximum value is determined from the plurality of controller numbers, and a plurality of target Serdes PHYs with the same number as the maximum value are determined, and a plurality of different working modes are set respectively, so as to match the target controllers and the plurality of target Serdes PHYs in the different application scenarios under the plurality of different working modes. The embodiments of the present application set a plurality of different working modes, and match different controllers and Serdes PHYs under different modes, so that the Serdes PHY is flexibly multiplexed, thereby reducing the number of Serdes PHYs, greatly reducing the area of the chip, improving the system integration, and reducing the cost.

[0061] In some specific embodiments, the number counting module 11 can further include:

[0062] The controller type counting unit is configured to count the types of all the target controllers required in the plurality of different application scenarios to obtain a first number of target controller types.

[0063] In some specific embodiments, the working mode setting module 13 can specifically include:

[0064] The working mode setting unit is configured to set a plurality of different working modes by reasonably configuring a working mode register by a central processing unit.

[0065] In some specific embodiments, the working mode setting module 13 can specifically include:

[0066] The selector determining unit is configured to determine a plurality of target selectors with the same number as the maximum value through the working mode register.

[0067] The matching unit is configured to match each target selector with a plurality of controllers with the same number and target controller type as the first number, and match the plurality of target selectors after matching with a plurality of target Serdes PHYs one by one.

[0068] In some specific embodiments, the Serdes PHY multiplexing device may further include:

[0069] A statistical unit is configured to, when a new application scenario is detected, count the number and type of controllers required in the new application scenario to obtain the number of new application scenario controllers and a second number of new application scenario controller types;

[0070] A first judging unit, configured to judge whether the new application scenario controller types all belong to the target controller types;

[0071] A second judging unit is configured to judge whether the number of the new application scenario controllers exceeds the number of the plurality of target SerDes PHYs if the types of the new application scenario controllers all belong to the types of the target controllers;

[0072] The first Serdes PHY matching unit is configured to match the controller in the new application scenario with the multiple target Serdes PHYs using the target selector if the number of controllers in the new application scenario does not exceed the number of the multiple target Serdes PHYs.

[0073] In some specific embodiments, the first SerDes PHY matching unit may specifically include:

[0074] The second Serdes PHY matching unit is configured to use the target selector to match a plurality of controllers of the same type as the second number and the new application scenario controllers one by one with the plurality of target Serdes PHYs.

[0075] In some specific embodiments, the quantity statistics module 11 may specifically include:

[0076] The quantity statistics unit is used to count the number of PCIE controllers, SATA controllers and EMAC controllers required in various application scenarios, and obtain the corresponding number of PCIE controllers, SATA controllers and EMAC controllers.

[0077] Furthermore, the embodiment of the present application also discloses an electronic device, Figure 6 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram should not be considered as any limitation to the scope of application of the present application.

[0078] Figure 6This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps of the SerDes PHY multiplexing method disclosed in any of the aforementioned embodiments. Furthermore, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0079] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world. Its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0080] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0081] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device 20, and can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to implement the SerDes PHY multiplexing method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to perform other specific tasks.

[0082] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the SerDes PHY multiplexing method disclosed above is implemented. The specific steps of this method can be referred to the corresponding contents disclosed in the aforementioned embodiments and will not be repeated here.

[0083] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0084] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality, without referring to a specific sequence of operations for implementing the functions. The order of various illustrative blocks, modules, circuits, and steps may be re-arranged or otherwise implemented without departing from the spirit of the application, which is defined by the appended claims.

[0085] The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0086] Finally, it should be noted that the terms "first", "second", and the like, herein do not denote any order, quantity, combination, or importance, but rather are used to distinguish one element from another, and are more especially used for the purpose of distinction from other elements in the specification. Also, the terms "comprise", "include" or "contain" or any other variant thereof are intended to encompass non-exclusive inclusions, such that processes, methods, articles, or apparatuses that comprise, include, or contain a list of elements are not limited to those elements, but can include other elements not expressly listed or inherent to such processes, methods, articles, or apparatuses. Without further limitation, an element defined by the phrase "comprising a... " does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0087] The above provides a Serdes PHY multiplexing method, device, equipment and storage medium. The principles and implementation manners of the application are described by specific examples. The above example is only used to help understand the method and core idea of the application. For those skilled in the art, according to the idea of the application, the specific implementation manner and application range can be changed. The above description should not be understood as limiting the application.

Claims

1. A Serdes PHY multiplexing method, characterized in that: include: Count the number of target controllers required in various application scenarios to obtain the corresponding number of controllers; Determine a maximum value from the plurality of controller quantities, and determine a plurality of target SerDes PHYs having the same number as the maximum value; Setting a plurality of different operating modes respectively, so as to match the target controller and the plurality of target SerDes PHYs in the different application scenarios in the plurality of the different operating modes; After counting the number of target controllers required in the various application scenarios to obtain the corresponding number of controllers, the method further includes: counting the types of all the target controllers required in the various application scenarios to obtain a first number of target controller types; The said setting of a plurality of different working modes respectively includes: setting a plurality of different working modes by reasonably configuring the working mode registers by the central processing unit; The matching of the target controller and the multiple target SerDes PHYs in the different application scenarios under the multiple different operating modes includes: determining a plurality of target selectors that is the same as the maximum number through the operating mode register; matching each of the target selectors with a plurality of controllers that are the same as the first number and the type of the target controller, and matching the matched multiple target selectors one by one with the multiple target SerDes PHYs.

2. The Serdes PHY multiplexing method according to claim 1, wherein: Also includes: When a new application scenario is detected, the number and type of controllers required in the new application scenario are counted to obtain the number of new application scenario controllers and the second number of new application scenario controller types; Determine whether the new application scenario controller types all belong to the target controller types; If the new application scenario controller types all belong to the types of the target controller types, determining whether the number of the new application scenario controllers exceeds the number of the plurality of target SerDes PHYs; If the number of controllers in the new application scenario does not exceed the number of the multiple target SerDes PHYs, the target selector is used to match the controllers in the new application scenario with the multiple target SerDes PHYs.

3. The Serdes PHY multiplexing method according to claim 2, wherein: The using the target selector to match the controller in the new application scenario with the plurality of target SerDes PHYs includes: The target selector is used to match a plurality of controllers of the same type as the second number and the new application scenario controllers one by one with a plurality of the target SerDes PHYs.

4. The SerDes PHY multiplexing method according to any one of claims 1 to 3, wherein: The number of target controllers required in various application scenarios is counted to obtain corresponding numbers of controllers, including: The numbers of PCIE controllers, SATA controllers, and EMAC controllers required in various application scenarios are counted respectively to obtain the corresponding numbers of PCIE controllers, SATA controllers, and EMAC controllers.

5. A Serdes PHY multiplexing device, characterized in that: include: A quantity statistics module is used to count the number of target controllers required in various application scenarios and obtain the corresponding number of multiple controllers; a determination module, configured to determine a maximum value from the plurality of controller quantities, and determine a plurality of target SerDes PHYs having the same number as the maximum value; A working mode setting module, configured to respectively set a plurality of different working modes, so as to match the target controller and the plurality of target SerDes PHYs in the different application scenarios under the plurality of the different working modes; The device is further configured to collect statistics on the types of all target controllers required in the multiple different application scenarios to obtain a first number of target controller types; The working mode setting module is specifically used to set a plurality of different working modes by reasonably configuring the working mode register by the central processing unit; and determine a plurality of target selectors having the same number as the maximum value through the working mode register; Each of the target selectors is matched with a plurality of controllers having the same first number and type as the target controller, and the matched target selectors are matched one by one with a plurality of target SerDes PHYs.

6. An electronic device, characterized in that: The device comprises a processor and a memory; wherein, when the processor executes the computer program stored in the memory, the Serdes PHY multiplexing method according to any one of claims 1 to 4 is implemented.

7. A computer-readable storage medium, characterized in that Used to store a computer program; wherein, when the computer program is executed by a processor, the Serdes PHY multiplexing method according to any one of claims 1 to 4 is implemented.

Images