Method and apparatus for error detection and correction in memory

Abstract

The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. Embodiments include a memory having a group of self-selected memory cells that store data corresponding to a codeword from an error correction code; and circuitry configured to: perform a sensing operation on the group of self-selected memory cells; based on the sensing operation, identify a memory cell in the group that is unable to store data; flag data sensed from the identified memory cell as erased; and perform an error correction operation on data sensed from the group of self-selected memory cells if the data sensed from the identified memory cell is flagged as erased.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memories and methods, and more specifically, to error detection and correction in memories. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits and / or external removable devices in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory provides persistent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, read-only memory (ROM), and resistive variable memory such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and programmable conductive memory, etc.

[0003] Memory devices can be used as volatile and non-volatile memory in a variety of electronic applications that require high memory density, high reliability, and low power consumption. Non-volatile memory can be used in, for example, personal computers, Memory Sticks, solid-state drives (SSDs), digital cameras, cellular phones, portable music players and video players such as MP3 players, and other electronic devices.

[0004] A variable resistance memory device may include a variable resistance memory cell capable of storing data based on the resistance state of a memory element (e.g., a memory element with variable resistance). Thus, the variable resistance memory cell can be programmed to store data corresponding to a target data state by changing the resistance level of the memory element. The cell can be programmed to a target data state (e.g., corresponding to a specific resistance state) by applying an electric field or energy source (e.g., positive or negative electrical pulses, such as positive or negative voltage or current pulses) to the variable resistance memory cell (e.g., the memory element of the cell) for a specific duration. The state of the cell can be determined by sensing the current through the variable resistance memory cell in response to an applied interrogation voltage. The sensed current, varying based on the resistance level of the cell, indicates the state of the cell.

[0005] Various memory arrays can be organized into a crosspoint architecture, where memory cells (e.g., variable-resistance cells) are located at the intersection of a first signal line and a second signal line for accessing the cell (e.g., the intersection of a word line and a bit line). Some variable-resistance memory cells may include a selection element (e.g., a diode, transistor, or other switching device) connected in series with a storage element (e.g., a phase-change material, a metal oxide material, and / or some other material programmable to different resistance levels). Some variable-resistance memory cells, which may be called self-selecting memory cells, may contain a single material that can serve as both the selection element and the storage element of the memory cell. Summary of the Invention

[0006] One aspect of this disclosure provides an apparatus for error detection and correction in a memory, wherein the apparatus includes: a memory having a group of selectable memory cells storing data corresponding to codewords from error correction codes; and a circuit system configured to: perform a sensing operation on the group of selectable memory cells; identify memory cells in the group that cannot store data based on the sensing operation; mark data sensed from the identified memory cells as to be erased; and, in the case that the data sensed from the identified memory cells is marked as to be erased, perform an error correction operation on the data sensed from the group of selectable memory cells.

[0007] Another aspect of this disclosure provides a method of operating a memory, wherein the method includes: performing a first sensing operation on a group of selectable memory cells, the group of selectable memory cells including a word for sensing data from the group of selectable memory cells; performing a second sensing operation on the group of selectable memory cells after the first sensing operation to identify memory cells in the group that cannot store data; marking bits in the word corresponding to the identified memory cells in the group as erased; and performing an error correction operation on the data sensed from the group of selectable memory cells using the orientation of the bits marked as erased in the word.

[0008] Another aspect of this disclosure provides an apparatus for error detection and correction in a memory, wherein the apparatus includes: a memory having a group of selectable memory cells; and a circuit system configured to: perform a sensing operation on the group of selectable memory cells to: sense data from the group of selectable memory cells; identify memory cells in the group that cannot store data; mark the data sensed from the identified memory cells of the group as erased; and, in the case that the data sensed from the identified memory cells of the group is marked as erased, perform an error correction operation on the data sensed from the group of selectable memory cells.

[0009] Another aspect of this disclosure provides a method of operating a memory, wherein the method includes: performing a bipolar sensing operation on a group of selectable memory cells to identify memory cells in the group that cannot store data; marking data sensed from the identified memory cells in the group as to be erased; and, in the case that the data sensed from the identified memory cells is marked as to be erased, performing an error correction operation on the data sensed from the group of selectable memory cells. Attached Figure Description

[0010] Figure 1 This is a three-dimensional view of an example of a memory array according to an embodiment of the present disclosure.

[0011] Figure 2A This describes the distribution of threshold voltages associated with various states of memory cells according to embodiments of the present disclosure.

[0012] Figure 2B The embodiments corresponding to this disclosure Figure 2A An example of a current-to-voltage curve for memory states.

[0013] Figure 2C The embodiments corresponding to this disclosure Figure 2A Another example of a current-to-voltage curve for a memory state.

[0014] Figure 3 This is a block diagram illustration of an example device according to an embodiment of the present disclosure.

[0015] Figure 4 This is a flowchart of an example method for error detection and correction according to embodiments of the present disclosure.

[0016] Figure 5 An example sensing circuit system according to an embodiment of the present disclosure is described.

[0017] Figure 6 An example of an error detection table according to an embodiment of this disclosure is described. Detailed Implementation

[0018] This disclosure includes apparatus, methods, and systems for error detection and correction in memory. Embodiments include a memory having a group of selectable memory cells storing data corresponding to codewords from a subset of error correction codes; and a circuit system configured to: perform a sensing operation on the group of selectable memory cells; identify memory cells in the group that cannot store data based on the sensing operation; mark data sensed from the identified memory cells as to be erased; and, in the case that the data sensed from the identified memory cells is marked as to be erased, perform an error correction operation on the data sensed from the group of selectable memory cells.

[0019] During the sensing of a variable resistance memory cell, such as a self-select memory cell, a voltage can be applied to the memory cell, and the data state of the cell can be determined based on the amount of current flowing through the cell in response to the applied voltage. For example, when a voltage is applied to the memory cell, the amount of current obtained on a signal line (e.g., a bit line or word line) coupled to the memory cell can be compared with a reference current, and the state of the memory cell can be determined based on the comparison. For example, if the comparison indicator signal line current is less than the reference current, then the cell can be determined to be in a first (e.g., reset) data state, and if the comparison indicator signal line current is greater than the reference current, then the cell can be determined to be in a second (e.g., set) data state.

[0020] However, during memory operations, various mechanisms, such as read interference, can cause a memory cell to be determined (e.g., sensed) to be in a data state different from the state to which the cell is actually programmed. For example, a memory cell programmed to a first data state may be incorrectly sensed as being in a second data state, indicating an error within the selected memory cell. Such erroneous data sensing can degrade memory performance and / or lifetime, and may be more severe in memories with increased cell density.

[0021] Certain mechanisms can cause a memory cell to be continuously sensed as one state or another, regardless of a previous programming operation on that cell. For example, a memory cell shorted to an adjacent line will always be sensed as being in the same state regardless of any programming operation; however, the sensed data state will depend on how the jumper is connected to the sensing circuitry. Memory cells affected by this type of mechanism cannot store data.

[0022] Operations can be performed to detect and correct such errors in the sensed data. These operations utilize redundant bits and information bits to generate codewords. Error correction is performed on the received word to recover the original codeword, and the presence of redundant bits allows the decoding algorithm to recover the original information bits even if a certain number of information or redundant bits are lost. However, as the amount of error in the sensed data increases, the correction rate of these operations may not be high enough to correct the errors, and the correction operation may fail. Furthermore, it may be difficult to increase the correction rate of the correction operation without changing the algorithm of the operation or reducing the amount of data being processed.

[0023] However, embodiments of this disclosure can improve error correction capability by identifying failed memory cells and using this knowledge when performing error correction operations. For example, during a failure identification operation, certain memory cells may be identified as unable to store data. The positions within the received word corresponding to these memory cells are marked as erased. For example, the erase may be caused by a short circuit within the memory cell. An error correction operation can then be performed on the received word to correct for the presence of the erase, as well as any other possible bit errors, and to recover the contained codeword and information bits. Identifying and using erase in this way improves the correction capability (e.g., the original bit error rate) of the error correction operation compared to the same error correction operation without knowing the erase positions.

[0024] Embodiments of this disclosure can utilize several methods for identifying and using erase operations. For example, one method may include performing a secondary sensing operation and comparing information obtained in the secondary sensing operation with information from a previous sensing operation. Another method may include using a sensing amplifier to detect a sudden return from a memory cell by checking a signal. This method can use a sensing circuitry system and system changes to identify and mark the erase operation. Another method may include performing a bipolar sensing operation, wherein two consecutive sensing voltages of opposite polarities can be applied to the memory cell. For example, a sensing voltage with positive polarity can be applied to the memory cell and then a sensing voltage with negative polarity can be applied to the same cell, and the resulting data from these two polarities can be compared.

[0025] As used herein, “a / an” or “a plurality of” can refer to one or more of something, and “a plurality of” can refer to two or more of such things. For example, a memory device can refer to one or more memory devices, and a plurality of memory devices can refer to two or more memory devices. Additionally, the designations “N” and “M” as used herein, especially with respect to reference numerals in the drawings, indicate that several specific features so specified may be included with several embodiments of this disclosure.

[0026] The figures in this document follow a numbering rule, where the first one or more digits correspond to the figure number, and the remaining digits identify elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits.

[0027] Figure 1 This is a three-dimensional view of an example of a memory array 100 (e.g., a cross-point memory array) according to embodiments of the present disclosure. The memory array 100 may include a plurality of first signal lines (e.g., first access lines) that intersect each other (e.g., intersect in different planes), referred to as word lines 110-0 to 110-N, and a plurality of second signal lines (e.g., second access lines) that are referred to as bit lines 120-0 to 120-M. For example, each of the word lines 110-0 to 110-N may intersect with the bit lines 120-0 to 120-M. Memory cells 125 may be located between the bit lines and word lines (e.g., at each bit line / word line intersection).

[0028] For example, memory cell 125 may be a variable-resistance memory cell. Memory cell 125 may contain materials programmable to different data states. In some instances, each of memory cells 125 may contain a single material located between a top electrode (e.g., a top plate) and a bottom electrode (e.g., a bottom plate) that can act as both a selection element (e.g., a switching material) and a storage element, such that each memory cell 125 can act as both a selector device and a memory element. Such memory cells may be referred to herein as self-selecting memory cells. For example, each memory cell may contain a chalcogenide material that can be formed from various doped or undoped materials, may or may not be a phase-change material, and / or may or may not undergo a phase change during reading and / or writing to the memory cell. Chalcogenide materials may be materials or alloys containing at least one of the elements S, Se, and Te. Chalcogenide materials may include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), and platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-A s, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, T e-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-B i-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. Example chalcogenide materials may also include SAG-based glass non-phase change materials, such as SeAsGe. Hyphenated chemical composition symbols, as used herein, indicate elements contained in a particular compound or alloy and are intended to represent all chemical calculations involving the indicated element. For example, Ge-Te may include GexTey, where x and y can be any positive integers.

[0029] In various embodiments, the threshold voltage of memory cell 125 may snap back in response to an applied voltage difference exceeding its threshold voltage. These memory cells may be referred to as snap-back memory cells. For example, memory cell 125 may change (e.g., snap back) from a non-conductive (e.g., high impedance) state to a conductive (e.g., low impedance) state in response to an applied voltage difference exceeding its threshold voltage. For example, a memory cell snap back may refer to a memory cell transitioning from a high impedance state to a lower impedance state in response to an applied voltage difference greater than the memory cell's threshold voltage. For example, the threshold voltage of a memory cell snap back may be referred to as a snap-back event. In some instances, a snap may be counted as an erase operation.

[0030] The architecture of memory array 100 can be called a cross-point architecture, in which memory cells are formed as follows: Figure 1 The topological intersections between word lines and bit lines are described in the diagram. This type of intersection architecture offers relatively high-density data storage at a lower manufacturing cost compared to other memory architectures. For example, intersection architectures can have memory cells with a smaller area and therefore a higher memory cell density compared to other architectures.

[0031] However, the embodiments disclosed herein are not limited to Figure 1 The example memory array architecture described herein. For example, embodiments of this disclosure may include a three-dimensional memory array having a plurality of vertically oriented (e.g., vertical) access lines and a plurality of horizontally oriented (e.g., horizontal) access lines. The vertical access lines may be bit lines arranged in a columnar architecture, and the horizontal access lines may be word lines arranged in a plurality of conductive planes or decks separated from each other by a dielectric material (e.g., insulated). The chalcogenide material of the respective memory cell of such a memory array may be located at the intersection of the respective vertical bit line and horizontal word line.

[0032] Furthermore, in some architectures (not shown), multiple first access lines may be formed on a parallel plane or tier parallel to the substrate. The multiple first access lines may be configured to include multiple vias to allow multiple second access lines to be formed orthogonally to the plane of the first access lines, such that each of the multiple second access lines passes through a vertically aligned set of vias (e.g., second access lines positioned perpendicular to the plane of the first access lines and the horizontal substrate). Memory cells containing memory elements (e.g., self-select memory cells containing chalcogenide material) may be formed at the intersection of the first and second access lines (e.g., the space between the first and second access lines in the vertically aligned set of vias). Memory cells (e.g., self-select memory cells containing chalcogenide material) may be operated (e.g., read and / or programmed) by selecting a corresponding access line and applying a voltage or current pulse.

[0033] Figure 2A The description of the memory cell (e.g., according to embodiments of the present disclosure) is illustrated. Figure 1 The threshold distribution associated with various states of the memory cell 125 described herein. For example, as Figure 2A As shown, the memory cell can be programmed to one of two possible data states (e.g., state 0 or state 1). That is, Figure 2A This describes the threshold voltage distribution associated with two possible data states that the memory cell can be programmed to.

[0034] exist Figure 2A In this context, the voltage VCELL can correspond to the voltage difference applied to a memory cell (e.g., applied across memory cells), such as the difference between the bit line voltage (VBL) and the word line voltage (VWL) (e.g., VCELL = VBL - VWL). Threshold voltage distributions (e.g., ranges) 201-1, 201-2, 202-1, and 202-2 can represent the statistical variation of the threshold voltage of a memory cell programmed into a particular state. Figure 2A The distribution described in the text corresponds to further combination Figure 2B and 2C The described current versus voltage curve, Figure 2B and 2C This explains the sudden reversal asymmetry associated with the assigned data state.

[0035] In some instances, the threshold voltage of memory cell 125 in a particular state may be asymmetrical for different polarities, such as... Figure 2A , 2B As shown in 2C. For example, the threshold voltage of memory cell 125 programmed to a reset state (e.g., state 0) or a set state (e.g., state 1) may differ in value in one polarity from its value in the opposite polarity. For example, in Figure 2A In the example described, a first data state (e.g., state 0) is associated with a first asymmetric threshold voltage distribution (e.g., threshold voltage distributions 201-1 and 201-2) where the magnitude is greater for negative polarity than positive polarity, and a second data state (e.g., state 1) is associated with a second asymmetric threshold voltage distribution (e.g., threshold voltage distributions 202-1 and 202-2) where the magnitude is greater for positive polarity than negative polarity. In this example, the applied voltage magnitude sufficient to cause a sudden return of memory cell 125 may differ from (e.g., be higher or lower than) the applied voltage polarity for one applied voltage polarity.

[0036] Figure 2AThe boundary voltages VDM1 and VDM2 are explained, which can be used to determine the state of a memory cell (e.g., to distinguish between states as part of a read operation). In this example, VDM1 is a positive voltage used to distinguish cells in state 0 (e.g., in threshold voltage distribution 201-2) from cells in state 1 (e.g., threshold voltage distribution 202-2). Similarly, VDM2 is a negative voltage used to distinguish cells in state 1 (e.g., threshold voltage distribution 202-1) from cells in state 0 (e.g., threshold voltage distribution 201-1). Figure 2A-2C In the example, memory cell 125 in positive state 1 does not suddenly return in response to the application of VDM1; memory cell 125 in positive state 0 suddenly returns in response to the application of VDM1; memory cell 125 in negative state 1 suddenly returns in response to the application of VDM2; and memory cell 125 in negative state 0 does not suddenly return in response to the application of VDM2.

[0037] Examples are not limited to Figure 2A The example shown. For instance, the designations of state 0 and state 1 can be interchanged (e.g., distributions 201-1 and 201-2 can be designated as state 1 and distributions 202-1 and 202-2 can be designated as state 0). The VDM described herein can be used for bipolar sensing operations (such as...). Figure 2A (as described in the text) in and / or unipolar sensing operation. In unipolar sensing operation, VDM can be in the same polarity but have different magnitudes.

[0038] Figure 2B and 2C The embodiments corresponding to this disclosure Figure 2A An example of the current-to-voltage curve for the memory state. Therefore, in this example, Figure 2B and 2C The curves in the diagram correspond to cells where state 1 is designated as a higher threshold voltage state in a specific polarity (positive polarity direction in this example) and where state 0 is designated as a higher threshold voltage state in the opposite polarity (negative polarity direction in this example). As mentioned above, the state designations are interchangeable, such that state 0 can correspond to a higher threshold voltage state in the positive polarity direction, while state 1 corresponds to a higher threshold voltage state in the negative polarity direction.

[0039] Figure 2B and 2C This describes a memory cell burst as described herein. VCELL can represent the voltage applied across the memory cell. For example, VCELL can be the voltage applied to the top electrode corresponding to the cell minus the voltage applied to the bottom electrode corresponding to the cell (e.g., via the respective word line and bit line). Figure 2BAs shown, in response to an applied positive polarity voltage (VCELL), a memory cell programmed to state 1 (e.g., threshold voltage distribution 200-2) is in a non-conductive state until VCELL reaches voltage Vtst02, at which point the cell transitions to a conductive (e.g., lower resistance) state. This transition can be called a backsliding event, which occurs when the voltage applied across the cell (in a particular polarity) exceeds the cell's threshold voltage. Therefore, voltage Vtst02 can be called the backsliding voltage. Figure 2B In this context, voltage Vtst01 corresponds to the sudden return voltage of a cell programmed to state 1 (e.g., threshold voltage distribution 202-1). That is, as... Figure 2B As shown, when VCELL crosses Vtst01 in the negative polarity direction, the memory cell transitions (e.g., switches) to a conductive state.

[0040] Similarly, such as Figure 2C As shown, in response to an applied negative voltage (VCELL), a memory cell programmed to state 0 (e.g., threshold voltage distribution 201-1) is in a non-conductive state until VCELL reaches voltage Vtst11, at which point the cell abruptly returns to a conductive (e.g., lower resistance) state. Figure 2C In this context, voltage Vtst12 corresponds to the sudden return voltage of a cell programmed to state 0 (e.g., threshold voltage distribution 201-2). That is, as... Figure 2C As shown, when VCELL exceeds Vtst12 in the positive polarity direction, the memory cell abruptly returns from a high-impedance non-conductive state to a lower-impedance conductive state.

[0041] In various situations, a backslip event can cause a memory cell to switch states. For example, if a VCELL greater than Vtst02 is applied to a state 1 cell, the resulting backslip event can reduce the cell's threshold voltage to a level below VDM1, causing the cell to be read as state 0 (e.g., threshold voltage distribution 201-2). Therefore, in several embodiments, a backslip event can be used to write a cell to the opposite state (e.g., from state 1 to state 0, and vice versa).

[0042] When memory cells 125 are repeatedly programmed (e.g., written to) and sensed (e.g., read from), the magnitudes of their surge voltages (e.g., Vtst 01, Vtst 02, Vtst 11, and Vtst 12) can change due to the stress caused by the continuous application of programming and sensing voltages to the electrodes of the cells. This can make the cells more or less prone to surge. This can cause selected cells to be sensed in a data state during sensing operations that is different from the state to which the cells are actually programmed. For example, a memory cell programmed to a reset state (e.g., state 0) may be incorrectly sensed to be in a set state (e.g., state 1). Such errors can be corrected using error correction operations, as will be further described herein.

[0043] Figure 3 This is a block diagram illustration of an example device (e.g., electronic memory system 300) according to embodiments of the present disclosure. Memory system 300 may include devices, such as memory device 302, and a controller 304, such as a memory controller (e.g., a host controller). Controller 304 may include, for example, a processor. Controller 304 may be coupled to, for example, a host and may receive command signals (or commands), address signals (or addresses), and data signals (or data) from the host, and may output data to the host.

[0044] Memory device 302 includes a memory array 306 of memory cells. For example, memory array 306 may include one or more memory arrays of memory cells disclosed herein (e.g., a cross-point array). Memory device 302 may include an address circuitry 308 to latch address signals provided via I / O connections 310 through an I / O circuitry 312. Row decoders 314 and column decoders 316 may receive and decode address signals to access memory array 306. For example, row decoders 314 and / or column decoders 316 may include drivers.

[0045] Memory device 302 may use a sensing / buffer circuitry system to sense (e.g., read) data in memory array 306 by sensing voltage and / or current changes in the memory array columns. In some instances, the sensing / buffer circuitry system may include a read / latch circuitry system 320 and / or a sensing circuitry system 305. Read / latch circuitry system 320 may read and latch data from memory array 306. Sensing circuitry system 305 may include several sensing amplifiers coupled to memory cells of memory array 306, which may operate in combination with read / latch circuitry system 320 to sense (e.g., read) memory states from target memory cells, as will be further described herein. I / O circuitry system 312 may be included for bidirectional data communication with controller 304 via I / O connector 310. Write circuitry system 322 may be included for writing data to memory array 306.

[0046] The control circuitry 324 can decode signals provided from the controller 304 via the control connection 326. These signals may include chip signals, write enable signals, and address latch signals for controlling operations on the memory array 306, including data read and data write operations.

[0047] The control circuitry 324 may be included, for example, in the controller 304. The controller 304 may include other circuitry, firmware, software, etc., individually or in combination. The controller 304 may be an external controller (e.g., in a die separate from the memory array 306, whether fully or partially) or an internal controller (e.g., included in the same die as the memory array 306). For example, an internal controller may be a state machine or a memory sequencer.

[0048] In some instances, controller 304 may be configured to identify failed memory cells in memory array 306 and use this knowledge to improve the error correction capability of the operation when performing error correction operations on data sensed from memory array 306. For example, controller 304 may perform a sensing operation on a group of memory cells in memory array 306 and, based on the sensing operation, identify memory cells in the group that cannot store data.

[0049] In one instance, a memory cell that cannot store data may fail to store data due to a short circuit associated with the memory cell. In another instance, a memory cell that cannot store data may fail to store data due to a leak in the data line associated with the memory cell.

[0050] In some instances, memory cells may be groups of selectable memory cells. Each memory cell may contain a single material located between a top electrode (e.g., a top plate) and a bottom electrode (e.g., a bottom plate) that can act as both a selector device and a memory element, as previously described herein. Alternatively, a group of memory cells may be, for example, pages of memory cells in array 306 storing codeword data patterns. For instance, memory array 306 may be divided into addressable groups of memory cells that can be programmed (e.g., write) in response to a programming command addressing the group and sensed (e.g., read) in response to a sensing command addressing the group. In some instances, a group of memory cells may have physical addresses corresponding to logical addresses received from a host. Controller 304 may include a logic-to-physical (L2P) mapping component that maps logical addresses from the host to physical addresses of the groups of memory cells. A group of memory cells may be a page corresponding to a logical address. For example, each group can store data patterns (e.g., data structures) that can be called managed units (e.g., codewords).

[0051] After identifying memory cells in the group that cannot store data, the controller 304 may mark any data sensed from these cells as erased, and may perform any error correction operations performed by the controller 304 on the data sensed from the group of memory cells if the data sensed from the identified memory cells is marked as erased.

[0052] Error correction operations can be performed using error correction codes such as Hamming codes, Reed-Solomon (RS) codes, Bose-Chaudhuri-Hochquenghem (BCH) codes, Cyclic Redundancy Check (CRC) codes, Golay codes, Reed-Muller codes, Goppa codes, adjacent cell-assisted error correction codes, low-density parity check (LDPC) error correction codes, and Denniston codes, and / or other types of error correction codes that facilitate error correction. For example, controller 304 can use the BCH algorithm to perform error correction operations. Performing error correction operations when data sensed from memory cells is marked for erasure can improve the error correction rate of the error correction operation.

[0053] In one embodiment, controller 304 may perform a first sensing operation on a group of selectable memory cells to sense data from the group of selectable memory cells. The data sensed during the first sensing operation may be transmitted to controller 304 as standard data. Controller 304 may then perform a second sensing operation on the group of memory cells after the first sensing operation to identify memory cells in the group that cannot store data. For example, the second sensing operation may be performed to detect short circuits within the memory cells of the group (e.g., any cell in the group where a short circuit is detected may be identified as a memory cell that cannot store data). Controller 304 may mark the data sensed from the identified cells (e.g., cells that cannot store data) in the group as erased, and perform error correction on the data sensed from the group of cells if the data sensed from the identified cells is marked as erased.

[0054] In one example, the second sensing operation may include applying a first voltage to a sensing line coupled to a memory cell and applying a second voltage, less than the first voltage, to an access line coupled to the memory cell. In another example, the second sensing operation may include applying a first voltage to a sensing line coupled to a memory cell and applying a second voltage, equal to the first voltage, to an access line coupled to the memory cell. For example, the second sensing operation may use the same sensing voltage as the first sensing operation.

[0055] In another embodiment, controller 304 may perform a sensing operation on a group of selectable memory cells to sense data from the group of selectable memory cells and identify memory cells in the group that cannot store data. Controller 304 may mark the data sensed from cells in the group that are identified as unable to store data as to be erased. Controller 304 may perform an error correction operation on the data sensed from the group of cells if the data sensed from the identified cells is marked as erased.

[0056] As an example, a sense amplifier can be used to detect a sudden return of a memory cell via a check signal within the sense circuit system 305. Memory cells in the group that cannot store data can be identified based on binary data from a check state latch coupled to the sense amplifier. In this example, the location of the cells in the group that cannot store data within the memory can also be identified. The sensing operation can be performed by grounding the access line coupled to the memory cell and charging the access line after grounding it. During the sensing operation, all sensed data is marked as being in a first data state (e.g., 0), and data sensed from memory cells identified as unable to store data is marked as being in a second data state (e.g., 1). This will be discussed herein (e.g., in conjunction with...). Figure 5 Further descriptions of such sensing amplifiers and examples of sensing operations are provided.

[0057] In another embodiment, controller 304 may perform a bipolar sensing operation on a group of selected memory cells to identify memory cells in the group that cannot store data, mark the data sensed from the identified inability to store data as erased, and perform an error correction operation on the data sensed from the identified memory cells marked as erased. The bipolar sensing operation may include performing two consecutive read operations on the group of memory cells with opposite polarities (e.g., using two sensing voltages of opposite polarities). The bipolar sensing operation can be used to detect short circuits associated with the memory cells (e.g., any cell with a short circuit detected by the bipolar sensing operation can be identified as a cell that cannot store data). For example, a memory cell may be identified as unable to store data when it is sensed to be in the same data state in both consecutive reads (e.g., if two consecutive opposite sensing voltage polarities produce the same data state in the memory cell). The bipolar sensing operation may include performing a first read in two consecutive reads using a first voltage and a second read in two consecutive reads using a second voltage with the opposite polarity to the first voltage and a magnitude less than the first voltage. In this article (e.g., in conjunction with) Figure 6 Further, an example of an error detection table that can be used in conjunction with this type of bipolar sensing operation to identify memory cells that cannot store data is described.

[0058] In one example, the additional sensing operation can be performed as a standard sensing operation to identify units in the group that cannot store data. In one embodiment, the additional sensing operation can be performed before the bipolar sensing operation. In another embodiment, the additional sensing operation can be performed after the bipolar sensing operation.

[0059] Figure 4 This is a flowchart of an example method 450 for error detection and correction according to embodiments of the present disclosure. Method 450 may be derived from, for example... Figure 3 The controller 304 executes.

[0060] At block 451 of method 450, a sensing (e.g., reading) operation is performed. As previously described herein, the sensing operation can be performed using a first boundary voltage (e.g., VDM0) applied to the group of select memory cells.

[0061] At block 452 of method 450, an initial error correction operation can be performed on the data sensed during the sensing operation. The error correction operation can be performed using an error correction code. The error correction code can be a BCH code. For example, the BCH algorithm can be used to perform the error correction operation. If the error correction operation is successful at 454, then access to the data 453 stored in the memory cell is unimpeded. If the error correction operation is unsuccessful (e.g., fails) 455, then at block 456, a sensing (e.g., reading) operation can be performed to detect memory cells that cannot store data due to short circuits in the memory cells.

[0062] At block 457 of method 450, memory cells in the group that cannot store data are identified, and data sensed from these memory cells during a sensing operation performed using a first boundary voltage (e.g., VDM0) can be marked as erased. At block 458 of method 450, if data sensed from the cells identified at block 457 is marked as erased, a subsequent error correction operation can be performed on the data sensed during the sensing operation (e.g., using the BCH algorithm). If the error correction operation is successful at 460, then access to the data 453 stored in the memory cell is unimpeded. If the error correction operation is unsuccessful (e.g., fails) 459, then a subsequent sensing (e.g., read) operation can be performed at block 461 to detect memory cells that cannot store data due to a short circuit in the memory cell. The subsequent sensing operation can be performed using a second boundary voltage (e.g., VDM1).

[0063] At block 462 of method 450, memory cells in the group that cannot store data are identified, and data sensed from these memory cells during a sensing operation performed using a second boundary voltage (e.g., VDM1) may be marked as erased. At block 463 of method 450, if data sensed from cells identified in block 462 is marked as erased, a subsequent error correction may be performed on the data sensed during the sensing operation (e.g., using the BCH algorithm). If the error correction operation is successful at 464, then access to data 453 stored in the memory cell is unimpeded. If the error correction operation is unsuccessful (e.g., fails) 465, then a subsequent sensing (e.g., read) operation to detect memory cells that cannot store data due to a short circuit within the memory cell may be performed at block 466. The subsequent sensing operation may be performed using a third boundary voltage (e.g., VDM2).

[0064] At block 467 of method 450, memory cells in the group that cannot store data are identified, and data sensed from these memory cells during a sensing operation performed using a third threshold voltage (e.g., VDM2) may be marked as erased. At block 469 of method 450, if data sensed from cells identified in block 467 is marked as erased, a subsequent error correction operation may be performed on the data sensed during the sensing operation (e.g., using the BCH algorithm). If the error correction operation is successful at 468, then access to data 453 stored in the memory cells is unimpeded. If the error correction operation is unsuccessful (e.g., fails) 470, then errors in the data are considered uncorrectable errors 471.

[0065] Figure 5 This describes an example sensing circuit system 505 according to an embodiment of the present disclosure. The sensing circuit system 505 may be, for example, the previously combined... Figure 3 The described sensing circuit system 305.

[0066] like Figure 5 As shown, the sensing circuit system 505 may include a sensing amplifier 532. Although for simplicity... Figure 5 The description of a single sensing amplifier 532 does not obscure the embodiments of this disclosure, but sensing circuit system 505 (e.g., sensing circuit system 305) may include any number of sensing amplifiers similar to sensing amplifier 532.

[0067] Sensing amplifier 532 can be used to perform sensing operations on a group of selectable memory cells to sense data from the group of selectable memory cells and identify memory cells in the group that cannot store data. During the sensing operation, a boundary voltage (e.g., VDM1 and / or VDM2) can be applied to the memory cell, as previously described herein. In response to the application of the boundary voltage, current can flow through the cell and flow on a signal (e.g., access) line 533 coupled to the cell, as previously described herein. The access line (e.g., bit line) 533 can be coupled to sensing amplifier 532 to input this current, represented as array 506, into sensing amplifier 532, as... Figure 5 As shown. In some instances, access line 533 may be coupled to a memory array (e.g., memory array 306) to couple to an associated memory cell. In one embodiment, sensing operation can be performed by charging access line 533 while grounding or maintaining the word lines of the array at a very low voltage relative to the voltage to which access line 533 is charged.

[0068] The sensing amplifier 532 can compare the magnitude of the current on the access line with... Figure 5The magnitude of the reference current 534 shown is compared, and the result of the comparison is output to multiplexer 512 and then sent to latches 536 and 538. One of the latches (e.g., latch 536) may be a data latch that indicates the data state of a cell, and the other of the latches (e.g., latch 538) may be a check state latch that indicates whether the cell is unable to store data (e.g., a memory cell unable to store data can be identified based on binary data from a check state latch). For example, if the output of sense amplifier 532 (e.g., the result of the comparison) indicates that the magnitude of access line 533 is less than that of reference line 534, then the memory cell can be determined to be in a first (e.g., reset) data state, and if the output of sense amplifier 532 indicates that the magnitude of access line 533 is greater than that of reference line 534, then the memory cell can be determined to be in a second (e.g., set) data state. This result can be latched in the data latch. Additionally, during sensing operations, all sensed data can be marked as being in a first data state (e.g., 0) in a check state latch, and memory cells identified as unable to store data can be marked as being in a second data state (e.g., 1) in the check state latch. For example, a multiplexer 512 can be coupled to a check signal line 531 that can be used to detect a sudden return from a memory cell, and the result can be latched in the check state latch. The use of the sensing circuitry 505 can identify cells that cannot store data based on data from the check state latch and also uses the access lines to identify the orientation of those cells within the memory to determine where the sensed memory cells are located.

[0069] Figure 6 An example of an error detection table 640 according to an embodiment of the present disclosure is described below. For example, the error detection table 640 may be combined with bipolar sensing operations to identify memory cells that cannot store data. The upper portion of table 640 illustrates the possible outcomes (e.g., possible data states) of a bipolar sensing operation having two sensing operations (641 and 643) performed using sensing voltages of opposite polarities. For example, negative sensing operation 641 lists its possible outcomes, while positive sensing operation 643 lists its possible outcomes.

[0070] When a memory cell is sensed to be in the same data state in two consecutive reads, the bipolar erase 645 can identify cells that cannot store data. For example, if two consecutive reads of opposite polarities produce the same data state in a memory cell (e.g., both produce 0 or both produce 1), as described in set state 642-2 and reset state 644-2, then the cell can be identified as unable to store data. However, if two consecutive reads of opposite polarities produce different data states (e.g., one produces 0 and the other produces 1), as described in set state 642-1 and reset state 644-1, then the cell can store data. Therefore, the bipolar sensing operation can be used to detect short circuits within memory cells used for these two sensing operations in opposite polarities, such as... Figure 6 As explained in the text.

[0071] Error detection table 640 can also be combined with unipolar sensing operations (e.g., sensing operations using a sensing voltage of unipolar polarity) to identify memory cells that cannot store data. Row 646 of table 640 illustrates possible data states that will be set to standard data from a first sensing operation using negative polarity. Unipolar erase 647 can identify cells that cannot store data. For example, if a unipolar sensing operation produces data state 1, then the cell can be identified as unable to store data. Row 648 of table 640 illustrates possible data states that will be set to standard data from a first sensing operation using positive polarity. Bipolar short erase 649 can identify cells that cannot store data. Additionally, multiple sensing operations can be performed such that combined erase 639 can identify cells that cannot store data based on data sensed using sensing operations using opposite polarities.

[0072] While specific embodiments have been shown and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of several embodiments of this disclosure. It should be understood that the above description has been carried out illustratively and not restrictively. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the above description. The scope of the several embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the several embodiments of this disclosure should be determined with reference to the appended claims and the full scope of equivalents to which such claims are given.

[0073] In the foregoing detailed embodiments, some features are grouped together in a single embodiment for the purpose of simplifying this disclosure. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments must use more features than expressly stated in each claim. In fact, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is, in itself, a separate embodiment.

Claims

1. An apparatus for error detection and correction in a memory, comprising: A memory having a group of self-selected memory cells that store data corresponding to codewords from error correction codes; and The circuit system is configured as follows: Perform bipolar sensing operation on the group of the self-selected memory cells; Based on the bipolar sensing operation, memory cells in the group that cannot store data are identified; The data sensed from the identified memory cells will be marked as erased; and In the event that the data sensed from the identified memory cell is marked as erased, an error correction operation is performed on the data sensed from the group of the selected memory cells.

2. The device of claim 1, wherein each of the self-selection memory cells comprises a single material serving as both a selection element and a storage element.

3. The device of claim 1, wherein the circuitry is configured to perform the error correction operation using the Boser-Chowdhury-Hokungom BCH algorithm.

4. The device of claim 1, wherein the identified memory cell that cannot store data has an associated short circuit or data line leakage or a combination of both.

5. A method of operating a memory, comprising: Performing bipolar sensing operation on a group of self-selected memory cells includes: A first sensing operation is performed on a group of self-selected memory cells using a first voltage, the group of self-selected memory cells including words for sensing data from the group of self-selected memory cells; and After the first sensing operation, a second sensing operation is performed on the group of the self-selected memory cells using a second voltage having the opposite polarity to the first voltage to identify memory cells in the group that cannot store data. Mark the bit in the word corresponding to the identified memory cell in the group as erased; and Error correction is performed on the data sensed from the group of the self-selected memory cells using the orientation of the bit marked as erased in the word.

6. The method of claim 5, wherein the magnitude of the second voltage is less than the magnitude of the first voltage.

7. The method of claim 5, wherein the second sensing operation is performed to detect a short circuit associated with the identified memory cell of the group.

8. The method of claim 5, further comprising performing the first sensing operation and the second sensing operation using the same sensing circuitry system.

9. An apparatus for error detection and correction in a memory, comprising: A memory, which is a group of self-selected memory cells; and The circuit system is configured as follows: Perform a bipolar sensing operation on the group of the self-selected memory cells to: Sensing data from the group of the selected memory cells; and Identify memory cells in the group that cannot store data; The data sensed from the identified memory cells of the group will be marked as erased; and In the event that the data sensed from the identified memory cells of the group is marked as erased, an error correction operation is performed on the data sensed from the group of the selected memory cells.

10. The device of claim 9, wherein the circuitry is configured to perform the bipolar sensing operation by detecting a sudden return of the self-selected memory cell by activating a sensing amplifier with a check signal.

11. The device of claim 9, wherein the circuitry is configured to identify memory cells in the group that cannot store data based on binary data from a check state latch.

12. The device according to any one of claims 9 to 11, wherein the circuitry is configured to identify the location of the memory cells in the memory in which data cannot be stored within the group.

13. The device according to any one of claims 9 to 11, wherein the circuitry is configured to perform the bipolar sensing operation by: Ground the access lines that are group-coupled to the self-selected memory cells; and The access line is charged after it has been grounded.

14. The device according to any one of claims 9 to 11, wherein the circuit system is configured to: The data sensed from the group of the self-selected memory cells is marked as a first standard data state; and The data sensed from the identified memory cells in the group that cannot store data is marked as a second data state.

15. A method of operating a memory, comprising: Perform bipolar sensing on a group of self-selected memory cells to identify memory cells in the group that cannot store data; The data sensed from the identified memory cells of the group will be marked as erased; and In the event that the data sensed from the identified memory cell is marked as erased, an error correction operation is performed on the data sensed from the group of the selected memory cells.

16. The method of claim 15, wherein performing the bipolar sensing operation comprises performing two consecutive reads of the group of the self-selected memory cells in opposite polarities.

17. The method of claim 16, further comprising identifying memory cells that are sensed to be in the same data state in the two consecutive reads as memory cells that cannot store data.

18. The method of claim 16, wherein performing the bipolar sensing operation comprises: The first of the two consecutive reads is performed using a first voltage; and The second read of the two consecutive reads is performed using a second voltage that has the opposite polarity to the first voltage and whose magnitude is less than that of the first voltage.

19. The method of claim 15, wherein the bipolar sensing operation detects a short circuit associated with the identified memory cell of the group.

20. The method of claim 15, further comprising performing additional sensing operations before or after performing the bipolar sensing operation to identify memory cells in the group that cannot store data.

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