Methods of manufacturing microelectronic devices and related microelectronic devices, tools, and apparatuses

Abstract

A method for manufacturing a microelectronic device, along with related microelectronic devices, tools, and apparatus, is disclosed. The microelectronic device may have side surfaces, each side surface comprising a first portion and a second portion. The first portion may have a highly irregular surface configuration extending from an adjacent surface of the microelectronic device. The second portion may have a less pronounced surface irregularity extending from the first portion to an opposing surface of the microelectronic device. The method of forming the microelectronic device may include: generating dislocations in a wafer by implanting ions in a channel between one or more microelectronic devices; and splitting the wafer in response to stress concentration faults near the dislocations by applying heat, tension, or a combination thereof. Related packaging and methods are also disclosed.

Description

[0001] Priority requirements

[0002] This application claims the benefit of U.S. Patent Application No. 17 / 241,386, filed April 27, 2021, entitled “METHOD OF FABRICATING MICROELECTRONIC DEVICES AND RELATED MICROELECTRONIC DEVICES, TOOLS, AND APPARATUS,” the disclosure of which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a method of manufacturing a microelectronic device. Specifically, embodiments relate to a method of separating a wafer comprising an array of microelectronic device locations into individual microelectronic devices, as well as related microelectronic devices, tools, and apparatus. Background Technology

[0004] As the performance of electronic devices and systems improves, there is an associated need to enhance the performance of microelectronic components in such systems while maintaining or even reducing the physical dimensions (i.e., length, width, and height) of the microelectronic devices or assemblies. This need is typically, but not exclusively, associated with mobile devices and high-performance devices. To maintain or reduce the footprint and height of component assemblies in the form of microelectronic devices (e.g., semiconductor dies), three-dimensional (3D) assemblies of stacked components equipped with so-called through-silicon vias (TSVs) for vertical electrical (i.e., signal, power, ground / bias) communication between stacked components have become more common. This combines a reduction in component thickness with the use of pre-fabricated dielectric films in the bonding lines (i.e., the spaces between stacked components) to reduce bonding line thickness while increasing bonding line uniformity. Such dielectric films include, for example, so-called non-conductive films (NCFs) and wafer-level base fillers (WLUFs), terms which are often used interchangeably. While effective in reducing the height of 3D microelectronic device assemblies, reducing the thickness of microelectronic devices, such as semiconductor dies, to about 50 μm or less (e.g., 30 μm, 20 μm) increases device fragility and susceptibility to cracking under stress, specifically compressive (i.e., impact) and bending stresses. Reducing the thickness of the bonding wires can also exacerbate the vulnerability of such extremely thin microelectronic devices because, when, for example, the devices are stacked on top of another device to form a 3D assembly, the thin dielectric material (e.g., NCF) in the bonding wires may no longer provide any cushioning effect or the ability to contain particulate contaminants in the bonding wires. Non-limiting examples of microelectronic device assemblies containing stacked microelectronic devices that may suffer stress-induced cracking include assemblies of semiconductor memory dies, either alone or in combination with other die functions (e.g., logic), including so-called high-bandwidth memory (HBMx), hybrid memory cubes (HMC), and chip-to-wafer (C2W) assemblies.

[0005] Furthermore, the increasing demand for microelectronic devices has led to a greater demand for low-cost microelectronic devices, thereby driving a continuous increase in circuit density and devices per wafer. The cost of manufacturing microelectronic devices can be reduced by increasing process efficiency, increasing the yield of microelectronic devices per wafer per corresponding process, and reducing losses (e.g., attributable to circuit failures, physical die cracking, microcracks, and fissures). Reducing the cost of microelectronic devices can in turn reduce the cost of associated electronic assemblies and systems. In some cases, reducing the cost of microelectronic devices can also achieve increased performance of associated electronic devices without excessive cost. Summary of the Invention

[0006] Embodiments of this disclosure may include a microelectronic device. The microelectronic device may include a semiconductor material, an active surface, and a rear surface opposite the active surface. The microelectronic device may further include a side surface of the semiconductor material extending between the active surface and the rear surface. The side surface may include a first portion having a highly irregular surface configuration extending from one of the active surface and the rear surface of the microelectronic device by a distance between about 2 μm and about 6 μm. The side surface may further include a second portion extending from the first portion to the other of the active surface and the rear surface, having a less pronounced degree of surface irregularity.

[0007] Another embodiment of this disclosure may include a microelectronic package. The microelectronic package may include one or more microelectronic devices. Each microelectronic device may include a side surface of semiconductor material. The side surface may include a first portion having a highly irregular surface configuration, extending from a neighboring main surface of the microelectronic device at a distance between approximately 2 μm and approximately 6 μm. The side surface may further include a second portion adjacent to the first portion and having a less pronounced surface irregularity.

[0008] Another embodiment of this disclosure may include a method of manufacturing a microelectronic device. The method may include forming the microelectronic device on an active surface of a wafer. The method may further include securing the wafer to a carrier wafer. The method may also include implanting ions to induce dislocations in the semiconductor material of the wafer along channels between the microelectronic devices. The method may further include thinning the wafer to about 30 micrometers (μm) or less. The method may also include heating the wafer to form cracks along the channels from stress concentrations near the dislocations.

[0009] Another embodiment of this disclosure may include a method for separating microelectronic devices from a wafer. The method may include using an ion implantation process to induce dislocations in a semiconductor wafer within a passageway between the microelectronic devices. The method may further include transferring the semiconductor wafer to a laterally expandable carrier material and adhering the semiconductor wafer to the surface of the carrier material. The method may also include applying tension to the wafer through the expansion of the carrier material to create cracks in the passageway between the microelectronic devices and separate the microelectronic devices. Attached Figure Description

[0010] Although this specification is concluded with claims that precisely point out and clearly assert embodiments of the present disclosure, the advantages of the embodiments of the present disclosure may be more readily apparent from the following description of the embodiments of the present disclosure when read in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A schematic diagram illustrating a microelectronic device assembly including stacked semiconductor dies;

[0012] Figure 2 A perspective view illustrating a wafer having a microelectronic device position array formed thereon;

[0013] Figures 3 to 8 A cross-sectional view illustrating the process of forming a microelectronic device according to an embodiment of the present disclosure;

[0014] Figure 9 A plan view illustrating the side surface of a microelectronic device according to an embodiment of the present disclosure;

[0015] Figure 10 A side view illustrating the side surface of a microelectronic device according to an embodiment of the present disclosure;

[0016] Figure 11 A top view illustrating a microelectronic device according to an embodiment of the present disclosure; and

[0017] Figure 12 A schematic side view illustrating a microelectronic device package including a stack of microelectronic devices according to an embodiment of the present disclosure. Detailed Implementation

[0018] The illustrations presented herein are not intended to be actual views of any particular microelectronic device, assembly, or component thereof, but are merely idealized representations used to describe illustrative embodiments. The illustrations are not necessarily to scale.

[0019] As used herein, the term “substantially” with respect to a given parameter means and includes the degree to which a given parameter, characteristic, or condition is satisfied with small variability (e.g., within acceptable manufacturing tolerances) as would be understood by one of ordinary skill in the art. For example, a parameter that is substantially satisfied may be satisfied with at least about 90%, at least about 95%, at least about 99%, or even at least about 100%.

[0020] As used herein, relational terms such as “first,” “second,” “top,” “bottom,” etc., are used to clearly and conveniently understand this disclosure and the accompanying drawings, without implying or depending on any particular preference, orientation, or order, unless the context clearly indicates otherwise.

[0021] As used in this document, the term “and / or” means and includes any and all combinations of one or more of the associated listed items.

[0022] As used in this article, the terms “vertical,” “horizontal,” and “lateral” refer to the orientation depicted in the figure.

[0023] As the demand for microelectronic components increases, so does the demand for lower-cost microelectronic components. The cost of manufacturing microelectronic devices can be reduced by increasing the yield of the microelectronic device at each step of the manufacturing process. Yield can be increased by reducing losses (e.g., faulty devices, broken devices, etc.). Another way to increase yield is by reducing the area of ​​the semiconductor wafer required between adjacent microelectronic device locations. For example, reducing the width of the so-called “aisle” or “scribe” area between adjacent individual microelectronic device locations (where a semiconductor wafer is individually diced or cut to separate the wafer into individual microelectronic devices) increases the area of ​​the semiconductor wafer available for forming the microelectronic device. Therefore, reducing the aisle width between individual microelectronic devices allows for the formation of a larger number of microelectronic devices from each semiconductor wafer.

[0024] Figure 1 Microelectronic device 100 is described. Microelectronic device assembly 100 may include a plurality of semiconductor dies 102 arranged in a stack. Dielectric films 104, such as non-conductive film (NCF) or wafer-level base adhesive (WLUF), may be positioned in so-called bonding lines between each of the semiconductor dies 102. Microelectronic device 100 may include through-silicon vias (TSVs) 106 aligned with contacts in the form of conductive posts 108p, the conductive posts optionally capped with solder 108s and bonded to terminal pads 108t adjacent to the semiconductor dies 102, thereby providing electrical contacts between and / or through the die stack of semiconductor dies 102. For example, TSV 106 and aligned contacts may provide power, ground / bias, and signal connectivity.

[0025] The height of the microelectronic device 100 can be reduced by decreasing the thickness of the semiconductor die 102 and / or the dielectric film 104. Reducing the thickness of the semiconductor die 102 may make it more brittle and susceptible to damage in the form of microcracks, fissures, and edge chipping during pick-up and stacking processes, as described in further detail below. Reducing the thickness of the dielectric film 104 reduces its ability to provide any buffering effect between adjacent semiconductor dies 102 during stacking, and its ability to accommodate particulate contaminants generated during separation of the semiconductor dies 102 in bonding lines thinner than the grain size without damaging the semiconductor dies 102. For example, contaminant particles between semiconductor dies 102 may cause one or more of the semiconductor dies 102 to develop cracks or microcracks due to stress concentration caused by the presence of contaminant particles larger than the thickness of the dielectric film 104 when picking up the semiconductor die 102 from the carrier, transferring it to the bonding end, or stacking it on another semiconductor die 102 or substrate. Furthermore, in some cases, contaminant particles between semiconductor dies 102 can substantially prevent one or more of the conductive posts 108p from making electrical contact with the aligned termination pads 108t, or impair the integrity of such contact.

[0026] Reducing and / or eliminating the introduction of contaminant particles onto the surface of semiconductor wafers during the single-stage process can increase the yield of microelectronic devices by significantly reducing losses caused by damage from such particles. Increased microelectronic device yield can reduce the costs associated with manufacturing microelectronic devices. These cost reductions can similarly reduce the cost of associated electronic products containing microelectronic devices (e.g., mobile phones, computers, laptops, etc.).

[0027] Some embodiments of this disclosure may include a method of manufacturing a microelectronic device, comprising forming an array of microelectronic device sites on an active surface of a wafer. The method may further include securing the wafer to a carrier wafer. The method may also include thinning the wafer to about 30 micrometers (μm) or less. The method may further include implanting ions to induce dislocations in the semiconductor material of the wafer along channels between the microelectronic devices. The method may also include heating the wafer to form cracks along the channels from stress concentrations near the dislocations.

[0028] During the manufacturing process, semiconductor dies can be formed on a wafer in an array. Individual dies 204 can be formed on the active surface 208 of the wafer 202. The wafer 202 can be formed from a semiconductor material such as silicon, and is configured to provide a substrate for manufacturing integrated circuits and structural support for the dies 204. The dies 204 can be formed by accumulating layers of insulating and conductive materials on the active surface 208 of the wafer 202 via processes such as plating, sputtering, etc. The process of forming the dies 204 may also include material removal processes, such as wet etching, dry etching, photolithography, etc. The material removal and / or accumulation processes can utilize masks to control the location of the removed and / or accumulated materials. The accumulation and removal processes can form features of microelectronic devices, such as through-silicon vias (TSVs), wiring paths, under-bump metallization (UBM), etc.

[0029] Each die 204 can be separated from its neighboring dies 204 via a channel 206. The width of the channel 206 defines the distance between the dies 204. When using a conventional dicing process, reducing the width of the channel 206 can be limited by the width required of the tools (e.g., wafer saws, laser beams, etc.) used to dic (e.g., cut, slice, separate) the wafer 202 into individual dies 204. Depending on the blade width, conventional blade cutting operations may require a channel 206 width between approximately 20 micrometers (μm) and approximately 80 μm, or even greater. Therefore, a significant portion of the surface of the wafer 202 must be dedicated to the area of ​​the channel 206 between the dies 204. Reducing the width of the channel 206 allows for the formation of a larger number of dies 204 on each wafer 202, which increases the yield per wafer 202.

[0030] After the bare die 204 is formed on the active surface 208 of the wafer 202, the wafer 202 can be coupled to the carrier wafer 304 through the adhesive 306, such as Figure 3 As described herein, adhesive 306 couples the active surface 208 of wafer 202 to the carrier wafer 304, thereby keeping the rear surface 302 of wafer 202 exposed. Adhesive 306 may be an adhesive material configured to bond wafer 202 at high temperatures above ambient (e.g., about 25°C), such as temperatures between about 150°C and about 250°C, for example between about 170°C and about 220°C, or between about 180°C and about 200°C. Some examples of adhesives formulated to bond wafers at high temperatures may include those from BREWER, Missouri. For Sale Materials, from Taiwan TA series adhesives for sale, or by DOW in Michigan. XP series adhesives are available for sale. The carrier wafer 304 can be configured to support the wafer 202 via additional prior processing actions (such as wafer thinning). For example, an extremely thin wafer 202 may require extra-rigid supports to substantially prevent the wafer 202 from cracking, warping, and other potential damage to the wafer during processing actions that may include temperature changes, mechanical material removal, chemical material removal, etc.

[0031] Once the wafer 202 adheres to the carrier wafer 304, the wafer 202 can be thinned, such as... Figure 4 As described herein, wafer 202 may be thinned from an initial thickness (e.g., between approximately 775 μm and approximately 600 μm) via a material removal process (e.g., back-side grinding, polishing, and wet etching). The material removal process may remove material from the exposed rear surface 302 of wafer 202. In some embodiments, a later portion of the material removal process (i.e., wet etching) may be used to remove sufficient semiconductor material to expose features, such as TSVs through the rear surface 302 of wafer 202, thereby forming an electrical connection between the rear surface 302 and the integrated circuit of the active surface 208 of wafer 202.

[0032] The material removal process can thin the wafer 202 to less than about 50 μm, for example, less than about 30 μm, less than about 20 μm, or less than about 10 μm. Reducing the thickness of the wafer 202 can further reduce the thickness of the resulting microelectronic device. For example, the thickness of the resulting microelectronic device can be between about 30 μm and about 8 μm, for example, between about 20 μm and about 7 to 10 μm. In the latter case, the microelectronic device can include an integrated circuit with a depth of about 5 μm to 8 μm and a supporting semiconductor material thickness of about 2 μm. During the processing of the wafer 202, one or more implantation (i.e., dopant) materials can be implanted into the channels 206 between the bare dies 204 during the implantation process, such as... Figure 5 As explained in the text. Figure 5 Explanation in Figure 4 The implantation process occurs on the rear surface 302 of wafer 202 after the thinning process described herein; however, it should be noted that the implantation process may be performed at an earlier stage and / or on the active surface 208 of wafer 202, as will be described in detail below.

[0033] During implantation, ions of the implanted material (e.g., hydrogen, helium, arsenic, boron, phosphorus, etc.) can be accelerated toward the surface of wafer 202. Implantation tool 506 may include beam generator 508 configured to accelerate ions and form an energy beam 512 of ions to impact the surface of wafer 202. Beam generator 508 can receive ions of the corresponding material from an ion source. The ions can then be accelerated to high energies via an electrostatic accelerator (e.g., a magnet or a magnetic field). After acceleration, the ions may have an energy of at least about 10 keV, for example at least about 100 keV, or at least about 250 keV. The implantation tool 506 of this disclosure can be configured to implant ions into wafer 202 without the aid of increased temperature (commonly referred to as temperature-driven in this art). Preventing the temperature from rising above ambient levels (e.g., approximately 25°C) allows the implantation process to be performed after the die 204 has been formed, without compromising the thermal budget of the die 204 or causing damage to the associated features of the integrated circuit and the die 204. Furthermore, not increasing the temperature allows the implantation process to be performed on the wafer 202 after the thinning process, without the risk of warping or otherwise damaging the wafer under excessive heat.

[0034] The energy imparted to the ions during implantation can affect the depth to which the ions penetrate into wafer 202. For example, ions with higher energy can penetrate wafer 202 to a greater depth than ions of the same material with lower energy. The ionic material itself can also affect the penetration depth of the ions. For example, ions of smaller molecules (e.g., hydrogen or helium) can have a greater penetration depth than ions of larger molecules (e.g., boron, phosphorus, or arsenic). In some embodiments, multiple different implantation materials can be used on the same wafer 202, allowing multiple different penetration depths to be achieved in the same region of wafer 202. The penetration of ions from the implantation material into the semiconductor material of wafer 202 can cause damage to wafer 202 at and / or along the path to the penetration depth, such as point defects, dislocations, etc. During the implantation process, ions can penetrate to a depth of at least about 2 μm, for example, at least about 3 μm or at least about 4 μm. Smaller ionic materials can penetrate to a greater depth, for example, at least about 4 μm, and can cause a smaller amount of damage during penetration. On the other hand, while larger ionic materials may not be able to penetrate the wafer to the same depth as smaller materials, they can cause greater damage at a smaller depth. In one embodiment, hydrogen or helium ions can be implanted first to the final implantation depth, after which boron, phosphorus, or arsenic ions can be implanted above the hydrogen or helium molecules to a depth smaller than that of the hydrogen or helium molecules.

[0035] Mask 502 may be positioned between implantation tool 506 and wafer 202. Mask 502 may be configured to control and limit the portion of wafer 202 subjected to ion impact. For example, mask 502 may include a pattern of openings 504. Openings 504 may be arranged such that ions impact only the portion of the surface of wafer 202 that overlaps with the passageway 206 between the wafer 202 and the bare die 204.

[0036] In some embodiments, mask 502 may be positioned above wafer 202, for example, via a mask aligner or stepper. For instance, mask 502 may be aligned with the back surface 302 of wafer 202, such as... Figure 5 As described herein, the opening 504 in the mask 502 is substantially aligned with the channel 206 on the active surface 208 of the wafer 202. In some embodiments, relative to Figure 2 During the die fabrication process described above, a mask 502 may be formed on the active surface 208 of the wafer 202. For example, the mask 502 may be positioned or formed on the active surface 208 of the wafer 202, and ions may be implanted into the channels 206 between the dies 204 using an implantation tool 506 after the die 204 is formed and before the active surface 208 of the wafer 202 is coupled to the carrier wafer 304. In some embodiments, the mask 502 may be as described above regarding... Figure 2One of the masks used in the material addition or removal process discussed. Implantation tool 506 can then implant ions into the active surface 208 of wafer 202 during, before or after, one of the material accumulation or removal processes.

[0037] In some embodiments, a material removal process, such as dry etching, can be used to remove material from channel 206 and form trenches or channels in the region of channel 206 prior to the implantation process. Removing material from channel 206 prior to the implantation process allows implanted ions to penetrate a greater distance from the active surface 208 into the wafer 202 before the material removal process. In some embodiments, the material removal process and the implantation process may utilize the same mask 502.

[0038] In some embodiments, mask 502 may be coupled to implantation tool 506. For example, mask 502 may be a reusable mask configured for coupling to a specific die type (i.e., length and width) of facet 510 of implantation tool 506, or it may be mounted inside a tool chamber. Implantation tool 506 may then be substantially aligned with wafer 202 such that openings 504 in mask 502 are substantially aligned with passageways 206. Implantation tool 506 may then implant ions into active surface 208 and / or back surface 302 of wafer 202 via openings 504 in mask 502.

[0039] The width of the opening 504 in the mask 502 may correspond to the desired spacing of the passageway between the positions of the bare die 204, which is less than about 10 μm, for example, between about 1 μm and about 10 μm, or between about 1 μm and about 5 μm, or between about 1 μm and about 2 μm.

[0040] Figure 6 illustrate Figure 4 The thinning process and Figure 5 The wafer 202 after the implantation process. After the implantation process, the wafer 202 may include an implantation region 602. The implantation region 602 may contain molecules of implanted material as well as dislocations and point defects associated with the implantation process. As a result of implanting the wafer 202 via a mask 502, the implantation region 602 may substantially coincide with an opening 504 in the mask 502. Therefore, the implantation region 602 may substantially coincide with a passage 206 between the bare wafers 204. The implantation region 602 may contain an implanted material concentration between approximately 1e12 atoms / cm³ and approximately 10e16 atoms / cm³, for example, between approximately 1e12 atoms / cm³ and approximately 5e16 atoms / cm³.

[0041] A higher concentration of implanted ionic material can lead to greater damage to the wafer 202 in the implantation region 602. Since the implantation region 602 may overlap with the channel 206 between the bare die 204, the damage to the wafer 202 can be largely concentrated within the channel 206. As noted above, the size of the opening 504 in the mask 502 can be set such that the implantation region 602 can have a width 604 of less than about 10 μm, for example, between about 1 μm and about 5 μm or between about 1 μm and about 2 μm.

[0042] The implantation region 602 may have a significant amount of damaged and residual implanted ions near the active surface 208 or the back surface 302 of the wafer 202, which are implanted into the active surface or back surface by the implantation tool 506. The damaged and / or residual implanted ions may gradually decrease with increasing depth into the wafer 202.

[0043] In some embodiments, such as Figure 7 As described, wafer 202 can be heated when coupled to carrier wafer 304. Heating wafer 202 can cause it to fracture within implantation region 602. For example, damage caused by implanted ions in implantation region 602 may create stress concentration within wafer 202. When wafer 202 is heated, stress concentration in implantation region 602 can cause crack 702 to propagate through the thickness of wafer 202 in a region substantially aligned with implantation region 602 and to split the semiconductor material along the region of via 206. Crack 702 can substantially separate (e.g., isolate) wafer 202 into individual dies 204. Heating wafer 202 above ambient temperature (e.g., about 25°C) can cause the temperature of wafer 202 to rise to between about 150°C and about 250°C, for example, between about 170°C and about 220°C, or between about 180°C and about 200°C. Under conditions of high ion concentration and damage in the implantation region 602, relatively low temperature variations can induce cracks 702 and shard 202. Similarly, deeper penetration allows cracks 702 to be induced at lower temperatures. Therefore, implanting ions of smaller material (e.g., hydrogen or helium) allows crack 702 to propagate at lower temperatures, reducing the time and energy required to shard 202 and mitigating the risk of temperature-induced damage to wafer 202 and associated die 204. In embodiments of this example, implanting ions of smaller material, such as hydrogen or helium, may also be necessary given the greater penetration depth achievable at reasonable energy levels compared to larger materials. Additionally, sharding at lower temperatures significantly reduces the impact on the thermal budget of the semiconductor die, thereby reducing any potential degradation of the integrated circuit.

[0044] Heating tools, such as hot plates, hot clamps, lasers, resistance heaters, etc., can be used to heat the wafer 202. For example, the carrier wafer 304 and the wafer 202 can be placed on a hot plate or hot clamp. In some cases, the hot plate or hot clamp can contact the rear surface 302 of the wafer 202. In other embodiments, a laser beam can impinge on the surfaces 208, 302 of the wafer 202, or a resistance heater can be placed very close above the wafer 202 to increase the temperature of the wafer 202. Heating the wafer 202 from above can result in a smaller temperature gradient between the heat source and the implantation area.

[0045] During the heating process, the carrier wafer 304 and adhesive 306 can be combined to support the wafer 202 against any displacement. For example, the carrier wafer 304 allows the wafer 202 to absorb heat after thinning without any significant thermal damage, such as warping or displacement of the semiconductor die 204 after it has been separated from the wafer. Furthermore, separating the semiconductor die 204 on the carrier wafer 304 and picking it up from the carrier wafer after releasing the adhesive 306 eliminates the potential damage to the wafer 202 and semiconductor die 204 caused by transferring it to an expandable carrier material (e.g., dicing tape, mounting tape, or film) for subsequent pick-and-place operations with a pick-up tool, as well as the potential damage from peeling the die from the adhesive that holds the semiconductor die 204 to the carrier material. The adhesive 306 can be formulated to release upon exposure to light in the infrared (IR) or ultraviolet (UV) range. Light in the IR or UV range can penetrate the carrier wafer 304, causing the adhesive 306 to release.

[0046] In some embodiments, semiconductor die 204 may be picked up from the surface of carrier wafer 304 using a die stacking tool (e.g., a bonding head) configured to lift semiconductor die 204 from rear surface 302. The die stacking tool may be configured to clean the active surface 208 of semiconductor die 204 to remove any residual adhesive and / or particles from the active surface 208. For example, the die stacking tool may include nozzles for cleaning the active surface 208 of semiconductor die 204. In some embodiments, semiconductor die 204 may be transferred to a cleaning tool, such as a cleaning platform configured to clean residual adhesive from the active surface 208. The die stacking tool may then be configured to couple semiconductor die 204 to other semiconductor dies to form a die stack, as discussed in further detail below.

[0047] Some embodiments of this disclosure may include methods for separating microelectronic devices (e.g., semiconductor dies) from a wafer. The methods may include using an ion implantation process to induce dislocations in the semiconductor wafer within a passageway between the microelectronic devices. The methods may further include transferring the semiconductor wafer to a laterally expandable carrier material and adhering the semiconductor wafer to the surface of the carrier material. The methods may also include applying tension to the wafer through the expansion of the carrier material to create cracks in the passageway between the microelectronic devices and separate the microelectronic devices.

[0048] In some embodiments, such as Figure 8 As described, wafer 202 can be flipped on and transferred to carrier material 802 on carrier wafer 304, for example, by cutting tape or mounting tape or film. To transfer wafer 202 from carrier wafer 304 to carrier material 802, adhesive 306 can be released to release wafer 202 from carrier wafer 304. For example, adhesive 306 can be released by light or laser impacting wafer 202 or carrier wafer 304. In other embodiments, adhesive 306 can be released by other known methods, such as chemical release and / or mechanical release. Carrier material 802 can be secured to and supported by membrane frame 804. Carrier material 802 may contain adhesive 806, which is formulated to secure wafer 202 to carrier material 802. The rear surface 302 of wafer 202 can adhere to carrier material 802 such that the active surface 208 of wafer 202 faces upward and away from carrier material 802.

[0049] The carrier material 802 may be a flexible material that can expand in the XY plane (i.e., laterally). After the wafer 202 is secured to the carrier material 802, the carrier material 802 can be stretched by the membrane frame 804. Stretching the carrier material 802 can apply tension to the wafer 202. Stress concentration around the damaged area in the implantation region 602 can cause the wafer 202 to fracture and split along the implantation region 602 of the channel 206, thereby creating a crack 702 that substantially coincides with the implantation region 602 and / or the channel 206 through the wafer 202. The crack 702 can substantially separate the wafer 202 into individual semiconductor dies 204.

[0050] Significant damage in the implantation region 602 allows for the formation of crack 702 under reduced tension. Therefore, implanting the implantation region 602 with ions from a larger material allows crack 702 to form under lower tension. Reduced tension allows for the use of lighter materials for the carrier material 802 and reduces the amount, thickness, and strength of the adhesive required on the carrier material 802. More options for the carrier material 802 and adhesive reduce manufacturing costs because the carrier material 802 will not have to support stresses induced by conventional blade cutting or heat from laser or stealth cutting. Additionally, the carrier material 802 offers advantages such as chemical resistance, use at lower temperatures, and a thinner adhesive for better fixation of the semiconductor die 204. Suitable carrier materials include those from DuPont Corporation. Polyimide films, and various adhesive films available from NITTOAmericas and LINTEC.

[0051] In some embodiments, the chip 202 may be transmitted via, for example, Figure 7 The heating process described in the document and Figure 8 The stretching process described herein separates the two. For example, wafer 202 can be heated on carrier wafer 304, such as... Figure 7 As described, this allows cracks and fissures 702 to propagate through wafer 202. After cracks 702 form during heating, wafer 202 can be transferred to carrier material 802 and stretched. Stretching wafer 202 can complete any incomplete cracks or fissures 702, for example, in areas where damage and ion concentration are insufficient to completely break through the thickness of wafer 202 at the temperatures used during heating. In some embodiments, significantly lower temperatures can be used on carrier wafer 304 to reduce the risk of temperature-induced damage to wafer 202, allowing the heating process to expand damage and form some cracks 702, wherein... Figure 8 The stretching process can complete any unfinished crack 702.

[0052] In some embodiments, wafer 202 may be heated after transfer to expandable carrier material 802. For example, some types of carrier material 802 may be selected to withstand relatively high temperatures, allowing wafer 202 to be heated while being secured to expandable carrier material 802. In some cases, wafer 202 may then be stretched on expandable carrier material 802 to finish any unfinished cracks 702 before the bare die 204 is picked up from the surface of carrier material 802. In other cases, the bare die 204 may be picked up from the surface of carrier material 802 without further stretching of wafer 202.

[0053] In some embodiments, the chip 202 may be completely isolated via only one of the above processes. For example, it may be isolated via... Figure 7The heating process creates cracks 702, and after the heating process is complete, individual dies 204 can then be picked up from the surface of the carrier wafer 304 or the expandable carrier material 802 for further processing, such as stacking. In some embodiments, the wafer 202 can be transferred to the carrier material 802 without undergoing any heating, and the wafer 202 can then be stretched as described above to separate the wafer 202 into individual dies 204, which can then be picked up from the carrier material 802 for further processing.

[0054] In the method of this embodiment, it can be confirmed by optical inspection from above that the wafer 202 on the carrier wafer 304 has successfully split due to heating. If the wafer 202 splits on the expandable carrier material 802, the carrier material can be illuminated from below, and any unsplit passage area can be optically detected as opaque or partially obscured.

[0055] Some embodiments of this disclosure may include a microelectronic device (e.g., a semiconductor die). The microelectronic device 100 may include an active surface and a rear surface opposite the active surface. The microelectronic device may further include a side surface of semiconductor material extending between the active surface and the rear surface. The side surface may include a first portion having a highly irregular (i.e., serrated) surface configuration. Depending on the embodiment used to separate the microelectronic device 100 from the wafer 202, the highly irregular surface configuration may extend from at least one of the active surface 208 and the rear surface 302 of the microelectronic device by a distance between about 2 μm and about 6 μm. The side surface may further include a second portion extending from the first portion to the other of the active surface and the rear surface, having a less pronounced surface irregularity.

[0056] Figure 9 This diagram illustrates a plan view of the side surface 906 of the semiconductor die 900, isolated using the method described above. The side surface 906 of the semiconductor die 900 may exhibit damage 908 caused by implanted ions. As described above, damage 908 may include dislocations and point defects caused by the impact of individual ions during the implantation process. Damage 908 may be manifested as peaks and valleys in the side surface of the semiconductor die 900 extending at least from the ion implantation surface of the die 900 to the region of maximum material penetration. The side surface 906 may also include fracture lines 910 extending from the serrated or fractured edges of the damage 908. Fracture lines 910 may be the result of cracks 702 formed by heating and / or stretching the wafer 202 as described above.

[0057] The side surface 906 of the semiconductor die 900 may also contain residual ions 912 embedded within the side surface 906, such that the residual ions 912 from the side surface 906, and possibly not on the outer portion of the side surface 906 connected to the break line 910, can be detected, for example, via secondary ion mass spectrometry (SIMS) or energy-dispersive X-ray spectroscopy (ERX). Some portions of the damage 908 and / or residual ions 912 may be larger than others. For example, as described above, some of the ionic materials may be larger, such as boron, phosphorus, and arsenic, while some may be smaller, such as hydrogen. In some embodiments, the implantation process may use a variety of different ionic materials to achieve damage at different depths. Larger damage 908 and / or residual ions 912 may be closer to the first surface 902 than smaller damage 908 and / or residual ions 912. The first surface 902 may be the surface adjacent to and transverse to the implanted ions on the side surface 906.

[0058] In some embodiments, only one substance may be used. Some of the ions may travel a longer distance into the wafer, while others may experience earlier collisions and stop closer to the first surface 902. Ions that travel further into the wafer may experience collisions as they pass through wafer regions closer to the first surface 902. Thus, a larger amount of damage 908 and / or a larger number of residual ions 912 may remain closer to the first surface 902, wherein the amount and / or number of damage to residual ions 912 gradually decreases with increasing distance from the first surface 902. Such a method can produce a wedge effect, thereby enhancing the likelihood of splitting at lower temperatures, lower tensile stresses, or both.

[0059] Damage 908 and / or residual ions 912 can extend to a distance between about 1 μm and about 6 μm from the first surface 902, for example, between about 2 μm and about 5 μm, or between about 2 μm and about 4 μm.

[0060] As described above, ions can be implanted into the active surface 208 or the back surface 302 of wafer 202. Therefore, in some embodiments, the first surface 902 may coincide with the active surface 208 of wafer 202 and the associated semiconductor die 900. In other embodiments, the first surface 902 may coincide with the back surface 302 of wafer 202 and the associated semiconductor die 900. A second surface 904 on the opposite side of the semiconductor die 900 may be the active surface 208 or the back surface 302 opposite to the first surface 902 of wafer 202 and the associated semiconductor die 900. Figure 4 After the thinning process described herein, the distance between the first surface 902 and the second surface 904 can be substantially the same as the final thickness of the associated wafer 202. Therefore, the distance between the first surface 902 and the second surface 904 can be less than about 30 μm, for example less than about 20 μm, or less than about 10 μm.

[0061] Figure 10 A side view illustrating the side surface 906 of the semiconductor die 900 is shown. The presence of the side surface 906 in the damaged portion of the damaged 908 can exhibit a highly irregular configuration 1002, characterized by sharp edges, protrusions, and recesses surrounding the point of damage 908, where ions collide with the wafer material upon implantation into the first surface 902 of the wafer 202. Therefore, the irregular configuration 1002 can begin near the first surface 902 of the semiconductor die 900 and extend toward the second surface 904. The highly irregular configuration 1002 can extend from the first surface 902 by a distance between approximately 1 μm and approximately 6 μm, for example, between approximately 2 μm and approximately 5 μm, or between approximately 2 μm and approximately 4 μm.

[0062] The remainder of the side surface 906 may be a slightly irregular but less pronounced uneven surface 1004, characterized by a flat surface interspersed with break lines 910. The uneven surface 1004 may extend from the highly irregular configuration 1002 to the second surface 904.

[0063] As described above, residual ions 912 can also be embedded in the semiconductor die 900 to a depth below the side surface 906 of the die semiconductor 900. The residual ions 912 can be located in the semiconductor die 900 in a region substantially the same as the highly irregular configuration 1002 and laterally adjacent to the highly irregular configuration 1002.

[0064] Figure 11 This illustration shows a top view of a semiconductor die 900. The semiconductor die 900 may include an active region 1106 in which an integrated circuit and associated features of the semiconductor die 900 may be formed. The active region 1106 of the semiconductor die 900 may be substantially surrounded by a barrier layer 1104 extending downward from the surface containing the active region 1106 into a semiconductor material of the die 900, and configured to separate the active region 1106 from a side surface 906 that may form the outer perimeter of the semiconductor die 900. The barrier layer 1104 may be formed of a material selected to substantially prevent the diffusion of other materials (e.g., ions from the implantation process) into the peripheral region of the active region 1106 carrying the integrated circuit. The barrier layer 1104 may be formed of materials such as tungsten, titanium, cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, titanium nitride, etc. In some embodiments, the barrier layer 1104 may also be configured to mechanically protect the active region 1106 such that any resulting cracks on the side surface 906 do not propagate into the active region 1106 when the wafer is being spun.

[0065] Side surface 906 may contain residual ions 912 embedded during the implantation process. Active region 1106 may be substantially free of residual ions 912. As described above, the implantation process may include a mask 502 configured to substantially control the direction of implanted ions to a position coinciding with channel 206. Furthermore, as noted above, barrier layer 1104 may be configured to substantially prevent any erroneous ions from entering active region 1106 from semiconductor material adjacent to side surface 906.

[0066] Some embodiments of this disclosure may include a microelectronic package. The microelectronic package may include one or more microelectronic devices. Each microelectronic device may include a side surface of semiconductor material. The side surface may include a first portion having a highly irregular configuration. The highly irregular configuration may extend to a distance between approximately 2 μm and approximately 6 μm from a neighboring main surface of the microelectronic device. The side surface may further include a second portion adjacent to the first portion and having a less pronounced surface irregularity.

[0067] Figure 12 This describes a microelectronic device 1200 formed by a stack of semiconductor dies 1202. The sides of the stack of semiconductor dies 1202 can be characterized by a pattern of alternating highly irregular surface configurations 1208 and uneven surfaces 1204. As shown, the semiconductor dies 1202 are fabricated by implanting a wafer from the back surface 302 of a wafer 202, thereby creating a highly irregular surface configuration 1208 on the upper portion of the side surface of the substrate 1206 of the semiconductor die 1202.

[0068] Semiconductor dies 1202 may be stacked on a substrate 1206 configured to electrically couple the stack of dies 1202 to another component. The substrate 1206 may include discrete connection elements configured to connect to higher-level packages in the form of solder bumps 1210. The substrate 1206 may be electrically coupled to the stack of dies 1202, for example, via a TSV (not shown) formed through each semiconductor die 1202. Similarly, each semiconductor die 1202 may be electrically coupled to an adjacent die 1202 via a TSV and conductive elements extending through a bonding line between adjacent semiconductor dies 1202 in the stack. For example, conductive (e.g., copper) pillars may be connected to aligned termination pads of adjacent semiconductor dies via solder reflow or diffusion bonding to operatively couple the TSVs of adjacent dies 1202.

[0069] Embodiments of this disclosure reduce the width of the passageways between die locations on the wafer because a much smaller area is needed to perform the dicing operation to divide the wafer into individual dies. Reducing the width of the passageways between die locations on the wafer allows for the fabrication of a larger number of dies from a single wafer of semiconductor material.

[0070] Furthermore, embodiments of this disclosure can significantly reduce organic (e.g., polymer film residues, adhesive residues) and inorganic (e.g., semiconductor material) contaminant particles generated during the process of dicing or sizing individual semiconductor dies from a wafer. As previously mentioned, residual contaminant particles on individual semiconductor dies can cause damage and / or malfunction in associated microelectronic devices. Therefore, reducing the volume of contaminant particles generated during the dicing or sizing process can similarly reduce the likelihood of damage or malfunction to the dies and associated microelectronic devices. Reducing the number of damaged or malfunctioning dies or microelectronic devices and reducing the space required between individual dies on each wafer can increase the yield and reliability of semiconductor dies and microelectronic devices containing such dies.

[0071] Increasing the yield of microelectronic devices by reducing the number of damaged semiconductor dies or their assemblies and packages can increase the yield of such assemblies and packages, thereby generating greater benefits due to the reduced costs of producing the associated microelectronic devices. These microelectronic devices can be incorporated into a variety of different types of electronic devices, such as personal electronics (e.g., mobile devices, telephones, tablets, etc.), computers (e.g., personal computers, laptops, etc.). Reducing the cost of producing microelectronic devices can, in turn, reduce the cost of producing associated electronic devices.

[0072] Non-limiting example embodiments may include:

[0073] Example 1: A microelectronic device comprising: a semiconductor material including an active surface and a rear surface opposite to the active surface; a side surface of the semiconductor material extending between the active surface and the rear surface, and comprising: a first portion having a highly irregular surface configuration extending from one of the active surface and the rear surface of the microelectronic device by a distance between about 2 μm and about 6 μm; and a second portion extending from the first portion to the other of the active surface and the rear surface, having a less uneven surface.

[0074] Example 2: The microelectronic device according to Example 1 further includes an active region, the active region including an integrated circuit that is laterally recessed from the side surface above the active surface.

[0075] Example 3: The microelectronic device according to Example 2 further includes a barrier layer region located on the periphery between the active region and the side surface.

[0076] Example 4: The microelectronic device according to Example 3, wherein the barrier layer region is formed of a material selected to substantially prevent the diffusion of a material different from the semiconductor material into the active region.

[0077] Example 5: A microelectronic device according to any one of Examples 3 or 4, wherein the barrier layer region is formed of a material selected from the group consisting of: tungsten, titanium, cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, and titanium nitride.

[0078] Example 6: The microelectronic device according to any one of Examples 2 to 5 further includes residual implanted ions adjacent to the first portion of the side surface.

[0079] Example 7: The microelectronic device according to Example 6, wherein the residual implanted ions include one or more of boron, phosphorus, arsenic, helium and hydrogen.

[0080] Example 8: The microelectronic device according to Example 7, wherein the residual implanted ions include one of hydrogen or helium from the active surface or the rear surface at a depth adjacent to the first portion and one of boron, phosphorus or arsenic from the same surface as the hydrogen at a smaller depth adjacent to the first portion.

[0081] Example 9: A microelectronic device according to any one of Examples 1 to 8, wherein the highly irregular surface configuration includes point damage caused by the ion implantation process.

[0082] Example 10: A microelectronic device according to any one of Examples 1 to 9, wherein the less severe uneven surface includes a flat surface interspersed with break lines.

[0083] Example 11: A microelectronic device according to any one of Examples 1 to 10, wherein the distance between the active surface and the rear surface is less than about 30 micrometers (μm).

[0084] Example 12: A microelectronic package comprising: one or more microelectronic devices, each comprising: a side surface of semiconductor material, and including: a first portion having a highly irregular surface configuration extending from a neighboring main surface of the microelectronic device by a distance between about 2 μm and about 6 μm; and a second portion adjacent to the first portion and having a less uneven surface.

[0085] Example 13: The microelectronic package according to Example 12, wherein the highly irregular surface configuration exhibits point damage in response to the ion implantation process.

[0086] Example 14: A microelectronic package according to any of Examples 12 or 13, wherein the less severe uneven surface comprises a flat surface interspersed with break lines.

[0087] Example 15: A microelectronic package according to any of Examples 12 to 14, wherein the highly irregular surface configuration is a portion of the semiconductor material adjacent to implanted ions comprising one or more of hydrogen, helium, boron, phosphorus and arsenic.

[0088] Example 16: A method of manufacturing a microelectronic device, the method comprising: forming the microelectronic device on an active surface of a wafer; securing the wafer to a carrier wafer; implanting ions to induce dislocations in a semiconductor material of the wafer along a channel between the microelectronic devices; thinning the wafer to about 30 micrometers (μm) or less; and heating the wafer to form cracks along the channel from stress concentrations near the dislocations.

[0089] Example 17: The method according to Example 16, wherein implanted ions include implanted ions via a mask having an opening substantially aligned with the passage between the microelectronic device.

[0090] Example 18: The method according to Example 17, wherein the mask comprises the same mask as the mask used to manufacture the features of the microelectronic device.

[0091] Example 19: The method according to any of Examples 17 or 18, wherein the mask includes a reusable mask coupled to a face of the implantation tool or within a cavity of the implantation tool.

[0092] Example 20: The method according to any one of Examples 16 to 19 includes implanting ions from the active side of the wafer along the channel between the microelectronic devices.

[0093] Example 21: The method according to any one of Examples 16 to 20 includes implanting ions from the rear side of the wafer along the passage between the microelectronic devices.

[0094] Example 22: The method according to any of Examples 16 to 21, wherein initiating a dislocation in the wafer includes initiating a dislocation from the active surface or back surface of the wafer to a depth between about 1 μm and about 6 μm.

[0095] Example 23: The method according to any of Examples 16 to 22, wherein heating the wafer includes raising the temperature of the wafer above the ambient temperature by about 150°F to about 250°F.

[0096] Example 24: The method according to any of Examples 16 to 23, wherein the implanted ion comprises one or more of hydrogen, helium, boron, phosphorus and arsenic.

[0097] Example 25: The method according to Example 24 further includes implanting hydrogen or helium ions from the active or rear surface of the wafer to a greater depth than the depth of implantation of boron, phosphorus, or arsenic ions from the same surface.

[0098] Example 26: A method for separating a microelectronic device from a wafer, the method comprising: using an ion implantation process to induce dislocations in a semiconductor wafer in a passageway between the microelectronic devices; transferring the semiconductor wafer to a laterally expandable carrier material and adhering the semiconductor wafer to a surface of the carrier material; and applying tension to the wafer by the expansion of the carrier material to form a crack in the passageway between the microelectronic devices and separate the microelectronic devices.

[0099] Example 27: The method according to Example 26, wherein implanted ions are made into the surface of the semiconductor wafer via a mask having an opening substantially aligned with the passage between the microelectronic device.

[0100] Example 28: The method according to any of Examples 26 or 27, wherein the surface of the semiconductor wafer includes an active surface or a rear surface opposite to the active surface.

[0101] Example 29: The method according to any one of Examples 26 to 28 further includes, before using the ion implantation process: thinning the semiconductor wafer from its rear surface from an initial thickness to a thickness of about 30 μm or less while the semiconductor wafer is supported on and secured to the rigid carrier structure; and after using the implantation process: flipping the carrier structure to transfer and adhere the semiconductor wafer to the laterally expandable carrier material; and releasing the carrier structure from the semiconductor wafer before expanding the carrier material.

[0102] The embodiments of this disclosure described above and illustrated in the accompanying drawings do not limit the scope of the invention, as these embodiments are merely examples of embodiments of the invention, which is defined by the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of this disclosure. In fact, various modifications to this disclosure will become apparent to those skilled in the art, in addition to the alternative applicable combinations of elements described herein, such as those described. Such modifications and embodiments are also intended to be within the scope of the appended claims and their legal equivalents.

Claims

1. A microelectronic device comprising: A semiconductor material comprising an active surface and a rear surface opposite to the active surface; The side surface of the semiconductor material, extending between the active surface and the rear surface, includes: A first portion having a highly irregular surface configuration, the first portion containing residual ions, the highly irregular surface configuration extending from one of the active surface and the rear surface of the microelectronic device by a distance between 2 μm and 6 μm; as well as The second part, which does not contain the residual ions, extends from the first part to the other of the active surface and the rear surface and has a less uneven surface.

2. The microelectronic device of claim 1, further comprising an active region, the active region including an integrated circuit laterally recessed above the active surface from the side surface.

3. The microelectronic device of claim 2, further comprising a barrier layer region located peripherally between the active region and the side surface.

4. The microelectronic device of claim 3, wherein the barrier layer region is formed of a material selected to substantially prevent diffusion of a material different from the semiconductor material into the active region.

5. The microelectronic device of claim 3, wherein the barrier layer region is formed of a material selected from the group consisting of tungsten, titanium, cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, and titanium nitride.

6. The microelectronic device of claim 2, further comprising residual implanted ions adjacent to the first portion of the side surface.

7. The microelectronic device of claim 6, wherein the residual implanted ions comprise one or more of boron, phosphorus, arsenic, helium, and hydrogen.

8. The microelectronic device of claim 7, wherein the residual implanted ions comprise one of hydrogen or helium from the active surface or the rear surface at a depth adjacent to the first portion and one of boron, phosphorus, or arsenic from the same surface as the hydrogen at a smaller depth adjacent to the first portion.

9. The microelectronic device according to any one of claims 1 to 8, wherein the highly irregular surface configuration includes point damage caused by an ion implantation process.

10. The microelectronic device according to any one of claims 1 to 8, wherein the less severe uneven surface comprises a flat surface interspersed with break lines.

11. The microelectronic device according to any one of claims 1 to 8, wherein the distance between the active surface and the rear surface is less than 30 micrometers (μm).

12. A microelectronic package, comprising: One or more microelectronic devices, each comprising: The side surface of the semiconductor material, and includes: A first portion having a highly irregular surface configuration, the first portion comprising one or more point defects and dislocations extending from a distance between 2 μm and 6 μm from a neighboring main surface of the microelectronic device; and The second part, which does not contain the point defects and dislocations, is adjacent to the first part and has a less uneven surface.

13. The microelectronic package of claim 12, wherein the highly irregular surface configuration exhibits point damage in response to the ion implantation process.

14. The microelectronic package of claim 12, wherein the less severe uneven surface comprises a flat surface interspersed with break lines.

15. The microelectronic package according to any one of claims 12 to 14, wherein the highly irregular surface configuration is a portion adjacent to implanted ions of the semiconductor material comprising one or more of hydrogen, helium, boron, phosphorus, and arsenic.

16. A method of manufacturing a microelectronic device, the method comprising: Microelectronic devices are formed on the active surface of a wafer; Secure the wafer to the carrier wafer; Implanted ions are used to induce dislocations in the semiconductor material of the wafer along the passageway between the microelectronic devices, the dislocations extending from one of the active surface and the back surface of the wafer to a distance between 2 μm and 6 μm. The wafer is thinned to 30 micrometers (μm) or less; as well as The wafer is heated to form a crack along the channel from the stress concentration near the dislocation.

17. The method of claim 16, wherein implanting ions comprises implanting ions via a mask having an opening substantially aligned with the passageway between the microelectronic device.

18. The method of claim 17, wherein the mask comprises the same mask as the mask used for manufacturing features of the microelectronic device.

19. The method of claim 17, wherein the mask comprises a reusable mask coupled to a face of the implantation tool or within a cavity of the implantation tool.

20. The method according to any one of claims 16 to 19, comprising implanting ions from the active side of the wafer along the passage between the microelectronic devices.

21. The method according to any one of claims 16 to 19, comprising implanting ions from the rear side of the wafer along the passage between the microelectronic devices.

22. The method according to any one of claims 16 to 19, wherein initiating a dislocation in the wafer comprises initiating a dislocation from an active surface or a back surface of the wafer to a depth between 1 μm and 6 μm.

23. The method according to any one of claims 16 to 19, wherein heating the wafer comprises raising the temperature of the wafer above ambient temperature by between 150°F and 250°F.

24. The method according to any one of claims 16 to 19, wherein the implanted ion comprises one or more of hydrogen, helium, boron, phosphorus and arsenic.

25. The method of claim 24, further comprising implanting hydrogen or helium ions from the active or rear surface of the wafer to a greater depth than the depth to which boron, phosphorus, or arsenic ions are implanted from the same surface.

26. A method for separating a microelectronic device from a wafer, the method comprising: An ion implantation process is used to induce dislocations in a semiconductor wafer in the passageway between the microelectronic devices, the dislocations extending from the adjacent main surface of the semiconductor wafer to a distance between 2 μm and 6 μm. The semiconductor wafer is transferred to a laterally expandable carrier material and the semiconductor wafer is adhered to the surface of the carrier material; as well as Tension is applied to the wafer by the expansion of the carrier material to form cracks in the passageways between the microelectronic devices and to separate the microelectronic devices.

27. The method of claim 26, wherein implanted ions are delivered to the surface of the semiconductor wafer via a mask having an opening substantially aligned with the passageway between the microelectronic device.

28. The method of claim 26, wherein the surface of the semiconductor wafer comprises an active surface or a rear surface opposite to the active surface.

29. The method according to any one of claims 26 to 28, further comprising, prior to using the ion implantation process: While the semiconductor wafer is supported on and secured to the rigid carrier structure, the semiconductor wafer is thinned from its rear surface from its initial thickness to a thickness of 30 μm or less; and after using the implantation process: Flipping the carrier structure to transfer and adhere the semiconductor wafer to the laterally expandable carrier material; and The carrier structure is released from the semiconductor wafer before the carrier material is expanded.

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