Method for manufacturing a wafer with spacing holders

Abstract

The invention relates to a method for manufacturing a wafer (100) having a spacing holder (150) for protecting a surface to be protected (110), comprising providing a coupled wafer (101) comprising an SOI wafer (140) and a functional wafer (120) connected thereto, wherein the SOI wafer (140) comprises a carrier wafer (146), a functional layer (142) having a first structure (143a, 143b) and a silicon dioxide layer (144) arranged between the carrier wafer (146) and the functional layer (142), and the functional wafer (120) has a second structure (120a, 120b); and creating (340) the spacing holder (150) by locally removing the carrier wafer (146) and the silicon dioxide layer (144), thereby exposing the surface to be protected (110).

Description

Technical Field

[0001] This invention relates to the field of wafer fabrication, and more particularly to a method for manufacturing a wafer having a spacer holding portion for protecting a surface to be protected. Furthermore, the invention also relates to a corresponding wafer and a method for fabricating such a wafer. Background Technology

[0002] US 2008 / 0303129 A1 discloses a method for preventing damage to sensitive surfaces in the field of MEMS (Micro-Electro-Mechanical Systems) fabrication. To this end, a chuck with structured contact surfaces is proposed. Specifically, a cover wafer is described, which is to be attached to an interposer wafer during fabrication. The cover wafer is positioned on the chuck, and the structure is responsible for preventing mechanical damage. DE 10 2015 206 996 A1 discloses the so-called EPyC process (Epithelial Polysilicon Cycling) for fabricating MEMS structures with large vertical extensions. This EPyC process uses epitaxial polysilicon as both the functional and sacrificial material and constructs a layered structure consisting of epitaxial polysilicon layers (EpiPoly layers) by means of repeated cycles. Summary of the Invention

[0003] According to the present invention, a method for manufacturing a wafer having a spacer holding portion (the spacer holding portion is used to protect the surface to be protected) is provided, as well as a corresponding wafer and a method for processing such a wafer.

[0004] According to a first aspect of the invention, a method for manufacturing a wafer having spacer holding portions for protecting a surface to be protected is provided. The method includes providing a coupled wafer comprising an SOI wafer (silicon-on-insulator) and a functional wafer connected (bonded) thereto, wherein the SOI wafer comprises a carrier wafer, a functional layer having a first structure (also referred to as a "device layer"), and a silicon dioxide layer (also referred to as a "buried oxide layer" (BOX)) disposed between the carrier wafer and the functional layer, and the functional wafer has a second structure. The connection between the functional wafer and the SOI wafer can be fabricated using common wafer bonding methods, such as direct silicon bonding, thermoforming bonding, or eutectic bonding. For the purposes of this invention, it is irrelevant, for example, whether the coupled wafer is provided by bonding the SOI wafer to a structured functional wafer, or whether the SOI wafer is started and the functional wafer is constructed and structured thereon. The first structure of the SOI wafer can be generated before or after connection to the functional wafer.

[0005] Furthermore, the method includes creating spacer holding portions by partially removing the carrier wafer and silicon dioxide layer, thereby exposing the surface to be protected. Thus, not only the carrier wafer but also the silicon dioxide layer is removed in specific areas of the SOI wafer, exposing the underlying surface to be protected, which is typically formed through the surface of a functional layer that now contacts the external environment of the wafer through a space previously covered by other layers. The resulting combination of a functional wafer, a functional layer, and spacer holding portions constitutes the manufactured wafer.

[0006] Functional wafers typically have or are composed of one or more semiconductors, such as silicon. The functional layer and carrier wafer of an SOI wafer are composed of or contain silicon. Metals and / or semiconductor oxides may also be included in the functional wafer and / or functional layer. Therefore, the functional wafer and / or functional layer may include sacrificial regions composed of semiconductors (such as silicon) and / or semiconductor oxides (such as silicon dioxide). The first and / or second structures may, for example, be or include structures for one or more electronic circuits, integrated circuits (ICs), MEMS, electrodes, and / or through-hole contacts (such as through-silicon vias (TSVs)). These structures may also be or include structures for multiple semiconductor chips (also referred to as chips within the scope of this invention). The silicon dioxide layer of the SOI wafer is composed of or contains silicon dioxide (SiO2).

[0007] The spacer holding portion is created by locally removing the carrier wafer and silicon dioxide layer of the SOI wafer, wherein the removal of the carrier wafer and the removal of the silicon dioxide layer can be performed in separate steps. Therefore, the removal of the carrier wafer is preferably performed by etching, for example by trench etching using a trench mask (e.g., a resist mask), while the removal of the silicon dioxide layer can be performed in subsequent steps, for example by HF vapor phase etching, plasma etching, and / or wet chemical etching. The trench mask here defines the bottom surface of the spacer holding portion. Preferably, the wafer is subsequently separated by an etching process, for example, simultaneously with or after the exposure of the MEMS structure, so it is generally not necessary to reserve space for sawing or similar separation methods.

[0008] Furthermore, the creation of the spacer holding portion may also include back-side thinning of the carrier wafer, which may be performed, for example, before partial removal of the carrier wafer. Back-side thinning can be performed, for example, by grinding. Preferably, chemical mechanical polishing (CMP) is subsequently performed to improve the roughness and surface quality of the carrier wafer after back-side thinning. This also ensures particularly high precision regarding the height of the carrier wafer after back-side thinning. The height of the carrier wafer after back-side thinning (i.e., the amount of extension in the direction perpendicular to the surface to be protected) together with the thickness of the silicon dioxide layer determines the subsequent height of the spacer holding portion, and can be, for example, in the range of 1 μm to 1000 μm, preferably in the range of 50 μm to 300 μm. Therefore, the height of the carrier wafer after back-side thinning can be, for example, 100 μm.

[0009] The spacer holding portion can have any shape and can consist of a single connected element or multiple spatially separated elements. The element thus formed from the carrier wafer and silicon dioxide layer (which is part of the spacer holding portion) is also called the spacer holding structure. The spacer holding portion can be created, for example, by forming grooves in the carrier wafer and silicon dioxide layer. The spacer holding portion and / or its spacer holding structure can, for example, take the form of a continuous or discontinuous frame, such as with walls, arches, grids, and / or pillars. The spacer holding structure of the spacer holding portion can also take the form of walls, cuboids, cylinders, corners, and / or crosses. Such frames and support structures are preferably arranged in a grid. In particular, one or more spacer holding structures can take the form of one or more rectangular frames and / or rectangular grids.

[0010] Preferably, the spacer holding portion is passivated during or after its formation to protect it from subsequent silicon sacrificial layer etching (hereinafter referred to as sacrificial layer etching), for example, during further wafer processing. The passivation layer thus formed can preferably consist of or contain silicon dioxide (SiO2) and / or silicon nitride (e.g., stoichiometric silicon nitride, i.e., Si3N4, and / or non-stoichiometric silicon nitride, i.e., silicon nitride with non-stoichiometric components). In particular, it is conceivable that the passivation layer consists of or contains a silicon nitride layer and a silicon dioxide layer, wherein it is conceivable that the silicon dioxide layer or silicon nitride layer is first applied to the functional layer for this purpose. A bilayer containing both stoichiometric and non-stoichiometric silicon nitride layers can also be used as the passivation layer. The passivation layer is preferably used as an etch stop layer for subsequent silicon sacrificial layer etching, wherein, for this purpose, sulfur hexafluoride (SF6) and / or xenon difluoride (XeF2) can be used as the etching gas. A particular advantage is that passivation of the spacer holding portion is performed after the carrier wafer is partially removed, since the surface to be protected is not yet exposed and therefore will not be re-covered by the passivation layer. Here, a passivation layer containing or composed of a passivation material, such as a silicon dioxide layer or a polymer layer, for example, composed of polyimide, is formed on the spacer holding portion. Passivation techniques such as plasma-assisted chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), thermal oxidation, and / or other methods for depositing passivation materials can be used, such as in the case of tetraethyl orthosilicate (TEOS deposition).

[0011] Preferably, after the spacer holding portion is formed, and particularly preferably after the spacer holding portion is passivated, the manufactured wafer is placed on a support surface such that only the spacer holding portion contacts the support surface. The support surface may be, for example, the surface of a chuck.

[0012] Preferably, the first structure in the functional layer and / or the second structure in the functional wafer may comprise a MEMS structure, and this MEMS structure is exposed within the scope of the method. The first and / or second structures may be exposed before or after the generation of the spacer. Such a MEMS structure may, for example, be a structure for one or more MEMS structural elements such as MEMS sensors and / or MEMS actuators, such as MEMS inertial sensors, MEMS pressure sensors, MEMS microphones, MEMS micromirrors, MEMS resonators, and / or components of such MEMS structural elements. For example, the second structure may be a MEMS structure for an actuator of a MEMS micromirror, and the mirror plate of the MEMS micromirror is implemented through the MEMS structure in the functional layer. Here, the surface to be protected may be the mirror surface, which is formed by the exposed surface of the functional layer. The exposure of the MEMS structure is typically performed at least in part by etching of a silicon sacrificial layer, and may be performed, for example, by means of plasma-free and / or plasma-assisted etching. In cases where there are silicon sacrificial regions to be removed, sacrificial layer etching is preferably performed using sulfur hexafluoride (SF6), xenon difluoride (XeF2), chlorine trifluoride (ClF3), and / or nitrogen trifluoride (NF3). Alternatively, deep reactive ion etching (DRIE) can be used during exposure. In silicon dioxide etching following common silicon sacrificial layer etching, hydrogen fluoride (HF) can be used as the etching gas (HF vapor phase etching) and / or BOE (buffered oxide etching) can be used as the wet etchant, for example.

[0013] Finally, after exposing the MEMS structure, one or more passivation layers, such as those formed by passivating the spacer portion, can be at least partially removed from the spacer holding wafer. These passivation layers may be, for example, oxide layers, particularly silicon dioxide layers. Removal can be performed, for example, using HF vapor etching, plasma etching, and / or wet chemical etching. If desired, certain areas can be selectively protected from HF vapor etching by applying a non-stoichiometric layer of silicon nitride.

[0014] According to a second aspect of the invention, a wafer manufactured according to the method described above is provided. Thus, the manufactured wafer includes a functional wafer, a functional layer, and spacer holding portions. A connection exists between the functional wafer and the functional layer, which is manufactured, for example, by direct silicon bonding, thermoforming bonding, or eutectic bonding. Preferably, the spacer holding portions of the wafer have a plurality of spacer holding structures, i.e., spatially separated elements, which are preferably frames, particularly preferably rectangular frames and / or continuous frames.

[0015] According to a third aspect of the invention, a method for processing such a wafer is provided, wherein a wafer is first provided, wherein a first structure and a second structure in the provided wafer are structures for multiple chips, wherein a chip may include multiple MEMS structural elements. Subsequently, the wafer is separated into chips, wherein each chip has a surface to be protected, and the chips are removed from the wafer, for example by means of a pick-and-place device, such as a pick-and-place robot.

[0016] Here, the wafer preferably has a retaining structure and / or the retaining structure is formed in and / or exposed in the wafer before and / or during wafer separation. Here, the retaining structure is configured to restrict possible movement of the chip in at least one direction perpendicular to the surface of the respective chip to be protected after separation.

[0017] Preferably, prior to wafer separation, a gap structure is formed and / or exposed surrounding a single chip, partially perforating the wafer. This gap structure has multiple gaps within the wafer. Furthermore, separation is performed at least partially along said multiple gaps, wherein tabs are preferably formed between the respective gaps by forming and / or exposing the partially perforated gap structure. These tabs extend horizontally or vertically relative to the surface of the respective chip to be protected, thereby holding the chip within the wafer. Thus, after this partial separation, the tabs connect the chip to the remainder of the wafer.

[0018] Within the scope of this invention, a gap structure should be understood as one or more potentially filled, i.e., non-empty recesses (gaps) in a layer of a wafer, which completely penetrate the layer in the vertical direction. Therefore, the gap structure can be filled with one or more other materials such as silicon dioxide (if necessary, combined with silicon as a sacrificial region) and exposed for subsequent use by an etching method. Accordingly, the filled gap structure constitutes an etched structure, thereby exposing the corresponding recesses. This etched structure can be constructed as a silicon dioxide region, which is subsequently removed by an etching process such as HF vapor phase etching, or the etched structure can include silicon sacrificial regions. For example, an EPyC process can be used to etch such that it contains silicon, which is surrounded laterally by silicon dioxide, and subsequently made accessible by sacrificial layer etching (e.g., using SF6 and / or XeF2). This etched structure constitutes a gap structure filled with silicon and silicon dioxide. Even in this case, the silicon dioxide can be removed by HF vapor phase etching after such sacrificial layer etching. All the methods mentioned can be used not only to completely separate a wafer into chips, but also to partially separate a wafer into chips, where partial separation means that the chip remains connected to the remaining part of the wafer via a bonding pad after partial separation.

[0019] Separating a wafer along a partially perforated gap structure refers to separation in such a way that multiple grooves in the gap structure are used to remove a chip from the remaining wafer by disrupting, for example, the remaining connection between the chip and the wafer (e.g., in the form of a splice). The gaps in the gap structure can differ from simple gaps extending vertically through the wafer (i.e., rectangular grooves and voids); for example, horizontal gaps extending parallel to the first surface of the wafer can be considered. In particular, the gaps can be configured such that retaining structures are formed at least locally, as described above, which continue to hold the individual chips in place after wafer separation, i.e., specifically restricting movement of the individual chips in a particular direction after separation, for example, to prevent accidental chip displacement from the wafer during movement. Retaining structures can exist not only in partially perforated gap structures (i.e., when using splices) but also in fully perforated gap structures. In particular, the combination of a die-attachment and a retaining structure is especially advantageous when pressure must be applied to the chip in the opposite direction of subsequent removal before the chip is removed (e.g., in the context of wafer-level testing), because the retaining structure can be configured and arranged to resist the pressure, i.e., also to act as a stop.

[0020] Preferably, a gap structure surrounding a single chip and fully penetrating the wafer is formed and / or exposed before or during wafer separation, the gap structure having one or more gaps in the wafer, wherein separation is achieved at least in part by forming and / or exposing the gap structure.

[0021] It is conceivable that, in the method for fabricating a wafer according to the invention as described above, the first structure and the second structure comprise MEMS structures for the same MEMS structural elements, and the surface of the chip to be protected is part of the MEMS structure, wherein exposure of the MEMS structure occurs before or during wafer separation. It is conceivable that a chip may have multiple MEMS structural elements. Thus, the second structure may be a MEMS structure for actuators of one or more MEMS micromirrors, and the first structure may be a MEMS structure belonging to a mirror plate of a MEMS micromirror. The surface to be protected may be a mirror surface formed by exposed surfaces of functional layers.

[0022] Preferably, the gaps, and thus fully penetrated gap structures and / or partially perforated gap structures, are formed by an etching process. Here, deep reactive ion etching (DRIE) can be used, for example, as the etching method. Such an etching process can also be combined with an etching process (e.g., silicon sacrificial layer etching) for exposing the first and / or second structures of the chip (such as MEMS structures), so that not only are fully penetrated gap structures and / or partially perforated gap structures formed in one process step, but the structure of the chip is also exposed. Alternatively, the gap structure can also be generated in a previous process step and filled, for example, with silicon dioxide, and only exposed later, for example, by HF vapor phase etching. In particular, gap structures with complex structures, such as retaining structures, can be achieved by the EPyC process. In the case of using the EPyC process, silicon dioxide acts as a separating layer between the functional region (the region with functional silicon) and the sacrificial region (the region with sacrificial silicon) of the gap structure. In this case, the exposure of the gap structure is performed by silicon sacrificial layer etching, which is preferably also used to expose the first and / or second structures, followed by removal of the silicon dioxide, for example, by HF vapor phase etching.

[0023] Advantages of this invention: This invention provides a possibility for protecting chips, such as MEMS chips, from mechanical damage during manufacturing. With this invention, SOI wafers with bonded functional wafers are reused as spacer holders. Thus, the manufacturing of the spacer holders is directly integrated into the manufacturing process. The spacer holder can flip the wafer and place it with the side having the surface to be protected, which is protected from mechanical damage by the spacer holder. Therefore, the wafer can be further processed from the other side.

[0024] Therefore, the spacer can protect particularly sensitive surfaces, such as mirror surfaces, from mechanical damage during subsequent processing steps. In particular, this allows the chip to be removed and separated from the wafer thus manufactured, and to be connected to other structural elements such as ASICs (Application-Specific Integrated Circuits), FPGAs (Field-Programmable Gate Arrays), and / or other MEMS structural elements, without concern for mechanical damage to the surface to be protected.

[0025] This method offers a high degree of flexibility to adapt to the specific framework conditions of the manufacturing process used in this invention. Therefore, the height of the spacer can be chosen, for example, to allow for safe wafer handling. For instance, the wafer can be placed with the spacer facing downwards, thus allowing it to be placed on a chuck in the manufacturing equipment for further processing without the risk of chuck or equipment contamination. Performing tests (e.g., wafer-level tests) during production can also be done without problems. Attached Figure Description

[0026] Embodiments of the present invention are described in detail with reference to the accompanying drawings and the following description. The drawings show: Figures 1A to 1F A schematic diagram of a wafer cross-section, used to illustrate the method for manufacturing a wafer according to the invention having a spacer holding portion and the method for processing a wafer according to the invention; Figure 2 A schematic diagram of a wafer with a spacer holding portion according to the present invention, viewed from below; and Figure 3 The following is a schematic flowchart illustrating an exemplary method according to the invention for manufacturing a wafer with a spacer holding portion, and an exemplary method according to the invention for processing a wafer according to the invention.

[0027] In the following description of embodiments of the present invention, the same or similar elements are referred to by the same reference numerals, wherein repeated descriptions of these elements are omitted in certain cases. The accompanying drawings are merely schematic representations of the invention. Detailed Implementation

[0028] Figures 1A to 1F A schematic diagram showing a cross-section of a wafer is provided to illustrate a method for manufacturing a wafer 100 according to the invention, having a spacer holding portion, and a method for processing a wafer according to the invention.

[0029] Figure 1A A schematic cross-section of the coupled wafer 101 is shown. The coupled wafer 101 includes an SOI wafer 140 (SOI: silicon-on-insulator) and a functional wafer 120, which are interconnected by bonding connections 130. Here, as shown below... Figures 1B to 1F Thus, only a portion of the functional chip 120 is shown, which continues to extend to the left and right of the area shown in the figure. The same applies to [the area from...]. Figure 1B The manufactured chip 100 is shown at the beginning.

[0030] exist Figure 1A In this design, the SOI wafer 140 includes a carrier wafer 146 and a functional layer 142, which are interconnected by a silicon dioxide layer 144. Furthermore, the SOI wafer has first structures 143a and 143b, which in this example include MEMS structures 143a' and 143b' for MEMS chips 105a and 105b (hereinafter also simply referred to as chips 105a and 105b), such as mirror plates for MEMS micromirrors, wherein each chip 105a and 105b may include multiple MEMS micromirrors. An etched structure 170 is also shown, which may include, for example, trenches filled with silicon dioxide and / or silicon. Figure 1AThe gap structure corresponding to the filled gap is used for subsequent separation of wafer 100. The etched structure 170 can be specifically configured as a silicon dioxide region, which is subsequently removed by an etching process such as HF vapor phase etching, or it can include a silicon sacrificial region. The etched structure 170 can also use an EPyC process configuration. The etched structure then includes silicon coated with silicon dioxide, which is reached by the sacrificial layer etching (e.g., by means of SF6 and / or XeF2). After such sacrificial layer etching, even in this case, the silicon dioxide can be subsequently removed by HF vapor phase etching. There is no structure in the region 143c that does not belong to a single chip 105a, 105b. The functional wafer 120 also has second structures 120a, 120b in specific regions, which in this example also include MEMS structures 120a', 120b' for MEMS chips 105a, 105b. There are also unstructured regions in the remaining portion 120c of the wafer that is not part of chips 105a, 105b. The functional wafer 120 has a passivation layer 122, which may include, for example, a silicon dioxide layer. Metal contacts 124, which are also part of the functional wafer 120, are covered by this silicon dioxide layer. In the fabricated chips 105a and 105b, the metal contacts 124 can be used to establish electrical connections to components (e.g., actuators and / or sensors) of the chips 105a and 105b. The functional wafer 120 has an etched structure 170, similar to that in the SOI wafer 140; however, this etched structure also serves to implement horizontal tabs 150a and holding structures 150b, which later prevent the chips 105a and 105b from falling out during separation of the wafer 100.

[0031] Now, the carrier wafer 146 is thinned on the back side, and then a trench mask 160 is provided in the area where it should not be etched. Figure 1B The result is shown after the corresponding etching process, which stops on the silicon dioxide layer 144 of the SOI wafer 140. Therefore, the silicon dioxide layer 144 acts as an etching stop layer. This etching process produces the element 151 for the spacer holding portion. Figure 1B The grooves in the back-side thinned carrier wafer 146' are shown, corresponding to the areas of the chips 105a, 105b that should be surrounded by spacer portions. In the next step, as in Figure 1C As can be intuitively illustrated, the trench mask 160 can now be removed and replaced by a passivation layer 155 on the spacer holding element 151, which protects the element 151 in subsequent process steps, especially the subsequent sacrificial layer etching (e.g., with the aid of SF6 and / or XeF2).

[0032] In the next step, the MEMS structures 143a' and 143b' in functional layer 142 and the second MEMS structures 120a' and 120b' in functional chip 120 can now be exposed. For this purpose, as... Figure 1D As shown, wafer 100 is placed on the support surface 191 of chuck 190 with its spacer holding element 151 facing downwards, wherein the surfaces 110 to be protected of chips 105a and 105b also face downwards accordingly. Silicon sacrificial layer etching is then performed, for example using SF6, XeF2, ClF3, and / or NF3, thereby exposing MEMS structures 120a', 120b', 143a', and 143b'. To visually illustrate this removal of silicon in MEMS structures 120a', 120b', 143a', and 143b' in the accompanying drawings, Figure 1D and 1F The MEMS structures 120a', 120b', 143a', and 143b' used the same as those in the previous section. Figures 1A to 1C Different shaded lines are shown. Next, after actual exposure, the silicon dioxide layer and the passivation material of structure 170 are removed, for example, by HF vapor phase etching. Figure 1D The result of this etching process is shown. In the example shown, the passivation layer 122 is completely removed and the silicon dioxide layer 144 is removed to such an extent that the remaining area of ​​the silicon dioxide layer 144 has a smaller extension than the element 151 of the spacer 150. The spacer 150 and the corresponding spacer structure are formed through these remaining areas of the element 151 and the silicon dioxide layer 144. Furthermore, through the etching process, the surfaces 110 to be protected of the chips 105a and 105b (the surfaces constituting the functional layer 142) and the gaps 182a and 182b of the gap structures 180a and 180b (corresponding to the previous...) are also removed. Figures 1A to 1C The etched structure 170 has been exposed. Similarly, the metal contact 124 is now also accessible.

[0033] exist Figure 1D Different variants can also be seen separated.

[0034] Therefore, located Figure 1DThe chip 105a on the right has a horizontal tab 150a that connects the chip to the remainder 120c of the wafer 100. Conversely, the chip 105b on the left has been completely separated and is not held by tabs in the wafer 100. Accordingly, the gap structure 180a now exposed, with a gap 182a, is a partially perforated gap structure. The gap structure 180b can be a fully penetrating gap structure with a gap 182b surrounding the chip 105b, through which the chip 105b is ejected from the wafer 100. However, movement of the chip 105b in a direction 102 perpendicular to the surface 110 to be protected (visually illustrated in the figures by corresponding arrows) is restricted by a holding structure 150b in the form of a protrusion in the remainder 120c of the wafer 100 (the protrusion extends into the gap 182c). These retaining structures 150b block the path of the chip 105b as it moves along direction 102, wherein the retaining structure 150b is configured such that it only contacts areas of the chip 105b that are not part of the surface 110 to be protected.

[0035] like Figure 1E As shown, the separated chip 105b and the partially separated chip 105a, still held by the horizontal connector 150a, can now undergo wafer-level testing and be connected to other structural components 194. Therefore, in Figure 1E The diagram shows a wafer-level test for chip 105b with a corresponding contact probe 192a that contacts metal contact 124. For such wafer-level testing, it is particularly advantageous to implement a horizontal tab 150a and a retaining structure 150b in parallel (not shown) for a single chip, because in this case the retaining structure 150b can act as a stop to prevent accidental breakage of the horizontal tab 150a upon contact with the contact probe 192a. Following possible wafer-level testing, a chip is then... Figure 1E As exemplarily shown for chip 105a, it can be electrically connected to another structural element 194 (such as an ASIC, FPGA, and / or another MEMS structural element) via metal contacts 124, typically via soldering. The resulting chip-structural element composite can be remeasured after this connection, for example, as in... Figure 1F As shown by the corresponding measuring probe 192b, the pick-and-place device 196 (such as a pick-and-place robot) can now remove chips 105a and 105b from the remaining portion 120c of wafer 100. This is in Figure 1F The image shows chip 105a. Here, the horizontal contact 150a is broken. Therefore, in... Figure 1F The remaining portion 150a' of the broken horizontal joint 150a is shown in the figure.

[0036] Figure 2A schematic diagram of a wafer 100 according to the invention, viewed from below, with spacer holding portions 150 is shown. Twenty chips 205 are shown, each surrounded by spacer holding structures 250 in the form of a rectangular continuous frame of spacer holding portions 150, wherein these frames may alternatively have non-rectangular and / or discontinuous shapes. Instead of frames, other shapes of spacer holding structures are also conceivable, such as cross-shaped, angular, prism-shaped, or cuboid. Alternative or additional spacer holding structures may be separate walls, for example, placed in the middle of the edges of the chips 205.

[0037] Figure 3 An exemplary method according to the invention for manufacturing a wafer with a spacer holding portion and an exemplary method according to the invention for processing a wafer according to the invention are illustrated in flowchart form.

[0038] Here, a 310-coupled wafer is provided, comprising an SOI wafer and a functional wafer connected thereto. The SOI wafer includes a carrier wafer, a functional layer having a first structure, and a silicon dioxide layer disposed between the carrier wafer and the functional layer. The functional wafer has a second structure. The first and second structures are structures for multiple MEMS chips, each of which may include multiple MEMS structural elements. Here, each MEMS structural element is implemented through a portion of the first structure and a portion of the second structure.

[0039] In step 330, the carrier wafer undergoes back-side thinning, for example, by grinding. Then, in step 340, the carrier wafer and the silicon dioxide layer are locally removed using a suitable etching method, thereby creating spacer holding portions. More precisely, a localized removal of the carrier wafer 340a (trench etching) is first performed, followed by a localized removal of the silicon dioxide layer 340b, thereby exposing the surface to be protected, such as a mirror surface. Between steps 340a and 340b, the trench-etched carrier wafer can be passivated to protect it in subsequent process steps, such as exposure via silicon sacrificial layer etching. After creating the spacer holding portions, the fabricated wafer is typically placed 350 on a support surface, such as the support surface of a chuck, such that only the spacer holding portions contact the support surface. The wafer provided by the aforementioned step 360 can now be further processed. Thus, typically in one step, the MEMS structure is exposed 370 by silicon sacrificial layer etching.

[0040] Subsequently, in preparation for separation, gap structures with partial through-holes for forming tabs can be constructed and / or exposed (step 374) and / or gap structures that fully penetrate the wafer (step 376). Here, by constructing and / or exposing the gap structures with partial through-holes in step 374, tabs are preferably formed between the gaps, extending horizontally or vertically relative to the first surface, and holding the MEMS chip within the wafer. The subsequent separation 380 then proceeds at least partially along these multiple gaps. A holding structure can also be constructed and / or exposed (step 372), which typically occurs during the etching process common to steps 374 and / or 376. The function of this holding structure is to restrict possible movement of the MEMS chip in a direction perpendicular to the surface to be protected of the respective chip after separation 380. Preferably, all the aforementioned structures have already been formed during the fabrication of the functional wafer (see [reference needed] for this). Figure 1A And the etched structure 170 therein). The gap structure and / or retaining structure can be achieved here by etching the structure, wherein the gap structure can be filled, for example, with silicon dioxide and / or silicon, so that only these structures need to be exposed in steps 372, 374, 376. This is done, depending on the material to be removed, for example by HF vapor phase etching and / or silicon sacrificial layer etching.

[0041] Following the exposure of the MEMS structure at 370, the passivation layer of the spacer holding portion wafer, which is no longer needed at 375, can be at least partially removed, preferably by means of HF vapor phase etching. This vapor phase etching also exposes any possible gap structures, bonding pads, and holding structures, allowing step 375 to be combined with steps 372, 374, and 376. Similarly, steps 372, 374, and 376 can at least partially overlap with exposure 370, for example, when silicon sacrificial layer etching is used for steps 372, 374, and 376.

[0042] Before separation, the exposed wafer can be connected to structural element wafers such as ASIC wafers or individual structural elements such as ASICs. Separation 380 can then be performed to obtain an individual MEMS structural element. Alternatively, separation 380 can be performed before connecting to the structural element wafer or individual structural element. Finally, in step 390, the MEMS chip is removed from the remaining portion of the wafer, for example, by a pick-and-place device, where, if present, the contacts are broken. The chip is then finally separated, with separation 380 and removal 390 coinciding in time.

[0043] The invention is not limited to the embodiments described herein and the aspects highlighted therein. Rather, various modifications can be made within the scope given by the claims, which are within the capabilities of those skilled in the art.

Claims

1. A method for manufacturing a wafer (100) having a spacer holding portion (150) for protecting a surface (110) to be protected, the method comprising the steps of: a. Providing (310) a coupled wafer (101), the coupled wafer comprising an SOI wafer (140) and a functional wafer (120) connected to the SOI wafer, wherein the SOI wafer (140) comprises a carrier wafer (146), a functional layer (142) having a first structure (143a, 143b), and a silicon dioxide layer (144) disposed between the carrier wafer (146) and the functional layer (142), and the functional wafer (120) having a second structure (120a, 120b); and b. The spacer holding portion (150) is generated by partially removing (340a, 340b) the carrier wafer (146) and the silicon dioxide layer (144), thereby exposing the surface (110) to be protected.

2. The method according to claim 1, wherein, The back side of the carrier wafer (146) is thinned (330) before the spacer holding portion (150) (340) is produced.

3. The method according to any one of the preceding claims, wherein, After the spacer holding portion (150) is generated (340), the manufactured wafer (100) is placed (350) on the support surface (191) such that only the spacer holding portion (150) contacts the support surface (191).

4. The method according to any one of the preceding claims, wherein, The first structure (143a, 143b) and / or the second structure (120a, 120b) comprise a MEMS structure (120a', 120b', 143a', 143b') for one or more MEMS structural elements and / or components of such MEMS structural elements, such as MEMS sensors and / or MEMS actuators, preferably MEMS inertial sensors, MEMS pressure sensors, MEMS microphones, MEMS micromirrors, MEMS resonators, and the exposure (370) of the MEMS structure (120a', 120b', 143a', 143b') is preferably performed by means of plasma-free etching and / or plasma-assisted etching and / or in the case of using SF6, XeF2, ClF3 and / or NF3.

5. The method according to claim 4, wherein, After exposing (370) the MEMS structure (120a', 120b', 143a', 143b'), at least (375) one or more passivation layers (155) are removed (375) from the spacer holding portion (150), preferably by means of HF vapor phase etching.

6. A wafer (100) manufactured by the method according to any one of claims 1 to 5.

7. The wafer (100) according to claim 6, wherein, The spacer holding part (150) has a plurality of spacer holding structures (250) in the form of a frame.

8. A method for processing a wafer (100) according to claim 6 or 7, comprising the following steps: a. Provide (360) the wafer (100), wherein the first structure (143a, 143b) and the second structure (120a, 120b) are structures for a plurality of chips (105a, 105b, 205); b. Separating (380) the wafer (100) into chips (105a, 105b, 205), wherein each chip (105a, 105b, 205) has a surface (110) to be protected; and c. Remove (390) the chip (105a, 105b, 205) from the wafer (100).

9. The method according to claim 8, wherein, The wafer (100) has a holding structure (150b), and / or the holding structure (150b) is formed and / or exposed (372) in the wafer (100) before and / or during separation (380) of the wafer (100), wherein the holding structure (150b) is configured to restrict possible movement of the chip (105b, 205) after separation (380) in at least one direction (102) perpendicular to the surface (110) to be protected of the respective chip (105b, 205).

10. The method according to claim 8 or 9, wherein, Prior to the separation (380) of the wafer (100), a gap structure (180a) is formed and / or exposed (374) around the respective chips (105a, 205) and partially perforates the wafer (100), the gap structure having a plurality of gaps (182a) in the wafer (100), and the separation (380) is carried out at least partially along the plurality of gaps (182a), wherein, by forming and / or exposing (374) the gap structure (180a) with partial perforations, horizontal tabs (150a) are preferably formed between these gaps (182a), the horizontal tabs extending horizontally or vertically relative to the surface (110) to be protected of the respective chip (105a, 205), and the chip (105a, 205) is thereby held in the wafer (100).

11. The method according to any one of claims 8 to 10, wherein, Before or during the separation (380) of the wafer (100), a gap structure (180b) is formed and / or exposed (376) surrounding each chip (105b, 205) and fully penetrating the wafer (100), the gap structure having one or more gaps (182b) in the wafer (100), and the separation (380) is carried out at least in part by forming and / or exposing (376) the gap structure (180b).

12. The method according to any one of claims 8 to 11, wherein, The first structure (143a, 143b) and the second structure (120a, 120b) include MEMS structures (120a', 120b', 143a', 143b') for the same MEMS structural elements, and the surface (110) to be protected of the chip (105a, 105b, 205) is part of the MEMS structure (120a', 120b', 143a', 143b'), wherein the exposure (370) of the MEMS structure (120a', 120b', 143a', 143b') is performed before or during the separation (380) of the wafer (100).

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