A silicon carbide mos device and a method of fabricating the same

Abstract

This invention discloses a silicon carbide MOS device and its fabrication method, belonging to the field of semiconductor power device technology. It solves the problems of complex and demanding gate oxide layer processes, which often involve ultra-high temperature oxidation or high-temperature annealing in different atmospheres. The device comprises a lower surface electrode, a SiC epitaxial wafer, a gate oxide layer, and a polysilicon electrode stacked sequentially. Pentium-valent and / or trivalent elements implanted in the polysilicon electrode diffuse to the gate oxide layer. The method involves oxidizing the SiC epitaxial wafer, using the upper surface oxide layer as the gate oxide layer, and forming a polysilicon layer on the surface of the upper surface oxide layer. Pentium-valent and / or trivalent elements are implanted into the polysilicon layer, followed by activated annealing, allowing the pentavalent and / or trivalent elements to diffuse to the gate oxide layer. A patterning process is then performed on the polysilicon layer to form the polysilicon electrode, resulting in a silicon carbide MOS device (mainly including MOSFET devices and MOS capacitors). This silicon carbide MOS device and method can be used in power electronic devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, and in particular to a silicon carbide MOS device and its fabrication method. Background Technology

[0002] Compared to first-generation semiconductors represented by silicon and second-generation semiconductors represented by gallium arsenide (GaAs), third-generation semiconductor material SiC boasts a wider bandgap and a higher critical breakdown field strength. Compared to silicon power devices under the same conditions, SiC's breakdown voltage is approximately 100 times that of silicon. Furthermore, SiC exhibits higher thermal conductivity and lower intrinsic carrier concentration, allowing it to withstand junction temperatures of approximately 600°C, significantly increasing the operating temperature limit of SiC devices. In addition, SiC devices exhibit higher electron saturation velocity, lower forward on-resistance, and lower power loss, making them suitable for high-current, high-power applications and reducing the requirements for heat dissipation equipment. Unlike other third-generation semiconductors such as GaN, SiC can be thermally oxidized to form silicon dioxide, allowing for replication or transfer of traditional silicon MOSFET processes to silicon carbide. Therefore, SiC is considered an important development direction for next-generation high-efficiency power electronic devices, with broad application prospects in new energy vehicles, rail transportation, locomotive traction, and smart grids.

[0003] However, in SiC power devices, the gate oxide layer generated by thermal oxidation introduces a large number of defects such as carbon clusters and oxygen vacancies at the SiO2 / SiC interface, resulting in a significant increase in the interface state density. This leads to a substantial decrease in the effective mobility of inversion layer carriers in SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) and reduces the reliability of the gate oxide layer. The threshold voltage becomes unstable during use and is prone to drift, severely restricting the development and application of SiC power devices.

[0004] For SiC MOS capacitors, the current main methods to improve the interface characteristics and gate oxide reliability of SiC MOS devices are ultra-high temperature oxidation or high temperature annealing processes with different atmospheres. However, these processes usually need to be carried out in oxidation furnaces with special silicon carbide devices, which makes the preparation process and equipment complex. Summary of the Invention

[0005] Based on the above analysis, the present invention aims to provide a silicon carbide MOS device and its fabrication method, which solves the problems of complex and demanding gate oxide layer processes in the prior art, which use ultra-high temperature oxidation or high temperature annealing processes with different atmospheres.

[0006] The objective of this invention is mainly achieved through the following technical solutions:

[0007] The present invention provides a silicon carbide MOS device, comprising a lower surface electrode, a SiC epitaxial wafer, a gate oxide layer and a polysilicon electrode stacked sequentially, wherein pentavalent and / or trivalent elements implanted in the polysilicon electrode diffuse to the gate oxide layer.

[0008] Furthermore, the pentavalent element is at least one of nitrogen or phosphorus, and the trivalent element is at least one of boron, indium, or gallium.

[0009] Furthermore, pentavalent and / or trivalent elements diffuse to the entire gate oxide layer, that is, pentavalent and / or trivalent elements diffuse to the interface between the gate oxide layer and the SiC epitaxial wafer.

[0010] Furthermore, the SiC epitaxial wafer comprises a SiC substrate and an epitaxial layer stacked sequentially.

[0011] Furthermore, the aforementioned silicon carbide MOS device is a MOSFET device or a MOS capacitor device.

[0012] This invention also provides a method for fabricating a silicon carbide MOS device, comprising the following steps:

[0013] Provide a SiC epitaxial wafer, such as an N-type SiC epitaxial wafer or a P-type SiC epitaxial wafer;

[0014] The SiC epitaxial wafer is oxidized to form oxide layers on the upper and lower surfaces of the SiC epitaxial wafer. The oxide layer on the upper surface serves as the gate oxide layer, and a polysilicon layer is formed on the surface of the oxide layer on the upper surface.

[0015] Ion implantation samples are obtained by implanting pentavalent and / or trivalent elements into a polycrystalline silicon layer.

[0016] The ion-implanted sample is activated by annealing to activate the pentavalent and / or trivalent elements in the polysilicon layer, allowing the pentavalent and / or trivalent elements to diffuse to the gate oxide layer. The polysilicon layer is then patterned (e.g., photolithography, etching) to form polysilicon electrodes, resulting in a silicon carbide MOS device.

[0017] Furthermore, the patterning process is either photolithography or etching.

[0018] Furthermore, the activation annealing temperature is 900–1100℃ (e.g., 900℃, 930℃, 970℃, 0℃, 0℃, or 1100℃, etc.), and the activation annealing time is 30–120 min (e.g., 30 min, 55 min, 70 min, 95 min, min, or 120 min, etc.).

[0019] Furthermore, in the oxidation process of the SiC epitaxial wafer, the oxidation process is either dry oxygen oxidation or wet oxygen oxidation, the oxidation atmosphere is an oxygen atmosphere, and the oxidation temperature is 1100–1450℃.

[0020] Furthermore, the oxidation treatment of the SiC epitaxial wafer described above includes the following steps:

[0021] In an oxygen atmosphere, SiC epitaxial wafers are subjected to high-temperature dry oxygen oxidation treatment or high-temperature wet oxygen oxidation treatment at 1100–1450°C.

[0022] Furthermore, in the step of forming a polycrystalline silicon layer on the oxide layer surface of the upper surface, a plasma-enhanced chemical vapor deposition method is used to form the polycrystalline silicon layer.

[0023] Furthermore, providing a SiC epitaxial wafer includes the following steps:

[0024] Provide a SiC substrate;

[0025] An epitaxial layer is formed on the upper surface of a SiC substrate, and the epitaxial layer is made of 4H-SiC.

[0026] Furthermore, the aforementioned MOS device is a MOSFET device, and after forming the polysilicon electrode, the following steps are also included:

[0027] The oxide layer on the lower surface is removed by etching (e.g., dry etching) or corrosion (e.g., wet corrosion).

[0028] A drain electrode is formed on the lower surface of SiC.

[0029] Furthermore, the above-mentioned MOS device is a MOS capacitor device, and after forming the polysilicon electrode, the following steps are also included:

[0030] The oxide layer on the lower surface is removed by etching (e.g., dry etching) or corrosion (e.g., wet corrosion).

[0031] A back electrode is formed on the lower surface of SiC.

[0032] Furthermore, dry etching uses an etching machine, while wet etching uses a hydrofluoric acid solution with a concentration of 5-15% as the etching solution.

[0033] Furthermore, prior to the oxidation treatment of the SiC epitaxial wafer, the following steps are also included:

[0034] The SiC epitaxial wafer is cleaned.

[0035] Furthermore, the above cleaning includes the following steps:

[0036] SiC epitaxial wafers are immersed in a mixture of 98wt% concentrated sulfuric acid and 27wt% hydrogen peroxide at a volume ratio of 1:1 to 2, heated in a water bath at 90 to 100°C for 15 to 18 minutes, rinsed with deionized water, and dried with N2.

[0037] SiC epitaxial wafers were immersed in a mixed solution of 28wt% ammonia and 27wt% hydrogen peroxide at a volume ratio of 1:1 to 1.2, heated in a water bath for 15 to 20 minutes, rinsed with deionized water, and dried with N2.

[0038] The SiC epitaxial wafer was immersed in a mixed solution of 10wt% hydrochloric acid and 27wt% hydrogen peroxide at a volume ratio of 1:1 to 1.5, heated in a water bath at 90 to 100°C for 15 to 20 minutes, rinsed with deionized water, and dried with N2.

[0039] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0040] a) The silicon carbide MOS device provided by the present invention allows pentavalent and / or trivalent elements implanted in the polysilicon electrode to diffuse into the gate oxide layer, thereby introducing pentavalent and / or trivalent elements into the gate oxide layer. The pentavalent and / or trivalent elements can form Si≡N and C≡N bonds with the residual C clusters and O vacancies in the gate oxide layer, reducing the number of defects in the gate oxide layer, passivating dangling bonds or other defects in the gate oxide layer, improving the quality of the gate oxide layer, achieving the effect of traditional oxidation followed by annealing, and effectively improving the stability of the threshold voltage, interface performance and gate dielectric layer reliability of the silicon carbide MOS device.

[0041] b) In the silicon carbide MOS device provided by the present invention, pentavalent and / or trivalent elements diffuse to the interface between the gate oxide layer and the SiC epitaxial wafer. In this way, the implanted pentavalent and / or trivalent elements can form Si≡N and C≡N bonds with all the remaining C clusters and O vacancies in the gate oxide layer, thereby further reducing the number of defects in the gate oxide layer, passivating dangling bonds or other defects in the gate oxide layer, and improving the quality of the gate oxide layer.

[0042] c) The method for fabricating a silicon carbide MOS device provided by the present invention involves implanting pentavalent and / or trivalent elements into a polycrystalline silicon electrode, and then activating annealing to allow the pentavalent and / or trivalent elements to diffuse into the gate oxide layer, thereby introducing the pentavalent and / or trivalent elements into the gate oxide layer. The pentavalent and / or trivalent elements can form Si≡N and C≡N bonds with the residual C clusters and O vacancies in the gate oxide layer, reducing the number of defects in the gate oxide layer, passivating dangling bonds or other defects in the gate oxide layer, improving the quality of the gate oxide layer, and achieving the effect of traditional oxidation followed by annealing. This method can effectively improve the stability of the threshold voltage, interface performance, and reliability of the gate dielectric layer of the silicon carbide MOS device.

[0043] d) The method for fabricating silicon carbide MOS devices provided by the present invention enables pentavalent and / or trivalent elements to diffuse into the gate oxide layer through activation annealing. It achieves the dual effects of activating pentavalent and / or trivalent elements to form polycrystalline silicon electrodes and removing the number of defects in the gate oxide layer in one step, effectively simplifying the fabrication process of silicon carbide MOS devices, shortening the fabrication cycle, and reducing the fabrication cost.

[0044] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0045] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0046] Figure 1 A schematic diagram of the silicon carbide MOS device provided by the present invention;

[0047] Figure 2 A flowchart illustrating the fabrication method of the silicon carbide MOS device provided by this invention;

[0048] Figure 3 The schematic diagram illustrates the principle of forming Si≡N and C≡N bonds with residual C clusters and O vacancies in the gate oxide layer in the fabrication method of silicon carbide MOS device provided by the present invention, taking the pentavalent element N as an example;

[0049] Figure 4 This is a comparison of the flat band voltage and accumulation region voltage curves of the silicon carbide MOS device prepared in Embodiment 1 of the present invention and the existing Al electrode sample.

[0050] Figure 5 This is a graph showing the interface state density of a silicon carbide MOS device prepared according to Embodiment 1 of the present invention.

[0051] Figure 6 The image shows the SIMS analysis spectra of N and P elements of the silicon carbide MOS device prepared in Embodiment 1 of the present invention.

[0052] Figure label:

[0053] 1-SiC substrate; 2-Epipolar layer; 3-Gate oxide layer; 4-Polysilicon layer; 5-Polysilicon electrode; 6-Drain electrode; 6'-Back electrode; 7-Oxide layer on the lower surface. Detailed Implementation

[0054] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of the present invention and, together with the embodiments of the present invention, serve to illustrate the principles of the present invention.

[0055] The main factors affecting the interface characteristics of silicon carbide MOS devices are dangling bonds and carbon clusters caused by oxidation at the interface. These interface defects can trap electrons or holes during later device use, causing threshold voltage drift and affecting device reliability. Current technologies primarily employ a post-oxidation annealing process (annealing atmospheres such as NO, N2, and POCl3) to passivate dangling bonds and carbon clusters in the gate oxide layer.

[0056] This invention provides a silicon carbide MOS device, see [link to relevant documentation]. Figure 1 The structure includes a lower surface electrode, a SiC epitaxial wafer, a gate oxide layer 3, and a polycrystalline silicon electrode 5 stacked sequentially. Pentavalent and / or trivalent elements (e.g., phosphorus P, nitrogen N, boron B, indium In, gallium Ga, etc.) implanted in the polycrystalline silicon electrode 5 diffuse into the gate oxide layer 3.

[0057] Compared with the prior art, the silicon carbide MOS device provided by the present invention allows pentavalent and / or trivalent elements implanted in the polysilicon electrode 5 to diffuse into the gate oxide layer 3, thereby introducing pentavalent and / or trivalent elements into the gate oxide layer 3. The pentavalent and / or trivalent elements can form Si≡N and C≡N bonds with the residual C clusters and O vacancies in the gate oxide layer 3, reducing the number of defects in the gate oxide layer 3, passivating dangling bonds or other defects in the gate oxide layer 3, improving the quality of the gate oxide layer 3, achieving the effect of traditional oxidation followed by annealing, and effectively improving the stability of the threshold voltage, interface performance and gate dielectric layer reliability of the silicon carbide MOS device.

[0058] It is worth noting that the implantation depth of pentavalent and / or trivalent elements directly affects the number of defects in the gate oxide layer 3. Since the residual C clusters and O vacancies are mainly located at the interface between the gate oxide layer 3 and the SiC epitaxial wafer, in the above-mentioned silicon carbide MOS device, the pentavalent and / or trivalent elements diffuse to the entire gate oxide layer 3, that is, the pentavalent and / or trivalent elements diffuse to the interface between the gate oxide layer 3 and the SiC epitaxial wafer. In this way, the implanted pentavalent and / or trivalent elements can basically form Si≡N and C≡N bonds with all the residual C clusters and O vacancies in the gate oxide layer 3, thereby further reducing the number of defects in the gate oxide layer 3, passivating dangling bonds or other defects in the gate oxide layer 3, and improving the quality of the gate oxide layer 3.

[0059] Specifically, the structure of the SiC epitaxial wafer includes a stacked SiC substrate 1 and an epitaxial layer 2, wherein the epitaxial layer 2 is made of 4H-SiC material with higher breakdown electric field strength and higher carrier mobility.

[0060] It is understood that the aforementioned silicon carbide MOS device can be a MOSFET device or a MOS capacitor device. Accordingly, for a MOSFET device, the lower surface electrode is the drain electrode 6; for a MOS capacitor device, the lower surface electrode is the back electrode 6'.

[0061] This invention also provides a method for fabricating a silicon carbide MOS device, see [link to documentation]. Figure 2 It includes the following steps:

[0062] Provide a SiC epitaxial wafer, such as an N-type SiC epitaxial wafer or a P-type SiC epitaxial wafer;

[0063] The SiC epitaxial wafer is oxidized to form oxide layers on the upper and lower surfaces of the SiC epitaxial wafer. The oxide layer on the upper surface serves as the gate oxide layer 3, and a polysilicon layer 4 is formed on the surface of the oxide layer on the upper surface.

[0064] Pentavalent and / or trivalent elements, such as phosphorus (P), nitrogen (N), boron (B), indium (In), gallium (Ga), etc., are implanted into polycrystalline silicon layer 4 to obtain an ion-implanted sample;

[0065] The ion-implanted sample is activated and annealed in an N2 or O2 atmosphere to activate the pentavalent and / or trivalent elements in the polysilicon layer 4, so that the pentavalent and / or trivalent elements diffuse to the gate oxide layer 3. The polysilicon layer 4 is then patterned (e.g., photolithography, etching) to form the polysilicon electrode 5, thus obtaining a silicon carbide MOS device.

[0066] Compared with the prior art, the method for fabricating a silicon carbide MOS device provided by the present invention involves implanting pentavalent and / or trivalent elements into a polycrystalline silicon electrode 5, and then using activated annealing to allow the pentavalent and / or trivalent elements to diffuse into the gate oxide layer 3, thereby introducing the pentavalent and / or trivalent elements into the gate oxide layer 3. These pentavalent and / or trivalent elements can form Si≡N and C≡N bonds with residual C clusters and O vacancies in the gate oxide layer 3. (See [link to previous text]). Figure 3 This reduces the number of defects in the gate oxide layer 3, passivates dangling bonds or other defects in the gate oxide layer 3, improves the quality of the gate oxide layer 3, and achieves the effect of traditional oxidation followed by annealing. It can effectively improve the stability of the threshold voltage, interface performance and reliability of the gate dielectric layer of silicon carbide MOS devices.

[0067] Furthermore, the method for fabricating silicon carbide MOS devices achieves the dual effects of activating pentavalent and / or trivalent elements to form polycrystalline silicon electrodes 5 and reducing the number of defects in the gate oxide layer 3 through activation annealing. This effectively simplifies the fabrication process of silicon carbide MOS devices, shortens the fabrication cycle, and reduces the fabrication cost.

[0068] It should be noted that in the fabrication method of the silicon carbide MOS device of the present invention, the activation annealing is for the polycrystalline silicon electrode 5. In order to perform ion activation after ion implantation, a common furnace tube can be used, and the activation annealing temperature is 900-1100°C. In the prior art, the post-oxidation annealing is for the gate oxide layer 3, which needs to be performed in a high-temperature silicon carbide oxidation furnace. The post-oxidation annealing temperature exceeds 1100°C, and after the post-oxidation annealing, ion implantation and activation annealing of the polycrystalline silicon electrode 5 are still required.

[0069] It is worth noting that the implantation depth of pentavalent and / or trivalent elements directly affects the number of defects in the gate oxide layer 3. Since the residual C clusters and O vacancies are mainly located at the interface between the gate oxide layer 3 and the SiC epitaxial wafer, in the above-mentioned method for fabricating silicon carbide MOS devices, the pentavalent and / or trivalent elements diffuse to the entire gate oxide layer 3, that is, the pentavalent and / or trivalent elements diffuse to the interface between the gate oxide layer 3 and the SiC epitaxial wafer. In this way, the implanted pentavalent and / or trivalent elements can basically form Si≡N and C≡N bonds with all the residual C clusters and O vacancies in the gate oxide layer 3, thereby further reducing the number of defects in the gate oxide layer 3, passivating dangling bonds or other defects in the gate oxide layer 3, and improving the quality of the gate oxide layer 3.

[0070] Considering that the implantation depth of pentavalent and / or trivalent elements mainly depends on the implantation temperature and implantation time, in order to regulate the diffusion of pentavalent and / or trivalent elements to the interface between the gate oxide layer 3 and the SiC epitaxial wafer, for example, the activation annealing temperature is 900–1100°C (e.g., 900°C, 930°C, 970°C, 0°C, 0°C, or 1100°C, etc.), and the activation annealing time is 30–120 min (e.g., 30 min, 55 min, 70 min, 95 min, min, or 120 min, etc.). Thus, by limiting the activation annealing temperature and activation annealing time within the above ranges, the implantation depth of pentavalent and / or trivalent elements can be effectively controlled, enabling them to diffuse to the interface between the gate oxide layer 3 and the SiC epitaxial wafer.

[0071] For example, in the oxidation process of the SiC epitaxial wafer, the oxidation process is dry oxygen oxidation or wet oxygen oxidation, the oxidation atmosphere is an oxygen atmosphere, and the oxidation temperature is 1100 to 1450°C, thereby forming an oxide layer on the upper and lower surfaces of the SiC epitaxial wafer.

[0072] In other words, the oxidation treatment of SiC epitaxial wafers described above includes the following steps:

[0073] In an oxygen atmosphere, SiC epitaxial wafers are subjected to high-temperature dry oxygen oxidation treatment or high-temperature wet oxygen oxidation treatment at 1100–1450°C.

[0074] Furthermore, in step 4 of forming a polycrystalline silicon layer on the oxide layer surface of the upper surface, a plasma-enhanced chemical vapor deposition (PECVD) method is used to form the polycrystalline silicon layer 4.

[0075] Specifically, the structure of the SiC epitaxial wafer includes a stacked SiC substrate 1 and an epitaxial layer 2, wherein the epitaxial layer 2 is made of 3C-SiC / 4H-SiC / 6H-SiC material with higher breakdown electric field strength and higher carrier mobility. Accordingly, providing a SiC epitaxial wafer includes the following steps:

[0076] Provide a SiC substrate 1;

[0077] An epitaxial layer 2 is formed on the upper surface of the SiC substrate 1. The epitaxial layer 2 is made of 3C-SiC / 4H-SiC / 6H-SiC.

[0078] It is understood that the above preparation method can be used for MOS devices having a gate oxide layer 3 and a polysilicon electrode 5 structure. For example, the above MOS device can be a MOSFET device or a MOS capacitor device.

[0079] Specifically, for MOSFET devices, after forming the polysilicon electrode 5, the following steps are also included:

[0080] The oxide layer 7 on the lower surface is removed by photoresist etching (e.g., dry etching) or corrosion (e.g., wet corrosion);

[0081] A drain electrode 6 is formed on the lower surface of SiC.

[0082] This is because, during the oxidation process of SiC epitaxial wafers, oxide layers inevitably form on the upper and lower surfaces of the SiC epitaxial wafers. The oxide layer on the upper surface can serve as the gate oxide layer 3, and the oxide layer 7 on the lower surface needs to be removed before the drain electrode 6 is formed.

[0083] Similarly, for MOS capacitors, after forming the polysilicon electrode 5, the following steps are also included:

[0084] The oxide layer 7 on the lower surface is removed by etching (e.g., dry etching) or corrosion (e.g., wet corrosion);

[0085] A back electrode 6' is formed on the lower surface of SiC.

[0086] This is because, during the oxidation process of SiC epitaxial wafers, oxide layers inevitably form on the upper and lower surfaces of the SiC epitaxial wafers. The oxide layer on the upper surface can serve as the gate oxide layer 3. However, the presence of the oxide layer 7 on the lower surface will affect the formation of the back electrode 6'. Therefore, the oxide layer 7 on the lower surface needs to be removed before the back electrode 6' is formed.

[0087] It should be noted that the above-mentioned dry etching can be performed using an etching machine, while wet etching can be performed using a hydrofluoric acid solution with a molar concentration of 5-15% as the etching solution.

[0088] To reduce the impact of impurities on the surface of SiC epitaxial wafers on subsequent processes, the following steps are included before the oxidation treatment of the SiC epitaxial wafers:

[0089] The SiC epitaxial wafer is cleaned.

[0090] In this way, the cleaning process can sequentially remove contaminants such as organic contaminants, natural oxide films, and metal particles from SiC epitaxial wafers. Specifically, firstly, organic contaminants on the surface of the SiC epitaxial wafer are removed to prevent them from partially obscuring the surface, thus making it easier to remove naturally formed oxide films and metal particles. Secondly, the oxide layer acts as a "contamination trap," introducing epitaxial defects; the cleaning process can dissolve the oxide film. Finally, particulate metal contaminants are removed, and the surface of the silicon carbide wafer is passivated.

[0091] Specifically, the above cleaning includes the following steps:

[0092] First, the SiC epitaxial wafer is immersed in a mixture of 98wt% concentrated sulfuric acid and 27wt% hydrogen peroxide (volume ratio 1:1-2) and heated in a water bath at 90-100°C for 15-18 minutes. After rinsing with deionized water, it is dried with nitrogen. Next, the SiC epitaxial wafer is immersed in a mixture of 28wt% ammonia and 27wt% hydrogen peroxide (volume ratio 1:1-1.2) and heated in a water bath for 15-20 minutes. After rinsing with deionized water, it is dried with nitrogen. Finally, the SiC epitaxial wafer is immersed in a mixture of 10wt% hydrochloric acid and 27wt% hydrogen peroxide (volume ratio 1:1-1.5) and heated in a water bath at 90-100°C for 15-20 minutes. After rinsing with deionized water, it is dried with nitrogen.

[0093] It should be noted that the above cleaning process is only an example of the RCA cleaning process, and other standard RCA processes are also applicable to the cleaning process of this invention.

[0094] Example 1

[0095] This embodiment provides a silicon carbide MOS device and its fabrication method. See [link to documentation]. Figure 2 It includes the following steps:

[0096] Step S201: Use a 3C-SiC / 4H-SiC / 6H-SiC SiC substrate 1 and a 3C-SiC / 4H-SiC / 6H-SiC material with higher breakdown electric field strength and higher carrier mobility as an epitaxial layer 2.

[0097] Step S202: Cleaning the SiC epitaxial wafer using the standard RCA cleaning method. Specifically: First, immerse the SiC epitaxial wafer in a 1:1 mixture of 98wt% concentrated sulfuric acid and 27wt% hydrogen peroxide, heat in a water bath at 90°C for 15 minutes, rinse with deionized water, and dry with N2; then, immerse the SiC epitaxial wafer in a 1:1 mixture of 28wt% ammonia and 27wt% hydrogen peroxide, heat in a water bath for 15 minutes, rinse with deionized water, and dry with N2; finally, immerse the SiC epitaxial wafer in a 1:1 mixture of 10wt% hydrochloric acid and 27wt% hydrogen peroxide, heat in a water bath at 90°C for 15 minutes, rinse with deionized water, and dry with N2.

[0098] Step S203: Use nitrogen (N2) to purge the air from the oxidation furnace. Under N2 protection, place the cleaned SiC epitaxial wafer into a quartz boat and slowly push it into the constant temperature zone of the oxidation furnace at an environment of 700°C. The constant temperature zone is heated at a rate of 20°C / min. When the temperature reaches 1200°C, it is then increased to the specified oxidation temperature at a rate of less than 10°C / min. At the same time, oxygen is slowly introduced. In a pure dry oxygen atmosphere, the SiC epitaxial wafer is oxidized to form an oxide layer on the upper surface with a thickness of 40-60 nm and an oxide layer on the lower surface with a thickness of 400-600 nm. The oxide layer on the upper surface serves as the gate oxide layer 3.

[0099] Step S204: Turn off the oxygen and cool the constant temperature zone under nitrogen protection until it reaches the equipment maintenance temperature, then remove it.

[0100] Step S205: Grow a layer of polycrystalline silicon of about 8000 Å on the surface of the above sample, perform polycrystalline silicon ion implantation process (implanting elements are pentavalent and / or trivalent elements), perform ion activation process, and perform activation annealing in an atmosphere such as oxygen or nitrogen at a temperature between 900-1100 and a time of 30-120 minutes, depending on the temperature.

[0101] Step S206: Form the front polycrystalline silicon electrode 5 using photolithography and etching processes. Specifically, the SiC sample can be placed in an HMDS oven for 15 minutes, and photoresist can be coated on the surface of the polycrystalline silicon electrode 5; then the SiC epitaxial wafer is pre-baked at 100°C for 2 minutes; after cooling for 2 minutes, the first electrode pattern is etched on the photoresist using the corresponding photomask of the first polycrystalline silicon electrode 5, wherein the pre-exposure time is 7 seconds and the reverse exposure time is 65 seconds; then the SiC sample is immersed in the developer for 75 seconds, and then subjected to hot plate hardening at 115°C for 90 seconds to expose the area outside the pattern of the first electrode; the polycrystalline silicon electrode 5 is formed using a dry etching process.

[0102] Step S207: Coat the polysilicon electrode 5 of the SiC epitaxial wafer with photoresist for protection, and use a hydrofluoric acid solution with a molar concentration of 5-10% as an etchant to etch the oxide layer on the lower surface. Then, use a sputtering / evaporation process to sputter / evaporate an Al metal layer with a thickness of 300nm on the lower surface as the drain electrode 6 or back electrode 6'. Use acetone solution to remove the photoresist on the front side, and then use fresh acetone, ethanol, and deionized water in sequence for ultrasonic cleaning for 5 minutes. Finally, blow dry with nitrogen to complete the silicon carbide MOS device.

[0103] For testing silicon carbide MOS devices, see [link to documentation]. Figures 4 to 6 .

[0104] Figure 4This is a comparison of the flat-band voltage and accumulation region voltage curves of the silicon carbide MOS device prepared in Example 1 and the existing Al electrode sample. Figure 4 It can be seen that the plateau voltage of the Al electrode sample drifts as the voltage applied to the accumulation region increases during the test, with a drift rate of 37%, while the plateau voltage of the silicon carbide MOS device prepared in this embodiment remains basically unchanged.

[0105] Figure 5 The interface state density curve of the silicon carbide MOS device prepared in Example 1 is obtained using the high- and low-frequency method. Figure 5 It can be seen that the interface state density of the silicon carbide MOS device prepared in this embodiment is significantly smaller than that of the Al electrode sample, indicating that the silicon carbide MOS device prepared in this embodiment has fewer defects at the interface.

[0106] Figure 6 The above are the SIMS spectra of N and P elements in the silicon carbide MOS device prepared in Example 1. Figure 6 It can be seen that by adjusting the activation annealing temperature and time, N and P elements can diffuse to the interface between the gate oxide layer and the SiC epitaxial wafer. SIMS analysis results show that, due to the diffusion of N and P elements, similar to previous studies on NO and POCl3 gas purification, a low interface state density is observed.

[0107] Example 2

[0108] This embodiment provides a silicon carbide MOS device and its fabrication method. See [link to documentation]. Figure 2 It includes the following steps:

[0109] Step S201: Use a SiC substrate 1 and a 4H-SiC material with higher breakdown electric field strength and higher carrier mobility as an epitaxial layer 2.

[0110] Step S202: Cleaning the SiC epitaxial wafer using the standard RCA cleaning method. Specifically: First, immerse the SiC epitaxial wafer in a 1:1 mixture of 98wt% concentrated sulfuric acid and 27wt% hydrogen peroxide, heat in a water bath at 90°C for 15 minutes, rinse with deionized water, and dry with N2; then, immerse the SiC epitaxial wafer in a 1:1 mixture of 28wt% ammonia and 27wt% hydrogen peroxide, heat in a water bath for 15 minutes, rinse with deionized water, and dry with N2; finally, immerse the SiC epitaxial wafer in a 1:1 mixture of 10wt% hydrochloric acid and 27wt% hydrogen peroxide, heat in a water bath at 90°C for 15 minutes, rinse with deionized water, and dry with N2.

[0111] Step S203: Use nitrogen (N2) to purge the air from the oxidation furnace. Under N2 protection, place the cleaned SiC epitaxial wafer into a quartz boat and slowly push it into the constant temperature zone of the oxidation furnace at an environment of 700°C. The constant temperature zone is heated at a rate of 20°C / min. When the temperature reaches 1400°C, it is then increased to the specified oxidation temperature at a rate of less than 10°C / min. At the same time, oxygen is slowly introduced. In a pure dry oxygen atmosphere, the SiC epitaxial wafer is oxidized to form an oxide layer on the upper surface with a thickness of 58-60 nm and an oxide layer on the lower surface with a thickness of 500-600 nm. The oxide layer on the upper surface serves as the gate oxide layer 3.

[0112] Step S204: Turn off the oxygen and cool the constant temperature zone under nitrogen protection until it reaches the equipment maintenance temperature, then remove it.

[0113] Step S205: Grow a layer of polycrystalline silicon of about 8000 Å on the surface of the above sample, perform polycrystalline silicon ion implantation process (implanting elements are pentavalent and / or trivalent elements), perform ion activation process, and perform activation annealing in an atmosphere such as oxygen or nitrogen at a temperature of 1050℃ for 45 minutes.

[0114] Step S206: Form the front polycrystalline silicon electrode 5 using photolithography and etching processes. Specifically, the SiC sample can be placed in an HMDS oven for 15 minutes, and photoresist can be coated on the surface of the polycrystalline silicon electrode 5; then the SiC epitaxial wafer is pre-baked at 100°C for 2 minutes; after cooling for 2 minutes, the first electrode pattern is etched on the photoresist using the corresponding photomask of the first polycrystalline silicon electrode 5, wherein the pre-exposure time is 7 seconds and the reverse exposure time is 65 seconds; then the SiC sample is immersed in the developer for 75 seconds, and then subjected to hot plate hardening at 115°C for 90 seconds to expose the area outside the pattern of the first electrode (other standard photolithography processes are also applicable); the polycrystalline silicon electrode 5 is formed using a dry etching process.

[0115] Step S207: The polysilicon electrode 5 of the SiC epitaxial wafer is protected with photoresist, and the lower surface oxide layer is etched with a hydrofluoric acid solution with a molar concentration of 5-10%. Then, an Al metal layer with a thickness of 300nm is sputtered on the lower surface as the drain electrode 6 or back electrode 6'. The photoresist on the front side is removed with acetone solution, and then ultrasonically cleaned with fresh acetone, ethanol, and deionized water for 5 minutes in sequence. Finally, it is dried with nitrogen gas to complete the silicon carbide MOS device.

[0116] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a silicon carbide MOS device, characterized in that, Includes the following steps: Provide a SiC epitaxial wafer; The SiC epitaxial wafer is oxidized to form oxide layers on the upper and lower surfaces of the SiC epitaxial wafer. The oxide layer on the upper surface serves as the gate oxide layer, and a polysilicon layer is formed on the surface of the oxide layer on the upper surface. Ion implantation samples are obtained by implanting pentavalent and / or trivalent elements into a polycrystalline silicon layer. The ion-implanted sample is activated by annealing, which is an annealing process for polycrystalline silicon electrodes. This process allows pentavalent and / or trivalent elements to diffuse to the entire gate oxide layer and to the interface between the gate oxide layer and the SiC epitaxial wafer. The implanted pentavalent and / or trivalent elements form Si≡N and C≡N bonds with all the remaining C clusters and O vacancies in the gate oxide layer. The polycrystalline silicon layer is then patterned to form polycrystalline silicon electrodes, resulting in a silicon carbide MOS device. Before oxidizing the SiC epitaxial wafer, the following steps are also included: First, the SiC epitaxial wafer is immersed in a mixture of 98wt% concentrated sulfuric acid and 27wt% hydrogen peroxide (volume ratio 1:1~2) and heated in a water bath at 90~100℃ for 15~18 minutes. After rinsing with deionized water, it is dried with N2. Next, the SiC epitaxial wafer is immersed in a mixture of 28wt% ammonia and 27wt% hydrogen peroxide (volume ratio 1:1~1.2) and heated in a water bath for 15~20 minutes. After rinsing with deionized water, it is dried with N2. Finally, the SiC epitaxial wafer is immersed in a mixture of 10wt% hydrochloric acid and 27wt% hydrogen peroxide (volume ratio 1:1~1.5) and heated in a water bath at 90~100℃ for 15~20 minutes. After rinsing with deionized water, it is dried with N2.

2. The method for fabricating a silicon carbide MOS device according to claim 1, characterized in that, The activation annealing temperature is 900~1100℃, and the activation annealing time is 30~120min.

3. The method for fabricating a silicon carbide MOS device according to claim 1, characterized in that, The oxidation treatment is either dry oxygen oxidation or wet oxygen oxidation, and the oxidation treatment temperature is 1100~1450℃.

4. The method for fabricating a silicon carbide MOS device according to claim 1, characterized in that, The silicon carbide MOS device is a MOSFET device, and after forming the polycrystalline silicon electrode, the following steps are also included: Remove the oxide layer from the lower surface; A drain electrode is formed on the lower surface of SiC; Alternatively, the silicon carbide MOS device is a MOS capacitor, and after forming the polycrystalline silicon electrode, the following steps are also included: Remove the oxide layer from the lower surface; A back electrode is formed on the lower surface of SiC.

Images