An adaptive interlocking half-bridge drive circuit and half-bridge drive system

Abstract

This invention provides an adaptive interlocked half-bridge drive circuit and a half-bridge drive system. The adaptive interlocked half-bridge drive circuit includes: an interlock control circuit that generates an interlock control signal based on an input voltage source; and a logic drive circuit, including an interlock circuit whose enable terminal receives the interlock control signal. When the interlock control signal is in a first state, the interlock circuit is disabled, and the half-bridge circuit is allowed to shoot through. When the interlock control signal is in a second state, the interlock circuit is enabled, and the half-bridge circuit is not allowed to shoot through. This half-bridge drive circuit can enable the interlock circuit according to usage requirements, allowing the upper and lower transistors of the half-bridge circuit to shoot through for a portion of the time, thus expanding the application of the half-bridge circuit.

Description

Technical Field

[0001] This invention relates to the field of electronics, specifically but not limited to an adaptive interlocking half-bridge drive circuit and a half-bridge drive system. Background Technology

[0002] Currently, AC motor speed control topologies primarily employ three-phase or single-phase bridge inverter topologies, composed of one or more half-bridge units. These half-bridge units have complementary upper and lower switches that convert the input DC source into the required AC voltage or current to drive the motor. Traditional inverter half-bridge units require a DC voltage source as input and their drive logic avoids simultaneous activation of the upper and lower switches. Simultaneous activation of the upper and lower switches would cause a short circuit in the half-bridge unit, resulting in irreversible damage. Therefore, traditional half-bridge drive circuits strictly control the upper and lower transistors of the half-bridge circuit, preventing simultaneous activation. However, such half-bridge drive circuits limit the application of half-bridge units in certain fields.

[0003] This application provides a new half-bridge drive circuit and system for expanding the application functions of half-bridge circuits. Summary of the Invention

[0004] To address one or more problems in the prior art, this invention proposes an adaptive interlocking half-bridge drive circuit and a half-bridge drive system.

[0005] According to one aspect of the present invention, a half-bridge driving circuit is provided for driving a half-bridge circuit, the half-bridge circuit including a first switch and a second switch, wherein a first terminal of the first switch is coupled to an input voltage source, a second terminal of the first switch is coupled to a first terminal of the second switch, and a second terminal of the second switch is coupled to a reference ground. The half-bridge driving circuit includes: an interlock control circuit, the input terminal of which is coupled to the input voltage source, and an output terminal of the interlock control circuit providing an interlock control signal, the interlock control signal being generated based on the input voltage source; and a logic driving circuit, the input terminal of which is coupled to the output terminal of the interlock control circuit, the two output terminals of the logic driving circuit being respectively coupled to the control terminals of the first switch and the second switch, wherein the logic driving circuit includes an interlock circuit having an enable terminal that receives the interlock control signal. When the interlock control signal is in a first state, the interlock circuit is disabled, and the first switch and the second switch are allowed to be turned on simultaneously. When the interlock control signal is in a second state, the interlock circuit is enabled, and the first switch and the second switch are not allowed to be turned on simultaneously.

[0006] Descriptions such as "its input terminal", "its first input terminal", and "its output terminal" do not imply that they only include the described input terminal or output terminal, but may also include input terminals or output terminals with other functions or connections.

[0007] In one embodiment, the interlock control circuit includes a comparison circuit for comparing an input voltage source with a reference threshold. When the input voltage source is less than a first reference threshold, the interlock control signal is in a first state.

[0008] In one embodiment, the first reference threshold is the reference ground voltage.

[0009] In one embodiment, the comparison circuit is a hysteresis comparison circuit.

[0010] In one embodiment, the logic driving circuit further includes a first driving amplifier circuit and a second driving amplifier circuit, wherein the interlocking circuit includes: a NAND gate, the first input of which is coupled to a first signal input, and the second input of which is coupled to a second signal input; a NOT gate, the input of which is coupled to an enable terminal of the interlocking circuit for receiving an interlocking control signal; an OR gate, the first input of which is coupled to the output of the NAND gate, and the second input of which is coupled to the output of the NOT gate; a first AND gate, the first input of which is coupled to a first signal input, the second input of which is coupled to the output of the OR gate, the output of which is coupled to the input of the first driving amplifier circuit, and the output of the first driving amplifier circuit is coupled to a first driving signal output; and a second AND gate, the first input of which is coupled to a second signal input, the second input of which is coupled to the output of the OR gate, the output of which is coupled to the input of the second driving amplifier circuit, and the output of the second driving amplifier circuit is coupled to a second driving signal output.

[0011] According to another aspect of the present invention, a half-bridge driving circuit is used to drive a half-bridge circuit, the half-bridge circuit including a first switching transistor and a second switching transistor, wherein a first terminal of the first switching transistor is coupled to an input voltage source, a second terminal of the first switching transistor is coupled to the first terminal of the second switching transistor, and a second terminal of the second switching transistor is coupled to a reference ground. The half-bridge driving circuit has a first signal input terminal, a second signal input terminal, an enable terminal, a first driving signal output terminal, and a second driving signal output terminal, wherein the first driving signal output terminal and the second driving signal output terminal are respectively used to couple to the control terminals of the first switching transistor and the second switching transistor, and the enable terminal receives an interlock control signal related to the input voltage source. The half-bridge driving circuit includes an interlock circuit, the first input terminal of which is coupled to the enable terminal, and the second input terminal of the interlock circuit is coupled to the first signal input terminal, interlocking... The circuit's third input terminal is coupled to the second signal input terminal; a first driving amplifier circuit, whose first input terminal is coupled to the first signal input terminal, and whose second input terminal is coupled to the output terminal of the interlock circuit, the output terminal of the first driving amplifier circuit controls the first switching transistor through the first driving signal output terminal; and a second driving amplifier circuit, whose first input terminal is coupled to the second signal input terminal, and whose second input terminal is coupled to the output terminal of the interlock circuit, the output terminal of the second driving amplifier circuit controls the second switching transistor through the second driving signal output terminal; when the interlock control signal at the enable terminal is in the first state, the interlock circuit is disabled, and the first and second switching transistors are allowed to be turned on simultaneously; when the interlock control signal at the enable terminal is in the second state, the interlock circuit is enabled, and the first and second switching transistors are not allowed to be turned on simultaneously.

[0012] In one embodiment, the half-bridge drive circuit as described in any of the above embodiments is used to drive the first half-bridge circuit and the second half-bridge circuit in the AC chopper circuit, wherein the first half-bridge circuit is coupled between a first terminal of the AC power supply and a reference ground, and the second half-bridge circuit is coupled between a second terminal of the AC power supply and a reference ground.

[0013] In one embodiment, when the voltage at the first terminal of the AC power supply is less than the voltage at the second terminal of the AC power supply, the first half-bridge circuit is allowed to pass through, but the second half-bridge circuit is not allowed to pass through; when the voltage at the first terminal of the AC power supply is greater than the voltage at the second terminal of the AC power supply, the second half-bridge circuit is allowed to pass through, but the first half-bridge circuit is not allowed to pass through.

[0014] In one embodiment, when the voltage at the first terminal of the AC power supply is less than the voltage at the second terminal of the AC power supply, the first half-bridge circuit is directly connected, and the second half-bridge circuit is complementaryly connected; when the voltage at the first terminal of the AC power supply is greater than the voltage at the second terminal of the AC power supply, the second half-bridge circuit is directly connected, and the first half-bridge circuit is complementaryly connected.

[0015] In one embodiment, the AC chopper circuit further includes an auxiliary power supply circuit having an input terminal, an output terminal, and a reference terminal, wherein the input terminal of the auxiliary power supply circuit is coupled to a first terminal or a second terminal of the AC power supply, the output terminal of the auxiliary power supply circuit is used to provide auxiliary power, and the reference terminal of the auxiliary power supply circuit is coupled to a reference ground.

[0016] According to another aspect of the present invention, a half-bridge drive system is provided, comprising a half-bridge drive circuit and a half-bridge circuit as described in any of the above embodiments.

[0017] According to another aspect of the present invention, an adaptive interlocking half-bridge drive circuit for a half-bridge circuit is proposed, wherein the state of the interlock control signal is controlled based on the input voltage of the half-bridge circuit. When the interlock control signal is in a first state, the interlock function of the adaptive interlocking half-bridge drive circuit is in a disabled state, and when the interlock control signal is in a second state, the interlock function of the adaptive interlocking half-bridge drive circuit is in an enabled state.

[0018] The half-bridge drive circuit and half-bridge drive system proposed in this invention can adaptively enable the interlock circuit according to the input voltage source state, realizing the adaptive interlock function of the half-bridge circuit to be enabled or disabled. It can control the upper and lower transistors of the half-bridge circuit to be either shoot-through or not, expanding the application functions of the half-bridge circuit. For example, it can be used to implement AC chopping with a simple structure, exhibiting high power factor and regulation accuracy, while also possessing high efficiency. Attached Figure Description

[0019] Figure 1 A schematic diagram of a half-bridge drive system according to an embodiment of the present invention is shown;

[0020] Figure 2 An embodiment of the present invention is shown for... Figure 1 A schematic diagram of the waveform of the signal.

[0021] Figure 3 A schematic diagram of a half-bridge drive system according to another embodiment of the present invention is shown;

[0022] Figure 4 A corresponding embodiment of the present invention is shown. Figure 3 A schematic diagram of the waveform of the signal.

[0023] Figure 5 A schematic diagram of an interlock control circuit according to an embodiment of the present invention is shown;

[0024] Figure 6 A schematic diagram of a logic driving circuit according to an embodiment of the present invention is shown;

[0025] Figure 7 A schematic diagram of an AC chopper circuit according to an embodiment of the present invention is shown;

[0026] Figure 8 A schematic diagram of an AC chopper circuit according to another embodiment of the present invention is shown;

[0027] Figure 9 A schematic diagram of a signal generation circuit 900 according to an embodiment of the present invention is shown;

[0028] Figure 10 A schematic diagram of an auxiliary power supply circuit 1000 according to an embodiment of the present invention is shown;

[0029] Figure 11 A corresponding embodiment of the present invention is shown. Figure 7 or Figure 8 A schematic diagram of the waveform of the signal. Detailed Implementation

[0030] To further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, and not for limiting the scope of the claims of the present invention.

[0031] The description in this section pertains to only a few typical embodiments, and the present invention is not limited to the scope of the embodiments described. Combinations of different embodiments, substitution of some technical features in different embodiments, and substitution of similar or identical prior art with some technical features in the embodiments are also within the scope of the description and protection of the present invention.

[0032] The terms "coupled" or "connected" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a connection through an electrically conductive medium like a conductor, which may contain parasitic inductance or capacitance. It can also be a connection through intermediate circuits or components described in the embodiments of this specification. Indirect connections may also include connections through other active or passive devices that achieve the same or similar function, such as connections through switches, signal amplification circuits, follower circuits, or other circuits or components. "Multiple" or "more" indicates two or more.

[0033] Figure 1A schematic diagram of a half-bridge drive system according to an embodiment of the present invention is shown. The half-bridge drive system includes a half-bridge circuit and a half-bridge drive circuit 10. The half-bridge circuit includes a first switch Q1 and a second switch Q2, wherein a first terminal of the first switch Q1 is coupled to an input voltage source VIN, a second terminal of the first switch Q1 is coupled to a first terminal of the second switch Q2, and a second terminal of the second switch Q2 is coupled to a reference ground RGND. The input voltage source VIN is also referred to as the input terminal of the half-bridge circuit and is used to provide input power. In the illustrated embodiment, the half-bridge drive circuit 10 has a reference terminal REF, a first drive signal output terminal HO, and a second drive signal output terminal LO, wherein the first drive signal output terminal HO and the second drive signal output terminal LO are respectively coupled to the control terminals of the first switch Q1 and the second switch Q2. The output terminal Vo of the half-bridge circuit can be coupled to a load or other circuit. The half-bridge drive circuit 10 is used to drive the first switch Q1 and the second switch Q2 in the half-bridge circuit. The half-bridge drive circuit 10 includes an interlock control circuit 11 and a logic drive circuit 12. The interlock control circuit 11 is coupled to the first terminal of the first switch Q1 via a reference terminal REF to couple to the input voltage source VIN. The interlock control circuit 11 provides an interlock control signal SS based on the input voltage source VIN. "Based on" does not exclude the possibility of further basing it on other signals besides the input voltage source. In one embodiment, when the input voltage source VIN drops to zero (reference ground RGND voltage), the interlock control signal SS switches to a first state. When the input voltage source VIN is greater than zero, the interlock control signal SS is in a second state. When the interlock control signal SS is in the first state (e.g., low level), the enable terminal EN of the logic drive circuit 12 of the half-bridge drive circuit 10 is invalid, the interlock function of the half-bridge drive circuit 10 is disabled, and the first switch Q1 and the second switch Q2 can be turned on simultaneously. When the interlock control signal SS is in the second state (e.g., high level), the interlock function of the half-bridge drive circuit 10 is enabled, and the first switch Q1 and the second switch Q2 cannot be turned on simultaneously. Therefore, the half-bridge driver circuit 10 implements the state of the interlock control signal SS based on the input voltage source VIN of the half-bridge circuit, and has an adaptive half-bridge drive interlock function. The logic driver circuit 12 has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal of the logic driver circuit 12 receives the input signal Vsin. The second input terminal of the logic driver circuit 12 is coupled to the output terminal of the interlock control circuit 11 to receive the interlock control signal SS. The first output terminal of the logic driver circuit 12 is coupled to the first drive signal output terminal HO. The second output terminal of the logic driver circuit 12 is coupled to the second drive signal output terminal LO. The logic driver circuit 12 controls the first switch Q1 and / or the second switch Q2 based on the input signal Vsin.The logic driver circuit 12 includes an interlock circuit 121. The interlock circuit 121 has an enable terminal EN, which is coupled to the second input terminal of the logic driver circuit 12 to receive an interlock control signal SS. When the interlock control signal SS is in a first state, the interlock circuit 121 is disabled, allowing the first switch Q1 and the second switch Q2 to be simultaneously turned on. When the interlock control signal SS is in a second state, the interlock circuit 121 is enabled, preventing the first switch Q1 and the second switch Q2 from being simultaneously turned on. The logic driver circuit 12 is used to selectively enable the interlock function of the half-bridge circuit based on the interlock control signal SS and the input signal Vsin, such as a pulse width modulation (PWM) signal, and selectively amplify the PWM signal into a first drive signal Vho and a second drive signal Vlo suitable for driving switches Q1 and Q2. This function overcomes the limitation of traditional half-bridge structures where the upper and lower transistors cannot be turned on simultaneously, and can be used to expand the functionality and application of half-bridge driver circuits.

[0034] Figure 2 A corresponding embodiment of the present invention is shown. Figure 1 A schematic diagram of the waveform of the signal. Figure 2 The interlock control signal SS, input signal Vsin, first drive signal Vho, and second drive signal Vlo are shown respectively. During the first time period T1, the interlock control signal SS, generated based on the input voltage source VIN, is in its first state (low level), which can be detected by checking whether the input voltage source VIN is equal to or less than zero. At this time, the interlock function of the interlock circuit 121 is not active, and the first switch Q1 and the second switch Q2 can be turned on simultaneously. Figure 2 In the illustrated embodiment, both the first drive signal Vho and the second drive signal Vlo are high, and the first switch Q1 and the second switch Q2 are simultaneously turned on. Of course, in other embodiments, during the first time period, the first switch Q1 and the second switch Q2 may also be simultaneously turned on only for a portion of the time period based on other logic drive signals. During the second time period T2, the interlock control signal SS generated based on the input voltage source VIN is in the second state (high level), which can be detected by checking whether the input voltage source VIN is greater than a reference threshold. At this time, the interlock control signal SS enables the interlock function of the interlock circuit 121, and the first switch Q1 and the second switch Q2 are mutually interlocked, preventing the first switch Q1 and the second switch Q2 from being simultaneously turned on. Figure 2 As shown in the embodiment, the first drive signal Vho and the second drive signal Vlo can be set to pulse width modulation signals with the same frequency and complementary phase according to the input pulse width modulation signal Vsin. In this way, the first switch Q1 and the second switch Q2 are complementaryly turned on. In one embodiment, during the second time phase T2, the first drive signal Vho and the second drive signal Vlo include a switching dead zone, during which the first switch Q1 and the second switch Q2 are simultaneously turned off, improving safety.

[0035] Figure 3 A schematic diagram of a half-bridge drive system according to another embodiment of the present invention is shown. The half-bridge drive circuit 30 in the half-bridge drive system has a first signal input terminal SHIN and a second signal input terminal SLIN, used to receive a first input signal Vhin and a second input signal Vlin. The two input signals Vhin and Vlin are amplified by the drive circuit in the logic drive circuit 32, respectively, and drive signals Vho and Vlo are provided at the first drive signal output terminal HO and the second drive signal output terminal LO of the half-bridge drive circuit, respectively, to drive the first switch Q1 and the second switch Q2. The interlock control circuit 31 generates an interlock control signal SS based on the input voltage source VIN, used to control whether the interlock circuit 321 in the logic drive circuit 32 allows the first drive signal Vho and the second drive signal Vlo to simultaneously turn on the first switch Q1 and the second switch Q2.

[0036] Figure 4 A corresponding embodiment of the present invention is shown. Figure 3 The waveform diagram of the signal is shown below. From top to bottom, they are the interlock control signal SS, input signals Vhin and Vlin, first drive signal Vho, and second drive signal Vlo. During the first time period T1, the input voltage source VIN at the input terminal of the half-bridge circuit meets a certain preset condition, such as being less than or reaching zero. The interlock control signal SS is at a low level, the interlock function is not active, and the first switch Q1 and the second switch Q2 are allowed to be turned on simultaneously. The waveforms of the first drive signal Vho and the second drive signal Vlo are the same as those of the input signals Vhin and Vlin. During the second time phase T2, if the input voltage source VIN at the input terminal of the half-bridge circuit is greater than a certain threshold, the interlock control signal SS is at a high level, the interlock function is enabled, and the first switch Q1 and the second switch Q2 are not allowed to be turned on simultaneously. Therefore, the period when the input signals Vhin and Vlin are both at a high level is blocked due to the activation of the interlock function. When the input signals Vhin and Vlin are both at a high level, the first drive signal Vho and the second drive signal Vlo are set to low values ​​at the same time, so that the first switch Q1 and the second switch Q2 are both turned off, thus avoiding simultaneous conduction.

[0037] Figure 5A schematic diagram of an interlock control circuit according to an embodiment of the present invention is shown. In this embodiment, the interlock control circuit includes a comparator circuit 51. The non-inverting input of the comparator circuit 51 is coupled to the input of the half-bridge circuit, i.e., the first terminal of the first switch Q1, to receive the input voltage source VIN. The inverting input of the comparator circuit 51 receives a reference threshold signal Vth. The output of the comparator circuit 51 provides an interlock control signal SS. The comparator circuit 51 compares the input voltage source VIN with the reference threshold Vth. When the input voltage source VIN is less than the reference threshold Vth, the interlock control signal SS is in a low-level state, i.e., a first state, which disables the interlock circuit, allowing the first and second switches of the half-bridge circuit to be turned on simultaneously. In a preferred embodiment, the reference threshold Vth is a zero-value signal, i.e., the reference ground RGND voltage, and the inverting input of the comparator circuit 51 is directly connected to the reference ground RGND. In one embodiment, the reference threshold Vth is a negative value. In one embodiment, the comparator circuit 51 includes a hysteresis comparator circuit. When the input voltage source VIN drops to the reference threshold Vth, the interlock control signal SS is in the first state. When the input voltage source rises to the second reference threshold Vth2, the comparator circuit 51 outputs a high-level interlock control signal SS to enable the interlock function. The second reference threshold Vth2 is greater than the threshold Vth, such as 500mV. In another embodiment, the interlock control circuit includes a first comparator circuit and a second comparator circuit. The first comparator circuit compares the input voltage source VIN with a first reference threshold. When the input voltage source VIN is less than the first reference threshold, the interlock control signal SS is in a first state, allowing the half-bridge circuits to be simultaneously turned on. The second comparator circuit compares the input voltage source VIN with the second reference threshold. When the input voltage source VIN is greater than the second reference threshold, the interlock control signal SS is in a second state, enabling the interlock function and preventing the half-bridge circuits from being simultaneously turned on. When the input voltage source VIN is less than the second reference threshold but greater than the first reference threshold, the interlock control circuit SS is in a third state, used to implement specific control over the half-bridge circuits, such as simultaneously turning off the first and second switches, or turning off the first switch and turning on the second switch. In one embodiment, the interlock control signal includes a first interlock control signal and a second interlock control signal, used to indicate the three states of the interlock control signal.

[0038] In one embodiment, the half-bridge drive circuit does not include an interlock control circuit, and the interlock control signal SS can be provided by other circuits. In this case, the reference terminal of the half-bridge drive circuit directly receives the interlock reference signal SS as the enable terminal of the interlock circuit.

[0039] Figure 6A schematic diagram of a logic driving circuit according to an embodiment of the present invention is shown. The logic driving circuit includes an interlock circuit 61, a first driving amplifier circuit 62, and a second driving amplifier circuit 63. The first driving amplifier circuit 62 and the second driving amplifier circuit 63 are respectively used to amplify the high-level value of the logic signal, providing a first driving signal Vho and a second driving signal Vlo suitable for driving the first switch Q1 and the second switch Q2. In the illustrated embodiment, the interlock circuit 61 includes a NAND gate 611, a NOT gate 612, an OR gate 613, a first AND gate 614, and a second AND gate 615, wherein the first input terminal of the NAND gate 611 is coupled to the first signal input terminal of the half-bridge driving circuit to receive the first input signal Vhin, the second input terminal of the NAND gate 611 is coupled to the second signal input terminal of the half-bridge driving circuit to receive the second input signal Vlin, and the output terminal of the NAND gate 611 is coupled to the first input terminal of the OR gate 613. The input of NOT gate 613 is coupled to the enable terminal of the interlock circuit to receive the interlock control signal SS. The output of NOT gate 612 is coupled to the second input of OR gate 613, and the output of OR gate 613 is coupled to the inputs of first AND gate 614 and second AND gate 615. The other input of first AND gate 614 is coupled to the first signal input terminal to receive the first input signal Vhin. The output of first AND gate 614 is coupled to the input of first driver amplifier circuit 62. The other input of second AND gate 615 is coupled to the second signal input terminal to receive the second input signal Vlin. The output of second AND gate 615 is coupled to the input of second driver amplifier circuit 63. When the interlock control signal SS is high, the interlock control signal SS enables interlock circuit 61, the output of NOT gate 612 is low, and the output of OR gate circuit 613 follows the output of NAND gate 611. If the first input signal Vhin and the second input signal Vlin are both high, then the NAND gate 611 outputs a low level, and the OR gate 613 outputs a low level, causing the first AND gate 614 and the second AND gate 615 to both output low levels. This avoids the possibility that the first driving signal Vho and the second driving signal Vlo are both high, and avoids the simultaneous conduction of the first switch Q1 and the second switch Q2 in the half-bridge circuit. When the interlock control signal SS is low, the NAND gate 612 outputs a high level, and the OR gate 613 also outputs a high level. The output of the first AND gate 614 follows the first input signal Vhin, and the output of the second AND gate 615 follows the second input signal Vlin. Then, the first driving amplifier circuit 62 and the second driving amplifier circuit 63 are used to amplify the first input signal Vhin and the second input signal Vlin, respectively, and are used to drive the first switch Q1 and the second switch Q2, respectively. Of course, the interlock circuit can also have other structures. In one embodiment, the half-bridge driving circuit includes Figure 6 The logic drive circuit shown does not include the circuit that generates the interlock control signal SS based on the input voltage source VIN.

[0040] Figure 7A schematic diagram of an AC chopper circuit according to an embodiment of the present invention is shown. The AC chopper circuit includes a switching circuit, a first half-bridge drive circuit 71, and a second half-bridge drive circuit 72. The switching circuit includes a first half-bridge circuit and a second half-bridge circuit. The first half-bridge circuit includes switching transistors Q1 and Q2, coupled between a first terminal 711 of the AC power supply Vac and a reference ground RGND. The second half-bridge circuit includes switching transistors Q3 and Q4, coupled between a second terminal 712 of the AC power supply Vac and a reference ground RGND. The output terminal 713 of the first half-bridge circuit is coupled to a first terminal of a load M, and the output terminal 714 of the second half-bridge circuit is coupled to a second terminal of the load M, forming an output voltage Vout across the load M. Each switching transistor may be connected in parallel with a body diode. Switches Q1-Q4 may include field-effect transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), or insulated-gate bipolar transistors (IGBTs). Preferably, the switching transistors Q1-Q4 include parasitic body diodes for asynchronous rectification. A first half-bridge drive circuit 71 drives the switching transistors Q1 and Q2 in the first half-bridge circuit, and a second half-bridge drive circuit 72 drives the switching transistors Q3 and Q4 in the second half-bridge circuit. The first half-bridge drive circuit 71 and the second half-bridge drive circuit 72 may each have the structure and function of the half-bridge drive circuits described in the above embodiments. In the illustrated embodiment, the first half-bridge drive circuit 71 includes a first interlock control circuit 711 and a first logic drive circuit 712. The first interlock control circuit 711 generates a first interlock control signal SS1 based on the voltage at the first terminal 711 of the AC power supply Vac, and the first logic drive circuit 712 controls the first switching transistor Q1 and the second switching transistor Q2 based on the pulse width modulation signal PWM and the first interlock control signal SS1. The second half-bridge drive circuit 72 includes a second interlock control circuit 721 and a second logic drive circuit 722. The second interlock control circuit 721 generates a second interlock control signal SS2 based on the voltage of the second terminal 712 of the AC power supply Vac. The second logic drive circuit 722 controls the third switch Q3 and the fourth switch Q4 based on the pulse width modulation signal PWM and the second interlock control signal SS2. Preferably, when the voltage at the first terminal 711 of the AC power supply Vac is equal to or less than zero relative to the reference ground RGND, that is, when the voltage at the first terminal 711 of the AC power supply Vac is less than the voltage at the second terminal 712 of the AC power supply Vac, the first interlock control signal SS1 is in the first state, the second interlock control signal SS2 is in the second state, the first half-bridge circuit is allowed to shoot through, that is, the switching transistors Q1 and Q2 are allowed to conduct simultaneously, and the second half-bridge circuit is not allowed to shoot through, that is, the switching transistors Q3 and Q4 are not allowed to be conducted simultaneously; when the voltage at the first terminal 711 of the AC power supply Vac is greater than the voltage at the second terminal 712 of the AC power supply Vac, the second half-bridge circuit is allowed to shoot through, and the first half-bridge circuit is not allowed to shoot through.

[0041] Figure 8 A schematic diagram of an AC chopper circuit according to another embodiment of the present invention is shown. Figure 7 Compared to the Chinese implementation, Figure 8 The first interlock control signal SS1 and the second interlock control signal SS2 are both generated by the signal generation circuit 81. The first half-bridge drive circuit 84 and the second half-bridge drive circuit 85 enable or disable the interlock circuit 841 in the first half-bridge drive circuit 84 and the interlock circuit 851 in the second half-bridge drive circuit 85 based on the first interlock control signal SS1 and the second interlock control signal SS2 generated by the signal generation circuit 81, respectively. The AC chopper circuit further includes an auxiliary power supply circuit 82, which generates a power supply voltage Vaux to power the signal generation circuit 81. Thus, Figure 8 Neither the first half-bridge drive circuit 84 nor the second half-bridge drive circuit 85 includes an interlock control circuit; they only include, for example,... Figure 7 The logic drive circuits 712 or 722 shown, the interlock circuit 841 in the half-bridge drive circuit 84 directly receives the first interlock control signal SS1 provided by the signal generation circuit 81 to control the first input signal PWM1 and the second input signal PWM2 received by the first half-bridge drive circuit 84, and selectively interlocks the switching transistors Q1 and Q2. The interlock circuit 851 in the half-bridge drive circuit 85 directly receives the second interlock control signal SS2 provided by the signal generation circuit 81 to control the first input signal PWM3 and the second input signal PWM4 received by the second half-bridge drive circuit 85, and selectively interlocks the switching transistors Q3 and Q4.

[0042] Figure 9 A schematic diagram of a signal generation circuit 900 according to an embodiment of the present invention is shown, which includes two comparison circuits 901 and 902 for generating a first interlock control signal SS1 and a second interlock control signal SS2, respectively.

[0043] Figure 10 A schematic diagram of an auxiliary power supply circuit 1000 according to an embodiment of the present invention is shown. The auxiliary power supply circuit 1000 has a first input terminal 1001, a second input terminal 1002, an output terminal 1003, and a reference terminal 1004. The first input terminal 1001 and the second input terminal 1002 of the auxiliary power supply circuit are respectively coupled to the first terminal 1011 and the second terminal 1012 of the AC power supply Vac. The output terminal 1003 of the auxiliary power supply circuit provides an auxiliary power supply Vaux for powering a signal generation circuit. The reference terminal RGND of the auxiliary power supply circuit is coupled to the reference ground RGND of the switching circuit to form a current loop between the input terminals 1001 / 1002 of the auxiliary power supply circuit, the reference terminal RGND of the auxiliary power supply circuit, the switching circuit, and the AC power supply Vac.

[0044] Figure 11 A corresponding embodiment of the present invention is shown. Figure 7 or Figure 8 The waveform diagram of the signal is shown below. From top to bottom, it shows the AC power supply Vac, the output voltage Vout, the first interlock control signal SS1, the second interlock control signal SS2, and the drive signals DV1-DV4 for the switching transistors Q1-Q4. The following will combine... Figure 8-11 The function of the AC chopper circuit is explained. Depending on the polarity of the input AC power supply Vac, the AC chopper control can include a first time period T1 and a second time period T2. In the first time period T1, the first switch Q1 and the second switch Q2 are allowed to conduct simultaneously, while the third switch Q3 and the fourth switch Q4 are not allowed to conduct simultaneously. In the second time period T2, the first switch Q1 and the second switch Q2 are not allowed to conduct simultaneously, while the third switch Q3 and the fourth switch Q4 are allowed to conduct simultaneously.

[0045] During the first time period T1, the AC power supply Vac > 0, and the voltage at the first terminal 811 of the AC power supply Vac is lower than the voltage at the second terminal 812 of the current power supply Vac. At this time, current flows through the second terminal 812 of the AC power supply Vac to the first input terminal of the auxiliary power supply, through the reference ground RGND, and through the body diodes of switching transistors Q2 and Q1 to the first terminal 811 of the AC power supply Vac. The voltage at the first terminal 811 of the AC power supply Vac is lower than the ground voltage RGND, and the voltage at the second terminal 812 of the AC power supply Vac is higher than a preset threshold. The first interlock control circuit SS1 is at a low level, and the second interlock control circuit SS2 is at a high level. The first interlock control signal SS1 being low allows the first switching transistor Q1 and the second switching transistor Q2 to conduct simultaneously, while the second interlock control signal SS2 being high disallows the third switching transistor Q3 and the fourth switching transistor Q4 to conduct simultaneously. Figure 11 As shown, in this stage, the first drive signal DV1 and the second drive signal DV2 are at a high level to simultaneously turn on the first switch Q1 and the second switch Q2, thereby reducing conduction losses and improving system efficiency. The third drive signal DV3 and the fourth drive signal DV4 are complementary pulse width modulation signals used to control the complementary conduction of the third switch Q3 and the fourth switch Q4, wherein the frequency of complementary conduction is higher than the frequency of the AC power supply Vac. Preferably, the frequency of the AC power supply is the power frequency, such as 50Hz, and the frequency of complementary conduction is higher than 500Hz. When the third switch Q3 is turned on, the fourth switch Q4 is turned off, and when the third switch Q3 is turned off, the fourth switch Q4 is turned on. The drive signal DV4 can also be a low value, and the fourth switch Q4 conducts through its body diode and current flows through it, causing the fourth switch Q4 to operate in a asynchronous rectification state.

[0046] During the first time period T2, when the AC power supply Vac < 0, the voltage at the first terminal 811 of the AC power supply is greater than the voltage at the second terminal 812 of the AC power supply Vac. At this time, the first interlock control signal SS1 is high, disallowing the first switch Q1 and the second switch Q2 from conducting simultaneously. The second interlock control signal SS2 is low, allowing the third switch Q3 and the fourth switch Q4 to conduct simultaneously. At this time, the first drive signal DV1 and the second drive signal DV2 are complementary pulse width modulation signals used to control the complementary conduction of the first switch Q1 and the second switch Q2. The third drive signal DV3 and the fourth drive signal DV4 are high, used to simultaneously turn on the third switch Q3 and the fourth switch Q4. The duty cycle of the pulse width modulation signal can be adjusted based on the feedback signal from the AC chopper circuit.

[0047] Through the above control, the output voltage Vout of the AC chopper circuit presents an AC chopper signal, which has a frequency and duty cycle corresponding to the pulse width modulation signal controlling the third switch Q3 or the first switch Q1. Furthermore, the envelope shape of the AC chopper signal Vout follows the shape of the AC power supply Vac. This generates a voltage signal at the output of the switching circuit with the same envelope and AC waveform as Vac, but whose average amplitude is proportional to the duty cycle, used to drive the load M. Because the envelope of the output voltage Vout corresponds to the shape of the AC power supply Vac, the system has a high power factor and avoids the problem of damage to the switching transistors when both the upper and lower transistors are simultaneously turned on, as is common in traditional half-bridge circuits.

[0048] In another embodiment, the AC chopper circuit further has a third time period operating mode between the first time period T1 and the second time period T2, to prevent the AC chopper circuit from breaking down the switching transistor when switching between the first time period T1 and the second time period T2, thereby enhancing system safety.

[0049] By selectively controlling the conduction of the upper and lower transistors of the half-bridge as described above, AC chopper technology can be implemented with a relatively simple structure to drive AC loads. Such an AC chopper circuit has a high power factor, high regulation accuracy, and high efficiency.

[0050] Besides being applied in Figures 7-11 In the AC chopper embodiment shown, enabling the interlock circuit in the half-bridge drive circuit to selectively control the simultaneous conduction of the upper and lower transistors in the half-bridge circuit can also be applied to other AC chopper schemes, such as three-phase induction motor drive topologies, or other types of non-AC chopper schemes.

[0051] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "non-inverting input" and "inverting input", "enable" and "enable disable" in the logic control involved in the specification or drawings can be interchanged or changed, and the same function or purpose as the above embodiment can be achieved by adjusting the subsequent logic control.

[0052] The description and application of the present invention herein are illustrative and not intended to limit the scope of the invention to the embodiments described above. The effects or advantages described in the specification may not be apparent in actual experimental cases due to uncertainties in specific conditions or other factors, and such descriptions are not intended to limit the scope of the invention. Variations and modifications to the embodiments disclosed herein are possible, and various substitutions and equivalents of the components in the embodiments are well known to those skilled in the art. It should be understood by those skilled in the art that the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the invention. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the invention.

Claims

1. A half-bridge driving circuit for driving a half-bridge circuit, the half-bridge circuit comprising a first switch and a second switch, wherein a first terminal of the first switch is coupled to an input voltage source, a second terminal of the first switch is coupled to a first terminal of the second switch, and a second terminal of the second switch is coupled to a reference ground, the half-bridge driving circuit comprising: an interlock control circuit having an input terminal coupled to the input voltage source, the interlock control circuit providing an interlock control signal at an output terminal, the interlock control signal being generated based on the input voltage source, the interlock control signal being in a first state when the input voltage source is less than a reference ground voltage; and a logic driving circuit having an input terminal coupled to the output terminal of the interlock control circuit, the logic driving circuit having two output terminals coupled to control terminals of the first switch and the second switch, respectively, wherein the logic driving circuit comprises an interlock circuit having an enable terminal, the enable terminal receiving the interlock control signal, the interlock circuit being disabled when the interlock control signal is in the first state, the first switch and the second switch being allowed to be turned on simultaneously, the interlock circuit being enabled when the interlock control signal is in a second state, the first switch and the second switch being not allowed to be turned on simultaneously.

2. The half-bridge driving circuit of claim 1, wherein the interlock control circuit comprises a comparison circuit for comparing the input voltage source with the reference ground voltage.

3. The half-bridge driving circuit of claim 2, wherein the comparison circuit is a hysteresis comparison circuit.

4. The half-bridge driving circuit of claim 1, wherein the logic driving circuit further comprises a first driving amplifier circuit and a second driving amplifier circuit, wherein the interlock circuit comprises: a NAND gate having a first input terminal coupled to a first input signal, and a second input terminal coupled to a second input signal; a NOT gate having an input terminal coupled to the enable terminal of the interlock circuit for receiving the interlock control signal; an OR gate having a first input terminal coupled to an output terminal of the NAND gate, and a second input terminal coupled to an output terminal of the NOT gate; a first AND gate having a first input terminal coupled to the first input signal, and a second input terminal coupled to an output terminal of the OR gate, the first AND gate having an output terminal coupled to an input terminal of the first driving amplifier circuit, the first driving amplifier circuit having an output terminal coupled to the control terminal of the first switch; and a second AND gate having a first input terminal coupled to the second input signal, and a second input terminal coupled to the output terminal of the OR gate, the second AND gate having an output terminal coupled to an input terminal of the second driving amplifier circuit, the second driving amplifier circuit having an output terminal coupled to the control terminal of the second switch.

5. The half-bridge driving circuit of any one of claims 1-4, for driving a first half-bridge circuit and a second half-bridge circuit in an AC chopper circuit, wherein the first half-bridge circuit is coupled between a first terminal of an AC power source and the reference ground, and the second half-bridge circuit is coupled between a second terminal of the AC power source and the reference ground. ​ ​ ​ ​ ​ ​ ​ ​ ​ 6. The half bridge drive circuit of claim 5, wherein when the voltage at the first terminal of the AC power source is less than the voltage at the second terminal of the AC power source, the first half bridge circuit is allowed to pass through and the second half bridge circuit is not allowed to pass through; when the voltage at the first terminal of the AC power source is greater than the voltage at the second terminal of the AC power source, the second half bridge circuit is allowed to pass through and the first half bridge circuit is not allowed to pass through.

7. The half bridge drive circuit of claim 5, wherein when the voltage at the first terminal of the AC power source is less than the voltage at the second terminal of the AC power source, the first half bridge circuit passes through and the second half bridge circuit is complementary on; when the voltage at the first terminal of the AC power source is greater than the voltage at the second terminal of the AC power source, the second half bridge circuit passes through and the first half bridge circuit is complementary on.

8. The half bridge drive circuit of claim 5, wherein the AC chopper circuit further comprises an auxiliary power supply circuit having an input terminal, an output terminal and a reference terminal, wherein the input terminal of the auxiliary power supply circuit is coupled to the first terminal of the AC power source or the second terminal of the AC power source, the output terminal of the auxiliary power supply circuit is used to provide an auxiliary power supply, and the reference terminal of the auxiliary power supply circuit is coupled to a reference ground.

9. A half bridge drive system comprising the half bridge drive circuit of any one of claims 1-4 and a half bridge circuit.

10. A half bridge drive circuit for driving a half bridge circuit, the half bridge circuit comprising a first switch and a second switch, wherein a first terminal of the first switch is coupled to an input voltage source, a second terminal of the first switch is coupled to a first terminal of the second switch, and a second terminal of the second switch is coupled to a reference ground, the half bridge drive circuit having a first signal input terminal, a second signal input terminal, an enable terminal, a first drive signal output terminal and a second drive signal output terminal, wherein the first drive signal output terminal and the second drive signal output terminal are respectively used to couple to a control terminal of the first switch and a control terminal of the second switch, and the enable terminal receives an interlock control signal related to the input voltage source, the interlock control signal being in a first state when the input voltage source is less than a voltage of the reference ground, the half bridge drive circuit comprising: an interlock circuit having a first input terminal coupled to the enable terminal, a second input terminal coupled to the first signal input terminal, and a third input terminal coupled to the second signal input terminal; a first drive amplifier circuit having an input terminal coupled to the first signal input terminal and an output terminal of the interlock circuit, and an output terminal for controlling the first switch through the first drive signal output terminal; and a second drive amplifier circuit having an input terminal coupled to the second signal input terminal and the output terminal of the interlock circuit, and an output terminal for controlling the second switch through the second drive signal output terminal; when the interlock control signal is in the first state, the interlock circuit is disabled and the first switch and the second switch are allowed to be turned on simultaneously, and when the interlock control signal is in a second state, the interlock circuit is enabled and the first switch and the second switch are not allowed to be turned on simultaneously. ​ ​ ​ ​ ​

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