A Programmable Integrated Circuit Automatic Test System and Method

Abstract

The present invention relates to a programmable integrated circuit automated test system and method. The system includes a host computer, a communication module, a main control FPGA, and a to-be-tested FPGA module. The host computer sends the code stream to be tested to the main control FPGA and controls it to burn the code stream to the to-be-tested FPGA module. In the burning stage, the host computer sends the code stream to the main control FPGA, and the main control FPGA then sends the code stream back to the host computer for verification. After the verification passes, the host computer sends a burning instruction to the main control FPGA to control the main control FPGA to burn the code stream to the to-be-tested FPGA. In the testing stage, the main control FPGA sends stimuli to the to-be-tested FPGA according to the instructions of the host computer, collects the responses of the to-be-tested FPGA, and generates instructions based on the responses and feeds them back to the host computer. In the loop traversal stage, the host computer controls the test process by judging the test results, and can automatically and batch-wise complete the burning and testing of multiple code streams.

Description

Technical Field

[0001] The present invention relates to an automated test system and method for programmable integrated circuits, belonging to the field of integrated circuit technology. Background Art

[0002] As a semi-custom circuit in the field of application-specific integrated circuits, a Field Programmable Gate Array (FPGA) has the advantages of high flexibility, low cost, low risk, low power consumption, etc. Since its emergence in the 1980s, it has gradually become one of the most dynamic and promising technologies in the field of electronic design and has been widely used in the fields of communication, data processing, network, military, aerospace, etc. With the development of the times, the gate level of FPGAs has now reached tens of millions or even hundreds of millions of gates, making it increasingly difficult to test FPGAs during the production and acceptance processes.

[0003] Currently, there are two main testing methods: board-level testing and testing based on an Automatic Test Equipment (ATE). Board-level testing uses a Printed Circuit Board (PCB) and a chip to build a simple working environment, burns the target logic of the FPGA into the chip, and then uses external devices to stimulate the chip and detect the response of the test chip. Board-level testing has a low cost and a simple and direct testing process, but the manual operation is cumbersome, and only one code stream can be "burned + tested" in one test, resulting in low efficiency. Testing based on ATE can complete the "burning + testing" of multiple code streams of the FPGA under test at one time, with fewer manual operations, high testing efficiency, and fast speed. However, ATE machines rely on imports, are expensive, and the shortage of machine numbers also affects the testing progress. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the deficiencies of the low efficiency of manual testing in board-level testing and the high cost of testing with ATE machines, and provide an automated test system and method for programmable integrated circuits to achieve automated board-level testing, improve the efficiency, and reduce the cost for mass production testing of FPGA chips.

[0005] The technical solution of the present invention is: a programmable integrated circuit automated test system, which includes a host computer, a communication module, a main control FPGA, and a FPGA module under test; the host computer communicates with the main control FPGA through the communication module.

[0006] Pre-store N test bitstream files of the FPGA module to be tested in the host computer; M test excitation generation and acquisition response modules are loaded in the master FPGA, and each test excitation generation and acquisition response module is matched with at least 1 test bitstream file to check whether the response of the FPGA module to be tested carrying the corresponding test bitstream is normal; both M and N are greater than or equal to 1;

[0007] In the programming stage, the host computer extracts one test bitstream file each time, sends the test bitstream to the master FPGA, and the master FPGA then sends the received test bitstream back to the host computer for verification. If the verification is qualified, the host computer sends a programming test instruction to the master FPGA. The programming test instruction includes the excitation type and the parameters of each excitation signal; otherwise, the host computer prompts the tester to check the bitstream file and the hardware connection;

[0008] After receiving the programming test instruction, the master FPGA programs the bitstream to the FPGA to be tested, and automatically enters the test stage after programming is completed;

[0009] In the test stage, according to the excitation type, the master FPGA enables the corresponding test excitation generation and acquisition response module to generate an excitation signal matching the test bitstream, sends the excitation signal to the FPGA to be tested, and acquires the response of the FPGA to be tested, and judges whether the FPGA to be tested is normal according to the response, and feeds back the judgment result to the host computer;

[0010] The host computer views the test result. If the FPGA to be tested is normal, it automatically extracts the next bitstream file, re-enters the programming stage, and automatically completes the programming and test of the next bitstream. If the FPGA to be tested is abnormal, it prompts the tester to check the FPGA to be tested.

[0011] If the test results output by the master FPGA all indicate that the FPGA to be tested is abnormal after testing the same test bitstream file three times, the host computer pops up a dialog box to display the information of the error bitstream to prompt the tester to check and process; once the test result output by the master FPGA indicates that the FPGA to be tested is normal, the programming and test of the next test bitstream are carried out until all test bitstreams are tested.

[0012] Preferably, the master FPGA is configured using a netlist file.

[0013] Preferably, the communication module uses a USB interface to communicate with the host computer and the master FPGA, and the working mode of the USB is the FIFO mode.

[0014] Preferably, the master FPGA includes a bitstream transceiver module, a FIFO buffer module, a selectMAP module, an instruction parsing and construction module, and M test excitation generation and acquisition response modules;

[0015] The bitstream transceiver module receives the test bitstream sent by the host computer, sends the test bitstream to the FIFO buffer module, and at the same time sends the test bitstream back to the host computer;

[0016] The FIFO buffer module stores the test bitstream in a first-in-first-out mode;

[0017] The selectMAP module reads the test bitstream from the FIFO buffer module and burns the test bitstream into the FPGA under test to configure the FPGA under test;

[0018] The instruction parsing and construction module parses the received test burn-in instruction, extracts the excitation type from it, enables the test excitation generation and acquisition response module corresponding to the excitation type, and feeds back the judgment result sent by the test excitation generation and acquisition response module to the host computer;

[0019] M test excitation generation and acquisition response modules, driven by the enable signal, each generate an excitation signal matching the test bitstream, collect the response of the FPGA under test, judge whether the FPGA under test is normal according to the response, and send the judgment result to the instruction parsing and construction module.

[0020] Preferably, the communication module is implemented using an FT232 chip, and the main control FPGA is implemented using a Spartan6 chip.

[0021] Another technical solution of the present invention is: a programmable integrated circuit automatic test method, the method comprising the following steps:

[0022] S1. The host computer extracts the test bitstream file, sends the test bitstream to the main control FPGA, and the main control FPGA then sends the received test bitstream back to the host computer for verification. If the verification is correct, the host computer sends a test burn-in instruction to the main control FPGA, and the test burn-in instruction includes the excitation type and each excitation signal; otherwise, the host computer prompts the tester to check the bitstream file and the hardware connection. After that, keeping the main control FPGA unchanged, repeat step S1;

[0023] S2. After receiving the test burn-in instruction, the main control FPGA burns the bitstream into the FPGA under test, and automatically enters the test phase after the burning is completed;

[0024] S3. In the test phase, the main control FPGA enables the corresponding test excitation generation and acquisition response module according to the excitation type. This module generates an excitation signal matching the test bitstream, sends the excitation signal to the FPGA under test, and collects the response of the FPGA under test. Judge whether the FPGA under test is normal according to the response, and feed back the judgment result to the host computer;

[0025] S4. The host computer checks the test results. If the FPGA under test is normal, the next bitstream file is automatically extracted and the programming stage is entered again. Steps S1 to S4 are repeated. If the FPGA under test is abnormal, the tester is prompted to check the FPGA under test.

[0026] If the test results output by the master FPGA indicate that the FPGA under test is abnormal after testing the same test bitstream file three times, the host computer pops up a dialog box to display the information of the error bitstream to prompt the tester to check and process it. Once the test results output by the master FPGA indicate that the FPGA under test is normal, the programming and testing of the next test bitstream are carried out until all test bitstreams are tested.

[0027] The master FPGA is configured using a netlist file.

[0028] The communication module communicates with the host computer and the master FPGA using a USB interface. The working mode of the USB is the FIFO mode.

[0029] The present invention has the following beneficial effects compared with the prior art:

[0030] (1). The present invention overcomes the deficiencies of manual operation and low test efficiency in board-level testing. Through the connection of the host computer, the master board and the test board, the tester can perform automated and batch programming and testing on the same chip, improving the test efficiency.

[0031] (2). Compared with ATE machines, the present invention only requires a host computer, a master FPGA, the FPGA under test module and corresponding connecting wires, etc., with low cost, avoiding the problems of limited number of ATE machines and tight machine time.

[0032] (3). The present invention configures the master FPGA based on the netlist, which can prevent source code leakage, and the netlist has stronger portability compared with the source code.

[0033] (4). The host computer of the present invention can perform automated and batch programming and testing on the chip, reducing manual operations and improving the test efficiency. Description of the Drawings

[0034] Figure 1 It is the module structure diagram of the programmable integrated circuit automated test system proposed by the present invention;

[0035] Figure 2 It is the stage flow chart of the programmable integrated circuit automated test system proposed by the present invention;

[0036] Figure 3 It is the flow chart of the host computer of the programmable integrated circuit automated test system proposed by the present invention. Specific Embodiments

[0037] To make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0038] As Figure 1 shown, a programmable integrated circuit automated test system based on netlist reuse provided by the present invention includes a host computer 101, a communication module 102, a main control FPGA 103, and a to-be-tested FPGA module 104. Figure 1 The connections between the modules are shown. The host computer 101 communicates with the main control FPGA 103 through the communication module 102. N test bitstream files of the to-be-tested FPGA module 104 are pre-stored in the host computer 101; the main control FPGA includes a bitstream transceiver module, a FIFO buffer module, a selectMAP module, an instruction parsing and construction module, and M test excitation generation and acquisition response modules. Each test excitation generation and acquisition response module is matched with at least 1 test bitstream file, that is, the test excitation generation and acquisition response module can generate the input signals required by the to-be-tested FPGA module carrying the corresponding test bitstream and check whether the response of the to-be-tested FPGA module carrying the corresponding test bitstream is normal; both M and N are greater than or equal to 1.

[0039] Figure 2 is a workflow diagram, which includes a programming stage 201, a testing stage 202, and a loop traversal stage 203. Figure 3 is a flowchart of the host computer 101.

[0040] In the programming stage 201, the host computer 101 first turns on the USB of the communication module 102 and sets it to the FIFO mode, that is, Figure 3 the state 301 in ; the host computer extracts one test bitstream file each time. The host computer 101 sends the bitstream to the main control FPGA 103, that is, the state 302; the main control FPGA 103 reads out the stored bitstream data and sends it to the host computer 101 through the USB. The host computer 101 checks the received bitstream against the pre-stored bitstream, that is, the state 303; if the check is qualified, a programming test instruction is sent to the main control FPGA. The programming test instruction includes the excitation type and the parameters of each excitation signal, and controls the main control FPGA 103 to program the bitstream to the to-be-tested FPGA module 104, that is, the state 305; otherwise, the host computer prompts the tester to check the bitstream file and the hardware connection, and then, under the current configuration of the main control FPGA 103, the programming operation is performed again, that is, the state 304.

[0041] In the programming stage 201, the bitstream transceiver module of the master FPGA 103 receives the bitstream and then caches it in the FIFO buffer module. The FIFO buffer module stores the test bitstream in a first-in-first-out mode. After the bitstream reception is completed, the master FPGA 201 sends the bitstream in the FIFO buffer module to the host computer 101 through the bitstream transceiver module for verification. After the verification passes, the host computer 101 sends a programming test instruction to the master FPGA 103. The instruction parsing and construction module parses it and reads the test bitstream from the FIFO buffer module through the SELECT MAP module to program the FPGA under test with the test bitstream to configure the FPGA under test.

[0042] In the test stage 202, the instruction parsing and construction module of the master FPGA 103 parses the received programming test instruction, extracts the excitation type from it, and enables the test excitation generation and response collection modules corresponding to the excitation type. The test excitation generation and response collection modules, driven by the enable signal, each generate an excitation signal matching the test bitstream, collect the response of the FPGA under test, and determine whether the FPGA under test is normal according to the response. The determination result is fed back to the host computer 101 through the instruction parsing and construction module.

[0043] In the loop traversal stage 203, the host computer 101 judges the test result, that is, status 306: if the bitstream test passes, the host computer 101 continues to judge whether all bitstreams have been tested, that is, status 308; if all bitstreams have been tested, the test ends and the host computer 101 prompts that the test is completed; if all bitstreams have not been tested, the host computer 101 will program the next bitstream to the master FPGA 103, that is, go to status 302. If the bitstream test fails, it is judged whether the bitstream has been tested three times, that is, status 307; if the bitstream fails to pass the test three times, the host computer 101 reports an error and prompts the information of the error bitstream to prompt the tester to check and process it, that is, go to status 304. After the problem is eliminated, the host computer 102 programs the bitstream to the master FPGA again, that is, go to status 302.

[0044] The master FPGA is configured using a netlist file, which can prevent source code leakage, and the portability of the netlist is also stronger than that of the source code.

[0045] Preferably, the communication module uses a USB interface to communicate with the host computer and the master FPGA, and the working mode of the USB is the FIFO mode.

[0046] Based on the above system, the present invention also provides a programmable integrated circuit automatic test method, which includes the following steps:

[0047] S1. The host computer extracts the test bitstream file, sends the test bitstream to the master FPGA, and the master FPGA then sends the received test bitstream back to the host computer for verification. If the verification is correct, the host computer sends a programming test instruction to the master FPGA. The programming test instruction includes the excitation type and each excitation signal; otherwise, the host computer prompts the tester to check the bitstream file and the hardware connection. After that, keep the master FPGA unchanged and repeat step S1;

[0048] S2. After receiving the programming test instruction, the master FPGA programs the bitstream to the FPGA under test. After the programming is completed, it automatically enters the test stage;

[0049] S3. In the test stage, according to the excitation type, the master FPGA enables the corresponding test excitation generation and acquisition response module. This module generates excitation signals matching the test bitstream, sends the excitation signals to the FPGA under test, and acquires the response of the FPGA under test. It judges whether the FPGA under test is normal according to the response and feeds back the judgment result to the host computer;

[0050] S4. The host computer checks the test result. If the FPGA under test is normal, it automatically extracts the next bitstream file and re-enters the programming stage, repeating steps S1 to S4. If the FPGA under test is abnormal, it prompts the tester to check the FPGA under test.

[0051] If the test results output by the master FPGA all indicate that the FPGA under test is abnormal after testing the same test bitstream file three times, the host computer pops up a dialog box to display the information of the error bitstream to prompt the tester to check and process it; once the test result output by the master FPGA indicates that the FPGA under test is normal, the programming and testing of the next test bitstream are carried out until all test bitstreams are tested.

[0052] Embodiment:

[0053] In a specific embodiment of the present invention, there are two types of excitation generation and acquisition response modules, namely, the excitation generation and acquisition response module for testing the interconnection unit and the excitation generation and acquisition response module for testing the CLB, IOB, and BRAM units.

[0054] When it is necessary to test the interconnection unit of the FPGA, the test bitstream uses a high-to-low level test, and the output pin outputs a falling edge when the test passes. The excitation generation and acquisition response module sends a high-to-low level to the FPGA under test and does not send a reset control signal. The excitation generation and acquisition response module uses edge detection. Detecting a falling edge means the test passes, and not detecting a falling edge means the test fails.

[0055] When testing the CLB, IOB, BRAM, etc. of the FPGA, the test bitstream is tested using a clock signal with a certain frequency (such as 20 MHz), and a reset control signal (such as a high reset control) needs to be sent. When the test passes, the output pin outputs a high level. The excitation generation and acquisition response module sends a clock signal and a reset control signal to the FPGA under test according to the instructions from the host computer. The reset control signal is generally active high, and the frequency of the clock signal is generally not higher than 50 MHz, depending on the specific design of the bitstream. The excitation generation and acquisition response module performs level detection. Detecting a high level indicates that the test passes, and detecting a low level indicates that the test fails.

[0056] Currently, there are three bitstreams: bitstream a for testing the test interconnection unit, bitstream b for testing the CLB, and bitstream c for testing the IOB. The test method for bitstream a is to send a high-to-low level and collect the falling-edge response; the test method for bitstream b is to send a 20 MHz clock and a high reset control signal and collect the high-level response; the test method for bitstream c is to send a 30 MHz clock and a low reset control signal and collect the high-level response.

[0057] The host computer first turns on the communication module USB and configures it in FIFO mode, and sends bitstream a to the master FPGA through the communication module.

[0058] The master FPGA returns bitstream a to the host computer through the communication module.

[0059] After the host computer verifies the returned bitstream a and the verification is successful, the host computer sends a programming test instruction 0x90EB11 to the master FPGA through the communication module. Here, 0x90EB is the frame header, and 0x11 indicates selecting the excitation generation and acquisition response module for the test interconnection unit.

[0060] The master FPGA programs bitstream a into the FPGA under test, sends a high-to-low level excitation, collects the response of the FPGA under test, and if a falling edge is detected, it is determined that the test of bitstream a is successful, and an instruction 0x11 is sent to the host computer to indicate that the test is successful.

[0061] After the host computer receives the information that the test is successful, it sends bitstream b to the master FPGA.

[0062] The master FPGA returns bitstream b to the host computer through the communication module.

[0063] After the host computer verifies the returned bitstream b and the verification is successful, the host computer sends a programming test instruction 0x 90EB22AA20 to the master FPGA through the communication module. Here, 0x 90EB is the frame header, 0x 22 indicates selecting the excitation generation and acquisition response module for testing units such as CLB, IOB, and BRAM, 0x AA indicates using a high reset control, and 0x 20 indicates that the clock frequency is 20 MHz.

[0064] The master FPGA burns the bitstream b to the FPGA under test, sends a 20MHz clock excitation and a high reset control signal, collects the response of the FPGA under test. If a high level is detected, it is determined that the bitstream b test is successful, and an instruction 0x11 is sent to the host computer to indicate that the test is successful.

[0065] After receiving the information that the test is successful, the host computer sends the bitstream c to the master FPGA.

[0066] The master FPGA sends the bitstream c back to the host computer through the communication module.

[0067] The host computer verifies the returned bitstream c. After the verification is successful, the host computer sends a programming test instruction 0x90EB22BB30 to the master FPGA through the communication module, where 0x90EB is the frame header, x22 indicates selecting the excitation generation and response acquisition module for testing units such as CLB, IOB, and BRAM, 0xBB indicates using a low reset control, and 0x30 indicates a clock frequency of 30MHz.

[0068] The master FPGA burns the bitstream c to the FPGA under test, sends a 30MHz clock excitation and a low reset control signal, collects the response of the FPGA under test. If a high level is detected, it is determined that the bitstream c test is successful, and an instruction 0x11 is sent to the host computer to indicate that the test is successful.

[0069] After all 3 bitstreams are tested, the host computer prompts the tester that the test is over.

[0070] In this embodiment, the communication module is implemented using an FT232 chip, and the master FPGA is implemented using a Spartan6 chip.

[0071] The content not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art.

Claims

1. A programmable integrated circuit automated test system, characterized in that It includes a host computer, a communication module, a main control FPGA, and a to-be-tested FPGA module; the host computer communicates with the main control FPGA through the communication module; N test bitstream files of the to-be-tested FPGA module are pre-stored in the host computer; M test excitation generation and response acquisition modules are loaded in the main control FPGA, and each test excitation generation and response acquisition module is at least matched with 1 test bitstream file, and is used to check whether the response of the to-be-tested FPGA carrying the corresponding test bitstream is normal; both M and N are greater than or equal to 1; In the programming stage, the host computer extracts one test bitstream file each time, sends the test bitstream to the main control FPGA, and the main control FPGA then sends the received test bitstream back to the host computer for verification. If the verification is qualified, the host computer sends a programming test instruction to the main control FPGA, and the programming test instruction includes the excitation type and the parameters of each excitation signal; otherwise, the host computer prompts the tester to check the test bitstream file and the hardware connection; After receiving the programming test instruction, the main control FPGA programs the bitstream to the to-be-tested FPGA, and automatically enters the test stage after the programming is completed; In the test stage, the main control FPGA enables the corresponding test excitation generation and response acquisition module according to the excitation type to generate an excitation signal matching the test bitstream, sends the excitation signal to the to-be-tested FPGA, and acquires the response of the to-be-tested FPGA, and judges whether the to-be-tested FPGA is normal according to the response, and feeds back the judgment result to the host computer; The host computer views the test result. If the to-be-tested FPGA is normal, it automatically extracts the next test bitstream file, re-enters the programming stage, and automatically completes the programming and test of the next bitstream. If the to-be-tested FPGA is abnormal, it prompts the tester to check the to-be-tested FPGA; If the test results output by the main control FPGA all indicate that the to-be-tested FPGA is abnormal after testing the same test bitstream file three times, the host computer pops up a dialog box to display the information of the error bitstream to prompt the tester to check and process; once the test result output by the main control FPGA indicates that the to-be-tested FPGA is normal, the programming and test of the next test bitstream are performed until all test bitstreams are tested.

2. The programmable integrated circuit automatic test system according to claim 1, characterized in that: The main control FPGA is configured using a netlist file.

3. The programmable integrated circuit automated test system according to claim 1, wherein: The communication module uses a USB interface to communicate with the host computer and the main control FPGA, and the working mode of the USB is the FIFO mode.

4. A programmable integrated circuit automated test system according to claim 1, characterized in that The main control FPGA includes a bitstream transceiver module, a FIFO buffer module, a selectMAP module, an instruction parsing and building module, and M test excitation generation and response acquisition modules; The bitstream transceiver module receives the test bitstream sent by the host computer, sends the test bitstream to the FIFO buffer module, and at the same time sends the test bitstream back to the host computer; The FIFO buffer module stores the test bitstream in a first-in first-out mode; The selectMAP module reads the test bitstream from the FIFO buffer module and programs the test bitstream to the to-be-tested FPGA to configure the to-be-tested FPGA; The instruction parsing and construction module parses the received programming test instruction, extracts the excitation type therefrom, enables the test excitation generation and acquisition response module corresponding to the excitation type, and feeds back the judgment result sent by the test excitation generation and acquisition response module to the host computer; M test excitation generation and acquisition response modules, driven by the enable signal, each generate an excitation signal matching the test bitstream, acquire the response of the FPGA under test, judge whether the FPGA under test is normal according to the response, and send the judgment result to the instruction parsing and construction module.

5. A programmable integrated circuit automated test system according to claim 1, characterized in that The communication module is implemented using an FT232 chip, and the master FPGA is implemented using a Spartan6 chip.

6. A test method for a programmable integrated circuit automated test system according to claim 1, characterized in that It includes the following steps: S1. The host computer extracts the test bitstream file, sends the test bitstream to the master FPGA, and the master FPGA then sends the received test bitstream back to the host computer for verification. If the verification is correct, the host computer sends a programming test instruction to the master FPGA. The programming test instruction includes the excitation type and each excitation signal; otherwise, the host computer prompts the tester to check the test bitstream file and the hardware connection. Then, keeping the master FPGA unchanged, repeat step S1; S2. After receiving the programming test instruction, the master FPGA programs the bitstream to the FPGA under test, and automatically enters the test phase after the programming is completed; S3. In the test phase, the master FPGA enables the corresponding test excitation generation and acquisition response module according to the excitation type. This module generates an excitation signal matching the test bitstream, sends the excitation signal to the FPGA under test, and acquires the response of the FPGA under test. Judge whether the FPGA under test is normal according to the response, and feed back the judgment result to the host computer; S4. The host computer checks the test result. If the FPGA under test is normal, automatically extract the next test bitstream file, re-enter the programming phase, and repeat steps S1 to S4. If the FPGA under test is abnormal, prompt the tester to check the FPGA under test; If the test results output by the master FPGA all indicate that the FPGA under test is abnormal after testing the same test bitstream file three times, the host computer pops up a dialog box to display the information of the error bitstream to prompt the tester to check and process it; once the test result output by the master FPGA indicates that the FPGA under test is normal, perform the programming and testing of the next test bitstream until all test bitstreams are tested.

7. The test method of a programmable integrated circuit automated test system according to claim 6, characterized in that: The master FPGA is configured using a netlist file.

8. The testing method of a programmable integrated circuit automated testing system according to claim 6, characterized in that: The communication module uses a USB interface to communicate with the host computer and the master FPGA, and the working mode of the USB is the FIFO mode.

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