Pin connection method, apparatus, device and medium for substrate

Abstract

The present disclosure provides a pin connection method, device, equipment and medium for a substrate, relates to the technical field of computer technology, and particularly relates to the field of integrated circuits, the field of chip packaging and the field of artificial intelligence. The implementation scheme is as follows: a reference pin in a first pin matrix of a substrate is determined; based on the determined reference pin, the following first process is performed: in the first pin matrix, at least one first adjacent pin meeting a preset condition of the reference pin is detected; in response to the detection that the adjacent signal pins of the reference pin include the first adjacent pin, a first mapping pin is acquired in a second pin matrix and the first adjacent pin and the first mapping pin are connected through a signal line; one of the at least one first adjacent pin is selected as an updated reference pin; and based on the updated reference pin, the first process is repeatedly performed until it is detected that the updated reference pin does not have a first adjacent pin meeting the preset condition.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to the fields of integrated circuits, chip packaging, and artificial intelligence. Specifically, it relates to a computer-executed method, apparatus, chip, electronic device, computer-readable storage medium, and computer program product for pin interconnection of a substrate. Background Technology

[0002] Artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies mainly include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0003] With the development of artificial intelligence (AI) technology, more and more applications are achieving results far exceeding those of traditional algorithms; deep learning is currently the core technology of AI. Deep learning is a data-intensive and computationally intensive algorithm, and also an algorithm that is rapidly iterating and developing.

[0004] Traditional general-purpose processing devices such as CPUs, GPUs, and DSPs are designed for general computing tasks. When handling deep learning applications, they suffer from low computational performance and efficiency, and cannot effectively support the large-scale deployment of deep learning algorithms in scenarios such as data centers. ASIC / FPGA-based dedicated acceleration devices for deep learning, with deeply customized hardware structures tailored to the computational characteristics of deep learning, can achieve higher computational performance and efficiency compared to traditional CPUs, GPUs, and DSPs.

[0005] The methods described in this section are not necessarily methods that had been previously conceived or adopted. Unless otherwise specified, no method described in this section should be assumed to be prior art simply because it is included in this section. Similarly, unless otherwise specified, the issues mentioned in this section should not be considered to be accepted in any prior art. Summary of the Invention

[0006] This disclosure provides a computer-executed method, apparatus, chip, electronic device, computer-readable storage medium, and computer program product for pin interconnection of a substrate.

[0007] According to one aspect of this disclosure, a computer-executed pin interconnection method for a substrate is provided, comprising: determining a reference pin in a first pin matrix of the substrate, wherein the reference pin has been interconnected; and performing a first process based on the determined reference pin, comprising: detecting at least one first adjacent pin of the reference pin that meets a preset condition in the first pin matrix; in response to detecting that the adjacent signal pins of the reference pin include the first adjacent pin, for each of the at least one first adjacent pin, obtaining a first mapping pin in a second pin matrix of the substrate and connecting the first adjacent pin and the first mapping pin via a signal line to complete the interconnection operation of the first adjacent pin; selecting one of the at least one first adjacent pins as an updated reference pin based on the number of first signal pins having each of the at least one first adjacent pins; and repeating the first process based on the updated reference pin until it is detected that the updated reference pin does not have a first adjacent pin that meets the preset condition.

[0008] According to another aspect of this disclosure, a computer-executed pin interconnection device for a substrate is provided, comprising: a first determining unit configured to determine a reference pin in a first pin matrix of the substrate, wherein the reference pin has been connected; and a first executing unit configured to execute a first process based on the determined reference pin, the first executing unit comprising: a detection subunit configured to detect at least one first adjacent pin of the reference pin in the first pin matrix that meets a preset condition; and an executing subunit configured to, in response to detecting that the adjacent signal pins of the reference pin include the first adjacent pin, perform a first process for at least one first phase... Each first adjacent pin in the adjacent pins obtains a first mapped pin in the second pin matrix of the substrate and connects the first adjacent pin and the first mapped pin through a signal line to complete the connection operation of the first adjacent pin; a first selection subunit is configured to select one of at least one first adjacent pins as the updated reference pin based on the number of first signal pins of each first adjacent pin of at least one first adjacent pin; and a second execution unit is configured to repeatedly execute the first process based on the updated reference pin until it is detected that the updated reference pin does not have a first adjacent pin that meets the preset conditions.

[0009] According to another aspect of this disclosure, a chip is provided in which the chip wafer is pin-connected on a chip packaging substrate according to the aforementioned pin interconnection method for a substrate executed by a computer.

[0010] According to another aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the aforementioned computer-executed pin interconnection method for a substrate.

[0011] According to another aspect of this disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to perform the aforementioned computer-executed pin interconnection method for a substrate.

[0012] According to another aspect of this disclosure, a computer program product is provided, including a computer program, wherein the computer program, when executed by a processor, implements the aforementioned computer-executed pin interconnection method for a substrate.

[0013] According to one or more embodiments of this disclosure, the overall design efficiency of pin connections can be improved.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0015] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of the claims. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0016] Figure 1 A schematic diagram of the channel structure from the controller to the memory chip in an AI chip according to an embodiment of the present disclosure is shown.

[0017] Figure 2 A schematic diagram of an exemplary system in which the various methods described herein may be implemented according to embodiments of the present disclosure is shown;

[0018] Figure 3 A flowchart is shown of a computer-executed pin interconnection method for a substrate according to an embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram of the pin distribution of a first pin matrix of a packaging substrate according to an exemplary embodiment of the present disclosure is shown.

[0020] Figure 5A schematic diagram of the pin distribution of a first pin matrix of a packaging substrate according to another exemplary embodiment of the present disclosure is shown;

[0021] Figure 6 A schematic diagram of the pin distribution of a first pin matrix of a packaging substrate according to another exemplary embodiment of the present disclosure is shown;

[0022] Figure 7 A schematic diagram of the pin distribution according to an exemplary embodiment of the present disclosure is shown;

[0023] Figure 8 A schematic diagram of the pin distribution according to another exemplary embodiment of the present disclosure is shown;

[0024] Figure 9 A schematic diagram of the pin distribution of a first pin matrix and a second pin matrix of a packaging substrate to be connected according to an exemplary embodiment of the present disclosure is shown.

[0025] Figure 10 A schematic diagram of the pin connections of a first pin matrix and a second pin matrix of a packaging substrate according to an exemplary embodiment of the present disclosure is shown.

[0026] Figure 11 A schematic diagram of the pin distribution of a first pin matrix and a second pin matrix of a PCB to be connected, according to an exemplary embodiment of the present disclosure, is shown.

[0027] Figure 12 A schematic diagram of the pin connections of a first pin matrix and a second pin matrix of a PCB according to an exemplary embodiment of the present disclosure is shown.

[0028] Figure 13 A schematic diagram of adjacent pin routing of an exemplary embodiment of the present disclosure is shown;

[0029] Figure 14 A comparison diagram showing the effects of pin connections according to embodiments of the present disclosure and those according to related technologies is provided.

[0030] Figure 15 A structural block diagram of a computer-executed pin interconnection device for a substrate according to an embodiment of the present disclosure is shown.

[0031] Figure 16 A structural block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure is shown. Detailed Implementation

[0032] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0033] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0034] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. Furthermore, the term "and / or" as used in this disclosure covers any one of the listed items and all possible combinations thereof.

[0035] To achieve higher computing power and real-time data processing, AI (Artificial Intelligence) chips are placing increasingly higher demands on DRAM (Dynamic Random Access Memory) interface speeds. GDDR6 (Graphics Double Data Rate 6), with its outstanding single-line speed of up to 16Gbps, has begun to be used in the DRAM interface design of high-performance AI chips. However, higher speeds also lead to tighter signal levels and timing margins, which poses new challenges to the signal integrity design of chip packaging and PCB (Printed Circuit Board).

[0036] Compared to previous DRAM interfaces, GDDR6's increased signal rate results in larger current (di / dt) and voltage (dv / dt) changes in the driving I / O signals. In the worst case, for a single 32-bit data width, this can lead to current or voltage fluctuations of 32*di / dt or 32*dv / dt, causing severe noise crosstalk between channels. This degrades the signal sampling level and timing window, increases the data transmission BER (Bit Error Rate), and prevents GDDR6 from functioning as designed.

[0037] The GDDR6 channel includes all physical structures on the packaging substrate and PCB through which the chip signals pass. Figure 1 A schematic diagram of the channel structure from the controller to the memory chip in an AI chip according to an embodiment of the present disclosure is shown.

[0038] Taking the channel structure from the controller to the memory chip in an AI chip as an example, it includes the following structures: the controller packaging substrate bump end (BUMP end), the controller packaging substrate trace, the controller packaging substrate ball end (BALL end), the connection solder ball from the controller ball end to the PCB, the controller end PCB fan-out via, the PCB inner layer trace, the memory chip end PCB fan-out via, the memory chip ball end to the PCB connection solder ball, the memory chip packaging substrate ball end (BALL end), the memory chip packaging substrate trace, and the memory chip packaging bump end (BUMP end).

[0039] In related technologies, most optimizations are made to a single structure or part of the structure in a channel similar to the one described above in order to reduce channel crosstalk, but the optimization effect is limited.

[0040] In related technologies, the connection and routing of the bump end to the ball end of the packaging substrate, and the connection and routing of the pins on both sides of the PCB, are usually designed first with the idea of ​​convenient routing. Then, low crosstalk pin connections are achieved through multiple simulations and iterative designs. This method requires a lot of labor costs. Moreover, for chips with hundreds of signal pins in parallel buses, the cycle of extracting crosstalk in the pin and via areas using a three-dimensional electromagnetic field simulator and iteratively optimizing based on the extraction results usually takes several weeks, resulting in low design efficiency.

[0041] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0042] Figure 2 A schematic diagram of an exemplary system 200 in which the various methods and apparatus described herein can be implemented according to embodiments of this disclosure is shown. Reference Figure 2 The system 200 includes one or more client devices 201, 202, 203, 204, 205, and 206, a server 220, and one or more communication networks 210 coupling the one or more client devices to the server 220. The client devices 201, 202, 203, 204, 205, and 206 can be configured to execute one or more applications.

[0043] In embodiments of this disclosure, server 220 may run one or more services or software applications that enable the execution of pin interconnection methods for a substrate.

[0044] In some embodiments, server 220 may also provide other services or software applications, which may include non-virtual environments and virtual environments. In some embodiments, these services may be provided as web-based services or cloud services, such as to users of client devices 201, 202, 203, 204, 205 and / or 206 under a Software as a Service (SaaS) model.

[0045] exist Figure 2 In the configuration shown, server 220 may include one or more components that implement the functions performed by server 220. These components may include software components, hardware components, or combinations thereof that can be executed by one or more processors. Users operating client devices 201, 202, 203, 204, 205, and / or 206 can sequentially interact with server 220 using one or more client applications to utilize the services provided by these components. It should be understood that various different system configurations are possible and may differ from system 200. Therefore, Figure 2 This is an example of a system used to implement the various methods described herein, and is not intended to be limiting.

[0046] Users can use client devices 201, 202, 203, 204, 205, and / or 206 to determine the pin distribution in the first and second pin matrices. The client devices can provide an interface that allows users to interact with the client devices. The client devices can also output information to the user via this interface. Although... Figure 2 Only six client devices are described, but those skilled in the art will understand that this disclosure can support any number of client devices.

[0047] Client devices 201, 202, 203, 204, 205, and / or 206 may include various types of computer devices, such as portable handheld devices, general-purpose computers (such as personal computers and laptops), workstation computers, wearable devices, smart screen devices, self-service terminal devices, service robots, gaming systems, thin clients, various messaging devices, sensors, or other sensing devices. These computer devices can run various types and versions of software applications and operating systems, such as Microsoft Windows, Apple iOS, UNIX-like operating systems, Linux or Linux-like operating systems (such as Google Chrome OS); or include various mobile operating systems, such as Microsoft Windows Mobile OS, iOS, Windows Phone, and Android. Portable handheld devices may include cellular phones, smartphones, tablets, personal digital assistants (PDAs), etc. Wearable devices may include head-mounted displays (such as smart glasses) and other devices. Gaming systems may include various handheld gaming devices, internet-enabled gaming devices, etc. Client devices are capable of executing various applications, such as various internet-related applications, communication applications (such as email applications), short message service (SMS) applications, and can use various communication protocols.

[0048] Network 210 can be any type of network well known to those skilled in the art, and can support data communication using any of a variety of available protocols (including but not limited to TCP / IP, SNA, IPX, etc.). By way of example only, one or more networks 210 can be a local area network (LAN), an Ethernet-based network, a token ring network, a wide area network (WAN), the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a blockchain network, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., Bluetooth, WIFI), and / or any combination of these and / or other networks.

[0049] Server 220 may include one or more general-purpose computers, special-purpose server computers (e.g., PC (personal computer) servers, UNIX servers, mid-range servers), blade servers, mainframe computers, server clusters, or any other suitable arrangement and / or combination. Server 220 may include one or more virtual machines running a virtual operating system, or other computing architectures involving virtualization (e.g., one or more flexible pools of logical storage devices that can be virtualized to maintain virtual storage devices for servers). In various embodiments, server 220 may run one or more services or software applications that provide the functionality described below.

[0050] The computing unit in server 220 can run one or more operating systems, including any of the aforementioned operating systems and any commercially available server operating system. Server 220 can also run any of a variety of additional server applications and / or middleware applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, etc.

[0051] In some implementations, server 220 may include one or more applications to analyze and merge data feeds and / or event updates received from users of client devices 201, 202, 203, 204, 205 and / or 206. Server 220 may also include one or more applications to display data feeds and / or real-time events via one or more display devices of client devices 201, 202, 203, 204, 205 and / or 206.

[0052] In some implementations, server 220 can be a server for a distributed system or a server integrated with blockchain. Server 220 can also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. A cloud server is a host product in the cloud computing service system, designed to address the shortcomings of traditional physical hosts and Virtual Private Server (VPS) services, such as high management difficulty and weak business scalability.

[0053] System 200 may also include one or more databases 230. In some embodiments, these databases may be used to store data and other information. For example, one or more of the databases 230 may be used to store information such as audio files and video files. Databases 230 may reside in various locations. For example, a database used by server 220 may be local to server 220, or it may be located remotely to server 220 and may communicate with server 220 via a network-based or dedicated connection. Databases 230 may be of different types. In some embodiments, the database used by server 220 may be, for example, a relational database. One or more of these databases may store, update, and retrieve data from and from the databases in response to commands.

[0054] In some embodiments, one or more of the databases 230 may also be used by an application to store application data. The databases used by the application may be of different types, such as key-value stores, object stores, or regular stores supported by a file system.

[0055] Figure 2The system 200 can be configured and operated in various ways to enable the application of the various methods and apparatus described in this disclosure.

[0056] According to embodiments of this disclosure, such as Figure 3 As shown, a computer-executed pin interconnection method for a substrate is provided, comprising: step S301, determining a reference pin in a first pin matrix of the substrate, wherein the reference pin has been interconnected; based on the determined reference pin, performing a first process, comprising: step S302, detecting at least one first adjacent pin of the reference pin that meets a preset condition in the first pin matrix; step S303, in response to detecting that the adjacent signal pins of the reference pin include a first adjacent pin, for each of the at least one first adjacent pins, obtaining a first mapping pin in a second pin matrix of the substrate and connecting the first adjacent pin and the first mapping pin through a signal line to complete the interconnection operation of the first adjacent pin; step S304, selecting one of the at least one first adjacent pins as an updated reference pin based on the number of first signal pins having each of the at least one first adjacent pins; and step S305, repeating the first process based on the updated reference pin until it is detected that the updated reference pin does not have a first adjacent pin that meets the preset condition.

[0057] Therefore, by first determining the reference pin on the reference side of the substrate, and then traversing its adjacent pins based on the reference pin, and connecting the adjacent pins according to a predetermined principle; then updating the reference pin and continuing the above operation until it is detected that the updated reference pin does not have a first adjacent pin that meets the preset conditions, the overall design efficiency of the pin connection can be improved by performing the pin connection of the substrate in the above manner.

[0058] In some embodiments, the above method can be used to design the interconnection of parallel bus channels for DRAM interfaces such as DDRx (xth generation dual data rate), LPDDRx (xth generation low power dual data rate), and GDDRx (xth generation graphics dual data rate).

[0059] According to some embodiments, the substrate can be a packaging substrate for packaging wafers.

[0060] Among them, the packaged chip can be a controller chip or a memory chip.

[0061] Taking the controller chip of an AI chip as an example, once its circuit structure is designed and determined, the pin distribution of the controller chip can be determined. The pin distribution is consistent with the bump distribution of the bump end (BUMP end) of the packaging substrate of the controller. Therefore, the bump end of the packaging substrate can be used as the reference side when connecting the pins. Then, the bumps on the bump end through which the signal passes are the signal pins on the reference side.

[0062] Correspondingly, the ball side of the packaging substrate can be used as the target side when connecting pins, and the ball point on the target side through which the signal passes is the signal pin of the target side.

[0063] In some embodiments, the chip may contain multiple chips with different functions, and these chips need to be connected in pairs. Accordingly, the package chip bump end corresponding to one chip can be used as the reference side, and the package chip bump end corresponding to another chip can be used as the target side.

[0064] According to some embodiments, the substrate can be a printed circuit board.

[0065] In some embodiments, the ball-point terminals of the controller chip and the memory chip are connected to the corresponding pads on the printed circuit board via solder balls, and signal lines are routed based on vias and inner layers.

[0066] In some embodiments, the pads corresponding to the ball-point terminals of the controller chip can be used as pins on the reference side of the printed circuit board, and the pads corresponding to the ball-point terminals of the memory chip can be used as pins on the target side of the printed circuit board.

[0067] In some embodiments, the reference side of the printed circuit board may also correspond to the pin matrix of control chips based on parallel buses, such as eMMC (Embedded Multi MediaCard), ONFI (Open NAND Flash Interface), and PCI (Peripheral Component Interconnect).

[0068] In some embodiments, the target side of the printed circuit board may also correspond to the pin matrix of the corresponding functional unit based on a parallel bus.

[0069] In some embodiments, the pins on the reference side can form a first pin matrix, and the pins on the target side can form a second pin matrix.

[0070] In some embodiments, both the first pin matrix and the second pin matrix include signal pins and ground pins. Furthermore, the distribution of signal pins and ground pins in the first pin matrix and the second pin matrix can be predetermined.

[0071] In some embodiments, the pin distribution of the first pin matrix of the packaging substrate corresponds to the pin distribution of the chip. Figure 4 , Figure 5 and Figure 6The diagrams show the pin distribution of the first pin matrix of the packaging substrate according to exemplary embodiments of the present disclosure. PS(i, j) represents the signal pin in the i-th row and j-th column (i, j are positive integers), and VSS represents the ground pin.

[0072] Understandably, the pin distribution in the first pin matrix of the packaging substrate can also be designed and determined by relevant technical personnel based on actual needs, and no restrictions are imposed here.

[0073] In some embodiments, the pin distribution of the second pin matrix of the packaging substrate, the first pin matrix and the second pin matrix of the printed circuit board can be preset. Figure 7 and Figure 8 Schematic diagrams of pin layouts according to exemplary embodiments of the present disclosure are shown. The pin layouts of the second pin matrix of the package substrate, the first pin matrix, and the second pin matrix of the printed circuit board can be, for example, as follows: Figure 7 or Figure 8 The pin distribution is shown below. Here, CS(i,j) represents the signal pin in the i-th row and j-th column (i,j are positive integers), and VSS represents the ground pin.

[0074] Understandably, the pin distribution of the second pin matrix of the packaging substrate, the first pin matrix and the second pin matrix of the printed circuit board can also be designed and determined by relevant technical personnel based on actual needs, and no restrictions are imposed here.

[0075] In some embodiments, the number of signal pins in the second pin matrix may be greater than or equal to the number of signal pins in the first pin matrix.

[0076] In some embodiments, the number of signal pins in the second pin matrix may be equal to the number of signal pins in the first pin matrix.

[0077] In some embodiments, before the first pin matrix and the corresponding second pin matrix are connected, a reference-side signal pin and a target-side signal pin can be selected first, and the two pins can be connected to determine the reference pin.

[0078] In some embodiments, the selection of the two pins can be randomized.

[0079] In some embodiments, a signal pin at a specific endpoint on the reference side can be selected (e.g., Figure 4 The reference pin is determined by identifying the pin PS(1,1) in the reference pin and randomly determining its mapped signal pin on the target side, then connecting them.

[0080] In some embodiments, a signal pin at a specific endpoint on the reference side can be selected (e.g., Figure 4In the context of pin PS(1,1), select a signal pin at a specific endpoint on the target side (e.g., ...). Figure 7 The pin CS(2,1) is used as the mapping pin, and the connection is made to determine the reference pin.

[0081] After determining the reference pin, you can first obtain the adjacent signal pins of the reference pin.

[0082] In some embodiments, adjacent signal pins of a reference pin can be determined by the distance between the reference pin and the reference pin. When the distance between a signal pin and the reference pin is less than a fifth preset distance, the signal pin is determined to be an adjacent signal pin of the reference pin.

[0083] In some exemplary embodiments, such as Figure 4 As shown, taking pin PS(2,2) as an example, a fifth preset distance can be preset so that PS(1,2), PS(1,3), PS(2,1), PS(2,3), PS(3,2) and PS(3,3) are their adjacent signal pins, while PS(1,1), PS(3,1), PS(1,4), PS(3,4) and signal pins further away are defined as non-adjacent signal pins.

[0084] In some exemplary embodiments, such as Figure 5 As shown, taking pin PS(2,2) as an example, a fifth preset distance can be preset so that PS(1,2), PS(2,1), PS(2,3) and PS(3,2) are their adjacent signal pins, while PS(1,1), PS(3,1), PS(1,3), PS(3,3) and signal pins further away are defined as non-adjacent signal pins.

[0085] In some exemplary embodiments, such as Figure 7 As shown, taking pin CS(2,2) as an example, a fifth preset distance can be preset so that CS(1,1), CS(1,2), CS(3,1) and CS(3,2) are its adjacent signal pins, while other signal pins are defined as non-adjacent signal pins.

[0086] In some exemplary embodiments, such as Figure 8 As shown, taking pin CS(2,2) as an example, a fifth preset distance can be preset so that CS(1,1), CS(2,1), CS(2,3), CS(3,1) and CS(3,2) are its adjacent signal pins, while other signal pins are defined as non-adjacent signal pins.

[0087] Understandably, relevant technical personnel can determine adjacent signal pins by adjusting the aforementioned fifth preset distance based on actual needs, and no restrictions are imposed here.

[0088] In some embodiments, after determining the adjacent signal pins of the reference pin, it is possible to detect whether each adjacent signal pin is connected and determine the unconnected adjacent signal pin as the first adjacent pin.

[0089] In some embodiments, in response to detecting that a first adjacent pin is included among the adjacent signal pins of a reference pin, a corresponding first mapping pin can be determined in a second pin matrix for each first adjacent pin. The first mapping pin is also a signal pin.

[0090] In some embodiments, for the currently processed first adjacent pin, at least one adjacent signal pin (i.e., at least one second adjacent pin) that is already connected can be obtained first, and the position of the corresponding mapping pin (i.e., the second mapping pin) of each of the at least one second adjacent pin can be determined. Subsequently, the position of the first mapping pin can be determined based on the positional relationship between the first mapping pin and each of the at least one second mapping pin.

[0091] In this case, the distance between each second adjacent pin and the first adjacent pin is less than the second preset distance.

[0092] In some embodiments, the second preset distance may be the same as the fifth preset distance described above.

[0093] In some embodiments, the first mapped pin and the second mapped pin may be spaced apart by at least one pin (signal pin or ground pin) in both the horizontal and vertical directions.

[0094] In some embodiments, the first mapped pin and the second mapped pin may be spaced apart by at least one pin (signal pin or ground pin) in the horizontal, vertical and diagonal directions.

[0095] According to some embodiments, obtaining a first mapped pin in a second pin matrix of a substrate includes: in response to obtaining a second signal pin in the second pin matrix, determining the second signal pin as a first mapped pin, wherein the distance between the second signal pin and each of the at least one second mapped pin is greater than a first preset distance, the at least one second mapped pin is a mapped pin corresponding to at least one second adjacent pin, and the distance between each of the at least one second adjacent pin and the first adjacent pin currently performing a wiring operation is less than a second preset distance.

[0096] Therefore, by setting a first preset distance to define the positional relationship between the first mapped pin and the second mapped pin, the process of determining the second mapped pin is simplified, while crosstalk between adjacent signal lines is further reduced, thereby improving the signal transmission quality of the overall signal path.

[0097] In some embodiments, when designing the pin layout of the second pin matrix, the distance between each signal pin can be set to be greater than a fourth preset distance. This design can reduce crosstalk between signal lines to a certain extent, but the area of ​​the substrate will also increase accordingly, and when the distance between the signal pins increases to a certain extent, the crosstalk between signal lines will no longer decrease significantly.

[0098] In some embodiments, by setting a fourth preset distance, signal pins that are horizontally or vertically adjacent to the second mapped pin can be defined as its adjacent signal pins, thereby avoiding the selection of these signal pins when determining the first mapped pin.

[0099] In some embodiments, by setting a fourth preset distance, signal pins that are horizontally, vertically, or diagonally adjacent to the second mapped pin can be defined as its adjacent signal pins, thereby avoiding the selection of these signal pins when determining the first mapped pin.

[0100] In some exemplary embodiments, such as Figure 7 As shown, taking pin CS(2,2) as an example, based on the fourth preset distance, CS(1,1), CS(1,2), CS(3,1) and CS(3,2) (the signal pins adjacent to its diagonal) can be defined as the adjacent signal pins of pin CS(2,2). When pin CS(2,2) is used as the second mapping pin, the selection of the first mapping pin of the first adjacent pipe currently being processed should avoid selecting the above-mentioned signal pins.

[0101] In some exemplary embodiments, such as Figure 8 As shown, taking pin CS(2,2) as an example, based on the fourth preset distance, CS(1,1), CS(2,1), CS(2,3), CS(3,1) and CS(3,2) (signal pins that are horizontally adjacent, vertically adjacent or diagonally adjacent to it) can be defined as adjacent signal pins of pin CS(2,2). When pin CS(2,2) is used as the second mapping pin, the selection of the first mapping pin of the first adjacent pipe currently being processed should avoid selecting the above-mentioned signal pins.

[0102] In some embodiments, by using the above conditions, it can be first determined whether the first adjacent pin includes a second signal pin that meets the above conditions. In response to obtaining one or more second signal pins that meet the above conditions for the first adjacent pin, a second signal pin can be randomly selected as the first mapping pin for the first adjacent pin.

[0103] In some embodiments, among the at least one second signal pin, one of the mapping pins that is closer to the reference pin can be selected as the first mapping pin of the first adjacent pin.

[0104] According to some embodiments, obtaining the first mapped pin in the second pin matrix further includes: in response to not obtaining the second signal pin in the second pin matrix, backtracking to the previous connection operation to redetermine the first mapped pin corresponding to the first adjacent pin processed in the previous connection operation; and in response to not being able to redetermine the first mapped pin or still not obtaining the second signal pin after redetermining the first mapped pin, continuing to backtrack the historical connection operation in sequence until the second signal pin is obtained.

[0105] Therefore, when a suitable first mapping pin cannot be found, the process backtracks to the previous wiring step and reselects the mapping pin (which must also meet the above requirements) before determining the first mapping pin in the current wiring step. If the mapping pin cannot be changed in the previous wiring step, or if the first mapping pin still cannot be obtained after changing it, the process continues to backtrack and execute the above operations until the second signal pin is obtained. This avoids performing simulation and wiring adjustments after completing all wiring, thereby further improving design efficiency.

[0106] In some embodiments, for a first pin matrix to be connected, each signal pin can be connected sequentially according to a certain order, and after each signal pin is connected, its mapping relationship with the mapped pin, routing information, and the second signal pin that meets the above conditions obtained by the new pin during connection are recorded.

[0107] When a first adjacent pin cannot obtain a second signal pin that meets the above conditions, the previous connection operation can be traced back according to the recorded information, and the second signal pin of the first adjacent pin processed in the previous operation can be obtained. If multiple second signal pins were obtained in the previous connection operation, a different second signal pin can be selected as the first mapping pin.

[0108] Subsequently, the second signal pin is retrieved again for the first adjacent pin currently being processed. When at least one second signal pin is retrieved, one of them can be selected as the first mapping pin of the previously processed first adjacent pin. If no second signal pin is retrieved, the process is backtracked to the previous connection operation and it is determined whether there is a replaceable second signal pin. If so, the first mapping pin in the previous connection is re-determined. If not, the connection operation needs to be backtracked further and the above method is executed until the second signal pin of the currently processed first adjacent pin is retrieved.

[0109] If only one second signal pin was obtained in the previous connection operation, the connection operation can be traced back further and the above method can be executed until the second signal pin of the first adjacent pin being processed is obtained.

[0110] In some embodiments, after determining the first mapped pins of all first adjacent pins of the current reference pin, the reference pin can be updated, and the above operations can continue based on the updated reference pin until it is detected that the updated reference pin does not have a first adjacent pin that meets the above preset conditions.

[0111] In some embodiments, one of the first adjacent pins of the reference pin can be selected as the updated reference pin based on the number of first signal pins possessed by each of the first adjacent pins of the reference pin. The distance between each of the first adjacent pins of the reference pin and the reference pin is less than the fifth preset distance mentioned above, and the distance between the first signal pin and its corresponding first adjacent pin is less than the sixth preset distance.

[0112] In some embodiments, the fifth preset distance may be the same as the sixth preset distance.

[0113] In some embodiments, the first adjacent pin of the reference pin that has the most first signal pins among all the first adjacent pins of the reference pin can be used as the updated reference pin.

[0114] Figure 9 A schematic diagram of the pin distribution of a first pin matrix and a second pin matrix of a package substrate to be connected according to an exemplary embodiment of the present disclosure is shown.

[0115] In some exemplary embodiments, such as Figure 9 As shown, the following procedure can be performed to... Figure 9 Connect the signal pins of the first and second pin matrices shown.

[0116] First, you can select a pin PS(1,1) located at the end of the first pin matrix of the BUMP end as the reference pin, and connect it with the CS(2,1) pin in the second pin matrix of the BALL end to generate the mapping pair PS(1,1)-CS(2,1).

[0117] After determining PS(1,1) as the reference pin, its adjacent signal pins are searched based on the fifth preset distance (the fifth preset distance can be a value that is greater than the distance between PS(1,1) and PS(1,2) and the distance between PS(1,1) and PS(2,1), but less than the distance between PS(1,1) and PS(2,2)). This allows us to obtain the two first adjacent pins, PS(1,2) and PS(2,1), which are not connected.

[0118] For PS(1,2), its second adjacent pin that is already connected is PS(1,1) (the second preset distance used for judgment is the same as the fifth preset distance). Therefore, at the BALL end, it is necessary to avoid selecting the signal pin adjacent to CS(2,1) (the second mapping pin) as the first mapping pin. The adjacent signal pin of the second mapping pin can be determined by the sixth preset distance. The sixth preset distance can be a value that is greater than the distance between CS(2,1) and CS(1,1) and less than the distance between CS(2,1) and CS(2,2) and the distance between CS(2,1) and CS(4,1).

[0119] In some embodiments, adjacent signal pin pairs can also be defined directly, thereby determining the adjacent signal pins of the second mapped pin based on the definition. For example, CS(2,1) and CS(1,1), CS(2,1) and CS(3,1), etc., can be defined as adjacent signal pin pairs.

[0120] Based on the above method, signal pins other than CS(1,1) and CS(3,1) (adjacent signal pins of CS(2,1)) can be identified as second signal pins, and the first mapping pin can be selected from them. For example, CS(5,2) can be selected as the first mapping pin and connected to generate the mapping pair PS(1,2)-CS(5,2).

[0121] For PS(2,1), its second adjacent pins that are already connected are PS(1,1) and PS(1,2). Accordingly, the signal pins other than CS(1,1), CS(3,1) (adjacent signal pins of CS(2,1)) and CS(4,2), CS(6,2) (adjacent signal pins of CS(5,2)) can be identified as the second signal pins, and the first mapping pin can be selected among them. For example, CS(4,1) can be selected as its first mapping pin and connected to generate the mapping pair PS(2,1)-CS(4,1).

[0122] Subsequently, the number of first adjacent pins of PS(1,2) and PS(2,1) can be obtained respectively. The first adjacent pins of PS(1,2) are PS(1,3) and PS(2,2), with a number of 2; the first adjacent pin of PS(2,1) is PS(2,2), with a number of 1. Then, PS(1,2) is used as the updated reference pin, and the connection operation of PS(1,3) and PS(2,2) is performed based on a similar operation as described above.

[0123] Subsequently, based on similar operations as described above, the reference pins are sequentially updated to PS(1,3), PS(1,4), PS(1,5), and PS(1,6), and the first adjacent pins of each reference pin are connected accordingly. When the reference pin is PS(1,6), its first adjacent pin is PS(2,6). After connecting PS(2,6), PS(2,6) can be used as the updated reference pin. At this point, since PS(2,6) cannot detect any further first adjacent pins that meet the preset conditions, the connection between the first pin matrix and the second pin matrix is ​​completed.

[0124] Figure 10 A schematic diagram of the pin connections of a first pin matrix and a second pin matrix of a packaging substrate according to an exemplary embodiment of the present disclosure is shown.

[0125] like Figure 10 As shown, in the signal lines obtained by the above method, for any two signal lines, if their two pins on the reference side (BUMP end) are adjacent, then their two pins on the target side (BALL end) are not adjacent; if their two pins on the reference side (BUMP end) are not adjacent, then their two pins on the target side (BALL end) can be either adjacent or not adjacent. That is, by connecting the pins using the above method, for any two signal lines, it is possible to ensure that their pins on at least one side are not adjacent to each other. This line structure can further reduce crosstalk between the two signal lines, thereby achieving overall crosstalk control based on the pins in the first and second pin matrices.

[0126] In some exemplary embodiments, the signal pin layout of the first pin matrix of the package substrate may be as follows: Figure 6 In the layout shown, the ground pin divides the signal pins in the first pin matrix into at least two regions. By detecting adjacent signal pins, it is impossible to detect the signal pins in the other region and connect them.

[0127] For example Figure 6 The layout shown can be connected using the method described above. First, [the following can be done]... Figure 6 PS(1,1) is determined as the reference pin, and based on a similar operation to the above method, the connection of each signal pin is performed, and finally PS(K,3) is used as the updated reference pin. At this time, the first adjacent pin that meets the preset conditions cannot be detected based on PS(K,3), but the first pin matrix still contains unconnected signal pins.

[0128] According to some embodiments, the above-described pin interconnection method for a substrate may further include: in response to the detection that the updated reference pin has a first adjacent pin that meets a preset condition and the first pin matrix still contains unconnected signal pins, performing a second process, including: selecting a first reference pin among the unconnected signal pins to redetermine the reference pin; determining a corresponding mapping pin for the first reference pin to connect the first reference pin and the corresponding mapping pin via signal lines; and repeating the first process and the second process based on the first reference pin until all signal pins in the first pin matrix are connected.

[0129] Therefore, when there are situations in the pin matrix where the spacing between signal pins is large or they are isolated by ground pins, resulting in a situation where the first adjacent pin is not detected but the first pin matrix still contains unconnected signal pins, the above operation can be continued by redetermining the reference pin until all signal pins in the first pin matrix are connected. This allows for the application to layouts of more signal pins, further improving the applicability of the above pin connection method.

[0130] In some exemplary embodiments, such as Figure 6 As shown, when the first adjacent pin that meets the preset conditions cannot be detected based on PS(K,3), but the first pin matrix still contains unconnected signal pins, PS(1,4) can be selected as the first reference pin to redetermine the reference pin. Then, based on the redetermined reference pin, the above pin connection method is continued until all signal pins in the first pin matrix are connected.

[0131] Figure 11 A schematic diagram of the pin distribution of a first pin matrix and a second pin matrix of a PCB to be connected, according to an exemplary embodiment of the present disclosure, is shown.

[0132] In some exemplary embodiments, such as Figure 11 As shown, the following procedure can be performed to... Figure 11 Connect the signal pins of the first and second pin matrices shown.

[0133] First, a pin CS(1,1) located at the end of the first pin matrix on the controller side can be selected as the reference pin, and connected to the MS(1,1) pin in the second pin matrix on the memory chip side to generate a mapping pair CS(1,1)-MS(1,1).

[0134] After determining CS(1,1) as the reference pin, its adjacent signal pins are searched based on the fifth preset distance (the fifth preset distance can be a value that is greater than the distance between CS(1,1) and CS(2,1) and less than the distance between CS(1,1) and CS(3,1) and the distance between CS(1,1) and CS(1,2)). This allows us to obtain the two first adjacent pins, CS(2,1) and CS(2,2), which are not connected.

[0135] In some embodiments, adjacent signal pin pairs can also be defined directly, thereby determining the adjacent signal pins of the second mapped pin based on the definition. For example, CS(1,1) and CS(2,1), CS(1,1) and CS(2,2), etc., can be defined as adjacent signal pin pairs.

[0136] For CS(2,1), its second adjacent pin that is already connected is CS(1,1) (the second preset distance used for judgment is the same as the fifth preset distance). Therefore, at the controller end, it is necessary to avoid selecting the signal pin adjacent to MS(1,1) (the second mapped pin) as the first mapped pin. The adjacent signal pin of the second mapped pin can be determined by the sixth preset distance. The sixth preset distance can be a value that is greater than the distance between MS(1,1) and MS(2,1) and less than the distance between MS(1,1) and MS(3,1) and the distance between MS(1,1) and MS(1,2).

[0137] In some embodiments, adjacent signal pin pairs can also be defined directly, thereby determining the adjacent signal pins of the second mapped pin based on the definition. For example, MS(1,1) and MS(2,1), MS(1,1) and MS(2,2), etc., can be defined as adjacent signal pin pairs.

[0138] Based on the above method, signal pins other than MS(2,1) and MS(3,1) (adjacent signal pins of MS(1,1)) can be identified as second signal pins, and the first mapping pin can be selected from them. For example, MS(1,2) can be selected as the first mapping pin and connected to generate the mapping pair CS(2,1)-MS(1,2).

[0139] For CS(2,2), its second adjacent pin that has been connected is CS(1,1). Accordingly, the signal pins other than MS(2,1) and MS(3,1) (adjacent signal pins of MS(1,1)) can be identified as the second signal pins, and the first mapping pin can be selected among them. For example, MS(4,2) can be selected as its first mapping pin and connected to generate the mapping pair CS(2,2)-MS(4,2).

[0140] Subsequently, the number of first adjacent pins of CS(2,1) and CS(2,2) can be obtained respectively. The first adjacent pin of CS(2,1) is CS(3,1), and the number is 1. The first adjacent pins of CS(2,2) are CS(3,1), CS(1,2) and CS(3,2), and the number is 3. Then, CS(2,2) is used as the updated reference pin, and the connection operation of CS(3,1), CS(1,2) and CS(3,2) is performed based on a similar operation as above.

[0141] Subsequently, based on a similar operation, the reference pins are updated sequentially to CS(3,1), CS(4,2), and CS(5,1), and the first adjacent pins are connected based on each reference pin. When the reference pin is CS(5,1), its first adjacent pins are CS(6,1) and CS(6,2). After connecting CS(6,1) and CS(6,2), either CS(6,1) or CS(6,2) can be used as the updated reference pin. At this point, no first adjacent pin meeting the preset conditions can be detected based on either CS(6,1) or CS(6,2), thus completing the connection between the first pin matrix and the second pin matrix.

[0142] Figure 12 A schematic diagram of the pin connections of a first pin matrix and a second pin matrix of a PCB according to an exemplary embodiment of the present disclosure is shown.

[0143] like Figure 12 As shown, in the signal lines obtained by the above method, for any two signal lines, if their two pins on the reference side (controller end) are adjacent, then their two pins on the target side (memory chip end) are not adjacent; if their two pins on the reference side (controller end) are not adjacent, then their two pins on the target side (memory chip end) can be either adjacent or not adjacent. That is, by connecting the pins using the above method, for any two signal lines, it is possible to ensure that their pins on at least one side are not adjacent to each other. This line structure can further reduce crosstalk between the two signal lines, thereby achieving overall crosstalk control based on the pins in the first and second pin matrices.

[0144] According to some embodiments, the substrate includes a plurality of first pin matrices and a plurality of second pin matrices, and the number of the plurality of first pin matrices is the same as the number of the plurality of second pin matrices. The above-described pin interconnection method for the substrate may further include: determining the correspondence between the plurality of first pin matrices and the plurality of second pin matrices; and performing an operation to determine a reference pin, a first process, and a second process on each of the plurality of first pin matrices and the corresponding second pin matrix of the first pin matrix, until all signal pins in the first pin matrix are connected.

[0145] Therefore, the signal pins are divided into functional areas (pin matrices) and correspond to each other, so that the pins in each functional area are connected to the pins in the corresponding functional area. This further reduces the design complexity, prevents signal interference between functional areas, and improves the signal transmission quality of the overall line.

[0146] Typically, a single controller chip integrates hundreds of signal pins. AI chips often integrate multiple controllers, so the number of signal pins on both the packaging substrate and the PCB is enormous.

[0147] In some embodiments, the signal pin array on the reference side can be divided into multiple first pin matrices, and correspondingly, the signal pin array on the target side can be divided into multiple second pin matrices, and a one-to-one correspondence between the first pin matrices and the second pin matrices can be determined.

[0148] Subsequently, based on the above correspondence, the above pin connection operation can be performed on the signal pins in the corresponding first pin matrix and second pin matrix respectively, thereby completing the connection of signal pins in the signal pin arrays of the reference side and the target side.

[0149] In some embodiments, there may be a pin matrix containing signal pins adjacent to signal pins in adjacent pin matrices. When connecting these signal pins, the position of the mapped pin of the signal pin in the adjacent pin matrix can be determined based on the method described above, and this position can also be used as a basis for determining the mapped pin of the signal pin.

[0150] According to some embodiments, the substrate is a printed circuit board, and the substrate includes multiple routing layers. The above-described pin interconnection method for the substrate may further include: for each of the multiple adjacent pin pairs, making the signal line of at least one of the two signal pins in the adjacent pin pair routed through the first routing layer, wherein the multiple adjacent pin pairs include at least one first adjacent pin pair in the first pin matrix and at least one second adjacent pin pair in the second pin matrix, the distance between the two signal pins in the first adjacent pin pair is less than a third preset distance, the distance between the two signal pins in the second adjacent pin pair is less than a fourth preset distance, and the number of layers between the first routing layer and the surface routing layer is less than a preset number of layers.

[0151] Therefore, by routing at least one of the adjacent pin pairs from a shallower layer, crosstalk at the via is further reduced, avoiding high crosstalk caused by excessively long vias, thereby further reducing the overall crosstalk of the signal path.

[0152] Figure 13 A schematic diagram of adjacent pin routing of an exemplary embodiment of the present disclosure is shown.

[0153] In some exemplary embodiments, such as Figure 13 As shown, for a network with n routing layers (routing layer L1 to routing layer L2)... n The printed circuit board (n can be a positive integer greater than 2) has pins PIN1 and PIN2 as adjacent pins, where pin PIN1 is connected by the trace layer L. n-2 For routing, pin PIN2 can be routed through a shallow routing layer (e.g., routing layer L3), so that two adjacent pins have only a short parallel signal path at the via, thereby reducing signal crosstalk at the via.

[0154] In some exemplary embodiments, for two adjacent pins, PIN3 and PIN4, both are routed using a shallow routing layer (e.g., routing layer L3), so that the two adjacent pins have only a short parallel signal path at the via, thereby reducing signal crosstalk at the via.

[0155] In some embodiments, the first adjacent pin pair can be determined by judging whether the distance between the two pins is less than a third preset distance. The second adjacent pin pair can be determined by judging whether the distance between the two pins is less than a fourth preset distance.

[0156] In some embodiments, the third preset distance may be the same as the fourth preset distance.

[0157] In some embodiments, the third preset distance and the fourth preset distance may both be the same as the fifth preset distance described above.

[0158] Understandably, the third preset distance, the fourth preset distance, and the preset number of layers can be determined based on actual needs, and no restrictions are imposed here.

[0159] According to some embodiments, the above-described pin interconnection method for a substrate may further include: for the substrate via corresponding to the third signal pin in the adjacent pin pair, controlling a hardware device to back-drill the plating layer of the non-signal path portion of the substrate via, wherein the signal line of the third signal pin is routed through the first trace layer.

[0160] Since there is also some crosstalk in the non-signal path portion of adjacent vias, back-drilling the plating of the non-signal path portion of the vias running from a shallower layer can further reduce crosstalk caused by excessively long vias and improve the overall signal transmission quality of the signal path.

[0161] In some exemplary embodiments, such as Figure 13 As shown, by controlling the hardware device, the non-signal path portion of the vias corresponding to pins PIN2, PIN3, and PIN4 can be back-drilled, and the plating of this portion can be removed to eliminate crosstalk between the non-signal path portions of adjacent vias.

[0162] In some embodiments, the aforementioned hardware device may be, for example, an electric drill, etc., and there is no limitation herein.

[0163] Figure 14 A comparison diagram showing the effects of pin connections according to embodiments of the present disclosure and those according to related technologies is provided.

[0164] like Figure 14 As shown, the pin connection on the channel from the controller in the AI ​​chip to the memory chip is performed based on the embodiments of this disclosure. Compared with the pin connection solution using related technologies, the far-end crosstalk obtained by three-dimensional magnetic field simulation is significantly reduced.

[0165] According to some embodiments, such as Figure 15As shown, a computer-executed pin interconnection device 1500 for a substrate is also provided. The device 1500 includes: a first determining unit 1510 configured to determine a reference pin in a first pin matrix of the substrate, wherein the reference pin has been connected; and a first executing unit 1520 configured to execute a first process based on the determined reference pin. The first executing unit 1520 includes: a detection subunit 1521 configured to detect at least one first adjacent pin of the reference pin that meets preset conditions in the first pin matrix; and an execution subunit 1522 configured to, in response to detecting that the adjacent signal pins of the reference pin include the first adjacent pin, perform a specific execution process. Each of at least one first adjacent pins acquires a first mapped pin in the second pin matrix of the substrate and connects the first adjacent pin and the first mapped pin via a signal line to complete the connection operation of the first adjacent pin; a first selection subunit 1523 is configured to select one of the at least one first adjacent pins as the updated reference pin based on the number of first signal pins of each of the at least one first adjacent pins; and a second execution unit 1530 is configured to repeatedly execute the first process based on the updated reference pin until it is detected that the updated reference pin does not have a first adjacent pin that meets the preset conditions.

[0166] The operations performed by units 1510-1530 and subunits 1521-1523 in device 1500 are similar to the operations of steps S301-S305 in the above-described method for pin connection of substrate, and will not be described in detail here.

[0167] According to some embodiments, the execution subunit can be configured to: in response to obtaining a second signal pin in a second pin matrix, determine the second signal pin as a first mapped pin, wherein the distance between the second signal pin and each of the at least one second mapped pins is greater than a first preset distance, the at least one second mapped pin is a mapped pin corresponding to at least one second adjacent pin, and the distance between each of the at least one second adjacent pins and the first adjacent pin currently performing the connection operation is less than a second preset distance.

[0168] According to some embodiments, the execution subunit may also be configured to: in response to the failure to obtain the second signal pin in the second pin matrix, backtrack to the previous connection operation to redetermine the first mapped pin corresponding to the first adjacent pin processed in the previous connection operation; and in response to the inability to redetermine the first mapped pin or the failure to obtain the second signal pin after redetermining the first mapped pin, continue to backtrack the historical connection operation in sequence until the second signal pin is obtained.

[0169] According to some embodiments, the above-described pin interconnection device for a substrate may further include: a third execution unit configured to perform a second process in response to the detection that an updated reference pin has a first adjacent pin that meets a preset condition and the first pin matrix still contains unconnected signal pins; the third execution unit includes: a second selection subunit configured to select a first reference pin among the unconnected signal pins to re-determine the reference pin; a determination subunit configured to determine a corresponding mapping pin of the first reference pin to connect the first reference pin and the corresponding mapping pin via a signal line; and a fourth execution unit configured to repeatedly execute the first process and the second process based on the first reference pin until all signal pins in the first pin matrix are connected.

[0170] According to some embodiments, the substrate includes a plurality of first pin matrices and a plurality of second pin matrices, and the number of the plurality of first pin matrices is the same as the number of the plurality of second pin matrices. The aforementioned pin interconnection device for the substrate may further include: a second determining unit configured to determine the correspondence between the plurality of first pin matrices and the plurality of second pin matrices; and a fifth executing unit configured to perform an operation of determining a reference pin, a first process, and a second process on the first pin matrix based on each of the plurality of first pin matrices and the corresponding second pin matrix of the first pin matrix, until all signal pins in the first pin matrix are connected.

[0171] According to some embodiments, the substrate is a packaging substrate for packaging wafers.

[0172] According to some embodiments, the substrate is a printed circuit board, and the substrate includes multiple routing layers. The pin interconnection device for the substrate may further include: a routing unit configured to route the signal line of at least one of the two signal pins in each of the multiple adjacent pin pairs through a first routing layer. The multiple adjacent pin pairs include at least one first adjacent pin pair in a first pin matrix and at least one second adjacent pin pair in a second pin matrix. The distance between the two signal pins in the first adjacent pin pairs is less than a third preset distance, the distance between the two signal pins in the second adjacent pin pairs is less than a fourth preset distance, and the number of layers between the first routing layer and the surface routing layer is less than a preset number of layers.

[0173] According to some embodiments, the above-described pin interconnection device for a substrate may further include: a control unit configured to control hardware to back-drill the plating of the non-signal path portion of the substrate via for the substrate via corresponding to the third signal pin in the adjacent pin pair, wherein the signal line of the third signal pin is routed through the first trace layer.

[0174] According to some embodiments, a chip is also provided, wherein the chip wafer is pin-connected on the chip packaging substrate according to the pin interconnection method for substrate executed by the computer described above.

[0175] According to embodiments of this disclosure, an electronic device, a readable storage medium, and a computer program product are also provided.

[0176] refer to Figure 16 The present invention describes a structural block diagram of an electronic device 1600 that can serve as a server or client of the present disclosure, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0177] like Figure 16 As shown, the electronic device 1600 includes a computing unit 1601, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1602 or a computer program loaded from a storage unit 1608 into a random access memory (RAM) 1603. The RAM 1603 may also store various programs and data required for the operation of the electronic device 1600. The computing unit 1601, ROM 1602, and RAM 1603 are interconnected via a bus 1604. An input / output (I / O) interface 1605 is also connected to the bus 1604.

[0178] Multiple components in electronic device 1600 are connected to I / O interface 1605, including: input unit 1606, output unit 1607, storage unit 1608, and communication unit 1609. Input unit 1606 can be any type of device capable of inputting information to electronic device 1600. Input unit 1606 can receive input digital or character information and generate key signal inputs related to user settings and / or function control of the electronic device, and may include, but is not limited to, a mouse, keyboard, touchscreen, trackpad, trackball, joystick, microphone, and / or remote control. Output unit 1607 can be any type of device capable of presenting information, and may include, but is not limited to, a monitor, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 1608 may include, but is not limited to, a hard disk and an optical disk. The communication unit 1609 allows the electronic device 1600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers and / or chipsets, such as Bluetooth™ devices, 802.11 devices, WiFi devices, WiMax devices, cellular communication devices and / or the like.

[0179] The computing unit 1601 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1601 performs the various methods and processes described above, such as the pin interconnection method for the substrate described above. For example, in some embodiments, the pin interconnection method for the substrate described above can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as storage unit 1608. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 1600 via ROM 1602 and / or communication unit 1609. When the computer program is loaded into RAM 1603 and executed by the computing unit 1601, one or more steps of the pin interconnection method for the substrate described above can be performed. Alternatively, in other embodiments, the computing unit 1601 may be configured to perform the pin wiring method for the substrate described above by any other suitable means (e.g., by means of firmware).

[0180] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0181] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0182] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0183] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0184] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0185] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0186] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0187] While embodiments or examples of this disclosure have been described with reference to the accompanying drawings, it should be understood that the methods, systems, and devices described above are merely exemplary embodiments or examples, and the scope of the invention is not limited by these embodiments or examples, but only by the granted claims and their equivalents. Various elements in the embodiments or examples may be omitted or replaced by their equivalents. Furthermore, the steps may be performed in a different order than that described in this disclosure. Further, various elements in the embodiments or examples may be combined in various ways. Importantly, as the technology evolves, many elements described herein can be replaced by equivalents that appear after this disclosure.

Claims

1. A computer-executed pin interconnection method for a substrate, wherein, The substrate includes a reference side and a target side, the reference side includes a first pin matrix, and the target side includes a second pin matrix. The method includes: Identify the reference pin in the first pin matrix, wherein the reference pin has been connected. Based on the determined reference pin, the first process is performed, including: In the first pin matrix, at least one first adjacent pin of the reference pin that meets the preset conditions is detected. The distance between each of the at least one first adjacent pin that meets the preset conditions and the reference pin is less than a fifth preset distance and none of them have completed the connection. In response to detecting that the adjacent signal pins of the reference pin include a first adjacent pin, for each of the at least one first adjacent pins, a first mapped pin is obtained in the second pin matrix and the signal line between the first adjacent pin and the first mapped pin is connected through vias and wiring layers inside the substrate to complete the wiring operation of the first adjacent pin. Obtaining the first mapped pin in the second pin matrix of the substrate includes: In response to obtaining a second signal pin in the second pin matrix, the second signal pin is determined as the first mapped pin, wherein the distance between the second signal pin and each of the at least one second mapped pins is greater than a first preset distance, the at least one second mapped pin is a mapped pin corresponding to at least one second adjacent pin, and the distance between each of the at least one second adjacent pins and the first adjacent pin currently performing the connection operation is less than a second preset distance; Based on the number of first signal pins in each of the at least one first adjacent pins, one of the at least one first adjacent pins is selected as the updated reference pin, wherein the distance between the first signal pin and the corresponding first adjacent pin is less than a sixth preset distance; and Based on the updated reference pin, the first process is repeated until it is detected that the updated reference pin does not have a first adjacent pin that meets the preset conditions.

2. The method according to claim 1, wherein, The step of obtaining the first mapped pin in the second pin matrix of the substrate further includes: In response to the failure to find the second signal pin in the second pin matrix, the process backtracks to the previous connection operation to redetermine the first mapped pin corresponding to the first adjacent pin processed in the previous connection operation; and If the first mapped pin cannot be re-determined or the second signal pin is still not obtained after re-determining the first mapped pin, the historical connection operation continues to be traced back until the second signal pin is obtained.

3. The method according to claim 1 or 2, further comprising: In response to the absence of a first adjacent pin meeting the preset conditions detected in the updated reference pin and the first pin matrix still containing unconnected signal pins, a second process is executed, including: Among the unconnected signal pins, select the first reference pin to redetermine the reference pin; Determine the corresponding mapped pin for the first reference pin, and connect the first reference pin to the corresponding mapped pin via a signal line; and Based on the first reference pin, repeat the first process and the second process until all signal pins in the first pin matrix are connected.

4. The method of claim 3, wherein the substrate comprises a plurality of first pin matrices and a plurality of second pin matrices, and the number of the plurality of first pin matrices is the same as the number of the plurality of second pin matrices, the method further comprising: Determine the correspondence between the plurality of first pin matrices and the plurality of second pin matrices; as well as Based on each of the plurality of first pin matrices and the corresponding second pin matrix of the first pin matrix, the operation of determining the reference pin, the first process and the second process are performed on the first pin matrix until all signal pins in the first pin matrix are connected.

5. The method according to claim 1 or 2, wherein the substrate is a packaging substrate for packaging wafers.

6. The method according to claim 1 or 2, wherein the substrate is a printed circuit board, the substrate includes multiple wiring layers, and the method further includes: For each of the plurality of adjacent pin pairs, the signal line of at least one of the two signal pins in the adjacent pin pair is routed through the first routing layer. The plurality of adjacent pin pairs includes at least one first adjacent pin pair in the first pin matrix and at least one second adjacent pin pair in the second pin matrix. The distance between the two signal pins in the first adjacent pin pair is less than a third preset distance, the distance between the two signal pins in the second adjacent pin pair is less than a fourth preset distance, and the number of layers between the first routing layer and the surface routing layer is less than a preset number of layers.

7. The method according to claim 6, further comprising: For the substrate via corresponding to the third signal pin in the adjacent pin pair, the control hardware device performs back drilling on the plating of the non-signal path portion of the substrate via, wherein the signal line of the third signal pin is routed through the first trace layer.

8. A computer-executed pin connection device for a substrate, wherein, The substrate includes a reference side and a target side, the reference side includes a first pin matrix, and the target side includes a second pin matrix. The device includes: The first determining unit is configured to determine the reference pin in the first pin matrix, wherein the reference pin has been connected. A first execution unit is configured to execute a first process based on a defined reference pin. The first execution unit includes: The detection subunit is configured to detect at least one first adjacent pin of the reference pin that meets a preset condition in the first pin matrix, wherein the distance between each of the at least one first adjacent pin that meets the preset condition and the reference pin is less than a fifth preset distance and none of them have completed the connection. An execution subunit is configured to, in response to detecting that an adjacent signal pin of the reference pin includes a first adjacent pin, for each of the at least one first adjacent pin, obtain a first mapped pin in a second pin matrix and connect the signal lines between the first adjacent pin and the first mapped pin through vias and wiring layers inside the substrate to complete the wiring operation of the first adjacent pin. Obtaining the first mapped pin in the second pin matrix of the substrate includes: In response to obtaining a second signal pin in the second pin matrix, the second signal pin is determined as the first mapped pin, wherein the distance between the second signal pin and each of the at least one second mapped pins is greater than a first preset distance, the at least one second mapped pin is a mapped pin corresponding to at least one second adjacent pin, and the distance between each of the at least one second adjacent pins and the first adjacent pin currently performing the connection operation is less than a second preset distance; A first selection subunit is configured to select one of the at least one first adjacent pins as an updated reference pin based on the number of first signal pins present in each of the at least one first adjacent pins, wherein the distance between the first signal pin and the corresponding first adjacent pin is less than a sixth preset distance; and The second execution unit is configured to repeatedly execute the first process based on the updated reference pin until it is detected that the updated reference pin does not have a first adjacent pin that meets the preset condition.

9. The apparatus according to claim 8, wherein, The execution subunit is further configured to: In response to the failure to obtain the second signal pin in the second pin matrix, backtrack to the previous connection operation to redetermine the first mapped pin corresponding to the first adjacent pin processed in the previous connection operation; as well as If the first mapped pin cannot be re-determined or the second signal pin is still not obtained after re-determining the first mapped pin, the historical connection operation continues to be traced back until the second signal pin is obtained.

10. The apparatus according to claim 8 or 9, further comprising: A third execution unit is configured to execute a second process in response to the absence of a detected first adjacent pin that meets the preset conditions and the first pin matrix still containing unconnected signal pins. The third execution unit includes: The second selection subunit is configured to select a first reference pin from the unconnected signal pins to redetermine the reference pin; The determination subunit is configured to determine the corresponding mapped pin of the first reference pin, so as to connect the first reference pin and the corresponding mapped pin via signal lines; and The fourth execution unit is configured to repeatedly execute the first process and the second process based on the first reference pin until all signal pins in the first pin matrix are connected.

11. The apparatus of claim 10, wherein the substrate includes a plurality of first pin matrices and a plurality of second pin matrices, and the number of the plurality of first pin matrices is the same as the number of the plurality of second pin matrices, the apparatus further comprising: The second determining unit is configured to determine the correspondence between the plurality of first pin matrices and the plurality of second pin matrices; as well as The fifth execution unit is configured to perform the operation of determining the reference pin, the first process, and the second process on each of the plurality of first pin matrices and the corresponding second pin matrix of the first pin matrix, until all signal pins in the first pin matrix are connected.

12. The apparatus according to claim 8 or 9, wherein the substrate is a packaging substrate for packaging a wafer.

13. The apparatus according to claim 8 or 9, wherein the substrate is a printed circuit board, the substrate includes a plurality of wiring layers, and the apparatus further includes: The routing unit is configured such that for each of a plurality of adjacent pin pairs, the signal line of at least one of the two signal pins in the adjacent pin pair is routed through a first routing layer. The plurality of adjacent pin pairs includes at least one first adjacent pin pair in the first pin matrix and at least one second adjacent pin pair in the second pin matrix. The distance between the two signal pins in the first adjacent pin pair is less than a third preset distance, the distance between the two signal pins in the second adjacent pin pair is less than a fourth preset distance, and the number of layers between the first routing layer and the surface routing layer is less than a preset number of layers.

14. The apparatus of claim 13, further comprising: The control unit is configured to control the hardware device to back-drill the plating of the non-signal path portion of the substrate via for the corresponding substrate via of the third signal pin in the adjacent pin pair, wherein the signal line of the third signal pin is routed through the first trace layer.

15. A chip, wherein the wafer of the chip is pin-connected on the chip's packaging substrate according to any one of claims 1-5.

16. An electronic device comprising: At least one processor; as well as A memory that is communicatively connected to the at least one processor; in The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

17. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-7.

18. A computer program product comprising a computer program, wherein, The computer program, when executed by a processor, implements the method of any one of claims 1-7.

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