Apparatus, system, and method for improving communication between a memory device and a controller

Abstract

An apparatus, system, and method are provided that improve communication between a memory device and a controller. A data communication apparatus includes a transceiver coupled to a data path and configured to send or receive data over the data path, and an interrupt circuit coupled to an interrupt path corresponding to the data path and configured to determine whether any device is allowed to occupy the data path. The interrupt circuit generates an interrupt signal to prevent another device from accessing the data path in response to an activation signal to send or receive data by the transceiver.

Description

TECHNICAL FIELD

[0001] Embodiments of the disclosed technology relate to a memory system or a system for performing data communication. BACKGROUND

[0002] Recently, computing environment paradigms are shifting towards ubiquitous computing, which enables computing to occur anytime and anywhere. The recent increase in the use of ubiquitous computing has led to an increase in the use of portable electronic devices (e.g., mobile phones, digital cameras, notebook computers, etc.). Such portable electronic devices can use or include a memory system having at least one memory device as its data storage medium. The memory system can be a data storage device that can be used as a main storage device or an auxiliary storage device of the portable electronic device.

[0003] Such semiconductor-based data storage devices offer advantages over conventional hard disk drives because semiconductor memory devices have no mechanical moving parts (e.g., mechanical arms) and thus offer superior stability and durability, high data rates, and low power consumption. Examples of semiconductor-based data storage devices include universal serial bus (USB) memory devices, memory cards having various interfaces, and solid state drives (SSDs). SUMMARY

[0004] The disclosed technology can be implemented in some embodiments to provide a data communication apparatus, a memory system, and a method for improving data input / output operations of a memory system.

[0005] In one embodiment, a data communication apparatus can include a transceiver and an interrupt circuit. The transceiver is coupled to a data path and configured to transmit or receive data, and the interrupt circuit is coupled to an interrupt path corresponding to the data path and configured to determine whether to allow any apparatus to occupy the data path. The interrupt circuit can generate an interrupt signal for preventing another apparatus from accessing the data path in response to an activation signal for transmitting or receiving data by the transceiver.

[0006] The interrupt circuit can further be configured to disable the transceiver upon receiving the interrupt signal via the interrupt path.

[0007] The data communication apparatus can further include a memory bank coupled to the data path. In one example, the memory bank includes a plurality of volatile memory cells or a plurality of non-volatile memory cells configured to store data.

[0008] After generating the interrupt signal in response to the activation signal, the interrupt circuit can generate a control signal for activating the transceiver.

[0009] The transceiver can include a tri-state buffer configured to transmit or receive data based on the control signal.

[0010] The data path and the interrupt path can be shared by a plurality of devices including the data communication device and the other device. The interrupt signal can be generated by any of the plurality of devices.

[0011] In one embodiment, a system can include a data path shared by a plurality of transceivers and configured to transfer data transmitted from one of the plurality of transceivers to another of the plurality of transceivers. In some implementations, the system can further include the plurality of transceivers sharing the data path. The system can include an interrupt path shared by a plurality of interrupt circuits and configured to transfer an interrupt signal for interrupting access to the data path corresponding to the interrupt path. In some implementations, the system can further include the plurality of interrupt circuits sharing the interrupt path. A first interrupt circuit of the plurality of interrupt circuits generates the interrupt signal that is sent through the interrupt path before a first transceiver corresponding to the first interrupt circuit sends data via the data path to interrupt access by the plurality of transceivers.

[0012] The system can include a plurality of memory chips each including at least one of a volatile memory cell array or a non-volatile memory cell array. The system can further include a controller configured to control data input / output operations performed in the plurality of memory chips. Each of the plurality of memory chips can include one of a plurality of transceivers and one of a plurality of interrupt circuits. The data path can include at least one channel configured to couple the controller to the plurality of memory chips.

[0013] The first interrupt circuit can be configured to disable the first transceiver upon receiving the interrupt signal via the interrupt path.

[0014] The first interrupt circuit can generate a control signal for activating the first transceiver after generating the interrupt signal in response to a first signal input to the first transceiver for sending data.

[0015] The first transceiver can include a tri-state buffer configured to send or receive data based on a control signal provided by the interrupt circuit.

[0016] The interrupt path can include a first line for transferring the interrupt signal, and the first line is coupled to a switch circuit configured to activate or disable the first line in response to a set signal provided by the plurality of interrupt circuits.

[0017] The switch circuit can include a plurality of transistors connected in series between a power supply terminal for providing a voltage and the first line.

[0018] The first interrupt circuit may include: a first component configured to generate a setting signal for activating an interrupt path in response to a first signal; a second component configured to generate a control signal for activating a first transceiver in response to the first signal; a third component configured to disable the control signal when the interrupt path is activated; and a fourth component configured to reset the control signal based on a status reset signal.

[0019] The first component may include a delay unit configured to delay the first signal by a preset time.

[0020] In another embodiment, a data communication method may include the following steps: receiving, through a first device among a plurality of devices, an activation signal for sending or receiving data via a data path shared by the plurality of devices; generating, based on the activation signal, a first interrupt signal for interrupting access to the plurality of devices; activating, based on the first interrupt signal and the activation signal, a control signal to be applied to the first device; and sending or receiving data through the first device based on the control signal.

[0021] The method may further include the following steps: maintaining a first state for disabling the control signal when no activation signal is input; and disabling the control signal based on the first state and a second interrupt signal.

[0022] The second interrupt signal can be output by a second device, which is different from the first device, among a plurality of devices.

[0023] The method may also include the following steps: disabling the control signal when the activation signal is disabled.

[0024] The method may also include the following step: applying a state reset signal when the control signal is disabled.

[0025] In some embodiments of the disclosed technology, a data communication device includes: a transceiver coupled to a data path and configured to transmit or receive data; and an interrupt circuit coupled to an interrupt path corresponding to the data path and configured to determine whether another device is using or occupying the data path, wherein the interrupt circuit is configured to receive an activation signal for transmitting or receiving data and generate an interrupt signal for preventing the other device from using or occupying the data path.

[0026] In some embodiments of the disclosed technology, a system includes: a data path for transmitting data; a plurality of transceivers sharing the data path; an interrupt path for transmitting an interrupt signal and corresponding to the data path; and a plurality of interrupt circuits sharing the interrupt path, wherein a first interrupt circuit among the plurality of interrupt circuits generates an interrupt signal to the interrupt path based on a first signal activating a first transceiver among the plurality of transceivers, the interrupt signal causing another transceiver among the plurality of transceivers to stop using the data path, the first transceiver corresponding to the first interrupt circuit.

[0027] In some embodiments of the disclosed technology, a method for performing data communication in a first device among a plurality of devices includes the steps of: receiving an activation signal for sending or receiving data via a data path shared by the plurality of devices; generating a first interrupt signal based on the activation signal; activating a control signal applied to a transceiver based on the first interrupt signal and the activation signal; and sending or receiving data via the transceiver based on the control signal. Attached Figure Description

[0028] Figure 1 Examples of memory systems based on some implementations of the disclosed technology are shown.

[0029] Figure 2 Examples of data processing systems based on some implementations of the disclosed technology are shown.

[0030] Figure 3 An example of a data path connected to multiple devices is shown.

[0031] Figure 4 Showing via Figure 3 The data path shown represents an example of data communication performed.

[0032] Figure 5 Examples of data communication devices, data paths, and interrupt paths based on some implementations of the disclosed technology are shown.

[0033] Figure 6 Show Figure 1 and Figure 2 The example construction of the memory device shown is illustrated.

[0034] Figure 7 Examples of interrupt circuits and interrupt paths are shown.

[0035] Figure 8 Show connection to Figure 7 An example of a switching circuit for an interrupt path is shown.

[0036] Figure 9 Example operation of an interrupt circuit based on some implementations of the disclosed technology is shown.

[0037] Figure 10 This illustrates an example operation of a data communication device.

[0038] Figure 11 This illustrates how data communication is performed based on some implementations of the disclosed technology. Detailed Implementation

[0039] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0040] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, features, etc.) included in “one embodiment,” “example embodiment,” “implementation,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may also be combined in the same embodiment or may not necessarily be combined in the same embodiment.

[0041] In this disclosure, the terms “comprising,” “including,” “having,” and “containing” are open-ended. As used in the appended claims, these terms specify the presence of the stated element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the inclusion of additional components (e.g., interface units, circuitry, etc.).

[0042] In this disclosure, various units, circuits, or other components may be described or declared as "configured to" perform one or more tasks. In such a context, "configured to" is used to indicate a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, a block / unit / circuit / component can be referred to as being configured to perform a task even when the specified block / unit / circuit / component is currently inoperable (e.g., not turned on or activated). Blocks / units / circuits / components used with the "configured to" language include hardware—e.g., circuits, memory storing program instructions executable to perform operations, etc. Additionally, "configured to" may include general structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., a general-purpose processor or FPGA executing software) to operate in a manner capable of performing the tasks in question. "Configured to" may also include adjusting manufacturing processes (e.g., semiconductor manufacturing facilities) to manufacture means (e.g., integrated circuits) suitable for implementing or performing one or more tasks. In this patent document, "circuit" or "logic" may include: (a) circuits, such as analog and / or digital circuits; (b) combinations of circuits and software (e.g., firmware) suitable for: (i) processors or combinations of processors; (ii) portions of processor / software, such as digital signal processors, software, and memory devices, which work together to enable electrical devices such as mobile phones or server systems to perform various functions; and (c) circuits, such as microprocessors or portions of microprocessors that require software or firmware to operate. "Circuit" or "logic" may also include one or more processors or portions of processors and associated software and / or firmware. "Circuit" or "logic" may also include integrated circuits for data storage devices.

[0043] As used herein, the terms “first,” “second,” “third,” etc., are used as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily imply that the first value must precede the second. Furthermore, while these terms can be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that would otherwise have the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0044] Furthermore, the term "based on" is used to describe one or more factors influencing a determination. This term does not exclude other factors that may influence the determination. That is, a determination can be based solely on these factors, or at least partially on them. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, such a phrase does not exclude the possibility that A is also determined based on C. In other cases, A can be determined solely based on B.

[0045] In this patent document, "data" can include bit sequences. For example, "data" can include the contents of a file, a portion of a file, a page in memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other information that can be represented by a bit sequence. In some implementations, data can include discrete objects. In some implementations, data can include information units within a transmission packet sent between two different components.

[0046] Some embodiments of the disclosed technology are described with reference to the accompanying drawings.

[0047] Figure 1 Examples of memory systems based on some implementations of the disclosed technology are shown. Specifically, in Figure 1 In the present invention, a memory system 110 based on some embodiments of the disclosed technology may include a plurality of memory chips 182, 184, 186, and 188.

[0048] Reference Figure 1 The memory system 110 may include a controller 130 and a memory device 150. The memory device 150 may include multiple memory chips 182, 184, 186, and 188. The multiple memory chips 182, 184, 186, and 188 may share data channels CH0 and CH1. For example, a first memory chip 182 and a second memory chip 184 may be connected to the controller 130 via a first data channel CH0. The first data channel CH0 can carry data between the controller 130 and the first memory chip 182 and the second memory chip 184, and the first data channel CH0 is shared by the first memory chip 182 and the second memory chip 184. In some embodiments of the disclosed technology, Figure 1 Other memory chips, not shown, can also be connected to the controller 130 via the first data channel CH0.

[0049] In some embodiments of the disclosed technology, each of the memory chips 182, 184, 186, and 188 may include at least one memory plane. For example, the memory chip may include a set of components disposed on a substrate. The memory chips 182, 184, 186, and 188, connected to the controller 130 via data channels CH0 and CH1, may include modules or interface circuitry for transmitting data and signals between the controller 130 and the memory chips 182, 184, 186, and 188. Furthermore, each of the memory chips 182, 184, 186, and 188 may include a memory group comprising a plurality of non-volatile memory cells. These plurality of non-volatile memory cells may be interconnected via multiple word lines and multiple bit lines. Each of the memory chips 182, 184, 186, and 188 may include... Figure 2 The diagram shows multiple storage blocks 152, 154, 156, or multiple memory planes.

[0050] In some embodiments of the disclosed technology, each of the memory chips 182, 184, 186, and 188 may include a memory bank comprising a plurality of volatile memory cells. For example, each of the memory chips 182, 184, 186, and 188 may include a plurality of memory banks.

[0051] Here, each of memory chips 182, 184, 186, and 188 is discussed as an example of a means or component for sending and receiving data via a channel or data path (through which data is transmitted). Each of the plurality of memory chips 182, 184, 186, and 188 may include a transceiver for sending and receiving data transmitted via a channel. Furthermore, each of memory chips 182, 184, 186, and 188 may include an interrupt circuit 192 (INT_CT) connected to interrupt lines INT_L0 and INT_L2 for sending and receiving interrupt signals.

[0052] In one implementation, when the controller 130 outputs an interrupt signal to a specific memory chip via interrupt lines INT_L0 and INT_L2, the specific memory chip delays its data transmission in response to the interrupt signal. In the event of a fault or unexpected situation during a data input / output operation or data transmission operation, the controller 130 may send an interrupt signal to at least one of a plurality of memory chips 182, 184, 186, and 188. In another implementation, the controller 130 may respond to an external device (e.g., Figure 2An interrupt signal is generated in response to a control signal or command from the host (shown). Multiple memory chips 182, 184, 186, and 188 can reset parameters associated with data input / output operations in response to an interrupt signal generated by the controller 130.

[0053] In one embodiment of the disclosed technology, before the first memory chip 182 activates the transceiver for inputting and outputting data items, the interrupt circuit 192 can cause a potential change in the first interrupt line INT_L0 connected to the first memory chip 182. For example, the interrupt circuit 192 can generate an interrupt signal and output the interrupt signal via the first interrupt line INT_L0. When the interrupt circuit 192 in the first memory chip 182 generates an interrupt signal, an interrupt circuit included in another memory chip (e.g., the second memory chip 184) connected via the first interrupt line INT_L0 can prevent that other memory chip from sending or receiving data via the first data channel CH0 corresponding to the first interrupt line INT_L0. After providing an interrupt signal to the first interrupt line INT_L0, the interrupt circuit 192 in the first memory chip 182 can activate the transceiver 194 connected to the first data channel CH0 (see [link to original text]). Figure 5 and Figure 6 Even if one memory chip is sending or receiving data through the first data channel CH0, when another memory chip generates an interrupt signal for the first data channel CH0, the memory chip will also stop sending / receiving data, thereby avoiding data collisions on the first data channel CH0 shared by the first memory chip 182 and the second memory chip 184.

[0054] Each of the memory chips 182, 184, 186, and 188 can generate an interrupt signal before sending and receiving data. This interrupt signal is different from and can be distinguished from the interrupt signal generated by the controller 130 based on the operational states of the multiple memory chips 182, 184, 186, and 188 detected by the controller 130. The controller 130 can receive the operational states from the multiple memory chips 182, 184, 186, and 188 via a preset communication method (e.g., a preset protocol) and generate command or interrupt signals to avoid contention on a particular data channel. However, if data communication of a memory chip 182, 184, 186, and / or 188 is scheduled to send data, each of the memory chips 182, 184, 186, and 188 must wait until the controller 130 generates a command or interrupt signal to avoid potential conflicts. Therefore, the controller's operation margin for generating command or interrupt signals may lead to a decrease in data input / output rates. However, some embodiments of the disclosed technology can allow each of the memory chips 182, 184, 186, and 188 to generate an interrupt signal that enables contention-free access to the shared data channel. In response to an interrupt signal generated by another memory chip, the memory chip sharing the data channel with that other memory chip can postpone its data transmission / reception. Through this process, multiple memory chips 182, 184, 186, and 188 can access the shared data channel without data input / output operation conflicts and delays, thereby improving the efficiency of data input / output operations.

[0055] In some implementations, execution can be performed without conflict when using data channels CH0 and CH1. Figure 1 The illustrated memory system 110 includes multiple memory chips 182, 184, 186, 188 and a controller 130 for data communication operations. The embodiments of the disclosed technology discussed in this patent document can be applied to multiple systems or devices connected via a shared data path (e.g., channel, bus, etc.) to perform data communication.

[0056] Figure 2 Examples of data processing systems based on some implementations of the disclosed technology are shown.

[0057] Reference Figure 2 The data processing system 100 may include a host 102 connected to or communicating with the memory system 110. For example, the host 102 and the memory system 110 may be interconnected via a data bus, host cable, etc. to perform data communication.

[0058] The memory system 110 may include a memory device 150 and a controller 130. The memory device 150 and the controller 130 in the memory system 110 may be physically separated from each other. The memory device 150 and the controller 130 may be connected via at least one data path. For example, the data path may include a channel and / or a way.

[0059] In some embodiments of the disclosed technology, the memory device 150 and the controller 130 may be functionally separated components or elements. In some embodiments of the disclosed technology, the memory device 150 and the controller 130 may be integrated into a single chip or multiple chips. For example, the memory device 150 may include… Figure 1 Multiple memory chips 182, 184, 186, and 188 are shown to increase the memory capacity. The controller 130 can perform data input / output operations in response to requests from external devices. For example, in response to a read request from an external device, the controller 130 performs a read operation by reading data stored in multiple non-volatile memory cells included in the memory device 150.

[0060] like Figure 2 As shown, the memory device 150 may include a plurality of memory blocks 152, 154, and 156. Memory blocks 152, 154, and 156 may be a plurality of non-volatile memory cells that are the smallest units that can be erased by a single erase operation. Although not shown, each of memory blocks 152, 154, and 156 may include a plurality of pages. Each page may include a plurality of non-volatile memory cells that are the smallest units that can be written to or read by a single programming operation or a single read operation.

[0061] For example, memory device 150 may include multiple memory planes or multiple memory dies. In some embodiments of the disclosed technology, a memory plane may include: a logical or physical partition containing at least one memory block, drive circuitry configured to control an array of non-volatile memory cells, and a buffer that can temporarily store data being written to or read from non-volatile memory cells.

[0062] Furthermore, based on some embodiments of the disclosed technology, a memory die may include at least one memory plane. A memory die may include a set of components disposed on a substrate. Each memory die may be connected to the controller 130 via a data path. Each memory die may include an interface for transmitting data and signals between the controller 130 and the memory die.

[0063] In some embodiments of the disclosed technology, the memory system may include a plurality of memory devices and a controller that communicates with the plurality of memory devices via at least one data path (e.g., a channel, bus, etc.). The memory system can perform data input / output operations or data transfer operations between the controller and the plurality of memory devices. Even when the plurality of memory devices share a data path to communicate with the controller, each of the memory devices is able to access the data path without contention during data input / output operations or data transfer operations.

[0064] In some implementations, during communication between a controller and multiple memory devices in a memory system implemented based on some embodiments of the disclosed technology, when one memory device generates an interrupt signal in response to an enable signal for data input / output operations, the other memory devices can disable their transceivers associated with the data path. That is, when one of the multiple devices sharing a data path generates an interrupt signal, the remaining devices sharing the data path postpone their data transmission in response to the interrupt signal.

[0065] In preventing multiple memory devices sharing a data path from sending / receiving data when an interrupt signal is activated, memory systems implemented based on some embodiments of the disclosed technology may not need to perform the transmission of signals generated to comply with the data communication protocols associated with the memory devices and the controller. Signal transmission in memory systems implemented based on some embodiments of the disclosed technology does not require the controller to check which memory device is currently occupying the data path used for communication. Multiple memory devices in the memory system can determine whether they are allowed to occupy the data path based on the presence of an interrupt signal or other information associated with an interrupt circuit.

[0066] In some embodiments of the disclosed technology, the memory device 150 may include at least one memory block 152, 154, 156, at least one memory plane, or at least one memory chip. The internal structure of the memory device 150 may differ from... Figure 2 The structure shown.

[0067] Reference Figure 2The memory device 150 may include a voltage supply circuit 170 to apply voltage to memory blocks 152, 154, and 156. The voltage supply circuit 170 may apply a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the memory blocks. For example, during a read operation to read data from the non-volatile memory cells included in memory blocks 152, 154, and 156, the voltage supply circuit 170 may apply a read voltage Vrd to the selected non-volatile memory cell. During a programming operation to write data to the non-volatile memory cells included in memory blocks 152, 154, and 156, the voltage supply circuit 170 may apply a programming voltage Vprog to the selected non-volatile memory cell. Furthermore, during a read or programming operation performed on a selected non-volatile memory cell, the voltage supply circuit 170 may apply a pass voltage Vpass to an unselected non-volatile memory cell. During the erase operation that erases data from the non-volatile memory cells included in memory blocks 152, 154, and 156, voltage supply circuit 170 may apply an erase voltage Vers to the memory blocks.

[0068] Memory device 150 can store information about various voltages to be applied to memory blocks 152, 154, and 156 during programming, reading, and erasing operations. For example, when the non-volatile memory cells in memory blocks 152, 154, and 156 can store multiple bits of data, multiple levels of the read voltage Vrd can be used to distinguish different threshold voltage distributions of the memory cells. Memory device 150 may include a table containing information corresponding to multiple levels of the read voltage Vrd corresponding to multiple bits of data. For example, the table may include bias values ​​stored in a register, such that each bias value corresponds to a specific level of the read voltage Vrd. The number of bias values ​​for the read voltage Vrd used for reading operations can be limited to a preset range. Furthermore, the bias values ​​can be quantized.

[0069] The host 102 may include portable electronic devices (e.g., mobile phones, MP3 players, laptops, etc.) or non-portable electronic devices (e.g., desktop computers, game consoles, televisions, projectors, etc.).

[0070] Host 102 may also include at least one operating system (OS) that supports the functions of host 102 and performs operations on host 102. The OS can act as an intermediary between host 102 communicating with memory system 110 and a user intending to store data in memory system 110. The OS can support functions corresponding to user requests and perform operations corresponding to user requests. By way of example and not limitation, the OS can be classified as a general-purpose operating system or a mobile operating system based on the mobility of host 102. General-purpose operating systems can be classified as personal operating systems or enterprise operating systems based on system requirements or user environment. Unlike personal operating systems, enterprise operating systems offer better security features and high-performance computing.

[0071] The mobile operating system can support the services or functions required by the mobile device (e.g., power-saving functions). Host 102 may include multiple operating systems. In response to user requests, host 102 may include multiple operating systems interlocked with memory system 110. Host 102 can send multiple commands corresponding to user requests to memory system 110, thereby executing operations corresponding to the multiple commands within memory system 110.

[0072] The controller 130 in the memory system 110 can control the memory device 150 in response to requests or commands from the host 102. For example, the controller 130 can perform a read operation to provide data read from the memory device 150 to the host 102, and can perform a write operation (or programming operation) to store data from the host 102 in the memory device 150. To perform data input / output (I / O) operations, the controller 130 can control internal operations such as data reading, data programming, and data erasure.

[0073] In some embodiments of the disclosed technology, controller 130 may include host interface 132, processor 134, error correction circuit (ECC) 138, power management unit (PMU) 140, memory interface 142, and memory 144. Depending on the structure, function, and operational performance of memory system 110, controller 130 may include different... Figure 2 The components shown.

[0074] For example, depending on the host interface protocol, the memory system 110 may include any of a variety of storage devices that can be electrically connected to the host 102. Examples of storage devices include solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), reduced-size MMCs (RS-MMCs), micro MMCs, secure digital cards (SDs), mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash storage (UFS) devices, compact flash (CF) cards, smart media (SM) cards, and memory sticks.

[0075] Each of the host 102 and the memory system 110 may include a controller or interface for sending and receiving commands, data, and other electrical signals according to one or more predetermined protocols. For example, the host interface 132 in the memory system 110 may include a device for sending commands, data, and other electrical signals to or from the host 102.

[0076] The host interface 132 included in controller 130 can receive commands (or requests), data, and other electrical signals from host 102. For example, host 102 and memory system 110 can send and receive data between them using predetermined protocols. Examples of protocols or interfaces supported by host 102 and memory system 110 for sending and receiving data include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Peripheral Component Interconnect Express (PCIe), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), and Mobile Industry Processor Interface (MIPI). In some embodiments of the disclosed technology, host interface 132 includes layers for exchanging data between host 102 and other devices, and includes firmware such as the Host Interface Layer (HIL).

[0077] Integrated Drive Electronics (IDE) devices or Advanced Technology Accessories (ATA) can be used as interfaces for sending and receiving data, and can, for example, use cables with multiple (e.g., 40) wires connected in parallel to support data transmission and reception between host 102 and memory system 110. When multiple memory systems 110 are connected to a single host 102, the multiple memory systems 110 can be divided into master and slave by using the positions or DIP switches to which the multiple memory systems 110 are connected. The memory system 110 set as master can be used as the primary memory device. IDE (ATA) can include, for example, Fast ATA, ATAPI, or Enhanced IDE (EIDE).

[0078] The Serial Advanced Technology Attachment (SATA) interface is a serial data communication interface compatible with various ATA standards for parallel data communication interfaces used by Integrated Drive Electronics (IDE) devices. The forty wires in an IDE interface can be reduced to six wires in a SATA interface. For example, the forty parallel signals of IDE can be converted to the six serial signals of a SATA interface. Due to its faster data transmission and reception rates and lower resource consumption for data transmission and reception in host 102, the SATA interface has been widely adopted. The SATA interface can connect up to thirty external devices to a single transceiver included in host 102. Furthermore, the SATA interface supports hot-plugging, allowing external devices to be attached to or detached from host 102 even while data communication between host 102 and another device is in progress. Therefore, the memory system 110 can be connected or disconnected as an attachment device, just like a device supported by Universal Serial Bus (USB), even when host 102 is powered on. For example, in a host 102 with an eSATA port, the storage system 110 can be freely attached to or detached from the host 102 like an external hard drive.

[0079] Small Computer System Interface (SCSI) is a serial data communication interface used to connect a computer or server to other peripheral devices. Compared to other interfaces such as IDE and SATA, SCSI can provide high transmission speeds. In SCSI, host 102 and at least one peripheral device (e.g., memory system 110) are connected in series, but data transmission and reception between host 102 and each peripheral device can be performed through parallel data communication. In SCSI, devices such as memory system 110 can be easily connected to or disconnected from host 102. SCSI can support up to 15 other devices connected to a single transceiver included in host 102.

[0080] Serial Attached SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, host 102 and multiple peripheral devices are connected in series, and data transmission and reception between host 102 and each peripheral device can be performed using a serial data communication scheme. SAS supports the connection between host 102 and peripheral devices via serial cables instead of parallel cables, making it easier to manage devices and enhance or improve operational reliability and communication performance. SAS can support up to eight external devices connected to a single transceiver included in host 102.

[0081] Non-volatile memory Express (NVMe) is an interface based at least on Peripheral Component Interconnect Express (PCIe), which is designed to improve the performance and design flexibility of a host 102, server, computing device, etc., equipped with a non-volatile memory system 110. PCIe can use slots or specific cables to connect computing devices (e.g., host 102) and peripheral devices (e.g., memory system 110). For example, PCIe can use multiple pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one wire (e.g., x1, x4, x8, or x16) to achieve high-speed data communication of hundreds of MB / s (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, or 1969 MB / s). In some embodiments of the disclosed technology, PCIe schemes can achieve bandwidths of tens to hundreds of gigabits per second. NVMe can support operating speeds of non-volatile memory systems 110 (e.g., SSDs) that are faster than hard drives.

[0082] In some embodiments of the disclosed technology, host 102 and memory system 110 can be connected via Universal Serial Bus (USB). Universal Serial Bus (USB) is a scalable, hot-pluggable, plug-and-play serial interface that provides a cost-effective standard connection between host 102 and peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, cameras, etc. Multiple peripheral devices, such as memory system 110, can be coupled to a single transceiver included in host 102.

[0083] Reference Figure 2 Error correction circuit 138 can correct erroneous bits in data read from memory device 150 and may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder performs error correction encoding on data to be programmed into memory device 150 to produce encoded data with added parity bits, and stores the encoded data in memory device 150. When controller 130 reads data stored in memory device 150, ECC decoder can detect and correct erroneous bits contained in the data read from memory device 150. For example, after performing error correction decoding on data read from memory device 150, error correction circuit 138 determines whether error correction decoding was successful and outputs a command signal (e.g., a correction success signal or a correction failure signal) based on the result of error correction decoding. Error correction circuit 138 can use parity bits generated during the ECC encoding process of data already stored in memory device 150 to correct erroneous bits in the read data. When the number of erroneous bits is greater than or equal to the number of correctable erroneous bits, error correction circuit 138 may not correct the erroneous bits but may instead output a correction failure signal indicating that the erroneous bit correction failed.

[0084] In some embodiments of the disclosed technology, the error correction circuit 138 may perform error correction operations based on coded modulation, such as low-density parity-check (LDPC) codes, Bosch-Chowdhury-Hokungamme (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc. The error correction circuit 138 may include all circuits, modules, systems, and / or devices for performing error correction operations based on at least one of the aforementioned codes.

[0085] For example, the EEC decoder can perform hard-decision decoding or soft-decision decoding on data sent from memory device 150. In one example, hard-decision decoding can correct erroneous bits by reading "0" or "1" bits of data from non-volatile memory cells in memory device 150. Because hard-decision decoding processes binary logic signals, the circuit / algorithm design or configuration can be simpler than soft-decision decoding, and the processing speed can be faster.

[0086] Soft-decision decoding can quantize the threshold voltage of a non-volatile memory cell in memory device 150 using two or more quantized values ​​(e.g., multi-bit data, approximations, analog values) to correct for erroneous bits based on the two or more quantized values. Controller 130 can receive two or more letters or quantized values ​​from multiple non-volatile memory cells in memory device 150 and then perform decoding based on information generated by characterizing the quantized values ​​as a combination of information such as conditional probabilities or likelihoods.

[0087] In some embodiments of the disclosed technology, the EEC decoder can use low-density parity-check generator matrix (LDPC-GM) codes for soft-decision decoding. Low-density parity-check (LDPC) codes use an algorithm capable of reading several bits from memory device 150 as data values ​​instead of simply reading the value "1" or "0" as in hard-decision decoding, and iteratively repeat this algorithm through message exchange to improve the reliability of the read values. The read value is then ultimately determined to be either "1" or "0". For example, the decoding algorithm using LDPC codes can be understood as probabilistic decoding. Unlike hard-decision decoding, soft-decision decoding can determine the value stored in a non-volatile memory cell based on random information. Soft-decision decoding can provide improved error correction capabilities when dealing with bit-flipping errors that may occur in memory device 150. In some implementations, the LDPC-GM code may include an internal LDGM code cascaded in series with a high-speed LDPC code.

[0088] In some embodiments of the disclosed technology, the EEC decoder can use, for example, low-density parity-check convolutional codes (LDPC-CC) for soft-decision decoding. Error correction associated with LDPC-CC can be achieved using linear-time coding and pipelined decoding based on variable block length and shift registers.

[0089] In some embodiments of the disclosed technology, the EEC decoder can use, for example, a log-likelihood ratio Turbo code (LLR-TC) for soft-decision decoding. The log-likelihood ratio (LLR) can be calculated as a nonlinear function of the distance between the sampled value and the ideal value. Furthermore, the Turbo code (TC) can include simple two-dimensional or three-dimensional codes (e.g., Hamming codes) and is repeatedly decoded in both row and column directions to improve the reliability of the values.

[0090] The power management unit (PMU) 140 can control the power supply to the controller 130. The PMU 140 can monitor the power supplied to the memory system 110 (e.g., the voltage supplied to the controller 130) and supply power to the components included in the controller 130. The PMU 140 can detect whether the memory system 110 is powered on or off and can generate a trigger signal so that the memory system 110 can use a backup power supply when the power supplied to the memory system 110 is unstable. In some embodiments of the disclosed technology, the PMU 140 may include means or components that can be recharged multiple times using an applied current to use power when no power supply is connected.

[0091] The memory interface 142 can be used as an interface for processing commands and data transferred between the controller 130 and the memory device 150, allowing the controller 130 to control the memory device 150 in response to commands or requests from the host 102. In the case that the memory device 150 is flash memory, the memory interface 142 can generate control signals for the memory device 150 and can process data input to or output from the memory device 150 under the control of the processor 134.

[0092] For example, when memory device 150 includes NAND flash memory, memory interface 142 includes a NAND flash controller (NFC). Memory interface 142 can provide an interface for processing commands and data between controller 130 and memory device 150. According to one embodiment, memory interface 142 can be implemented or driven by firmware called a flash interface layer (FIL) to exchange data with memory device 150.

[0093] In some embodiments of the disclosed technology, memory interface 142 may support Open NAND Flash Interface (ONFi), trigger mode, etc., for data input / output with memory device 150. For example, ONFi may use a data path (e.g., channel, path, etc.) including at least one signal line capable of supporting bidirectional transmission and reception in units of 8-bit or 16-bit data. Data communication between controller 130 and memory device 150 may be implemented through at least one interface relating to Asynchronous Single Data Rate (SDR), Synchronous Double Data Rate (DDR), Triggered Double Data Rate (DDR), etc.

[0094] Memory 144 can be used as working memory for memory system 110 or controller 130, while also temporarily storing transactional data for operations performed in memory system 110 and controller 130. For example, memory 144 can temporarily store read data output from memory device 150 in response to a read request from host 102 before the read data is output to host 102. Furthermore, controller 130 can temporarily store write data provided by host 102 in memory 144 before programming write data into memory device 150. When controller 130 controls the operation of memory device 150 (e.g., data read operation, data write or programming operation, data erase operation), data transmitted between controller 130 of memory system 110 and memory device 150 can be temporarily stored in memory 144.

[0095] In addition to reading or writing data, memory 144 may store information (e.g., mapped data, read requests, programming requests, etc.) used for inputting or outputting data between host 102 and memory device 150. In some embodiments of the disclosed technology, memory 144 may include one or more of a command queue, program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, mapping buffer / cache, etc. Controller 130 may allocate some storage space in memory 144 for components established for performing data input / output operations. For example, a write buffer established in memory 144 may be used to temporarily store target data for programming operations.

[0096] In one embodiment, memory 144 may include a volatile memory device. For example, memory 144 may include static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2The memory 144 is shown by way of example as being located inside the controller 130, but the disclosed technology is not limited thereto. The memory 144 may be located inside or outside the controller 130. For example, the memory 144 may include external volatile memory having a memory interface for transferring data and / or signals between the memory 144 and the controller 130.

[0097] Processor 134 can control the overall operation of memory system 110. For example, processor 134 can control programming or reading operations of memory device 150 in response to write or read requests from host 102. In some embodiments of the disclosed technology, processor 134 can perform firmware operations to control programming or reading operations in memory system 110. Here, firmware may include flash translation layer (FTL). Reference will be made below. Figure 3 and Figure 4 Examples describing FTL. In some embodiments of the disclosed technology, processor 134 may include a microprocessor, a central processing unit (CPU), or other similar processor.

[0098] In some embodiments of the disclosed technology, the memory system 110 may include at least one multi-core processor. A multi-core processor is a circuit or chip that integrates two or more cores that are considered different processing regions. For example, the data input / output speed (or performance) of the memory system 110 can be improved when multiple cores in the multi-core processor independently drive or execute multiple flash translation layers (FTLs). Based on some embodiments of the disclosed technology, data input / output (I / O) operations in the memory system 110 can be performed independently by different cores in the multi-core processor.

[0099] The processor 134 in controller 130 can execute operations corresponding to requests or commands from host 102. Furthermore, memory system 110 can perform operations independently of commands or requests from host 102. In one example, operations performed by controller 130 in response to requests or commands from host 102 can be considered foreground operations, while operations performed by controller 130 independently of requests or commands from host 102 can be considered background operations. Controller 130 can perform foreground or background operations to read, write, or erase data in memory device 150. Furthermore, parameter setting operations corresponding to setting parameter commands or setting function commands sent from host 102 can be considered foreground operations. As background operations performed without commands sent from host 102, controller 130 can perform garbage collection (GC), wear leveling (WL), bad block management for identifying and handling bad blocks, etc.

[0100] In the embodiments of the disclosed technology, the same or similar operations can be performed as foreground and background operations. For example, when the memory system 110 performs a garbage collection operation in response to a request or command from the host 102 (e.g., manual GC), the garbage collection operation can be considered a foreground operation. When the memory system 110 performs a garbage collection operation independently of the host 102 (e.g., automatic GC), the garbage collection operation can be considered a background operation.

[0101] When the memory device 150 includes multiple dies (or multiple chips), each die including multiple non-volatile memory cells, the controller 130 can perform parallel processing of multiple requests or commands regarding the host 102 to improve the performance of the memory system 110. For example, the sent requests or commands can be divided into multiple groups including at least some of the multiple planes, multiple dies, or multiple chips included in the memory device 150, and the requests or commands of multiple groups can be processed individually or in parallel in each plane, each die, or each chip.

[0102] The memory interface 142 in controller 130 can be connected to multiple dies or chips in memory device 150 via at least one channel and at least one path. When controller 130 distributes and stores data in multiple dies via each channel or path in response to a request or command associated with multiple pages including non-volatile memory cells, multiple operations corresponding to the request or command can be performed simultaneously or in parallel in multiple dies or planes. This processing method or scheme can be considered an interleaving method. Because the data input / output speed of memory system 110 is increased by utilizing the interleaving method, the data I / O performance of memory system 110 can be improved.

[0103] As an example and not a limitation, controller 130 can identify the status of multiple channels (or paths) associated with multiple dies included in memory device 150. Controller 130 can determine the status of each channel or path as one of busy, ready, active, idle, normal, and abnormal states. Determining which channel (and / or data) the controller transmits via can be associated with a physical block address. Controller 130 can refer to a descriptor transmitted from memory device 150. The descriptor can include blocks or pages containing parameters describing certain contents of memory device 150. The descriptor can have a predetermined format or structure. For example, the descriptor can include a device descriptor, configuration descriptor, cell descriptor, etc. Controller 130 can refer to or use the descriptor to determine which channel(s)(s) is used to exchange instructions or data.

[0104] Reference Figure 2The memory device 150 in the memory system 110 may include a plurality of memory blocks 152, 154, and 156. Each of the plurality of memory blocks 152, 154, and 156 includes a plurality of non-volatile memory cells. In some embodiments of the disclosed art, memory blocks 152, 154, and 156 may be a group of non-volatile memory cells erased together. Memory blocks 152, 154, and 156 may include a plurality of pages of a group of non-volatile memory cells that are read or programmed together.

[0105] In one embodiment, each memory block 152, 154, or 156 may have a three-dimensional stack-up structure for high integration. Furthermore, the memory device 150 may include multiple dies, each die including multiple planes, and each plane including multiple memory blocks 152, 154, 156. The configuration of the memory device 150 may vary depending on the performance of the memory system 110.

[0106] Figure 2 A memory device 150 is shown comprising multiple memory blocks 152, 154, and 156. Depending on the number of bits that can be stored in a single memory cell, the multiple memory blocks 152, 154, and 156 can be any of a single-level cell (SLC) memory block, a multi-level cell (MLC) memory block, etc. An SLC memory block comprises multiple pages implemented from memory cells, each memory cell storing one bit of data. SLC memory blocks can have higher data I / O performance and greater endurance than MLC memory blocks. An MLC memory block comprises multiple pages implemented from memory cells, each memory cell storing multiple bits of data (e.g., two or more bits of data). Compared to SLC memory blocks, MLC memory blocks can have a larger storage capacity for the same space. From a storage capacity perspective, MLC memory blocks can be highly integrated.

[0107] In one embodiment, the memory device 150 may include MLC memory blocks, such as two-level cell (DLC) memory blocks, three-level cell (TLC) memory blocks, four-level cell (QLC) memory blocks, and combinations thereof. A DLC memory block may include multiple pages implemented from memory cells, each memory cell capable of storing 2 bits of data. A TLC memory block may include multiple pages implemented from memory cells, each memory cell capable of storing 3 bits of data. A QLC memory block may include multiple pages implemented from memory cells, each memory cell capable of storing 4 bits of data. In another embodiment, the memory device 150 may include blocks comprising multiple pages implemented from memory cells, each memory cell capable of storing five or more bits of data.

[0108] In some embodiments of the disclosed technology, the controller 130 may use an MLC memory block included in the memory device 150 as an SLC memory block that stores one bit of data in a memory cell. The data input / output speed of a Multilevel Cell (MLC) memory block may be slower than that of an SLC memory block. That is, when an MLC memory block is used as an SLC memory block, the margin for read or programmable operations can be reduced. For example, when an MLC memory block is used as an SLC memory block, the controller 130 can perform data input / output operations at a higher speed. Therefore, since a buffer may require a high data input / output speed to improve the performance of the memory system 110, the controller 130 may use an MLC memory block as an SLC buffer to temporarily store data.

[0109] Furthermore, in some embodiments of the disclosed technology, the controller 130 can write data to the MLC more than once without performing an erase operation on a specific MLC memory block included in the memory device 150. Typically, non-volatile memory cells do not support data overwriting. However, since the MLC can be used to store multiple bits of data, the controller 130 can write one bit of data to the MLC more than once. For MLC overwrite operations, the controller 130 can store the number of write (programming) operations as separate operation information when writing one bit of data to the MLC. In some embodiments of the disclosed technology, write (programming) operations can be performed such that the threshold voltage of the MLC is uniformly distributed before performing another one-bit data write or programming operation.

[0110] In one embodiment, the memory device 150 includes a non-volatile memory such as flash memory (e.g., NAND flash memory, NOR flash memory, etc.). In another embodiment, the memory device 150 may be implemented by at least one of phase-change random access memory (PCRAM), ferroelectric random access memory (FRAM), transfer torque random access memory (STT-RAM), and spin-transfer torque magnetic random access memory (STT-MRAM).

[0111] Figure 3 An example of a data path connected to multiple devices is shown.

[0112] Reference Figure 3Multiple transceivers are connected to a data path (common bus). This data path is shared by the transceivers. In response to enable signals EN1, EN2, EN3, and EN4 and bus control signals CTLBUS1, CTLBUS2, CTLBUS3, and CTLBUS4, each transceiver can send or receive data via the shared data path (common bus). Because multiple transceivers share a single data path (common bus), they must send or receive data via the data path (common bus) at different timings or activation periods. When multiple transceivers send or receive data simultaneously on a single data path (common bus), or when the activation periods of enable signals EN1, EN2, EN3, and EN4 partially overlap, it may be difficult to ensure the integrity of the data transmitted via the data path (common bus).

[0113] Figure 4 Showing via Figure 3 The data path shown is an example of data communication.

[0114] Reference Figure 4 Used for control Figure 3 The control circuitry for the multiple transceivers described herein can transmit data in response to enable signals EN1, EN2, EN3, EN4 and bus control signals CTLBUS1, CTLBUS2, CTLBUS3, CTLBUS4 provided to the multiple transceivers based on a clock signal CLK. The clock signal CLK input to the control circuitry may be delayed or skewed due to various reasons (e.g., resistance). Skew can include the phenomenon that a signal that originally had the same or similar phase is offset at its point of arrival. For example, when a bit stream is transmitted simultaneously through two lines or channels, the bit streams may not arrive at the same time. When the bit streams arrive with a time difference, timing skew can be understood as having occurred. Even without two lines, the asynchronous timing of the clocks at the transmitting and receiving ends can be represented as skew. When skew occurs in the clock signal CLK, skew may also occur when processing the enable signals EN1, EN2, EN3, EN4 and bus control signals CTLBUS1, CTLBUS2, CTLBUS3, CTLBUS4 used to control the multiple transceivers.

[0115] Figure 4Two scenarios are illustrated as examples. In the first scenario (Scenario A), skew occurs when processing the clock signal CLK, enable signals EN1, EN2, EN3, EN4, and bus control signals CTLBUS1, CTLBUS2, CTLBUS3, CTLBUS4. Although the enable signals EN1 and EN2 controlling different transceivers are designed to activate at different timings or sequentially, due to the skew, some portions of the activation periods of enable signals EN1 and EN2 may overlap. This overlap presents a problem. When portions of the activation periods of enable signals EN1 and EN2 overlap, it may be difficult to ensure the integrity of data transmitted through the data path shared by the two transceivers. In this case, to prevent errors, the control circuit should delay the activation period of the first enable signal EN1 or shorten the activation period of the second enable signal EN2.

[0116] When different transceivers share a data path, they are designed to input or output data to the data path at different timings. However, in the second scenario (Case B), even if enable signals EN1 and EN2 are activated for different transceivers to input / output data at different timings, operational errors may cause overlap between the activation periods of enable signals EN1 and EN2. In this case, since the integrity of data transmitted through the shared data path may not be guaranteed, the control circuit should disable one of the enable signals EN2 and EN1 to prevent errors.

[0117] Figure 5 Examples of data communication devices, data paths, and interrupt paths based on some implementations of the disclosed technology are shown.

[0118] Reference Figure 5 Multiple data communication devices can be connected to data path 198 and interrupt path 196. That is, multiple data communication devices can share data path 198 and interrupt path 196. Each data communication device may include a transceiver 194 and an interrupt circuit 192. The transceiver 194 may include a tri-state buffer capable of inputting and outputting data in response to control signals. The transceiver 194 and interrupt circuit 192 included in each data communication device can be connected to data path 198 and interrupt path 196.

[0119] Figure 3 and Figure 5The data communication devices shown differ from one another. The enable signals EN1, EN2, EN3, and EN4 for transmitting and receiving data are not directly input to transceiver 194. However, these enable signals are input to interrupt circuit 192. For example, when the fourth enable signal EN4, activated to transmit / receive data, is applied to interrupt circuit 192, interrupt circuit 192 outputs a fourth control signal EN4_INT to control transceiver 194. Transceiver 194 can input / output data in response to the fourth control signal EN4_INT.

[0120] When the fourth enable signal EN4 is input to the interrupt circuit 192, the interrupt circuit 192 can modify the interrupt path 196. For example, the interrupt circuit 192 generates an interrupt signal corresponding to the fourth enable signal EN4. When the interrupt signal is applied to the interrupt path 196, the data communication device that has been sending and receiving data through the data path 198 can disable the control signals used to control the transceiver included therein. Furthermore, the interrupt circuit 192 can output a fourth control signal EN4_INT corresponding to the fourth enable signal EN4 to the transceiver 194, and the transceiver 194 can send / receive data through the data path 198. An interrupt signal is generated in response to the fourth enable signal EN4 before the transceiver 194 uses the data path 198 for data communication. In response to the interrupt signal, another data communication device or another transceiver using the data path 198 can be disabled before the transceiver 194 uses the data path 198. Therefore, conflicts or contentions can be avoided when the transceiver 194 uses the data path 198 in response to the fourth enable signal EN4.

[0121] Based on some embodiments of the disclosed technology, the data communication device may include an interrupt circuit 192 interoperable with transceiver 194. The interrupt circuit 192 can not only modify the interrupt path 196, but also recognize modifications in the interrupt path 196 (which may be implemented by another device). The interrupt circuit 192 can modify the interrupt path 196 to enable the transceiver 194 of the data communication device to send and receive data, and can detect modifications in the interrupt path 196 caused by another interrupt circuit included in another data communication device. Therefore, the interrupt circuit 192 can halt or stop the operation of the transceiver 194 in response to a detected modification in the interrupt path 196.

[0122] Reference Figure 5 The data communication device described, including transceiver 194 and interrupt circuit 192, can be applied to reference. Figure 1 to Figure 2 The memory device 150 is described. Figure 6 Show Figure 1 and Figure 2The example construction of the memory device is shown. Specifically, Figure 6 A portion of the first memory chip 182 included in the memory device 150 is shown as an example.

[0123] Reference Figure 6 The first memory chip 182 may include a transceiver 194 and an interrupt circuit 192. The transceiver 194 may be connected to a data path 198, and the interrupt circuit 192 may be connected to an interrupt path 196.

[0124] Data path 198 may include the first channel CH0 (see...) Figure 1 When the length of the first channel CH0 is short, the first channel CH0 may include wires used only for transmitting data. However, when the length of the first channel CH0 is long, changes in the magnitude or value of the data or signal transmitted in the first channel (CH0) may occur (e.g., overshoot / undershoot). Furthermore, in low-power environments with low drive power (e.g., low-power devices), changes in the magnitude or value of the data or signal may occur (e.g., overshoot / undershoot). To avoid this phenomenon (e.g., overshoot / undershoot), the data path 198 may include latches, pull-up / pull-down circuits, etc., to maintain or hold the data or signal transmitted via the first channel CH0.

[0125] Interrupt path 196 may include a first interrupt line INT_L0 and a switching circuit (such as...) Figure 8 As shown). Based on some implementations of the disclosed technology, the first interrupt line INT_L0 (such as...) Figure 1 (As shown) can be connected to a switching circuit capable of maintaining the active state (e.g., logic high) of the first interrupt line INT_L0. Similar to data path 198, the first interrupt line INT_L0 can be connected to other interrupt circuits included in other memory chips.

[0126] The first memory chip 182 can activate the enable signal EN to send / receive data. When the enable signal EN is activated, the interrupt circuit 192 can make changes to the first interrupt line INT_L0 included in the interrupt path 196. The interrupt circuit 192 can output setting signals EN_SET and EN_SETB to the interrupt path 196 in response to the enable signal EN. In addition, the interrupt circuit 192 can detect the change in the first interrupt line INT_L0 INTERRUPT. The interrupt circuit 192 can output a control signal EN_INT to the transceiver 194 in response to the enable signal EN and the change in the first interrupt line INT_L0 INTERRUPT. The transceiver 194 can send data DATA to the first channel CH0 included in the data path 198 in response to the channel control signal CH_CTRL and the control signal EN_INT.

[0127] Figure 7 An example of an interrupt circuit and interrupt path is shown. Specifically, Figure 7 Describe the circuit configuration of interrupt circuit 192 and interrupt path 196.

[0128] Reference Figure 7 Interrupt circuit 192 can receive enable signal EN and status reset signal POR, and output setting signals EN_SET, EN_SETB and control signal EN_INT. Interrupt path 196 may include interrupt line INT_L0 that changes its voltage value based on setting signals EN_SET and EN_SETB, and switch circuit 322 (PASS_TRS) connected to interrupt line INT_L0.

[0129] Interrupt circuit 192 may include a delay unit 302 capable of delaying the enable signal EN by a preset time. Delay unit 302 may include a first inverter 304 that inverts the enable signal EN to output an inverted enable signal ENB, and a delay unit 306 that delays the output of the first inverter 304 by a preset time. In some embodiments of the disclosed technology, delay unit 306 may include a plurality of inverters connected in series.

[0130] Interrupt circuit 192 may include a first NAND gate 308, which performs a NAND operation on the output of delay unit 302 and enable signal EN to generate setting signals EN_SETB and EN_SET. The first NAND gate 308 may output setting signals EN_SETB and EN_SET with pulse widths corresponding to the delay time of delay unit 302.

[0131] In some embodiments of the disclosed technology, the set inverted signal EN_SETB output from the first NAND gate 308 can be inverted by the second inverter 320, which can convert the set signal EN_SET. The set inverted signal EN_SETB and the set signal EN_SET can be applied to the interrupt path 196.

[0132] Interrupt circuit 192 may further include: a first NOR gate 310, which performs a NOR operation on the output of delay unit 302 and enable signal EN to produce a NOR operation result; and a second NOR gate 312, which performs a NOR operation on the output of first NOR gate 310 and status reset signal POR to output a NOR operation result. The second NOR gate 312 may generate an enable reset signal EN_RST.

[0133] Interrupt circuit 192 may include a first AND gate 318, which performs an AND operation on the flip-flop output signal EN_DFF and the enable signal EN to output a control signal EN_INT. Furthermore, interrupt circuit 192 may also include: a third NOR gate 314, which performs a NOR operation on the flip-flop output signal EN_DFF and the enable inverting signal ENB to output a NOR output signal EN_NOR; and a flip-flop 316 (DFF), which, in response to the interrupt signal INTERRUPT, outputs the NOR output signal EN_NOR from the third NOR gate 314 as the flip-flop output signal EN_DFF.

[0134] Reference Figure 7 The interrupt signal INTERRUPT, sent via interrupt path 196, is applied to the clock input CK of flip-flop 316. Flip-flop 316 can output a NOR signal EN_NOR as the flip-flop output signal EN_DFF in response to the interrupt signal INTERRUPT. Even if the input enable signal EN is activated, the control signal EN_INT output from the first AND gate 318 may not be activated immediately. The control signal EN_INT can be activated based on the flip-flop output signal EN_DFF output by flip-flop 316 in response to the interrupt signal INTERRUPT. Interrupt circuit 192 can generate the interrupt signal INTERRUPT in interrupt path 196 in response to the input enable signal EN, and then output it for use by transceiver 194 (e.g., ...). Figure 6 The control signal EN_INT (as shown) is used to input and output data.

[0135] Depending on the state of the enable signal EN, the third NOR gate 314 and the flip-flop 316 can output different results in response to the interrupt signal INTERRUPT. Because the enable inverting signal ENB is disabled when the enable signal EN is active, the third NOR gate 314 can be used as an inverter to invert the states of the NOR output signal EN_NOR and the flip-flop output signal EN_DFF. That is, the state opposite to the previous state can be output as the next state. However, because the enable inverting signal ENB is active when the enable signal EN is disabled, the third NOR gate 314 can disable the NOR output signal EN_NOR. Through these operations, in response to the interrupt signal INTERRUPT, the flip-flop 316 can be disabled when the control signal EN_INT is active, and can be kept in the disabled state when the control signal EN_INT is disabled.

[0136] In some embodiments of the disclosed technology, multiple interrupt circuits may be connected to interrupt path 196. The interrupt signal INTERRUPT transmitted via interrupt path 196 is also detected by another interrupt circuit included in another memory chip or another data communication device. If a transceiver is present using the first channel CH0 corresponding to the first interrupt line INT_L0, the interrupt circuit corresponding to that transceiver may abort or stop the operation of that transceiver in response to the interrupt signal INTERRUPT.

[0137] Figure 8 Show connection to Figure 7 An example of the switching circuit 322 for interrupt path 196 is shown.

[0138] Reference Figure 7 and Figure 8 The interrupt line INT_L0 included in interrupt path 196 can be kept active by switching circuit 322. The voltage of interrupt line INT_L0 can be changed in response to setting signals EN_SET and EN_SETB output from any interrupt circuit 192 connected to interrupt line INT_L0. According to an embodiment, because interrupt circuit 192 may not include a driver for lowering the potential of interrupt line INT_L0, switching circuit 322 can slightly or weakly activate interrupt line INT_L0. Interrupt circuit 192 may not meaningfully change the potential of interrupt line INT_L0 if switching circuit 322 might drive interrupt line INT_L0 with too much power.

[0139] In some embodiments of the disclosed technology, the switching circuit 322 may include a plurality of transistors connected in series between the internal power supply voltage VCCI and the interrupt line INT_L0. Because each transistor has a gate connected to the internal ground voltage VSSI, the plurality of transistors can remain in an on state.

[0140] Figure 9 An example operation of the interrupt circuit is shown. Specifically, Figure 9 Describes reference Figure 7 The internal operation of the interrupt circuit 192 is described.

[0141] The enable signal EN input to the interrupt circuit 192 can be activated. When the enable signal EN is activated, the setting signal EN_SET and the setting inverted signal EN_SETB can be generated simultaneously by the delay unit 302 after a preset time (refer to (1)). At the same time, in response to the enable inverted signal ENB, the third NOR gate 314 can activate the NOR output signal EN_NOR to a logic high level.

[0142] The set signal EN_SET and the set inverted signal EN_SETB can be sent to interrupt path 196 to trigger the interrupt signal INTERRUPT (see (2)).

[0143] When an interrupt signal INTERRUPT is generated (e.g., synchronized with a rising edge), flip-flop 316 can output the NOR signal EN_NOR as the flip-flop output signal EN_DFF (ref (3)).

[0144] When the flip-flop output signal EN_DFF is activated to a logic high level, the first AND gate 318 can activate the control signal EN_INT in response to the enable signal EN (see (4)). When the control signal EN_INT is activated, data can be input or output through the transceiver 194 (e.g., ...). Figure 6 (As shown).

[0145] After this, the input enable signal EN can be disabled. The disabled enable signal EN can disable the enable reset signal EN_RST and the control signal EN_INT (see (5)).

[0146] Reference Figure 9 In response to the enable signal EN activated for sending or receiving data, interrupt circuit 192 can generate an interrupt signal INTERRUPT and then activate the control signal EN_INT for controlling transceiver 194. If the interrupt signal INTERRUPT can be generated before data transmission / reception, another transceiver or other data communication device sharing interrupt path 196 can recognize that another device besides itself will perform data transmission / reception. Accordingly, any transceiver or data communication device already using data path 198 can stop data input / output operations or data transmission operations, allowing the data communication device that generated the interrupt signal INTERRUPT to perform data input / output operations or data transmission operations through the included transceiver. Through this process, even if multiple data communication devices share a single data path, contention for data path occupancy can be avoided. Therefore, the integrity of data transmitted through the data path can be ensured.

[0147] Figure 10 This illustrates an example of data communication device operation. Specifically, Figure 10 An example is shown where two data communication devices perform data input / output operations independently.

[0148] Reference Figure 10When the first enable signal EN1 is activated to a logic high level, the first set signal EN1_SET can be activated. When the first set signal EN1_SET is activated, an interrupt signal INTERRUPT can be generated. In response to the interrupt signal INTERRUPT and the first enable signal EN1, the first control signal EN1_INT can be activated. The process of activating the first control signal EN1_INT to a logic high level can be compared with reference to... Figure 9 The described processes are basically the same.

[0149] The second enable signal EN2 can be activated to a logic high level when the first enable signal EN1 is activated (see reference). Figure 4 (Example described). When multiple data communication devices share a single communication line, a data conflict may occur if one data communication device cannot control another data communication device before or during its data transmission. The second setting signal EN2_SET can be activated when the second enable signal EN2 is activated to a logic high level. When the second setting signal EN2_SET is activated, an interrupt signal INTERRUPT can be generated. When the interrupt signal INTERRUPT is generated, the first control signal EN1_INT can be disabled and the second control signal EN2_INT can be activated. Through this process, contention for occupying a single communication line can be avoided, and the integrity of data transmitted through the single communication line can be ensured.

[0150] Specifically, this can be achieved through the operation of the third NOR gate 314 and flip-flop 316 in the first interrupt circuit that outputs the first control signal EN1_INT (see...). Figure 7 The first control signal EN1_INT is disabled by a third NOR gate 314. When the first enable signal EN is activated, the first enable inverted signal ENB is disabled, allowing the third NOR gate 314 to be used as an inverter to invert the states of the NOR output signal EN_NOR and the flip-flop output signal EN_DFF. In other words, the flip-flop 316 in the first interrupt circuit can output the disabled state of the first control signal EN1_INT, which is the opposite of its previous state, as the next state. Simultaneously, the third NOR gate and flip-flop in the second interrupt circuit, which outputs the second control signal EN2_INT, can output the activated state of the second control signal EN2_INT, which is the opposite of its previous state, as the next state. Therefore, in response to the interrupt signal INTERRUPT, the first control signal EN1_INT can be disabled, while the second control signal EN2_INT can be activated.

[0151] Subsequently, when the second enable signal EN2 is disabled, the second control signal EN2_INT can also be disabled. As described above, even if the second enable signal EN2 is activated to a logic high level due to a fault while the first enable signal EN1 is activated, the first control signal EN1_INT can be disabled in response to the activation of the second enable signal EN2, and the second control signal EN2_INT can be activated. Therefore, two transceivers sharing a single data path can avoid collisions by receiving or transmitting data according to the first control signal EN1_INT and the second control signal EN2_INT.

[0152] In some embodiments of the disclosed technology, after the first control signal EN1_INT and the second control signal EN2_INT are disabled, the state reset signal POR (as shown in the image) is activated. Figure 7 As shown, the status reset signal POR can be applied to the interrupt circuit. In this document, the status reset signal POR can be applied to the first interrupt circuit after a preset time following the disable time of the first control signal EN1_INT. Furthermore, the status reset signal POR can be applied to the second interrupt circuit after a preset time following the disable time of the second control signal EN2_INT. Through these operations, the flip-flops included in the first and second interrupt circuits can be reset (Local DFF Reset).

[0153] In subsequent operations, after activating the second enable signal EN2, the second setting signal EN2_SET can be activated. When the second setting signal EN2_SET is activated, an interrupt signal INTERRUPT can be generated. When the interrupt signal INTERRUPT is generated, the second control signal EN2_INT can be activated. In this case, because the first enable signal EN1 is inactive, the first control signal EN1_INT may not be activated even when the interrupt signal INTERRUPT is generated. Thereafter, when the second enable signal EN2 is disabled, the second control signal EN2_INT can also be disabled.

[0154] After disabling the second enable signal EN2, the first enable signal EN1 can be activated. When the first enable signal EN1 is activated to a logic high level, the first set signal EN1_SET can be activated. When the first set signal EN1_SET is activated, an interrupt signal INTERRUPT can be generated. In response to the interrupt signal INTERRUPT and the first enable signal EN1, the first control signal EN1_INT can be activated. Even in this case, because the second enable signal EN1 is inactive, the second control signal EN2_INT may not be activated even when the interrupt signal INTERRUPT is generated. Subsequently, when the first enable signal EN1 is disabled, the first control signal EN1_INT can also be disabled.

[0155] As described above, when two transceivers sharing a data path send and receive data at different time intervals (i.e., when the first control signal EN1_INT and the second control signal EN2_INT are activated at different time intervals), each transceiver can reliably send and receive data through the shared data channel without interfering with the other transceiver.

[0156] Figure 11 This demonstrates how data communication can be performed based on some implementations of the disclosed technology.

[0157] Reference Figure 11 The method for performing data communication may include: receiving an activation signal for sending and receiving data (at 912), generating a first interrupt signal based on the activation signal (at 914), activating a control signal for the transceiver in response to the activation signal and the first interrupt signal (at 916), and sending or receiving data via the transceiver in response to the control signal (at 918). In some embodiments of the disclosed technology, the activation signal may correspond to reference... Figure 7 to Figure 10 The enable signal EN is described, and the control signal can correspond to the reference. Figure 7 to Figure 10 The control signal EN_INT is described.

[0158] Here, the data path used by one transceiver to send and receive data can be shared by another transceiver. That is, multiple transceivers or multiple data communication devices can send or receive data through a shared data path. Simultaneously, the first interrupt signal can be transmitted through the interrupt path instead of the data path. Multiple transceivers or multiple data communication devices sharing a data path can also share the interrupt path corresponding to the data path.

[0159] Although not illustrated, the method of performing data communication may also include maintaining a first state of disabling the control signal and disabling the control signal in response to the first state and a second interrupt signal. The data communication device may disable a previously activated control signal in response to a second interrupt signal generated after the control signal for activating the transceiver. In this document, the first and second interrupt signals may be generated and output from different data communication devices.

[0160] In some implementations, the method for performing data communication may further include disabling control signals when an activation signal is disabled. Furthermore, the method may also include applying a state reset signal after disabling control signals. In this way, collisions can be avoided even if multiple transceivers share a single data path to send or receive data. Each transceiver can perform data transmission or reception operations at different (i.e., non-overlapping) time periods.

[0161] Although some implementations of the disclosed technology include multiple memory devices, conflicts can be avoided during data input / output, thereby improving the security of data input / output operations.

[0162] Furthermore, memory systems based on some embodiments of the disclosed technology can avoid overlapping transmission of signals or data via multiple transceivers, thereby ensuring data integrity during data communication using data paths shared by multiple transceivers.

[0163] Although various implementation methods have been described, it will be apparent to those skilled in the art that various modifications and variations can be made based on the disclosure of this patent document.

[0164] Cross-references to related applications

[0165] This patent document claims priority and benefit to Korean Patent Application No. 10-2021-0056338, filed on April 30, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A data communication device comprising: a transceiver coupled to a data path and transmitting or receiving data through the data path; and an interrupt circuit coupled to an interrupt path corresponding to the data path and determining whether to allow any device to occupy the data path, wherein the data path is configured to transfer first data transmitted by the data communication device and second data transmitted by another device, and the interrupt path includes a first line configured to transfer a first interrupt signal transmitted by the data communication device and a second interrupt signal transmitted by the another device at different times, wherein the first line is coupled to a switching circuit including a plurality of transistors connected in series between a power supply terminal for providing a voltage and the first line, wherein the interrupt circuit generates the first interrupt signal for preventing the another device from accessing the data path in response to an activation signal for transmitting or receiving the first data by the transceiver. The interrupt circuit disables the transceiver when the second interrupt signal is received via the interrupt path.

2. The data communication device of claim 1, wherein, 3. The data communication device of claim 2, further comprising: a memory bank coupled to the data path, the memory bank including a plurality of volatile memory cells or a plurality of non-volatile memory cells storing the data. The interrupt circuit generates a control signal for activating the transceiver after generating the first interrupt signal in response to the activation signal.

4. The data communication device of claim 1, wherein, The transceiver includes a tri-state buffer transmitting or receiving the data based on the control signal.

5. The data communication device of claim 4, wherein, The second interrupt signal is generated by the another device.

6. The data communication device of claim 2, wherein, 7. A memory system comprising: a data path via which a plurality of transceivers can transmit data, and the data path is configured to transfer data transmitted from one of the plurality of transceivers to another transceiver; and an interrupt path via which a plurality of interrupt circuits can transmit an interrupt signal, the interrupt path is configured to transfer the interrupt signal for interrupting access to the data path corresponding to the interrupt path, wherein a first interrupt circuit of the plurality of interrupt circuits generates a first interrupt signal that is transmitted through the interrupt path before a first transceiver corresponding to the first interrupt circuit transmits data via the data path to interrupt access by the plurality of transceivers, and wherein the interrupt path includes a first line configured to transfer the first interrupt signal transmitted by the first transceiver and a second interrupt signal transmitted by a second transceiver different from the first transceiver at different times, wherein the first line is coupled to a switching circuit including a plurality of transistors connected in series between a power supply terminal for providing a voltage and the first line.

8. The memory system of claim 7, further comprising: ​ a plurality of memory chips each including at least one of a volatile memory cell array or a non-volatile memory cell array; and a controller controlling data input / output operations performed in the plurality of memory chips, wherein each of the plurality of memory chips includes one of the plurality of transceivers and one of the plurality of interrupt circuits, and wherein the data path includes at least one channel coupling the controller to the plurality of memory chips.

9. The memory system of claim 7, wherein, The first interrupt circuit disables the first transceiver when the second interrupt signal is received via the interrupt path.

10. The memory system of claim 7, wherein, The first interrupt circuit generates a control signal for activating the first transceiver after generating the first interrupt signal in response to a first signal input to the first transceiver for transmitting the data.

11. The memory system of claim 10, wherein, The first transceiver includes a tri-state buffer transmitting or receiving the data based on the control signal.

12. The memory system of claim 7, wherein, The switch circuit activates or disables the first line in response to a set signal provided by the plurality of interrupt circuits.

13. The memory system of claim 10, wherein, The first interrupt circuit includes: a first component generating a set signal for activating the interrupt path in response to the first signal; a second component generating a control signal for activating the first transceiver in response to the first signal; a third component disabling the control signal when the interrupt path is activated; and a fourth component resetting the control signal based on a state reset signal.

14. The memory system of claim 13, wherein, The first component includes a delay unit delaying the first signal by a preset time.

15. A data communication method, the data communication method comprising the steps of: receiving, by a first device of a plurality of devices, an activation signal for transmitting or receiving data via a data path via which the plurality of devices can transmit or receive data; generating a first interrupt signal for interrupting access of the plurality of devices based on the activation signal, wherein the first interrupt signal is transmitted via an interrupt path via which the plurality of devices can transmit interrupt signals, wherein the interrupt path includes a first line configured to convey the first interrupt signal transmitted by the first device and a second interrupt signal transmitted by a second device different from the first device at different times, wherein the first line is coupled to a switch circuit including a plurality of transistors connected in series between a power supply terminal for providing a voltage and the first line; activating a control signal to be applied to the first device based on the first interrupt signal and the activation signal; and transmitting or receiving the data by the first device based on the control signal.

16. The data communication method of claim 15, further comprising the steps of: maintaining a first state for disabling the control signal when the activation signal is not input; and disabling the control signal based on the first state and the second interrupt signal. ​ 17. The data communication method of claim 16, wherein, The second interrupt signal is output by the second device of the plurality of devices different from the first device.

18. The data communication method according to claim 15, further comprising the steps of: disabling the control signal upon disabling the activation signal.

19. The data communication method according to claim 15, further comprising the steps of: applying a state reset signal upon disabling the control signal.

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