Electronic devices and signal processing methods

Abstract

This application provides an electronic device and a signal processing method; wherein the electronic device includes a first processing unit and a second processing unit, the first processing unit and the second processing unit communicate via a first bus; the second processing unit is at least configured to send a first signal to the first processing unit based on the first bus; the first processing unit is at least configured to receive a second signal sent by the second processing unit via the first bus, the type of the second signal including a first type and / or a second type, wherein the first type is different from the second type, and the first type corresponds to the first bus.

Description

Technical Field

[0001] This application relates to electronic technology, including but not limited to electronic devices and signal processing methods. Background Technology

[0002] A bus is a common communication trunk line for transmitting information between various functional components of an electronic device. According to the types of information transmitted by the computer, the bus of an electronic device can be divided into a data bus, an address bus, and a control bus, which are used to transmit different types of signals, such as data, data addresses, and control signals. However, the existing bus structure and communication methods cannot fully utilize the resources of electronic devices. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, an electronic device is provided, the electronic device including a first processing unit and a second processing unit, the first processing unit and the second processing unit communicating via a first bus; the second processing unit is at least configured to send a first signal to the first processing unit based on the first bus; the first processing unit is at least configured to receive a second signal sent by the second processing unit via the first bus, the type of the second signal including a first type and / or a second type, wherein the first type is different from the second type, and the first type corresponds to the first bus.

[0004] According to one aspect of the embodiments of this application, a signal processing method is provided, applied in an electronic device, the electronic device including: a first processing unit and a second processing unit, the first processing unit and the second processing unit communicating through a first bus; the method including: receiving a first signal sent by the first processing unit via the first bus through the second processing unit; receiving a second signal sent by the second processing unit via the first bus through the first processing unit, wherein the type of the signal to be processed includes a first type and / or a second type, wherein the first type is different from the second type, and the first type corresponds to the first bus.

[0005] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0006] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0007] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0008] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0009] Figure 2 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0010] Figure 3 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0011] Figure 4 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0012] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0013] Figure 6 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0014] Figure 7 A schematic diagram illustrating the implementation flow of a signal processing method provided in an embodiment of this application;

[0015] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0016] Figure 9 This is a schematic diagram illustrating the implementation process of a signal processing method provided in an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of this application will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate this application, but are not intended to limit the scope of this application.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0019] In the following description, references to "some embodiments," "this embodiment," "this application embodiment," and examples, etc., describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subset of all possible embodiments and may be combined with each other without conflict.

[0020] This application provides an electronic device. Figure 1 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application, such as... Figure 1 As shown, the electronic device 10 includes at least: a first processing unit 101, a second processing unit 102, and a first bus 103; wherein,

[0021] The second processing unit 102 is at least configured to send a first signal to the first processing unit 101 based on the first bus 103; the first processing unit 101 is at least configured to receive a second signal sent by the second processing unit via the first bus 103, wherein the type of the second signal includes a first type and / or a second type; wherein the first type is different from the second type, and the first type corresponds to the first bus 103.

[0022] In some embodiments, the first processing unit may be an embedded controller (EC), which can at least be used to manage the input and output states of built-in components and / or external components of an electronic device, and the second processing unit may be an artificial intelligence (AI) chip.

[0023] In some embodiments, the first signal may be an interrupt signal. When a register inside the first processing unit changes, the first processing unit sends the first signal to the second processing unit so that the second processing unit can perform a corresponding task according to the first signal.

[0024] In some embodiments, the first bus may be an Inter-Integrated Circuit (I2C) bus, and the first processing unit and the second processing unit are connected via the I2C bus to realize communication between them. The I2C bus includes at least a serial data line (SDA) and a serial clock line (SCL). The connection between the first processing unit and the second processing unit via the I2C bus can also be understood as the first processing unit and the second processing unit being respectively connected to the SDA and SCL of the I2C bus.

[0025] In some embodiments, before sending the second signal to the first processing unit, the second processing unit may first determine the type of the second signal; the type of the second signal includes a first type and a second type; wherein, the first type corresponds to the I2C bus, and the second signal of the first type can be denoted as an I2C signal, which can be a data signal or a command signal, used to instruct the first processing submodule in the first processing unit to execute the task corresponding to the I2C signal, and is not used to instruct the setting of the registers inside the second processing submodule of the first processing unit; the second signal of the second type can be denoted as a second processing submodule signal, which can be a command signal, and the second signal of the second type can be used to instruct the second processing submodule of the first processing unit to set its own internal registers; that is, the second signal of the second type can be a control signal used to control the second processing submodule, and the second signal of the first type can be a data signal or a command signal transmitted by the second processing unit to the second processing submodule.

[0026] In some embodiments, if the second signal is a data signal, the second processing unit treats it as the first signal; if the second signal is a command signal, the second processing unit can determine the type of the second signal at least according to a pre-built signal configuration table.

[0027] In some embodiments, the signal configuration table is determined at least according to a predefined correspondence between a first device and the second signal type; the first device may be a switch of a built-in component and / or an external component of the electronic device.

[0028] In some embodiments, a second signal for controlling a switch of an internal component of an electronic device can be defined as a second signal of a first type; wherein, the switch of the internal component of the electronic device can be a switch for controlling the system state, etc., and correspondingly, the second signal of the first type can be a signal for turning the system state switch off and / or on, etc.

[0029] In some embodiments, a second signal for controlling a switch of an external component of an electronic device can be defined as a second type of second signal, wherein the switch of the external component of the electronic device can be an LED switch and a keyboard switch, etc. Accordingly, the second type of second signal is a signal for turning off and / or on an LED switch, a signal for turning off and / or on a keyboard switch, etc.

[0030] It should be noted that, in the embodiments of this application, the correspondence between the first device and the second signal type is not limited to the above definition method. The embodiments of this application do not limit the definition of the correspondence between the first device and the second signal type, and can be defined according to actual usage requirements.

[0031] Furthermore, in some embodiments, such as Figure 2As shown, the first processing unit 101 includes a signal port module 201, a first processing submodule 202, and a second processing submodule 203. The signal port module 201 can be an I2C port of an I2C bus. If a second signal of the first type is received, the signal port module 201 can send the second signal of the first type to the first processing submodule 202 so that the first processing submodule can process the second signal of the first type. If a second signal of the second type is received, the signal port module 201 sends the second signal of the second type to the second processing submodule 203 so that the second processing submodule 203 can control the output state of the first device corresponding to the second signal of the second type.

[0032] Understandably, in the embodiments of this application, the I2C port of the I2C bus can not only receive I2C signals of the same type as itself, but also receive second signals of the second type. In this way, the transmission of two types of signals can share a set of I2C pins, saving system resources.

[0033] In some embodiments, the first processing submodule may be a central processing unit (CPU); if the second signal is a data signal, the CPU may perform data processing and other operations on the data signal sent by the second processing unit via the I2C bus. If the second signal is a command signal, the CPU may control the output state of the first device corresponding to the second type of second signal by setting the value of at least one register in its internal I2C controller.

[0034] In some embodiments, the second processing submodule may be a general-purpose input / output (GPIO) controller, and correspondingly, the second signal of the second type may be referred to as a GPIO signal; the GPIO controller includes at least one GPIO module, different GPIO modules are connected to different first devices, and the second processing unit can control the output state of the corresponding first device by setting the value of the register in the GPIO module; correspondingly, the second signal of the second type may be a control signal used to control the second processing submodule, thereby controlling the output state of the first device.

[0035] For example, if the second signal is a command signal to turn off the LED switch, that is, the type of the second signal is the second type, then the signal port module sends the command signal to turn off the LED switch to the GPIO controller. The GPIO controller sets the value of the register in the GPIO module connected to the LED switch to the corresponding value according to the command signal, so that the output level of the GPIO module is low, thereby turning off the LED switch.

[0036] Understandably, the second processing unit can send GPIO signals to the second processing submodule of the first processing unit via the first bus, so that the second processing submodule can set the values ​​of the registers in the corresponding GPIO module to control the output state of the corresponding first device. In this way, the second processing unit can use the GPIO modules in the first processing unit when its own GPIO modules are insufficient, achieving efficient utilization of electronic device resources.

[0037] In some embodiments, such as Figure 3 As shown, the first processing submodule 202 includes a first control core 301 and a second control core 302; the first control core includes at least one acceleration unit for performing a first operation, the first operation including AI-related operations; the second control core is used to perform a second operation, the second operation being different from the first operation.

[0038] In some embodiments, the first operation includes at least one of the following: vector operation, feature extraction, and other neural network operations different from the vector operation and the feature extraction; correspondingly, the at least one acceleration unit includes at least one of the following: a vector acceleration unit (Vector) 3011, a signal processing acceleration unit (SignalProcessing Accelerator, SPA) 3012, and a deep learning acceleration unit (Deep Learning Accelerator, DLA) 3013; wherein, the vector acceleration unit 3011 is used to perform the vector operation; the signal processing acceleration unit 3012 is used to perform the feature extraction; and the deep learning acceleration unit 3013 is used to perform other neural network operations.

[0039] In some embodiments, the second processing core is further configured to allocate operations to be performed; the operations to be performed include the first operation and / or the second operation.

[0040] In some embodiments, the second processing core is configured to allocate the computational task to be executed based on at least one of the following: the computational task type; the task processing status of the first processing core; and the task processing status of the second processing core.

[0041] In some embodiments, the first processing core 301 may be a distributed processing unit (DPU) of a central processing unit, such as... Figure 3 As shown, the first processing core also includes a first fifth-generation reduced instruction set computer core (5... thReduced Instruction Set Computer (RISC-V core 1) 3014 and Rocket Custom Coprocessor Interface (ROCC I / F) 3015.

[0042] In some embodiments, the first processing module establishes a communication connection with the second processing core, and can obtain the computing tasks allocated by the second processing core to the first processing core through the communication connection, and allocate the first computing tasks to the corresponding acceleration units.

[0043] Understandably, after the second processing core allocates the computational tasks, the computational tasks can be further subdivided through the RISC-V core1 of the first processing core, making the subdivided computational tasks more suitable for each acceleration unit.

[0044] In some embodiments, the second processing core 302 includes a RISC-V core2 3021 and a floating point unit (FPU) 3022. The second processing core is also configured to initialize the first processing core upon its own startup; thus, starting the second processing core and initializing the first processing core occur simultaneously, rather than waiting until the second processing core has successfully started before initializing the first processing core. This earlier initialization allows the first processing core to be prepared in advance for task execution.

[0045] In some embodiments, such as Figure 3 As shown, the first processing unit 101 further includes a first storage unit 1011 and a second storage unit 1012.

[0046] In some embodiments, the first storage unit 1011 may be a dynamic random access memory (DRAM), and the second storage unit 1012 may be a static random access memory (SRAM); the read / write speed of the first storage unit is lower than that of the second storage unit; the first storage unit is used to transfer the data required for the first operation to the second storage unit; the first processing core is used to read the data required to execute the first operation from the first storage unit, thereby executing the first operation based on the required data; thus, the data related to the first operation to be executed is stored in a storage unit with a faster read / write speed, ensuring the processing speed of the current first operation task when executing multiple operation tasks.

[0047] In some embodiments, such as Figure 4As shown, the signal port module 201 includes a first port 401 and a second port 402; the first port 401 is used to receive a second signal of a first type, and the second port 402 is used to receive a second signal of a second type.

[0048] In some other embodiments, such as Figure 5 As shown, the signal port module 201 includes a third port 501 and a signal identification module 502. If the second processing module does not determine the type of the second signal before sending the second signal, the third port 501 will send the second signal to the signal identification module 502 after receiving the second signal. The signal identification module can identify the signal type of the second signal at least according to a pre-built signal configuration table, and send the second signal to the first processing submodule or the second processing submodule for processing according to the signal type.

[0049] In some embodiments, such as Figure 6 As shown, the first processing unit includes a fourth port 601. The fourth port can be a port used to transmit interrupt signals; the first processing submodule can send a first interrupt signal to the second processing unit through the fourth port 601, and the second processing submodule can send a second interrupt signal to the second processing unit through the fourth port 601. The fourth port is not limited to... Figure 6 As shown, Figure 6 This is just one example, where the function of the fourth port can be performed by the first, second, or third port. That is, the first, second, and third ports are bidirectional transmission ports, capable of receiving and sending data signals.

[0050] Understandably, in some embodiments, if a user wants to change the state of the first device, when the user gives an input instruction to change the state of the first device, the value of at least one register in the first processing submodule corresponding to the first device will change; accordingly, when the first processing submodule obtains the change, it sends a first interrupt signal to the second processing unit, so that the second processing unit reads the value of the at least one register based on the first interrupt signal, and changes the working state of the first device according to the value of the at least one register.

[0051] In some other embodiments, when a user provides an input command to change the state of the first device, the value of the register in the GPIO module connected to the first device in the second processing submodule changes. Accordingly, when the second processing submodule detects this change, it sends a second interrupt signal to the second processing unit, so that the second processor can read the value of the second register based on the second interrupt signal and change the operating state of the first device according to the value of the second register.

[0052] This application provides a signal processing method applied in an electronic device, the electronic device including a first processing unit and a second processing unit, the first processing unit and the second processing unit communicating through a first bus; Figure 7 This is a schematic diagram illustrating the implementation flow of the signal processing method provided in the embodiments of this application, such as... Figure 7 As shown, the method may include the following steps 701 to 703:

[0053] Step 701: The second processing unit receives the first signal sent by the first processing unit via the first bus.

[0054] In some embodiments, the first signal may be an interrupt signal. When a register inside the first processing unit changes, the first processing unit sends the first signal to the second processing unit so that the second processing unit can perform a corresponding task based on the first signal.

[0055] Step 702: The first processing unit receives a second signal sent by the second processing unit via the first bus. The type of the signal to be processed includes a first type and / or a second type, wherein the first type is different from the second type and the first type corresponds to the first bus.

[0056] In some embodiments, if the signal port module of the first processing unit receives a second signal of the first type, it sends the second signal of the first type to the first processing submodule of the first processing unit through the signal port module, so that the first processing submodule processes the first signal; if the signal port module receives a second signal of the second type, it sends the second signal of the second type to the second processing submodule of the first processing unit through the signal port module, so that the second processing submodule controls the working state of the corresponding first device based on the second signal of the second type.

[0057] Based on this, the following will describe an exemplary application of the embodiments of this application in a practical application scenario.

[0058] In some embodiments, electronic device systems are becoming increasingly intelligent, and many functions require the application of artificial intelligence computation. As comprehensive computing units, CPUs and graphics processing units (GPUs) need to process processes and events in parallel. If all artificial intelligence algorithms run on the CPU or GPU, it will increase the load on the CPU or GPU and the system power consumption, and cause some functions to be unresponsive.

[0059] Some AI chips focus primarily on video-related processing, using video streams from cameras to achieve functions such as human body recognition and facial recognition. However, they also have significant drawbacks: for example, using a single AI core to control all acceleration engines results in excessive load on the AI ​​core, relatively high power consumption, inability to support ultrasound, and the microphone (MIC) not supporting listening mode.

[0060] The first processing unit provided in this application embodiment integrates two AI computing cores. The second processing core mainly processes general system tasks and initializes the first processing core. The first processing core integrates a vector instruction set, a neural network (NN) acceleration engine, a SPA and a DLA acceleration engine.

[0061] The first processing unit provided in this application embodiment enhances the characteristics of heterogeneous multi-core. The resources and instructions used by the program may change at different stages of execution. The software can move the program to a more suitable processing core for execution according to resource requirements, which can make more efficient use of system resources and improve the overall system performance.

[0062] The I2C port module provided in this application embodiment can not only receive the second signal of the type corresponding to the I2C bus, but also receive other types of GPIO signals. In this way, the two types of signal transmission share a set of I2C pins, saving system resources.

[0063] In some embodiments, such as Figure 8 As shown, the second processing unit (e.g., EC) can send GPIO signals to the second processing submodule (e.g., GPIO controller) of the first processing unit (e.g., AI chip LA3) via the first bus (e.g., I2C bus). This allows the second processing submodule to set the values ​​of the registers in its corresponding GPIO module to control the output state of the corresponding first device. In this way, the EC can utilize the GPIO modules in the first processing unit when its own GPIO modules are insufficient, achieving efficient utilization of electronic device resources.

[0064] This application provides a signal processing method applied to electronic devices. Figure 9 This is a schematic diagram illustrating the implementation flow of the signal processing method provided in the embodiments of this application, such as... Figure 9 As shown, the method includes steps 901 to 910:

[0065] Step 901: The EC (an example of a second processing unit) has a command to communicate with the AI ​​chip (an example of a first processing unit);

[0066] Step 902: EC first checks whether the signal to be transmitted is an I2C command signal (an example of a second signal of the first type) or a GPIO signal (an example of a second signal of the second type); if it is an I2C command signal, proceed to step 903; otherwise, proceed to step 904.

[0067] Step 903: The EC selects the FW ID of the I2C port module in the AI ​​chip (an example of the first port), and then transmits the I2C command to the CPU of the AI ​​chip (an example of the first processing submodule).

[0068] Step 904: EC selects the HW ID of the I2C port module in the AI ​​chip (an example of the second port), and then transmits the GPIO command to the GPIO controller of the AI ​​chip (an example of the second processing submodule);

[0069] Step 905: The GPIO controller sets the Xth GPIO corresponding to the GPIO signal to GPIO by controlling the corresponding register;

[0070] Step 906: The GPIO controller sets the output state of GPIO X by setting the value in the corresponding register. The output state can be: high level, low level, or open drain (H / L / OD).

[0071] Step 907: The GPIO controller sets the Xth GPIO X to GPIO;

[0072] In step 908, the register of GPIO X changed;

[0073] Step 909: The GPIO controller sends an interrupt signal to EC int;

[0074] In step 910, the EC polls to detect whether the second signal comes from HW ID or FW ID, and executes the relevant commands.

[0075] The electronic device provided in this application embodiment has an output path from EC to GPIO controller as follows: EC can output commands to the outside through GPIO controller to control the output state of the first device; first, EC determines whether the second signal is an I2C command signal or a GPIO command signal (LED switch can be predefined as GPIO command, system status switch as I2C command); then, if it is a GPIO command signal, HW ID is selected, and the value of the register in the GPIO controller in the AI ​​chip is controlled.

[0076] In the electronic device provided in this application embodiment, one input path from the GPIO controller to the EC is as follows: when the GPIO register changes, the GPIO controller sends a second interrupt (INT) signal to the EC. The EC polls whether the interrupt signal comes from HW ID or FW ID and executes the relevant command.

[0077] It should be understood that the phrases "one embodiment," "an embodiment," or "some embodiments" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment," "in one embodiment," or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely for descriptive purposes and do not represent the superiority or inferiority of the embodiments. The descriptions of the various embodiments above tend to emphasize the differences between the various embodiments; their similarities or commonalities can be referred to mutually, and for the sake of brevity, they will not be repeated here.

[0078] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three kinds of relationships. For example, object A and / or object B can represent three situations: object A exists alone, object A and object B exist simultaneously, and object B exists alone.

[0079] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0080] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0081] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0082] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0083] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An electronic device, the electronic device comprising a first processing unit and a second processing unit, the first processing unit and the second processing unit communicating via a first bus; The second processing unit is at least configured to receive a first signal transmitted by the first processing unit via the first bus; The first processing unit is at least configured to receive a second signal transmitted by the second processing unit via the first bus, wherein the second signal includes a first type and a second type; wherein, The first type is different from the second type, and the first type corresponds to the first bus; The first processing unit includes a signal port module, a first processing submodule, and a second processing submodule. The signal port module is configured to send the second signal of the first type to the first processing submodule if it receives the second signal of the first type, so that the first processing submodule can process the second signal of the first type. The signal port module is used to send the second signal of the second type to the second processing submodule if it receives the second signal of the second type, so that the second processing submodule can control the working state of the corresponding first device based on the second signal of the second type.

2. The electronic device according to claim 1, characterized in that, The signal port module includes a first port and a second port; The first port is used to receive the second signal of the first type; The second port is used to receive the second signal of the second type; Alternatively, the signal port module may include a third port and a signal recognition module; The third port is used to receive the second signal; the signal identification module is used to identify the signal type of the second signal and send the second signal to the first processing submodule or the second processing submodule for processing according to the signal type.

3. The electronic device according to claim 2, characterized in that, The second processing unit is further configured to determine the type of the second signal according to the signal configuration table; and to send the signal to be sent to the first port and / or the second port according to the type of the signal to be sent.

4. The electronic device according to claim 3, characterized in that, The signal configuration table is determined based on a predefined correspondence between the types of the first device and the second signal.

5. The electronic device according to claim 2, characterized in that, The first processing unit includes a fourth port; The first processing submodule is further configured to send a first interrupt signal to the second processing unit through the fourth port and the first bus; The second processing unit is further configured to read the value of at least one register based on the first interrupt signal, and to perform a corresponding task according to the value of the at least one register; wherein the at least one register includes a first register.

6. The electronic device according to claim 5, characterized in that, The second processing submodule is further configured to send a second interrupt signal to the second processing unit through the fourth port and the first bus; The second processing unit is further configured to read the value of the second register based on the second interrupt signal, and execute a corresponding task according to the value of the second register.

7. The electronic device according to claim 1, characterized in that, The first processing submodule includes a first control core and a second control core; The first control core includes at least one acceleration unit for performing a first operation, the first operation including AI-related operations; The second control core is used to perform a second operation, which is different from the first operation.

8. A signal processing method applied in an electronic device, the electronic device comprising a first processing unit and a second processing unit, the first processing unit and the second processing unit communicating via a first bus; The method includes: The second processing unit receives the first signal sent by the first processing unit via the first bus. The first processing unit receives a second signal sent by the second processing unit via the first bus. The second signal includes a first type and a second type, wherein the first type is different from the second type and the first type corresponds to the first bus. The method further includes: If the signal port module of the first processing unit receives the second signal of the first type, it sends the second signal of the first type to the first processing submodule of the first processing unit through the signal port module, so that the first processing submodule can process the second signal of the first type. If the signal port module receives the second signal of the second type, it sends the second signal of the second type to the second processing submodule of the first processing unit through the signal port module, so that the second processing submodule controls the working state of the corresponding first device based on the second signal of the second type.

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