Bus design generation methods, devices, electronic equipment and storage media

Abstract

This invention relates to the field of computers and discloses a bus design generation method, apparatus, electronic device, and storage medium. The bus design generation method includes the following steps: determining boundary input interfaces and boundary output interfaces; wherein the boundary input interfaces are connected to the input-side module of the bus, and the boundary output interfaces are connected to the output-side module of the bus; generating a graphical description of the bus design based on the protocols supported by the boundary input interfaces and the boundary output interfaces; presenting the graphical description in a graphical interface; and, upon receiving a confirmation command, converting the graphical description into a Verilog code description of the bus. This bus design generation method enables rapid generation of bus designs.

Description

Technical Field

[0001] The present invention relates to the field of computers, and in particular to a bus design generation method, apparatus, electronic device and storage medium. Background Technology

[0002] A bus is a common communication trunk line for transmitting information between various functional components of a computer. It is a transmission line bundle composed of wires, arranged according to the type of information transmitted by the computer. It is a common channel for the processor, memory, input, and output devices to transmit information. The various components of the host computer are connected via the bus, and external devices are connected to the bus through corresponding interface circuits, thus forming the computer hardware system. In a computer system, the common path for transmitting information between various components is called the bus. Microcomputers use a bus structure to connect their various functional components.

[0003] The bus design refers to the way different modules are connected via a bus. After the bus design is determined, programmers need to write Verilog code to describe the bus connection methods between different modules in order to implement the bus connection between modules. Summary of the Invention

[0004] The purpose of this invention is to provide a bus design generation method, apparatus, electronic device, and storage medium that can enable rapid generation of bus designs.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a bus design generation method, comprising the following steps: determining boundary input interfaces and boundary output interfaces; wherein, the boundary input interface is connected to the input-side module of the bus, and the boundary output interface is connected to the output-side module of the bus; generating a graphical description of the bus design based on the protocols supported by the boundary input interface and the protocols supported by the boundary output interface; presenting the graphical description in a graphical interface; and, upon receiving a confirmation instruction, converting the graphical description into a Verilog code description of the bus.

[0006] Embodiments of the present invention also provide a bus design generation apparatus, comprising: an interface determination module for determining boundary input interfaces and boundary output interfaces; wherein the boundary input interfaces are connected to the input-side module of the bus, and the boundary output interfaces are connected to the output-side module of the bus; a graphics generation module for generating a graphical description of the bus design based on the protocols supported by the boundary input interfaces and the protocols supported by the boundary output interfaces; a graphics presentation module for graphically presenting the graphical description; and a code conversion module for converting the graphical description into a Verilog code description of the bus after receiving a confirmation instruction.

[0007] Embodiments of the present invention also provide an electronic device, comprising: at least one processor; a memory communicatively connected to the at least one processor; the memory storing instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the bus design generation method described above.

[0008] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-described bus design generation method.

[0009] In this embodiment of the invention, by determining boundary input interfaces and boundary output interfaces, wherein the boundary input interfaces are connected to the input-side module of the bus and the boundary output interfaces are connected to the output-side module of the bus, a graphical description of the bus design is generated based on the protocols supported by the boundary input interfaces and the boundary output interfaces. That is, after determining the boundary input interfaces and boundary output interfaces, which are the two endpoints of the bus, a graphical description of the bus design can be automatically generated, saving time for manual initial design. The graphical description is presented in a graphical interface. After receiving a confirmation command, the graphical description is converted into a Verilog code description of the bus. In other words, by presenting the bus design graphically, the rationality of the bus design can be confirmed intuitively and quickly. After confirmation, the graphical description can be converted into a Verilog code description of the bus without the need for engineers to perform Verilog code programming, thereby enabling rapid generation of the bus design.

[0010] Furthermore, the number of boundary output interfaces is the same as the number of output interfaces of the end modules of the bus design, and they are connected one-to-one; wherein, the end module is any bus design component directly connected to the boundary output interface; the graphical description of generating the bus design includes: generating an address decoder and an address selector between the boundary input interface and the boundary output interface, and generating the graphical description of the connection relationship between the boundary input interface and the boundary output interface; wherein, the number of address decoders is the same as the number of boundary input interfaces, and they are connected one-to-one, and the address selector is connected to the address decoder in a fully connected manner. In this application, by generating an address decoder and an address selector between the boundary input interface and the boundary output interface, and generating a graphical description of the connection relationship between the boundary input interface and the boundary output interface, since the number of address decoders and boundary input interfaces are the same and they are connected one-to-one, if the address selector is the end module, then the number of boundary output interfaces and the output interfaces of the address selector are the same and they are connected one-to-one. The address selector and the address decoder are connected in a fully connected manner. Since the address selector and the address decoder are connected by default in a fully connected manner, the situation of missing connections can be reduced, and the connection integrity of the bus design can be guaranteed.

[0011] Furthermore, based on the protocols supported by the boundary input interface and the boundary output interface, a graphical description of the bus design is generated, including: when the protocols supported by the boundary input interface and the boundary output interface are different, an intermediate protocol conversion unit is added between the address decoder and the address selector, and an output protocol conversion unit is added between the address selector and the boundary output interface; wherein, the intermediate protocol conversion unit is used to convert the data input by the boundary input interface into first data conforming to a preset intermediate protocol, and the output protocol conversion unit is used to convert the first data into second data conforming to the protocol supported by the boundary output interface. In this application, by adding an intermediate protocol conversion unit between the address decoder and the address selector when the protocols supported by the boundary input interface and the boundary output interface are different, the protocol used by the input data of the boundary input interface is converted into a unified intermediate protocol, and then the intermediate protocol is converted into the protocol used by the output data of the boundary output interface. This enables the connection between boundary input interfaces and boundary output interfaces with different protocols, and realizes the connection and data conversion between boundary input interfaces and boundary output interfaces supporting different protocols.

[0012] Furthermore, after the graphical description is presented in the interface but before receiving a confirmation instruction, the method further includes: receiving a modification instruction; modifying the graphical description according to the modification instruction; and presenting the modified graphical description in the interface. In this application, by receiving a modification instruction after the graphical description is presented in the interface but before receiving a confirmation instruction, modifying the graphical description according to the modification instruction, and then presenting the modified graphical description in the interface, engineers can directly and quickly modify the generated bus design, improving the efficiency of bus design generation. Attached Figure Description

[0013] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0014] Figure 1 This is a flowchart of the steps of a bus design generation method according to an embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of a bus design generation device according to an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of an electronic device structure according to an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of the present invention to facilitate a better understanding of this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with and referenced by each other without contradiction.

[0018] Embodiments of the present invention relate to a bus design generation method. The specific process is as follows: Figure 1 As shown, it includes:

[0019] Step 101: Determine the boundary input interface and the boundary output interface; wherein, the boundary input interface is connected to the input side module of the bus, and the boundary output interface is connected to the output side module of the bus;

[0020] Step 102: Generate a graphical description of the bus design based on the protocols supported by the boundary input interface and the boundary output interface.

[0021] Step 103: Present the graphical description in a user interface;

[0022] Step 104: After receiving the confirmation command, the graphical description is converted into a Verilog code description of the bus.

[0023] The bus design generation method of this embodiment is used in electronic devices that require bus design, such as computers and tablets. A bus is a common communication trunk line for transmitting information between various functional components of a computer. It is a transmission line bundle composed of wires, arranged according to the type of information transmitted by the computer. It is a common channel for the processor, memory, input, and output devices to transmit information. Various components of the host are connected through the bus, and external devices are connected to the bus through corresponding interface circuits, thus forming a computer hardware system. In a computer system, the common path for transmitting information between various components is called the bus. Microcomputers use a bus structure to connect various functional components. The bus connection method between different modules is the bus design. After the bus design is determined, programmers need to write Verilog code to describe the bus connection method between different modules to implement the bus connection between modules. Because Verilog code is relatively complex, it requires specialized engineers to write. Furthermore, describing bus connections with code is prone to errors and omissions, requiring repeated checks. Therefore, bus design efficiency is low, and modifications are complex.

[0024] In this application, by determining the boundary input interface and boundary output interface, where the boundary input interface is connected to the input-side module of the bus and the boundary output interface is connected to the output-side module of the bus, a graphical description of the bus design is generated based on the protocols supported by the boundary input interface and the boundary output interface. That is, after determining the boundary input interface and boundary output interface, which are the two endpoints of the bus, a graphical description of the bus design can be automatically generated, saving time for manual initial design. The graphical description is presented in a graphical interface, and after receiving a confirmation command, the graphical description is converted into a Verilog code description of the bus. In other words, the rationality of the bus design can be confirmed intuitively and quickly in a graphical form, and after confirmation, the graphical description can be converted into a Verilog code description of the bus without the need for engineers to perform Verilog code programming, thereby achieving rapid generation of the bus design.

[0025] The following is a detailed description of the implementation details of the bus design generation method in this embodiment. The following content is only for the convenience of understanding the implementation details and is not necessary for implementing this solution.

[0026] In step 101, the electronic device determines the boundary input interface and the boundary output interface. The boundary input interface is the interface connected to the input-side module, and the boundary output interface is the interface connecting the bus to the output-side module. In some scenarios, the input-side module is the master device that sends data, and the output-side module is the slave device that receives data.

[0027] In step 102, a graphical description of the bus design is generated based on the protocols supported by the boundary input interface and the boundary output interface. In the graphical description of the bus design, each device in the bus can be represented by a graphical module, and the connection between modules can be represented by lines, thereby automatically generating a concise and direct graphical description of the bus design.

[0028] In one example, the boundary input interface could be an Advanced High Performance Bus (AHB) interface, and the boundary output interface could be protocols such as AHB and Advanced Peripheral Bus (APB).

[0029] In one example, the number of boundary output interfaces is the same as the number of output interfaces of the end modules of the bus design, and they are connected one-to-one; wherein, the end modules are any bus design components that are directly connected to the boundary output interfaces, such as any one or combination of components such as address selectors, packet address decoders, and protocol converters.

[0030] The graphical description of the bus design is achieved as follows: An address decoder and an address selector are generated between the boundary input and boundary output interfaces, along with a graphical description of the connection relationships between them. The number of address decoders is the same as the number of boundary input interfaces, and they are connected one-to-one. The address selectors are fully connected to the address decoders. The address decoder and address selector are essential default components in the bus. The address decoder is used to decode and assign addresses to master devices, and the address selector is used to arbitrate and select the master device for each connected master device, enabling slave devices to select a master device during each data transmission and transmitting its data to the slave device.

[0031] In this embodiment, an address decoder and an address selector are generated between the boundary input interface and the boundary output interface, and a graphical description of the connection relationship between the boundary input interface and the boundary output interface is generated. Since the number of address decoders and boundary input interfaces is the same and they are connected one-to-one, if the address selector is the end module, the number of boundary output interfaces and the output interfaces of the address selector are the same and they are connected one-to-one. The address selector and the address decoder are connected in a fully connected manner. Since the address selector and the address decoder are connected by default in a fully connected manner, the situation of missing connections can be reduced, and the connection integrity of the bus design can be guaranteed.

[0032] Furthermore, when the protocols supported by the boundary input interface and the boundary output interface are different, the electronic device adds an intermediate protocol conversion unit between the address decoder and the address selector, and adds an output protocol conversion unit between the address selector and the boundary output interface. The intermediate protocol conversion unit is used to convert the data input by the boundary input interface into first data that conforms to a preset intermediate protocol, and the output protocol conversion unit is used to convert the first data into second data that conforms to the protocol supported by the boundary output interface.

[0033] In this embodiment, when the protocols supported by the boundary input interface and the boundary output interface are different, an intermediate protocol conversion unit is added between the address decoder and the address selector to convert the protocol used by the input data of the boundary input interface into a unified intermediate protocol, and then convert the intermediate protocol into the protocol used by the output data of the boundary output interface. This enables the connection between boundary input interfaces and boundary output interfaces with different protocols, and realizes the connection and data conversion between boundary input interfaces and boundary output interfaces that support different protocols.

[0034] In one example, when an electronic device generates a graphical description of a bus design, if it detects that there is an output interface group at the boundary output interface, then, if there is at least one output interface group, an address decoder, an address selector, and a group address decoder are generated between the boundary input interface and the boundary output interface. For example, between the boundary output interface and the corresponding boundary input interface belonging to the same output interface group, the address decoder, address selector, and group address decoder corresponding to this group are generated. The end module of the bus design can be a group address decoder. The output interface group contains multiple boundary output interfaces. The number of address decoders is the same as the number of boundary input interfaces and they are connected one-to-one. The address selector and the group address decoder correspond one-to-one and are connected in a fully connected manner.

[0035] In this embodiment, when there are output interface groups, by generating an address decoder, an address selector, and a group address decoder between the boundary input interface and the boundary output interface, and using one address selector and one group address decoder for each output interface group, the number of devices in the bus design can be reduced, thereby saving the area occupied by each output interface group in the bus and improving the area utilization efficiency in the bus.

[0036] Furthermore, the electronic device will pre-assign boundary output interfaces with the same protocol to the same output interface group according to the protocol supported by each boundary output interface.

[0037] In this embodiment, by grouping boundary output interfaces with the same protocol into the same output interface group, since the boundary output interfaces in each output interface group use the same protocol, even if the protocol used by the boundary output interface in the output interface group is different from the protocol used by the boundary input interface, it is not necessary to equip each boundary output interface with an output protocol conversion unit. Only one output protocol conversion unit needs to be equipped for each output interface group to meet the usage requirements, saving device area in the bus and improving the area utilization efficiency in the bus.

[0038] In step 103, the electronic device presents a graphical description in an interface. Specifically, the electronic device converts the graphical description into a display graphic and outputs it to a display device. Different components can be filled with different colors to help engineers quickly distinguish between them.

[0039] In one example, after the graphical description is presented in the interface, and before receiving a confirmation command, the electronic device also receives a modification command. Based on the modification command, the graphical description is modified, and the modified graphical description is then presented in the interface. The modification command can be generated by the electronic device after testing the bus design, or it can be entered by the engineer. The modification command can include changes to the number of devices, connection relationships, output interface grouping settings, etc.

[0040] In this embodiment, after the graphical description is presented in the interface, a modification instruction is received before the confirmation instruction is received. The graphical description is modified according to the modification instruction, and the modified graphical description is presented in the interface. This allows engineers to directly and quickly modify the generated bus design, thereby improving the efficiency of bus design generation.

[0041] In step 104, after receiving the confirmation command, the electronic device converts the graphical description into a Verilog code description of the bus. Specifically, the electronic device instantiates and displays bus devices in a tree diagram representing the chip logic structure, with the hierarchical relationship of each bus device represented by a tree structure. A functional description table of the customized bus devices is generated and displayed. Based on the functional description table of the customized modules, the corresponding design code and design document (i.e., Verilog code description) for the customized modules are generated. The different functions of the modules will affect the direction, width, and other attributes of the port connections of the bus devices.

[0042] The steps of the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this patent.

[0043] This invention also relates to a bus design generation apparatus, such as... Figure 2 As shown, it includes:

[0044] The interface determination module 201 is used to determine the boundary input interface and the boundary output interface; wherein, the boundary input interface is connected to the input side module of the bus, and the boundary output interface is connected to the output side module of the bus;

[0045] The graphics generation module 202 is used to generate a graphical description of the bus design based on the protocols supported by the boundary input interface and the boundary output interface.

[0046] The graphical presentation module 203 is used to present graphical descriptions in a user interface.

[0047] The code conversion module 204 is used to convert the graphical description into a bus Verilog code description after receiving the confirmation command.

[0048] In one example, the number of boundary output interfaces is the same as the number of output interfaces of the end modules of the bus design, and they are connected one-to-one; wherein, the end modules are any bus design components directly connected to the boundary output interfaces; the generation of a graphical description of the bus design includes: generating an address decoder and an address selector between the boundary input interfaces and the boundary output interfaces, and generating the graphical description of the connection relationship between the boundary input interfaces and the boundary output interfaces; wherein, the number of address decoders is the same as the number of boundary input interfaces, and they are connected one-to-one, and the address selector is connected to the address decoder in a fully connected manner.

[0049] In one example, a graphical description of the bus design is generated based on the protocols supported by the boundary input interface and the boundary output interface. This includes: when the protocols supported by the boundary input interface and the boundary output interface are different, an intermediate protocol conversion unit is added between the address decoder and the address selector, and an output protocol conversion unit is added between the address selector and the boundary output interface. The intermediate protocol conversion unit is used to convert the data input from the boundary input interface into first data that conforms to a preset intermediate protocol, and the output protocol conversion unit is used to convert the first data into second data that conforms to the protocol supported by the boundary output interface.

[0050] In one example, the number of boundary output interfaces is the same as the number of output interfaces of the end modules of the bus design, and they are connected one-to-one; wherein, the end modules are any bus design components directly connected to the boundary output interfaces; the graphical description of generating the bus design includes: in the presence of at least one output interface group, generating an address decoder, an address selector, and a group address decoder between the boundary input interfaces and the boundary output interfaces; wherein, the output interface group contains multiple boundary output interfaces, the number of address decoders is the same as the number of boundary input interfaces, and they are connected one-to-one, the address selectors and the group address decoders correspond one-to-one, and the address selectors and the address decoders are connected in a fully connected manner.

[0051] In one example, before generating the address decoder, address selector, and group address decoder between the boundary input interface and the boundary output interface, the method further includes: grouping boundary output interfaces with the same protocol into the same output interface group by default according to the protocol supported by each boundary output interface.

[0052] In one example, after the graphical description is presented in the interface and before a confirmation instruction is received, the method further includes: receiving a modification instruction; modifying the graphical description according to the modification instruction; and presenting the modified graphical description in the interface.

[0053] It is not difficult to see that this embodiment is a system embodiment corresponding to the above embodiments, and this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0054] It is worth mentioning that all modules involved in this embodiment are logical modules. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this invention, this embodiment does not introduce units that are not closely related to solving the technical problem proposed by this invention; however, this does not mean that other units are absent from this embodiment.

[0055] This invention relates to an electronic device, such as... Figure 3 As shown, it includes: at least one processor 301; a memory 302 communicatively connected to the at least one processor; wherein the memory 302 stores instructions executable by the at least one processor 301, and the instructions are executed by the at least one processor 301 to perform the bus design generation method described above.

[0056] The memory 302 and processor 301 are connected via a bus, which can include any number of interconnecting buses and bridges. The bus connects various circuits of one or more processors 301 and memory 302 together. The bus can also connect controllers of various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. A bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Information processed by processor 301 is transmitted over a wireless medium via an antenna, which further receives information and transmits it to processor 301.

[0057] Processor 301 is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory 302 can be used to store information used by the processor during operation.

[0058] This invention also relates to a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the above-described method embodiments.

[0059] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0060] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present invention.

Claims

1. A method of bus design generation, characterized by, The method comprises the following steps: determining a boundary input interface and a boundary output interface; wherein the boundary input interface is connected with an input side module of a bus, and the boundary output interface is connected with an output side module of the bus; generating a graphical description of the bus design according to a protocol supported by the boundary input interface and a protocol supported by the boundary output interface; presenting the graphical description in an interface manner; after receiving a confirmation instruction, converting the graphical description into a verilog code description of the bus; wherein the boundary output interface is connected with an output interface of a terminal module of the bus design in a one-to-one manner; wherein the terminal module is any bus design component directly connected with the boundary output interface; the generating of the graphical description of the bus design comprises: generating an address decoder and an address selector between the boundary input interface and the boundary output interface, and generating the graphical description of the connection relationship between the boundary input interface and the boundary output interface; wherein the address decoder is connected with the boundary input interface in a one-to-one manner, and the address selector is connected with the address decoder in a full connection manner.

2. The bus design generation method of claim 1, wherein, the generating of the graphical description of the bus design according to the protocol supported by the boundary input interface and the protocol supported by the boundary output interface comprises: in the case that the protocol supported by the boundary input interface and the protocol supported by the boundary output interface are different, adding an intermediate protocol conversion unit between the address decoder and the address selector, and adding an output protocol conversion unit between the address selector and the boundary output interface; wherein the intermediate protocol conversion unit is used for converting data input by the boundary input interface into first data conforming to a preset intermediate protocol, and the output protocol conversion unit is used for converting the first data into second data conforming to the protocol supported by the boundary output interface.

3. The bus design generation method of claim 1, wherein, the boundary output interface is connected with an output interface of a terminal module of the bus design in a one-to-one manner; wherein the terminal module is any bus design component directly connected with the boundary output interface; the generating of the graphical description of the bus design comprises: in the case that there is at least one output interface group, generating an address decoder, an address selector and a group address decoder between the boundary input interface and the boundary output interface; wherein the output interface group contains a plurality of the boundary output interfaces, the address decoder is connected with the boundary input interface in a one-to-one manner, the address selector and the group address decoder are one-to-one corresponding, and the address selector is connected with the address decoder in a full connection manner.

4. The method of claim 3, wherein, before the generating of the address decoder, the address selector and the group address decoder between the boundary input interface and the boundary output interface, the method further comprises: according to the protocols supported by the boundary output interfaces, the boundary output interfaces supporting the same protocol are divided into the same output interface group by default.

5. The bus design generation method of claim 1, wherein, after the presenting of the graphical description in an interface manner, before receiving the confirmation instruction, the method further comprises: receiving a modification instruction; modifying the graphical description according to the modification instruction; presenting the modified graphical description in an interface.

6. A bus design generation apparatus characterized by comprising: comprising: an interface determination module, configured to determine a boundary input interface and a boundary output interface; wherein the boundary input interface is connected with an input side module of a bus, and the boundary output interface is connected with an output side module of the bus; a graph generation module, configured to generate a graphical description of bus design according to a protocol supported by the boundary input interface and a protocol supported by the boundary output interface; a graph presentation module, configured to present the graphical description in an interface; a code conversion module, configured to convert the graphical description into a verilog code description of the bus after receiving a confirmation instruction; wherein the boundary output interface is the same as and one-to-one connected with an output interface of a terminal module of the bus design; wherein the terminal module is any bus design component directly connected with the boundary output interface; the generation of the graphical description of bus design comprises: generating an address decoder and an address selector between the boundary input interface and the boundary output interface, and generating the graphical description of the connection relationship between the boundary input interface and the boundary output interface; wherein the address decoder is the same as and one-to-one connected with the boundary input interface, and the address selector is connected with the address decoder in a full connection manner.

7. An electronic device, comprising: comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the bus design generation method in any one of claims 1 to 5.

8. A computer readable storage medium storing a computer program, characterized in that, the computer program is executed by the processor to implement the bus design generation method in any one of claims 1 to 5.

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