A Method for PI and SI Simulation Analysis of DDR3 Signals in a Microsystem Module

Abstract

The present invention discloses a method for simulating and analyzing PI and SI signals of DDR3 in a microsystem module, which realizes simulation analysis of power integrity and signal integrity of the microsystem module, provides simulation judgment criteria, and improves simulation accuracy. The method includes the steps of merging a silicon substrate and a tube shell and then performing a DC voltage drop simulation. The steps are as follows: importing the layout of the tube shell and the silicon substrate into simulation software and setting simulation parameters; adding a voltage source and a current source between the power pin and the ground pin of the chip, starting the simulation software to perform a DC voltage drop simulation and performing calculations to obtain a simulation result; judging whether the simulation result meets the requirements according to the simulation criteria, and if so, completing the simulation; if not, locating the items in the layout that do not meet the simulation criteria, and modifying the layout of the items that do not meet the simulation criteria until the requirements are met and the simulation is completed.

Description

Technical Field

[0001] The present invention relates to the technical field of microsystem module simulation, in particular to a method for simulating and analyzing PI and SI signals of DDR3 in a microsystem module. Background Art

[0002] As server memory becomes increasingly integrated, the challenges of PCB layout and routing for each board in the system are also increasing. Simulation optimization and good power and signal integrity are crucial in the modeling process.

[0003] Existing DDR3 signal power integrity (PI) and signal integrity (SI) simulation and analysis methods have already formed many mature specifications and PI and SI simulation and analysis methods for simple 2D PCB boards due to their simple board materials and structure. For example, the QJ3103A-2011 printed circuit board design requirements have clear qualification criteria for vias and current density. Some simulation software also has relatively mature simulation processes for 2D PCB boards.

[0004] However, with the increasing demand for integration, microsystem modules have emerged. Microsystem modules often require the use of new materials and complex 3D stacked TSV boards and packages. Signal paths pass through the TSV interposer board's traces, TSV holes, solder balls, and the package substrate's traces, vias, and solder balls to reach another silicon interposer. When used in modules, they also require external connections to PCB traces, vias, and chips. Signal PI and SI simulation analysis is a system concept: transmitter chip—signal path—receiver chip. The TSV silicon substrate and package require collaborative PI and SI simulation analysis and optimization. Complex subcomponents require modeling, and methods for extracting S parameters from the 3D stacked structure are analyzed to achieve simulation accuracy. Targeted power supply DC and AC analysis is also required, along with the definition of acceptance criteria. However, currently, there are no mature simulation methods or criteria for power integrity and signal integrity simulation analysis in microsystem modules, resulting in low simulation accuracy, modeling difficulties, and a lack of clear criteria. Summary of the Invention

[0005] In order to solve the problems existing in the prior art, the present invention provides a DDR3 signal PI and SI simulation analysis method in a microsystem module, which realizes the power integrity simulation analysis and signal integrity simulation analysis of the microsystem module, and provides a simulation judgment standard to improve the simulation accuracy.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A method for simulating and analyzing PI and SI of DDR3 signals in a microsystem module includes the steps of combining a silicon substrate and a tube shell and then simulating a DC voltage drop. The steps are as follows:

[0008] Import the layout of the tube shell and silicon substrate into the simulation software and set the simulation parameters;

[0009] After adding a voltage source and a current source between the power pin and the ground pin of the chip, start the simulation software to simulate the DC voltage drop and calculate the solution to obtain the simulation results;

[0010] According to the simulation standards, judge whether the simulation results meet the requirements.

[0011] If the requirements are met, the simulation is completed;

[0012] If the requirements are not met, the items in the layout that do not meet the simulation standards are located and the layout of the items that do not meet the simulation standards is changed until the requirements are met and the simulation is completed.

[0013] Preferably, the step of merging the silicon substrate and the housing comprises:

[0014] Merge the engineering files of the controller TSV substrate and tube shell, and merge the engineering files of the DDR3 particle TSV substrate micro-mold assembly and tube shell.

[0015] Preferably, the simulation parameters include material conductivity, dielectric constant, loss tangent and solder balls corresponding to the chip.

[0016] Preferably, adding a voltage source and a current source between the power pin and the ground pin of the chip specifically includes:

[0017] A current source is set on the TOP layer of the bare chip, and a voltage source is set on the power supply end at the BGA pad position on the BOTTOM layer of the bare chip.

[0018] Preferably, the simulation standard includes a DC voltage loss standard and a current density standard.

[0019] The DC voltage loss standard is that the DC voltage drop generated by the power supply network in the microsystem module does not exceed 3% of the chip supply voltage, and the current density standard is that the simulated current density does not exceed the limited current.

[0020] Preferably, after the step of simulating the DC voltage drop, the step of simulating the AC impedance is further included, and the steps are as follows:

[0021] Connect the power pins of the chip together to form a power pin group, and connect the ground pins together to form a ground pin group;

[0022] Add a resistor between the power pin group and the ground pin group of the power supply chip, and add an interface between the power pin group and the ground pin group of the power consumption chip;

[0023] After setting the Compute SYZ parameters in the simulation software, perform AC impedance simulation and solve the problem to obtain the target impedance curve at the interface of the power chip.

[0024] According to the target impedance standard, the obtained simulation results are judged to see whether they meet the requirements.

[0025] If the requirements are met, the simulation is completed;

[0026] If the requirements are not met, the target impedance standard is not met, and the decoupling network in the power supply network of the microsystem module is modified until the requirements are met and the simulation is completed.

[0027] Preferably, obtaining the decoupling network of the power supply network includes the following steps:

[0028] Extract the signal parameter model of the power supply network from the power supply end of the PCB board to the encapsulated microsystem module;

[0029] Build the entire PDN link in simulation software;

[0030] The chip CPM model is accessed at the module end of the entire PDN link;

[0031] Obtain the decoupling network of the power supply network based on decoupling capacitor optimization and time domain simulation.

[0032] Preferably, after the DC voltage drop simulation step, a signal integrity simulation step is also included, the steps are as follows:

[0033] Extract signal parameters of interconnect lines between controller bare chip pads and TSV lead-out pins;

[0034] Extract the signal parameters of the interconnection lines between the TSV lead-out pins and the DDR3 chip pads and the matching RC IPD chip pads;

[0035] Extract the signal parameters of the interconnection line between the controller TSV lead-out pin and the DDR3 chip TSV lead-out pin;

[0036] Cascade the extracted signal parameters, import them into the chip model, establish a time domain solution, and obtain the DDR3 signal SI simulation results;

[0037] Determine whether the obtained DDR3 signal SI simulation results meet the requirements according to the standard.

[0038] If the requirements are met, the simulation is completed;

[0039] If the requirements are not met, the items in the layout that do not meet the standards are located and the layout of the items that do not meet the standards is changed until the requirements are met and the simulation is completed.

[0040] Preferably, the DDR3 signal SI simulation result includes the frequency domain, time domain, level, edge, timing and eye diagram of the DDR3 signal.

[0041] Preferably, the timing of the DDR3 signal in the DDR3 signal SI simulation result is calculated using an embedded DDR3 script.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] The present invention provides a DDR3 signal PI and SI simulation analysis method in a microsystem module. For the PI analysis of DDR3 signals in a microsystem module, parameters are set for each component in the modeling process of the entire complex 3D structure link, from the controller TSV substrate to the tube shell in the microsystem module, and then to the DDR3 particle TSV substrate micro-mold assembly and IPD chip. During the simulation process, the engineering files of the controller TSV substrate and the tube shell are merged, and the engineering files of the DDR3 particle TSV substrate micro-mold assembly and the tube shell are merged. Then, a DC IRdrop voltage drop simulation is performed on the two merged projects. After the TSV board and tube shell are attached, an integrated simulation is performed. As an overall model, key parameters such as the overcurrent capacity, voltage drop, and current density at bottlenecks such as bumps and solder balls can be analyzed. In this way, the simulated current path is closer to the actual working conditions, with higher simulation accuracy and better results.

[0044] Furthermore, for the SI analysis of DDR3 signals in the microsystem module, a complete link cascade simulation of DDR3 signals is performed from the controller 690TSV component and tube shell to the DDR3 particle TSV5-layer micro-module component in the microsystem module. Reasonable modeling of sub-components and analysis of the S parameters extracted from the 3D stacking structure can achieve simulation accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Schematic diagram of two TSV substrate components and a tube shell of a NOP microsystem according to an embodiment of the present invention;

[0046] Figure 2 It is the PI and SI simulation flow chart of the microsystem of the present invention;

[0047] Figure 3 2. It is a schematic diagram of the TSV substrate stacking structure according to an embodiment of the present invention;

[0048] Figure 4 This is the full-link circuit diagram of the 1V5 power supply network CPS collaborative simulation of DDR3 of the present invention;

[0049] Figure 5 This is a power supply time domain waveform diagram of the power supply CPS collaborative analysis according to an embodiment of the present invention;

[0050] Figure 6 This is a complete circuit diagram of the Address and clock signals of an embodiment of the present invention;

[0051] Figure 7 This is a complete circuit diagram of DQ0 to DQ15 and corresponding DM and DQS signals in the data write state of an embodiment of the present invention;

[0052] Figure 8 This is a complete circuit diagram of DQ0 to DQ15 and corresponding DM and DQS signals in the data read state of an embodiment of the present invention;

[0053] Figure 9 This is the eye diagram of the differential clock signal at the U1 end of an embodiment of the present invention;

[0054] Figure 10 This is a time domain waveform diagram of the address signal at the U5 terminal according to an embodiment of the present invention;

[0055] Figure 11 1 is a time domain waveform diagram of the receiving end of the write state DQ0-DQ71 data signal according to an embodiment of the present invention;

[0056] Figure 12 This is an eye diagram of a DQS2 differential signal in the write direction according to an embodiment of the present invention;

[0057] Figure 13 This is a timing data diagram of running a script simulation in an embodiment of the present invention. DETAILED DESCRIPTION

[0058] The principles and features of the present invention are further described in detail below with reference to the accompanying drawings. The examples provided are intended only to illustrate the present invention and are not intended to limit the scope of the present invention. It should be noted that the drawings are all simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0059] It should be noted that when a component is referred to as being "fixed to" another component, it may be directly on the other component or there may be a central component. When a component is referred to as being "connected to" another component, it may be directly connected to the other component or there may be a central component. When a component is referred to as being "disposed on" another component, it may be directly disposed on the other component or there may be a central component.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0061] The present invention provides a method for simulating and analyzing PI and SI of DDR3 signals in a microsystem module, comprising the steps of combining a silicon substrate and a tube shell and performing a DC IRdrop voltage drop simulation, the steps being as follows:

[0062] Import the layout of the tube shell and silicon substrate into the simulation software and set the simulation parameters;

[0063] After adding a voltage source and a current source between the power pin and the ground pin of the chip, start the simulation software to perform DC voltage drop simulation (Compute DC IR) and calculate and solve to obtain the simulation results;

[0064] According to the simulation standards, judge whether the simulation results meet the requirements.

[0065] If the requirements are met, the simulation is completed;

[0066] If the requirements are not met, the items in the layout that do not meet the simulation standards are located and the layout of the items that do not meet the simulation standards is changed until the requirements are met and the simulation is completed.

[0067] This paper designs a simulation method for analyzing the power integrity (PI) of DDR3 signals in a microsystem module. Parameters are set for each component during the modeling process, along the entire complex 3D structure link, from the controller TSV substrate in the microsystem module to the housing, and then to the DDR3 particle TSV substrate, five-layer micromodule assembly, and IPD chip. Specifically, the PI simulation includes DC IRdrop simulation, analyzing the DC voltage loss, current density, and via current of the entire power delivery network (PDN) from the power supply chip VRM to the power-consuming chip, guiding design optimization. The power impedance simulation analyzes the impedance of the entire PDN, optimizes the PDN decoupling network, and achieves a low-impedance PDN design.

[0068] Due to the high density of three-dimensional stacking of microsystem modules, power supply DC IRdrop analysis is particularly important at the silicon substrate and package stage. The current-carrying capacity of the power plane layer must be examined based on key parameters such as overcurrent capability, voltage drop, and current density. Therefore, DC IRdrop simulations must be performed separately for the controller TSV substrate, the 5-layer micromodule assembly on the DDR3 chip TSV substrate, and the package. If any simulation results fail, the cause is identified and the layout modified until every component passes DC IRdrop voltage drop simulation. However, during the simulation process, if the TSV board and package are simulated separately for each component, the voltage source for the bumps and solder balls at the component is operated as a pin-group, and the current source is evenly distributed to each pin. This makes it impossible to analyze key parameters such as overcurrent capability, voltage drop, and current density at bottlenecks such as bumps and solder balls. Therefore, taking this into account, the present invention merges the engineering files of the controller TSV substrate and the tube shell during the simulation process, merges the engineering files of the DDR3 particle TSV substrate 5-layer micro-module assembly and the tube shell, and then performs a DC IRdrop voltage drop simulation on the two merged projects. After the TSV board and tube shell Attach operation is merged, an integrated simulation is performed. As an overall model, it can analyze key parameters such as the overcurrent capacity, voltage drop, and current density at bottlenecks such as bumps and solder balls. In this way, the simulated current path is closer to the actual working conditions, the simulation accuracy is higher, and the effect is better. The simulation method described in the present invention can be extended to different layout conditions to perform DDR3 signal power integrity and signal integrity simulation analysis.

[0069] Furthermore, after the DC IRdrop voltage drop simulation step, an AC impedance simulation step is also included, and the steps are as follows:

[0070] Pin groups are formed between the power pins and ground pins of the chip (that is, the power pins of the chip are connected together to form a power pin group, and the ground pins are connected together to form a ground pin group). A resistor is added between the power and ground pin groups of the VRM end of the power supply chip, and an interface port is added between the power and ground pin groups of the power consumption chip.

[0071] After setting the Compute SYZ parameters in the simulation software, perform AC impedance simulation and solve the problem to obtain the target impedance curve at the port of the power-consuming chip.

[0072] According to the target impedance standard, the obtained simulation results are judged to see whether they meet the requirements.

[0073] If the requirements are met, the simulation is completed;

[0074] If the requirements are not met, the target impedance standard is not met, and the decoupling network of the microsystem module power supply network is modified until the requirements are met and the simulation is completed.

[0075] Furthermore, after the DC IRdrop voltage drop simulation step, a signal integrity SI simulation step is also included, and the steps are as follows:

[0076] Extract the S parameters of the interconnects between the controller die pads and the TSV lead-out pins;

[0077] Extract the S parameters of the interconnection lines between the TSV lead-out pins and the DDR3 chip bare die pads and the matching RC IPD bare die pads;

[0078] Extract the S parameters of the interconnection lines between the controller TSV pins and the DDR3 chip TSV pins;

[0079] Cascade the extracted S parameters, import them into the chip model, establish a time domain solution, and obtain the DDR3 signal simulation results;

[0080] According to the standard, judge whether the obtained simulation results meet the requirements.

[0081] If the requirements are met, the simulation is completed;

[0082] If the requirements are not met, the items in the layout that do not meet the standards are located and the layout is changed for the items that do not meet the standards until the requirements are met and the simulation is completed.

[0083] The simulation method described in the present invention is intended to solve the following problems:

[0084] 1) Simulation modeling, stacking settings, and Solder Ball parameter setting methods for 3D stacked structure TSV silicon substrates and tube shells;

[0085] 2) Methods for DC simulation of TSV silicon substrate and shell components, and the advantages and basis for TSV board and shell integrated simulation;

[0086] 3) AC impedance simulation optimization method and judgment basis for TSV silicon substrate, tube shell and PCB board power supply;

[0087] 4) Full-link DDR3 signal simulation and analysis method from transmitting chip - signal channel - receiving chip in the microsystem.

[0088] For the entire complex 3D structure link of the microsystem module, parameter setting is performed on each component during the modeling process, and DDR3 power integrity, signal amplitude, and timing simulation of the cascaded complete link are performed. This invention can be applied to the simulation analysis of DDR3 signal power integrity and signal integrity in different layouts.

[0089] Example

[0090] This embodiment uses a certain NOP microsystem module to further illustrate the simulation method of the present invention.

[0091] 1.1 Post-PI and SI simulation analysis process of the complete link of NOP microsystem DDR3

[0092] In the microsystem NOP module, the front side of the TSV silicon transfer substrate uses microbumps to connect to the bare chip, while the back side uses relatively large bumps to interconnect with the package shell. The front and back RDLs redistribute the bumps, and the middle TSV structure enables conductivity between the front and back sides, ultimately achieving interconnection between the chip and the package shell. The complete DDR3 link includes: a controller 690TSV component, a shell, and a DDR3 particle TSV 5-layer micro-mold component. The DDR3 particle TSV 5-layer micro-mold component consists of five DDR3 chips and one IPD chip. The five DDR3 chips are homogeneously stacked in a 3D manner after RDL secondary wiring, and the one IPD chip is heterogeneously stacked with the DDR3 chip after RDL secondary wiring. The IPD chip integrates the DDR3 signal routing in a Fly-by topology, requiring matching resistors and capacitors at the signal end to reduce signal reflections and ensure signal integrity.

[0093] In this embodiment, the TSV substrate assembly and the tube shell are shown as follows Figure 1 shown.

[0094] After the PCB layout and routing is completed, the power supply and signal post-simulation verification is divided into power integrity PI simulation analysis and signal integrity SI simulation analysis. PI simulation analysis includes DC voltage drop simulation and power supply impedance simulation, and SI simulation analysis simulates DDR3 signals. DC voltage drop simulation takes precedence over power supply impedance simulation and SI post-simulation. If the PCB needs to be optimized based on the DC voltage drop simulation results, the power supply impedance simulation and SI post-simulation can be performed after the DC voltage drop simulation passes after the layout is changed. The microsystem post-PI and SI simulation flow chart in this embodiment is shown in Figure 2 shown.

[0095] Currently, the mainstream PCB PI and SI simulation software platform is Ansys' EM Suite, including SIwave and AEDT environments (Designer, HFSS 3Dlayout, HFSS, etc.). Additionally, given their ease of integration with PCB design tools and the advantages of other simulation tools, other simulation tools can also be used, such as Candence's Sigrity, Mentor's HyperLynx, Keysight's ADS, and CST's simulation suite.

[0096] 1.2NOP microsystem stacking and solder ball settings before simulation

[0097] Set the stacking information according to the stacking material and solder ball material, including layer thickness, material electrical characteristic parameters, etc.

[0098] 1.2.1 Controller TSV substrate stacking and solder ball parameter settings

[0099] According to the structural diagram of the TSV substrate (such as Figure 3 As shown in FIG, set the simulation parameters of the controller TSV substrate.

[0100] Wherein, FMx: the xth metal layer on the front side (x=1, 2, 3);

[0101] FPx: front side x-th dielectric layer (x=1, 2);

[0102] Oxide: Inorganic dielectric layer SiO2 (thickness 3±0.5μm) on the TSV hole wall and the front silicon substrate surface;

[0103] Oxide & PI: dielectric layer on the back surface of silicon substrate (SiO2: thickness 0.5-1μm, PI: thickness 1-4μm);

[0104] BMx: back metal layer x (x = 1, 2);

[0105] BPx: backside xth dielectric layer (x=1);

[0106] Solder Ball: convex point.

[0107] The solder ball parameters of the controller TSV substrate are set based on the solder ball diameter, height, and material of the FPGA bare chip 7VX690T provided by the manufacturer: the top layer corresponds to the bare chip 690T small ball with a diameter of 100 μm and a height of 70 μm; the material is Sn90Sn10 with a conductivity of 2.17e7S / m; the bottom layer of the TSV corresponds to the BGA large ball with a diameter of 250 μm and a height of 180 μm; the material is Sn63Pb37 with a conductivity of 8.7e6S / m.

[0108] Both the top and bottom layers of the TSV require bonding, using adhesive U8410-73c. The top layer is set to the height of the bare chip 7VX690T solder balls, and the bottom layer is set to the height of the BGA large balls. Therefore, the controller TSV substrate stackup is shown in Table 1.

[0109] Table 1 Controller TSV substrate stack design list

[0110]

[0111] 1.2.2 DDR3 TSV Substrate 5-Layer Micromold Assembly Stacking and Solder Ball Parameter Settings

[0112] The DDR3 TSV 5-layer micromold assembly is composed of five layers of TSVs. Therefore, the stacking order is based on the actual application. The TSVs are inverted and arranged in a combined manner. Each layer of TSVs is bonded with adhesive U8410-73c. The top and bottom layers require adhesive bonding, and the height is set to the actual solder ball height.

[0113] Solder Ball: Bump setting, according to the bare chip solder ball diameter, height, and material setting;

[0114] The top IPD chip corresponds to a ball with a diameter of 90um and a height of 70um;

[0115] The DDR3 bare chips are embedded in 5 layers of TSV, with a corresponding ball diameter of 40 μm and a height of 10 μm.

[0116] The diameter of the BGA ball at the bottom layer of the micromodule is 350um and the height is 260um;

[0117] The materials are all Sn63Pb37, with a conductivity of 8.7e6S / m.

[0118] Therefore, the stacking configuration of the DDR3 TSV5-layer micro-die assembly is shown in Table 2.

[0119] Table 2 DDR3 TSV substrate 5-layer micromodule stackup design list

[0120]

[0121]

[0122] 1.2.3 Tube and shell setting parameters

[0123] Dielectric materials commonly used for tube and shell packages include traditional high-temperature co-fired ceramic (HTCC) and the next-generation high-speed low-temperature co-fired ceramic tube and shell (HITCE). For some high-frequency, high-speed circuits, HITCE ceramic packaging can better meet high-speed path requirements. HITCE ceramic material is used here. Since the controller TSV substrate and the DDR3 chip TSV substrate five-layer micromold assembly both have parameters set for the bottom layer BGA solder balls and the filler material after soldering to the tube and shell, there is no need to repeatedly set the parameters for the solder balls and related filler when setting up the tube and shell stackup. Only the parameters for the intermediate dielectric layer and metal layer need to be set. The tube and shell stackup settings are shown in Table 3.

[0124] Table 3 Tube and shell stacking setting list

[0125]

[0126] 1.3 Power supply PI simulation analysis

[0127] PI simulation analysis includes DC IRdrop simulation and power supply AC impedance simulation. DC IRdrop simulation analyzes the DC voltage loss, current density, and via current across the entire power delivery network (PDN), from the power supply chip VRM to the power-consuming chip, guiding design optimization. Power supply impedance simulation analyzes the impedance of the entire PDN, optimizing the decoupling network to achieve a low-impedance PDN design.

[0128] 1.3.1 DC IRdrop voltage drop simulation analysis

[0129] Since the microsystem modules are stacked at a high density in three dimensions, it is particularly important to perform power supply DCIRdrop analysis at the silicon substrate and tube shell stage, examining the current carrying capacity of the power plane layer from key parameters such as overcurrent capability, voltage drop, and current density.

[0130] DC IRdrop simulations are required for the controller TSV substrate, the DDR3 chip TSV substrate 5-layer microdie assembly, and the package. If any simulation results fail, the cause is identified and the layout modified until each component passes DC IRdrop simulation. Then, in the simulation software, the engineering files for the controller TSV substrate and package are merged, as are the engineering files for the DDR3 chip TSV substrate 5-layer microdie assembly and package, and DC IRdrop simulations are performed on both projects.

[0131] During the simulation process, if the TSV board and tube shell are simulated separately according to the sub-components, the voltage source of the bumps and solder balls at the sub-components is operated as a pin-group, and the current source is evenly distributed to each pin for operation; if the TSV board and tube shell are combined and integrated for simulation, then as an overall model, key parameters such as the overcurrent capacity, voltage drop, and current density of bottlenecks such as bumps and solder balls can be analyzed. In this way, the simulated current path is closer to the actual working conditions.

[0132] The DC IRdrop simulation method for each project is as follows:

[0133] First, import the layout of the tube shell and silicon substrate into SIwave to set the stacking parameters, including material conductivity, dielectric constant, loss tangent, and chip-specific Solder Ball parameters. Second, add a voltage source and a current source between the chip's power and ground pins, with the voltage source's internal resistance set to 1e-06 Ohm. Next, set the DC voltage drop (Compute DCIR) and calculate the solution. Then, review the simulation results, including the voltage distribution diagram, current density distribution diagram, and via current of all layers where the power and ground are located. Finally, determine whether the simulation results meet the requirements based on the standards. If not, perform simulation optimization to guide the modification of the PDN network's wiring design.

[0134] During the simulation process, pay special attention to adding current sources. If the chip has multiple power and ground pins, three methods can be used to add current sources. The first method is to add a current source between each power pin and the adjacent ground pin, with the current source equal to the maximum operating current divided by the number of power pins. The second method is to group the power and ground pins into groups and add a current source equal to the maximum operating current between the groups. The third method is to configure the current based on the mapped pins according to the chip power model (CPM) provided by the device. Because the chip CPM is difficult to obtain, the second method is more convenient and universal.

[0135] The current source of the controller's TSV silicon-based component is located at the bare chip installation location (TOP layer), and the BGA pad at the other end is located to add a voltage source to the VRM end (BOTTOM layer); the current source of the DDR3 particle TSV substrate 5-layer micro-module component is located at the bare chip (a total of 5 chips), and the bottom BGA pad is located to add a voltage source to the VRM end (BOTTOM layer); the current source of the tube shell is located at the two silicon-based component pads (TOP layer), and the bottom BGA external lead pad is located to add a voltage source to the VRM end (BOTTOM layer); in the project after the silicon substrate and tube shell are merged, the current source is located at the bare chip installation location, and the bottom BGA external lead pad is located to add a voltage source to the VRM end (BOTTOM layer of the tube shell).

[0136] DC voltage loss standards: The VRM supplies power to the chip through the PDN. The DC voltage loss generated by the PDN must not exceed the chip supply voltage VCC * Ripple. Ripple is obtained from the chip manual and is generally 5%. For VRMs external to the microsystem module, the PDN consists of both the external circuit board and the microsystem itself. The combined voltage loss must not exceed Ripple. Therefore, the DC voltage drop within the microsystem's PDN is recommended to not exceed VCC * 3%.

[0137] Current density standards: The current carried by metal traces of the same cross-sectional area increases nonlinearly with increasing temperature. Therefore, better heat dissipation results in a higher permissible temperature rise and a higher permissible current density. This is a comprehensive analysis of electrical and thermal factors. Based on current density results, thermal simulations, prototype test runs, and several microsystem modules successfully manufactured and debugged in recent years, the empirical maximum simulated current density for silicon substrate and housing materials is 800A / mm². This value was subsequently revised based on accumulated measured data on process parameters. The current limits for commonly used vias in Siwave software are summarized in Tables 4 and 5.

[0138] Table 3 Via current determination table in Siwave software in TSV board

[0139]

[0140] Table 4 Via current determination table in Siwave software in tube shell

[0141] Via Name Via diameter (um) Via location Limit current (mA) VIR75 75 MP4-MP6 397 MP15-MP17 50 TOP-MP2 176

[0142] When the DC voltage drop simulation exceeds the standard, you can optimize the PCB design in the following ways.

[0143] (1) Increase the width of the traces and planes at the bottleneck of the PDN current path.

[0144] (2) Increase the aperture of the via that carries too much current; add more vias near the via; adjust the distribution of vias and move the via that carries less current to the main current path to share the current.

[0145] (3) Increase the copper thickness of the power ground plane.

[0146] 1.3.2 AC impedance simulation analysis

[0147] Power supply impedance simulation verification: When transient current changes occur on the power distribution network (PDN), the resulting voltage change exceeds the chip's allowable voltage variation. In other words, whether the PDN can provide clean, noise-free power to the chip. If the transient voltage variation is excessive, optimize the PDN's decoupling network through simulation to guide PDN design modifications.

[0148] Principles for determining AC impedance simulation:

[0149] (1) TSV substrate has no capacitance, so no AC impedance simulation is required;

[0150] (2) A decoupling capacitor is installed in the tube shell, so the AC impedance simulation of the tube shell power supply network is performed;

[0151] (3) For power supply networks undergoing AC impedance simulation analysis, specific analysis is performed based on the actual parallel capacitors. Capacitors are typically placed so that the PDN impedance is lower than the target impedance at the mid-frequency stage. Decoupling capacitors are selected and placed using a Multi-Ploe (MP) method with varying capacitance values. For example, the three-per-decade method can be used, where multiple capacitors are selected based on multiples of 10. The impedance curve can also effectively control the parallel resonance peak. Furthermore, considering the packaging parasitics, the capacitors should be placed close to the microsystem module's power supply pins.

[0152] (4) When placing capacitors, it is also necessary to consider that the current of the power-consuming chip is large, and the voltage regulator module cannot respond to the rapid changes in the load's current demand in real time. Therefore, large-capacity energy storage capacitors are placed at the four corners of the chip pads to prevent voltage drops.

[0153] AC impedance simulation analysis method:

[0154] Pin groups are created for the chip's power and ground pins. A small 0.01 ohm resistor is added between the power and ground pin groups on the VRM side. A port is added between the power and ground pin groups on the power-consuming chip. Next, ComputeSYZ Parameters are set and calculated. The simulation results and the Z impedance curve at the power-consuming chip's port are then examined. Finally, the simulation results are determined to determine whether they meet the target impedance requirements. If not, simulation optimization is performed to guide design modifications to the PDN decoupling network.

[0155] The target impedance method is commonly used at present. The definition of target impedance is as follows:

[0156]

[0157] Vcc is the power supply voltage, Ripple is the allowable voltage fluctuation, usually 5%, ΔI max The maximum transient current change of the load chip. The principle of power supply impedance design simulation is that the PDN impedance should not exceed the target impedance. The target impedance is not a constant value but increases with frequency. An accurate target impedance curve requires the maximum transient current change of the load chip at each frequency point, i.e., the current demand spectrum. If a chip power model (CPM) is available, PDN time-domain simulation can be performed directly to verify whether power supply noise exceeds the specified limit.

[0158] The PDN design can be carried out collaboratively with the chip, microsystem package and application prototype PCB. That is, the model S parameters of the power network from the VRM end of the prototype PCB board to the microsystem module pad, TSV board and tube shell Attach Package are extracted respectively. Then, a time domain circuit diagram is built in the simulation software Designer to construct the full PDN link. The chip CPM model is connected at the module end. Figure 4 By combining decoupling capacitor optimization with time-domain simulation, we analyze different numbers and values of capacitors to obtain a decoupling network design that keeps the power supply ripple within a limited range.

[0159] The time domain waveform of the chip-side 1V5 power supply network is as follows. The black dashed line is the voltage waveform after using the CPM model to accurately optimize the high-frequency decoupling capacitors of the microsystem module shell and coordinately optimize the PCB medium-frequency decoupling capacitors; the black solid line is the voltage waveform without the decoupling capacitor network. It can be seen that the chip-side power supply ripple is reduced by 33mV. Figure 5 shown.

[0160] 1.4.SI Simulation Analysis

[0161] The DDR3 bus's address, clock, data, and strobe signals have strict timing requirements, and each signal has detailed signal quality parameter requirements. DDR3's data DQ, DM, and DQS signals are all point-to-point interconnects. Impedance matching can be achieved by adjusting the drive capability on the driver side and the ODT impedance settings on the receiver side, thereby ensuring waveform integrity. Address, control, and clock signals require adjustments to the driver's drive capability and matching resistors and capacitors at the far end of the fly-by topology. Signal integrity simulation includes frequency and time domain analysis to verify signal overshoot, edge degradation, and whether levels and timing meet identification requirements. This optimization analysis guides PCB design.

[0162] First, the layout design of the TSV substrate and housing was imported into the simulation software to set the board stackup, capacitor, and resistor parameters. Next, the signal path S-parameters were extracted. Because the layout involved a dual-hole TSV design and a micromodule consisting of five stacked TSV layers, HFSS 3D Layout software was preferred for this purpose, given the software's algorithm's accuracy in calculating 3D layout structures. Due to its long calculation time, signals were grouped when extracting S-parameters. As shown in Table 6, signals were typically extracted as a group based on their actual operating timing and reference to each other.

[0163] Table 5 Classification based on whether the signal is one-way or not

[0164]

[0165] Next, we used the circuit Designer module of Ansys EM Desktop to perform time-domain circuit analysis. Based on the different directions of the signal read and write states, we imported and extracted the S parameters of the path. When building the circuit, we adjusted the direction of the S parameters during cascading according to the left-to-right direction of the signal, as shown in Table 7.

[0166] Table 6 Direction list of S parameter cascade

[0167]

[0168] Import the chip's IBIS model, AMI-IBIS model, or Spice model. Here, the controller chip uses the bare-chip IBIS model of the Fudan Microelectronics 7VX690T FPGA chip, and the receiver uses the bare-chip IBIS model of the SMIC SM41J256M16M memory chip. Because there's no IPD model for the resistor-capacitor matching chip, we use resistors and capacitors from the software component library instead for time domain analysis.

[0169] The simulation focuses on analyzing the characteristics of different chip driver ports and their topological termination matching methods. Generally speaking, as a data receiver, its ODT modes include ODT40, ODT60, ODT120, and ODToff, representing 40ohm, 60ohm, 120ohm, and unterminated terminations, respectively. As a transmitter, its electrical characteristics include iobuf34, iobuf40, and iobuf48 drive states. Given current trace widths, spacing, silicon stack dimensions, and material parameters, the optimal signal waveform design is as follows: ① The driver chip uses iobuf34; ② The address and control lines are terminated at their farthest ends with a pull-up to 0.75V, with matching resistors ranging from 40ohm to 80ohm; ③ The clock differential lines are terminated at their farthest ends with a 60ohm resistor connected in series with the first terminal of each positive and negative line. The two terminals of the two resistors are shorted, then connected in series with a 100pF capacitor, and then pulled up to 1.5V. Simulation drawings and detailed descriptions are provided in Section 7.

[0170] Next, review the simulation results, including levels, edges, timing, and eye diagrams. For DDR3 signals, use the built-in DDR3 script to calculate timing. Finally, determine whether the time domain and timing meet the requirements of the Electrical Characteristics and AC Timing section of the JESD79-3F standard for DDR3 signal identification. If not, perform simulation optimization to guide layout modifications.

[0171] As can be seen from the above, the present invention has the following beneficial effects compared with the prior art:

[0172] 1) Propose a method for parameter setting of TSV silicon substrate, package, and stacked TSV components in a microsystem during signal integrity simulation analysis;

[0173] 2) Propose a method and criteria for PI DC simulation analysis of TSV silicon substrates and tube shells in microsystems;

[0174] 3) Propose a method and judgment criteria for simulation analysis of the AC impedance of TSV silicon substrates and tube shell PI in microsystems, so as to achieve low-impedance design of power supply ripple PDN;

[0175] 4) A method is proposed to simulate the DDR3 signal in the complete link cascade from the controller 690TSV component, the tube shell, and the DDR3 particle TSV5 layer micro-module component in the microsystem.

[0176] In this embodiment, the simulation adopts the electromagnetic field and circuit collaboration, that is, the field-path collaboration simulation method, to solve the S parameters of the micromodule interconnection channel based on the electromagnetic field simulation, and to analyze the signal time domain waveform and termination matching based on the circuit simulation. In the simulation, the address and control signal rate is set to 800Mbps. Because the vertical interconnection path of the DDR micromodule interconnection structure is complex and the 3D effect is prominent, HFSS 3Dlayout software is used to extract the S parameters of the signal interconnection to ensure the accuracy of the S parameters. Because the amount of micromodule layout data is too large, the S parameters can be cut to simulate the board, such as cutting out the address and control lines in the left half area to reduce the amount of data.

[0177] In this embodiment, the data signal is a point-to-point network, with each micromodule providing a one-to-one connection between an external point and a memory chip pin. The data signal layout and the data lines of the top-level memory chip are interconnected in a point-to-point 3D manner. Simulation also utilizes field-circuit co-simulation. HFSS 3D Layout software was used to slice the board and solve for S-parameters, carving out the lower 8-bit data line group signals DQL0-DQL7, DM0, and DQSL differential pairs. The data signal rate in the simulation was 1600Mbps.

[0178] When building the circuit, the address, clock signal, and data write state are as follows from left to right: FPGA IBIS model, controller TSV substrate S parameters, tube-shell interconnect S parameters, DDR micromodule interconnect S parameter model, DDR3 memory IBIS model, see Figure 6 and Figure 7 shown.

[0179] When building the data read state circuit, the data read state is from left to right: DDR IBIS model, DDR3 micromodule interconnect S parameter model, tube shell interconnect line S parameter, controller TSV substrate S parameter, FPGA IBIS model, see Figure 8 shown.

[0180] In this embodiment, the controller is located on the 690TSV component, connected to the DDR3 TSV 5-layer micro-die through the NOP package, and then to the DDR3 bare chip. Therefore, during simulation, the 690TSV component (controller), NOP package, and DDR3 TSV 5-layer micro-die are cascaded to simulate DDR3 signal amplitude and timing.

[0181] The controller bit number is 690TSV, and the model uses 330t690t.ibs; the model of 5 DDR3 chips (bit numbers are: U1, U2, U3, U4, U5) uses sm41j256m16die.ibs.

[0182] The address line driver model 330t690t.ibs selects SSTL15_F_HR, and the receiving end model sm41j256m16die.ibs selects inbuf; in write state, the model 330t690t.ibs selects SSTL15_F_HR, and the model sm41j256m16die.ibs selects ODT60; in read state, the model sm41j256m16die.ibs selects iobuf34; the model 330t690t.ibs selects: SSTL15_F_HR_IN60 or SSTL15_DCI_AUX20_HP_IN60_I.

[0183] The control and address lines are routed using the FLY-BY model, with the farthest DDR3 device pulled up to 0.75V via a 60-ohm resistor. The differential clock lines are routed using the FLY-BY model, with the positive and negative lines of the farthest DDR3 device connected in series with a 60-ohm resistor, shorted, and then connected in series with a 100pF capacitor to 1.5V. Since the RDL chip used for the matching resistor and capacitor settings has no model, the matching resistor and capacitor are replaced with ideal resistors and capacitors from the simulation software DESIGNER library. See the simulation waveform diagram. Figures 9 to 12 , script running diagram see Figure 13 As shown in the figure, both the amplitude and timing comply with the DDR3 standard JESD79-3F.

[0184] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any ordinary technician in this industry can smoothly implement the present invention as shown in the drawings and described above. However, any equivalent changes, modifications and evolutions made by technicians familiar with this profession without departing from the scope of the technical solution of the present invention using the technical content disclosed above are all equivalent embodiments of the present invention. At the same time, any equivalent changes, modifications and evolutions made to the above embodiments based on the essential technology of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. A method for simulating and analyzing PI and SI signals of DDR3 in a microsystem module, characterized in that: The steps of simulating the DC voltage drop after merging the silicon substrate and the tube shell are as follows: Import the layout of the tube shell and silicon substrate into the simulation software and set the simulation parameters; After adding a voltage source and a current source between the power pin and the ground pin of the chip, start the simulation software to simulate the DC voltage drop and calculate the solution to obtain the simulation results; According to the simulation standards, judge whether the simulation results meet the requirements. If the requirements are met, the simulation is completed; If the requirements are not met, the items in the layout that do not meet the simulation standards are located and the layout of the items that do not meet the simulation standards is changed until the requirements are met and the simulation is completed.

2. The method for simulating and analyzing DDR3 signal PI and SI in a microsystem module according to claim 1, wherein: The merging of the silicon substrate and the tube shell comprises: Merge the engineering files of the controller TSV substrate and tube shell, and merge the engineering files of the DDR3 particle TSV substrate micro-mold assembly and tube shell.

3. The method for simulating and analyzing PI and SI signals of DDR3 in a microsystem module according to claim 1, wherein: The simulation parameters include material conductivity, dielectric constant, loss tangent and solder balls corresponding to the chip.

4. The method for simulating and analyzing PI and SI signals of DDR3 in a microsystem module according to claim 1, wherein: The adding of a voltage source and a current source between the power pin and the ground pin of the chip specifically includes: A current source is set on the TOP layer of the bare chip, and a voltage source is set on the power supply end at the BGA pad position on the BOTTOM layer of the bare chip.

5. The method for simulating and analyzing PI and SI signals of DDR3 in a microsystem module according to claim 1, wherein: The simulation standards include DC voltage loss standard and current density standard, The DC voltage loss standard is that the DC voltage drop generated by the power supply network in the microsystem module does not exceed 3% of the chip supply voltage, and the current density standard is that the simulated current density does not exceed the limited current.

6. The method for simulating and analyzing DDR3 signals PI and SI in a microsystem module according to claim 1, wherein: After the step of simulating the DC voltage drop, the step of simulating the AC impedance is also included, and the steps are as follows: Connect the power pins of the chip together to form a power pin group, and connect the ground pins together to form a ground pin group; Add a resistor between the power pin group and the ground pin group of the power supply chip, and add an interface between the power pin group and the ground pin group of the power consumption chip; After setting the Compute SYZ parameters in the simulation software, perform AC impedance simulation and solve the problem to obtain the target impedance curve at the interface of the power chip. According to the target impedance standard, the obtained simulation results are judged to see whether they meet the requirements. If the requirements are met, the simulation is completed; If the requirements are not met, the target impedance standard is not met, and the decoupling network in the power supply network of the microsystem module is modified until the requirements are met and the simulation is completed.

7. The method for simulating and analyzing DDR3 signals PI and SI in a microsystem module according to claim 6, wherein: The decoupling network acquisition of the power supply network comprises the following steps: Extract the signal parameter model of the power supply network from the power supply end of the PCB board to the encapsulated microsystem module; Build the entire PDN link in simulation software; The chip CPM model is accessed at the module end of the entire PDN link; Obtain the decoupling network of the power supply network based on decoupling capacitor optimization and time domain simulation.

8. The method for simulating and analyzing DDR3 signal PI and SI in a microsystem module according to claim 1, wherein: After the DC voltage drop simulation step, a signal integrity simulation step is also included, and the steps are as follows: Extract signal parameters of interconnect lines between controller bare chip pads and TSV lead-out pins; Extract the signal parameters of the interconnection lines between the TSV lead-out pins and the DDR3 chip pads and the matching RC IPD chip pads; Extract the signal parameters of the interconnection line between the controller TSV lead-out pin and the DDR3 chip TSV lead-out pin; Cascade the extracted signal parameters, import them into the chip model, establish a time domain solution, and obtain the DDR3 signal SI simulation results; Determine whether the obtained DDR3 signal SI simulation results meet the requirements according to the standard. If the requirements are met, the simulation is completed; If the requirements are not met, the items in the layout that do not meet the standards are located and the layout of the items that do not meet the standards is changed until the requirements are met and the simulation is completed.

9. The method for simulating and analyzing DDR3 signals PI and SI in a microsystem module according to claim 8, wherein: The DDR3 signal SI simulation results include the frequency domain, time domain, level, edge, timing and eye diagram of the DDR3 signal.

10. The method for simulating and analyzing DDR3 signals PI and SI in a microsystem module according to claim 8, wherein: The timing of the DDR3 signal in the DDR3 signal SI simulation result is calculated using an embedded DDR3 script.

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