An electronic synaptic circuit and a neural network circuit based on ferroelectric field effect transistors

Abstract

The present application relates to a neural network circuit, including a plurality of neuron circuits and a plurality of electronic synapse circuits, wherein at least one of the electronic synapse circuits is configured to receive an input and a control signal from a presynaptic neuron circuit and receive a feedback signal from a postsynaptic neuron circuit; wherein, the electronic synapse circuit at least includes a switching unit, an input unit and a weight calculation unit; the present application also relates to an electronic system including the neural network circuit as described above and an electronic device.

Description

Technical Field

[0001] This application relates to the field of neural network circuit design, and particularly to an electronic synapse circuit and a neural network circuit based on ferroelectric field effect transistors. Background Art

[0002] With the rapid development of information technology industries such as artificial intelligence and big data, the requirements for the processing speed and performance of computers in people's social production and daily life are getting higher and higher. The amount of data that computers need to process has increased exponentially, which has brought unprecedented pressure to both data storage and calculation. The most commonly used computer architecture currently is the traditional von Neumann architecture, which has the characteristic of separating storage and computing. Data needs to be frequently transferred between the storage unit and the computing unit, which will not only greatly reduce the computing speed but also greatly increase the computing power consumption.

[0003] To solve the problems of the von Neumann architecture, people have proposed an architecture method of neuromorphic computing based on bionics. By imitating the connection method of neurons and synapses in the brain, neuroscience theoretical modeling is completed to solve complex computing problems that cannot be processed at high speed in the traditional architecture. The LIF neuron model is one of the most basic models commonly used in neuromorphic computing architectures. Its essence is to abstract neurons into capacitors and convert the way neurons communicate into action potentials and pulses. In the LIF neuron model, the potential of the electrical signal input to the neuron and the stability of the finally output pulse are both one of the cores that can improve the stability and processing speed of the neuron model.

[0004] As an emerging computing paradigm, if the behavior of neurons or neural synapses is simulated from the physical level through hardware circuits, it is expected to achieve low-power and high-computing-performance neuromorphic computing. Therefore, choosing a reasonable computing method and designing and building a hardware circuit are also important issues for realizing neuromorphic computing. Summary of the Invention

[0005] In view of the technical problems existing in the prior art, the present application proposes a neural network circuit, including a plurality of neuron circuits and a plurality of electronic synapse circuits, wherein at least one of the electronic synapse circuits is configured to receive an input and a control signal from a presynaptic neuron circuit and receive a feedback signal from a postsynaptic neuron circuit; wherein, the electronic synapse circuit at least includes a switching unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, and configured to control the connection state between the electronic synapse circuit and the postsynaptic neuron circuit under the influence of a control signal from the presynaptic neuron circuit; an input unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, and configured to receive first and second input signals from the presynaptic neuron circuit under the control of a feedback signal from the postsynaptic neuron circuit; a weight calculation unit, coupled between the switching unit and the ground and coupled to the input unit, the weight calculation unit at least includes a ferroelectric transistor, and the ferroelectric transistor is configured to receive the first and second input signals from the input unit to update the channel resistance of the ferroelectric transistor.

[0006] Specifically, the postsynaptic neuron circuit includes a comparator, the positive input terminal of which is coupled to the switching unit of the electronic synapse circuit, the negative input terminal of the comparator is configured to receive a preset constant signal, and the output terminal of the comparator is coupled to the input unit of the electronic synapse circuit; a resistor, which is coupled between the positive input terminal of the comparator and the power supply; a capacitor, which is coupled between the positive input terminal of the comparator and the ground; when the switching unit connects the postsynaptic neuron circuit to the electronic synapse circuit and the ferroelectric transistor is turned on, the voltage at the positive input terminal of the comparator drops, and when this voltage drops below the preset constant signal, the comparator is configured to output the feedback signal.

[0007] Specifically, the switching unit includes a first transistor, the control electrode of which is configured to receive the control signal, the first pole of which is coupled to the positive input terminal of the comparator, and the second pole of which is coupled to the first pole of the ferroelectric transistor.

[0008] Specifically, the input unit includes a second transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is configured to receive the first input signal, and whose second electrode is coupled to the control electrode of the ferroelectric transistor; a third transistor, which has a type complementary to that of the second transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is grounded, and whose second electrode is coupled to the control electrode of the ferroelectric transistor; a fourth transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is configured to receive the second input signal, and whose second electrode is coupled to the second electrode of the ferroelectric transistor; and a fifth transistor, which has a type complementary to that of the fourth transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is grounded, and whose second electrode is coupled to the second electrode of the ferroelectric transistor.

[0009] Specifically, the postsynaptic neuron circuit further includes a delay unit, which is coupled between the output terminal of the comparator and the input terminal of the input unit, and is configured to generate a time interval between the effective levels of the control signal and the feedback signal.

[0010] Specifically, the control electrode of the ferroelectric transistor is configured to receive the first input signal, and the second electrode of the ferroelectric transistor is configured to receive the second input signal; the control signal and the second input signal simultaneously jump to the effective level, and the first input signal generates an effective level when the effective level of the second input signal jumps to the invalid level; the effective level of the second input signal gradually increases during one pulse, and the effective level of the first input signal gradually decreases during one pulse.

[0011] Specifically, the amplitude of the effective level of the feedback signal is greater than the maximum amplitude of the effective levels of the first or second input signals.

[0012] This application proposes an electronic synapse circuit, which is configured to receive an input and a control signal from a presynaptic neuron circuit and receive a feedback signal from a postsynaptic neuron circuit; wherein, the electronic synapse circuit at least includes a switch unit, which is coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, and is configured to control the connection state between the electronic synapse circuit and the postsynaptic neuron circuit under the influence of a control signal from the presynaptic neuron circuit; an input unit, which is coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, and is configured to receive a first input signal and a second input signal from the presynaptic neuron circuit under the control of a feedback signal from the postsynaptic neuron circuit; and a weight calculation unit, which is coupled between the switch unit and the ground and is coupled to the input unit, and the weight calculation unit at least includes a ferroelectric transistor, and the ferroelectric transistor is configured to receive the first input signal and the second input signal from the input unit to update the channel resistance of the ferroelectric transistor.

[0013] Specifically, the switching unit of the electronic synapse circuit includes a first transistor, whose control electrode is configured to receive the control signal, whose first pole is coupled to the postsynaptic neuron circuit, and whose second pole is coupled to the first pole of the ferroelectric transistor.

[0014] Specifically, the input unit of the electronic synapse circuit includes a second transistor, whose control electrode is configured to receive the feedback signal, whose first pole is configured to receive the first input signal, and whose second pole is coupled to the control electrode of the ferroelectric transistor; a third transistor, which has a type complementary to that of the second transistor, whose control electrode is configured to receive the feedback signal, whose first pole is grounded, and whose second pole is coupled to the control electrode of the ferroelectric transistor; a fourth transistor, whose control electrode is configured to receive the feedback signal, whose first pole is configured to receive the second input signal, and whose second pole is coupled to the second pole of the ferroelectric transistor; a fifth transistor, which has a type complementary to that of the fourth transistor, whose control electrode is configured to receive the feedback signal, whose first pole is grounded, and whose second pole is coupled to the second pole of the ferroelectric transistor.

[0015] Specifically, in the electronic synapse circuit as described above, the control electrode of the ferroelectric transistor is configured to receive the first input signal, and the second pole of the ferroelectric transistor is configured to receive the second input signal; the control signal and the second input signal simultaneously jump to the effective level, and the first input signal generates an effective level when the effective level of the second input signal jumps to the invalid level; the effective level of the second input signal gradually increases during one pulse, and the effective level of the first input signal gradually decreases during one pulse.

[0016] Specifically, in the electronic synapse circuit as described above, the amplitude of the effective level of the feedback signal is greater than the maximum amplitude of the effective level of the first or second input signal.

[0017] This application also proposes an electronic system, including the neural network circuit as described above.

[0018] This application also proposes an electronic device, including the neural network circuit as described above.

[0019] Adopting the solution of this application, on the one hand, since this solution simulates neurons from the physical structure of the circuit, advantages of low power consumption and high computing performance can be obtained; on the other hand, using the STDP mechanism to optimize the signal transmission of the neuron morphology circuit can further shorten the circuit processing time. Using ferroelectric field-effect transistors in the circuit design can once again reduce the power consumption of the circuit and improve the processing speed through its non-volatile characteristics and other features. The novel neural network circuit structure proposed by this solution also has a positive significance for promoting the development of neuromorphic circuits. Description of the Drawings

[0020] Next, the preferred embodiments of the present application will be further described in detail in conjunction with the accompanying drawings, where:

[0021] Figure 1 Shown is a schematic diagram of a neural network circuit model according to an embodiment of the present application.

[0022] Figure 2 Shown is a schematic diagram of the STDP mechanism characteristic curve of an electronic synapse.

[0023] Figure 3A Shown is a schematic diagram of an electronic synapse circuit and a partial postsynaptic neuron circuit according to an embodiment of the present application.

[0024] Figure 3B Shown as Figure 3A The working timing diagram of the circuit shown.

[0025] Figure 4 Shown is the variation curve of the normalized conductance of an electronic synapse circuit with time according to an embodiment of the present application. Detailed implementation manners

[0026] In the following detailed description of the embodiments, reference will be made to the accompanying drawings that form a part of the present application. The accompanying drawings illustrate, by way of example, specific embodiments that can implement the present application. The example embodiments are not intended to exhaust all embodiments according to the present application. It can be understood that, without departing from the scope of the present application, other embodiments can be utilized and structural or logical modifications can be made. Therefore, the following detailed description is not restrictive, and the scope of the present application is defined by the appended claims.

[0027] For technologies, methods, and devices known to those of ordinary skill in the relevant art, they may not be discussed in detail, but where appropriate, the said technologies, methods, and devices should be regarded as part of the specification. For the connections between the units in the drawings, it is only for the convenience of explanation, which indicates that at least the units at both ends of the connection communicate with each other, and it is not intended to limit that the units not connected cannot communicate. Additionally, the number of lines between two units is intended to represent at least the number of signals involved in the communication between the two units or at least the number of output terminals they have, rather than being used to limit that the two units can only communicate with the signals shown in the figure.

[0028] In the following detailed description, reference may be made to the various specification drawings that form a part of the present application and illustrate specific embodiments of the present application. In the drawings, like reference numerals generally describe substantially similar components in different figures. The specific embodiments of the present application are described in sufficient detail below so that those of ordinary skill in the relevant art and technology can implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0029] A transistor may refer to a transistor of any structure, such as a field-effect transistor (FET) or a bipolar junction transistor (BJT). When the transistor is a field-effect transistor, depending on the channel material, it can be hydrogenated amorphous silicon, metal oxide, low-temperature polysilicon, organic transistor, etc. Depending on whether the carriers are electrons or holes, it can be divided into N-type transistors and P-type transistors. Its control electrode refers to the gate of the field-effect transistor, the first electrode can be the drain or source of the field-effect transistor, and the corresponding second electrode can be the source or drain of the field-effect transistor; when the transistor is a bipolar junction transistor, its control electrode refers to the base of the bipolar junction transistor, the first electrode can be the collector or emitter of the bipolar junction transistor, and the corresponding second electrode can be the emitter or collector of the bipolar junction transistor.

[0030] Traditional computer architectures divide devices into computing units and storage units. To complete a calculation, the computing unit needs to be called to calculate the data to be processed, and then the calculation result is stored in the storage unit. When faced with large amounts of data and relatively complex calculation processes, traditional computer architectures need to split the calculation process into multiple simple calculations and repeat the above steps multiple times. Multiple intermediate values will be generated and stored in the storage unit before the final calculation result is obtained, and these intermediate values are called again during the calculation to complete the calculation of the final result.

[0031] The artificial neural network circuit proposed in the present application (hereinafter referred to as the neural network circuit) can effectively simplify complex calculation processes and at the same time avoid problems caused by the separation of storage and computing.

[0032] Figure 1 It is a schematic diagram of a neural network circuit model according to an embodiment of the present application. In the neural network circuit, there are multiple nodes, also known as neurons, and two neurons can be connected through an electronic synapse. The synapse transmits an electrical signal from the pre-synaptic neuron to the post-synaptic neuron, and the transmission path depends on the weight of the electronic synapse between the neurons. The higher the weight, the closer the connection between the two neurons.

[0033] Such as Figure 1As shown, according to an embodiment of the present application, a neuron in a neural network circuit can be connected to multiple neurons, and signals are transmitted between two neurons through an electronic synapse. The calculation to be completed can be converted into multiple loop calculations in the neural network circuit. A single calculation process can be converted into a process of transmitting signals in the neural network circuit starting from an initially set neuron by the user, passing through multiple neurons and electronic synapses, and finally being transmitted to the target neuron set by the user. The neural network circuit automatically adjusts the weights between neurons based on a preset learning mechanism, thereby realizing the calculation process for different problems.

[0034] Each electronic synapse can receive signals from at least one neuron (referred to as the presynaptic neuron with respect to this synapse), and / or can send signals to at least one neuron (referred to as the postsynaptic neuron with respect to this synapse).

[0035] Figure 2 Shown is a schematic diagram of the STDP learning mechanism characteristic curve of an electronic synapse. Among them, the time Δt on the horizontal axis represents the time difference between the moment when the postsynaptic neuron emits a signal and the moment when the presynaptic neuron emits a signal, and the ΔW on the vertical axis represents the weight change rate of the electronic synapse. From Figure 2 it can be seen that for this kind of electronic synapse, when Δt is positive, the weight change rate of the electronic synapse will decrease as Δt increases.

[0036] In order to fabricate an electronic synapse having the above STDP learning mechanism characteristic curve, the present application provides an electronic synapse circuit. In particular, this electronic synapse circuit includes a ferroelectric transistor (FeFET).

[0037] With the development of semiconductor device technology, some new devices with adjustable resistance and non-volatile characteristics have been proposed, including resistive random access memory, phase change memory, ferroelectric transistors (FeFETs), etc. Among them, FeFETs have advantages such as low power consumption and high operating speed, and thus have received extensive attention in the scientific research community and the industrial community.

[0038] A FeFET is a novel transistor that adds a ferroelectric material layer between the gate and the gate oxide layer of a traditional MOSFET. By changing the amplitude and duration of the voltage applied to the FeFET gate, the amount of charge induced on the gate oxide layer can be modulated, thereby changing the threshold voltage and channel resistance of the FeFET. When a specific voltage is applied between the gate and source of the FeFET, the electric dipoles formed in the crystal structure of the ferroelectric material will align with the direction of the electric field. Even if the gate voltage is removed, the above conduction characteristics will not change. Even after the electric field is removed, the electric dipoles formed in the crystal structure of the ferroelectric material will maintain this polarized state, so that the threshold voltage and channel resistance of the FeFET remain unchanged until the gate-source voltage changes and the threshold voltage and channel resistance are set again.

[0039] Figure 3A Shown is a schematic diagram of an electronic synapse circuit and a partial postsynaptic neuron circuit according to an embodiment of the present application. Figure 3B Shown as Figure 3A The working timing diagram of the circuit shown.

[0040] As Figure 3A As shown, the electronic synapse circuit 20 is coupled to its postsynaptic neuron circuit 30, and at the same time, the electronic synapse circuit 20 is also coupled to a presynaptic neuron circuit (not shown). According to an embodiment, the presynaptic neuron circuit may have a circuit structure similar to that of the postsynaptic neuron circuit.

[0041] According to an embodiment, each neuron circuit can emit at least four signals when emitting a signal, including STDP WL1, STDP WL2, LIF WL. These three signals can be provided to the subsequent neuron circuit as control signals and input signals at the postsynapse; there is also STDP BL, which can be provided as a control signal at the presynapse, and the presynapse is connected between the neuron circuit and the previous neuron circuit. Here, the so-called "front" or "back" are relative to the signal transmission path input by the user. Relatively closer to the most initial neuron circuit is "front", and relatively farther from the most initial neuron circuit is "back".

[0042] For a specific electronic synapse circuit, the control signal LIF WL provided by the presynaptic neuron circuit determines the connection state between the electronic synapse circuit and the postsynaptic neuron circuit. The input signals STDP WL1 and STDP WL2 provided by the presynaptic neuron circuit determine the updated value of the weight of the electronic synapse circuit. The feedback signal STDP BL is provided by the postsynaptic neuron circuit and determines the timing to modify the current weight of the electronic synapse circuit to the updated value.

[0043] According to one embodiment, as Figure 3A shown, the electronic synapse circuit 20 may at least include a switching unit 201, an input unit 202, and a weight calculation unit 203.

[0044] According to one embodiment, the switching unit 201 may at least include, for example, an NMOS transistor M21, whose gate may be configured to receive a control signal LIF WL from a presynaptic neuron circuit. As Figure 3B shown, LIF WL includes a plurality of high-level short pulses. When LIF WL is at a high level, the electronic synapse circuit 20 is activated to work, and the electrical connection with the postsynaptic neuron circuit 30 is conducted.

[0045] According to one embodiment, the input unit 202 may at least include, for example, NMOS transistors M23 and M25, and PMOS transistors M24 and M26.

[0046] According to one embodiment, the drain of M23 may be configured to receive an input signal STDP WL1 from a presynaptic neuron circuit, the source may be coupled to the weight calculation unit 203, and the gate may be configured to receive a feedback signal STDP BL from the postsynaptic neuron circuit.

[0047] According to one embodiment, the source of M24 may be coupled to the source of M23 and the weight calculation unit 203, its drain may be grounded, and its gate may be configured to receive a feedback signal STDP BL from the postsynaptic neuron circuit.

[0048] According to one embodiment, the drain of M25 may be configured to receive an input signal STDP WL2 from a presynaptic neuron circuit, the source may be coupled to the weight calculation unit 203, and the gate may be configured to receive a feedback signal STDP BL from the postsynaptic neuron circuit. Among them, the input signals STDP WL1 and STDP WL2 may come from the output in the same presynaptic neuron circuit. As Figure 3B shown, STDP WL1 and STDP WL2 may be pulse signals with the same period and different waveforms.

[0049] According to one embodiment, the source of M26 may be coupled to the source of M25 and the weight calculation unit 203, the gate may be configured to receive a feedback signal STDP BL from the postsynaptic neuron circuit, and the drain may be grounded.

[0050] According to one embodiment, the weight calculation unit 203 may at least include a FeFET transistor M22. According to one embodiment, the gate of M22 may be coupled to the source of M23 and the source of M24, the source of M22 may be coupled to the source of M25 and M26, and the drain may be coupled to the source of M21.

[0051] As Figure 3A shown, the neuron circuit, such as the postsynaptic neuron circuit 30, may at least include a comparator 301, a resistor 302, and a capacitor 303. The positive input terminal of the comparator 301 may be coupled to the electronic synapse circuit 20 (e.g., may be coupled to the drain of the transistor M21), and is also coupled to the power supply through the resistor 302. The negative input terminal of the comparator 301 is configured to receive a preset threshold voltage Vth. Once the voltage Vout at the positive input terminal of the comparator 301 is lower than the voltage Vth at the negative input terminal, the neuron will output an output signal Y (which includes LIF WL’, STDP WL1’, STDP WL2’, and STDP BL). According to one embodiment, the neuron circuit may further include a delay unit 304 configured to ensure a certain time difference between the high-level pulse of STDP BL and the high-level pulse of LIF WL output by the presynaptic neuron circuit.

[0052] According to one embodiment of the present application, there are no restrictions on device parameters such as the gate length, doping concentration, and gate insulation layer thickness of M21, M22, M23, M24, M25, and M26, which can be adjusted according to actual needs.

[0053] According to one embodiment, as Figure 3B shown, when Vout is higher than Vth, the postsynaptic neuron circuit does not output the signal Y, so STDP BL is also at a low level. In this case, the transistors M23 and M25 in the input unit 202 are turned off, and at this time, the transistors M24 and M26 are turned on, and both the gate and the source of the FeFET transistor M22 are grounded. In this case, the threshold voltage and channel resistance of the FeFET transistor M22 remain unchanged. According to one embodiment, M22 may still be turned on when the gate-source voltage is 0.

[0054] When the high level of LIF WL arrives, the charge in the capacitor 303 will be discharged through the path where M22 is located in the electronic synapse circuit. If, after one discharge, Vout drops to a level lower than Vth, the postsynaptic neuron circuit 30 emits the signal Y, and STDL BL jumps to a high level.

[0055] According to one embodiment, a neuron circuit may be coupled to multiple previous electronic synapse circuits. When any one of these electronic synapse circuits can make Vout drop to a level lower than Vth, the neuron circuit will emit the signal Y, and all the previous electronic synapse circuits coupled to it will receive the high level of STDP BL.

[0056] However, if after one discharge, Vout cannot be reduced to a level lower than Vth, and other previous electronic synaptic circuits have not achieved this goal, then after the LIF WL high level, the power supply will continue to charge capacitor 303, and discharge the charge in capacitor 303 again when the next LIF WL high level comes. After several discharges or integrations, the goal of reducing Vout to a level lower than Vth may be achieved.

[0057] When the STDP BL is at a high level, M24 and M26 are disconnected, and M23 and M25 are turned on, respectively providing STDP WL1 and STDP WL2 to the gate and source of M22, thereby changing the threshold voltage and channel resistance of M22 and updating the weight of this electronic synaptic circuit. Of course, as described above, the arrival of the STDP BL high level may be triggered by this electronic synaptic circuit itself, or may be triggered by other electronic synaptic circuits coupled to this neuron circuit 30.

[0058] However, no matter which electronic synaptic circuit triggers it, the neuron circuit 30 will emit STDP BL, so the weights of all the previous electronic synaptic circuits coupled to it will change. Since different presynaptic neurons provide input signals at different times, when the neuron circuit 30 emits STDP BL to each previous electronic synapse, the written weights may be different, or in other words, the set values of the threshold voltage and channel resistance of the FeFET transistor may be different.

[0059] When the input signal LIF WL high level comes again, the electronic synaptic circuit 20 with updated weight will discharge the charge in capacitor 303 with the updated channel resistance.

[0060] To achieve Figure 2 the electronic synaptic properties shown, according to one embodiment, for the Figure 3A circuit shown, as Figure 3B shown, the waveforms of the input signals STDP WL1 and STDP WL2 are different, but the periods are the same.

[0061] According to one embodiment, when LIF WL is emitted or at a high level, STDP WL2 is also emitted or at a high level at the same time. After the emission of STDP WL2 or after the high level has passed, STDP WL1 is emitted or at a high level.

[0062] According to one embodiment, the falling edge of STDP WL2 basically coincides with the rising edge of STDP WL1. According to one embodiment, there is a certain time interval between the rising edge of STDP WL2 (that is, the moment when the next high level of LIF WL arrives) and the falling edge of STDP WL1.

[0063] According to one embodiment, the amplitude of the STDP WL2 high-level pulse gradually increases with time. According to one embodiment, the amplitude of the STDP WL1 high-level pulse gradually decreases with time. According to one embodiment, the maximum values of the amplitudes of the STDP WL1 and STDP WL2 high-level pulses may be the same or different.

[0064] According to one embodiment, in order to satisfy the conduction rules of M23 and M25, the amplitude of the STDP BL high-level pulse should be greater than the maximum value of the amplitudes of the STDP WL1 and STDP WL2 high-level pulses.

[0065] Figure 4 Shown is the curve of the normalized conductance of the electronic synaptic circuit according to one embodiment of the present application changing with time. As Figure 4 shown, Δt on the horizontal axis is the time difference between the time when the postsynaptic neuron emits a signal and a preset time when the postsynaptic neuron emits a signal, and ΔW on the vertical axis represents the conductivity of M22 in the electronic synaptic circuit. To make the curve more intuitive, the curve of the conductivity change is normalized with respect to Δt.

[0066] According to one embodiment, the preset time when the postsynaptic neuron emits a signal in Δt is the time from the high-level pulse of STDP BL to the position where the falling edge of STDP WL2 coincides with the rising edge of STDP WL1 (Δt can also be calculated relative to other times, but the resulting change curve will Figure 4 be different and the mechanism of the characteristic curve shown in Figure 2 cannot be achieved). If the high level of STDP BL arrives after the position where the falling edge of STDP WL2 coincides with the rising edge of STDP WL1, then Δt is positive. In this stage, STDP WL1 is positive and gradually decreases, STDP WL2 is 0, and the conductivity of M22 and the corresponding weight change rate of the electronic synapse will decrease as Δt increases (the weight change rate of the electronic synapse is positively correlated with the conductivity of M22). If the high level of STDP BL arrives before the position where the falling edge of STDP WL2 coincides with the rising edge of STDP WL1, then Δt is negative. In this stage, STDP WL1 is 0, STDP WL2 is positive and gradually increases, and the conductivity of M22 and the corresponding weight change rate of the electronic synapse will decrease as Δt increases. The magnitude of the conductance change of M22 is affected by the maximum amplitude of the high level of STDP WL2.

[0067] Of course, according to the STDP mechanism curves of different electronic synapses, different input and control signals can also be used.

[0068] In the solution of this application, the memory characteristics and non-volatile characteristics of FeFET are utilized and applied to electronic synapses. By adjusting the voltage value applied to the gate of FeFET, the threshold voltage and channel resistance of FeFET are set, thereby setting specific weight values of the synapses, which can simplify the circuit design to a certain extent while realizing the functions of multiple components. At the same time, due to its advantages of low power consumption and high operating speed, the power consumption of the circuit and equipment can be further reduced, and the operating efficiency can be improved. Applying it to the network design of neuromorphic computing can achieve low-power and high-computation-performance neuromorphic computing.

[0069] During the calculation and optimization process, the circuit does not need to store the calculated weight values and intermediate values of other input signals, nor does it need to call the intermediate values again before the next calculation, reducing the number of times of using the circuit, improving the calculation speed, and reducing the circuit power consumption.

[0070] The above embodiments are only for illustrating this application and are not intended to limit this application. Those of ordinary skill in the relevant technical fields can make various changes and modifications without departing from the scope of this application. Therefore, all equivalent technical solutions should also fall within the scope of the disclosure of this application.

Claims

1. A neural network circuit, characterized in that, Comprising: A plurality of neuron circuits, and a plurality of electronic synaptic circuits, wherein at least one of the electronic synaptic circuits is configured to receive an input and a control signal from a presynaptic neuron circuit, and receive a feedback signal from a postsynaptic neuron circuit; Wherein, the electronic synaptic circuit at least comprises: A switch unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to control the connection state between the electronic synaptic circuit and the postsynaptic neuron circuit under the influence of a control signal from the presynaptic neuron circuit; An input unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to receive first and second input signals from the presynaptic neuron circuit under the control of a feedback signal from the postsynaptic neuron circuit; A weight calculation unit, coupled between the switch unit and ground, and coupled to the input unit, the weight calculation unit at least comprises a ferroelectric transistor, the ferroelectric transistor is configured to receive the first and second input signals from the input unit to update the channel resistance of the ferroelectric transistor.

2. The neural network circuit according to claim 1, characterized in that, The postsynaptic neuron circuit at least comprises: A comparator, whose positive input terminal is coupled to the switch unit of the electronic synaptic circuit, the negative input terminal of the comparator is configured to receive a preset constant signal, and the output terminal of the comparator is coupled to the input unit of the electronic synaptic circuit; A resistor, coupled between the positive input terminal of the comparator and the power supply; A capacitor, coupled between the positive input terminal of the comparator and ground; When the switch unit connects the postsynaptic neuron circuit to the electronic synaptic circuit, and the ferroelectric transistor is turned on, the voltage at the positive input terminal of the comparator drops, and when this voltage drops below the preset constant signal, the comparator is configured to output the feedback signal.

3. The neural network circuit according to claim 2, characterized in that, The switch unit at least comprises a first transistor, whose control electrode is configured to receive the control signal, whose first pole is coupled to the positive input terminal of the comparator, and whose second pole is coupled to the first pole of the ferroelectric transistor.

4. The neural network circuit according to claim 3, characterized in that, The input unit at least comprises, A second transistor, whose control electrode is configured to receive the feedback signal, whose first pole is configured to receive the first input signal, and whose second pole is coupled to the control electrode of the ferroelectric transistor; A third transistor, having a type complementary to that of the second transistor, whose control electrode is configured to receive the feedback signal, whose first pole is grounded, and whose second pole is coupled to the control electrode of the ferroelectric transistor; A fourth transistor, whose control electrode is configured to receive the feedback signal, whose first pole is configured to receive the second input signal, and whose second pole is coupled to the second pole of the ferroelectric transistor; A fifth transistor, having a type complementary to that of the fourth transistor, whose control electrode is configured to receive the feedback signal, whose first pole is grounded, and whose second pole is coupled to the second pole of the ferroelectric transistor.

5. The neural network circuit according to any one of claims 2-4, characterized in that, The postsynaptic neuron circuit further comprises a delay unit, coupled between the output terminal of the comparator and the input terminal of the input unit, configured to generate a time interval between the effective levels of the control signal and the feedback signal.

6. The neural network circuit according to any one of claims 1-4, characterized in that, The control electrode of the ferroelectric transistor is configured to receive the first input signal, and the second electrode of the ferroelectric transistor is configured to receive the second input signal; The control signal and the second input signal simultaneously transition to the active level, and the first input signal generates an active level when the active level of the second input signal transitions to the inactive level; The active level of the second input signal gradually increases during one pulse, and the active level of the first input signal gradually decreases during one pulse.

7. The neural network circuit according to claim 6, characterized in that, The amplitude of the active level of the feedback signal is greater than the maximum amplitude of the active level of the first or second input signal.

8. An electronic synaptic circuit, characterized in that, Configured to receive an input and a control signal from a presynaptic neuron circuit and receive a feedback signal from a postsynaptic neuron circuit; Wherein, the electronic synapse circuit at least includes: A switch unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to control the connection state between the electronic synapse circuit and the postsynaptic neuron circuit under the influence of a control signal from the presynaptic neuron circuit; An input unit, coupled to the presynaptic neuron circuit and the postsynaptic neuron circuit, configured to receive the first and second input signals from the presynaptic neuron circuit under the control of a feedback signal from the postsynaptic neuron circuit; A weight calculation unit, coupled between the switch unit and ground and coupled to the input unit, the weight calculation unit at least includes a ferroelectric transistor, and the ferroelectric transistor is configured to receive the first and second input signals from the input unit to update the channel resistance of the ferroelectric transistor.

9. The electronic synaptic circuit according to claim 8, characterized in that, The switch unit at least includes a first transistor, whose control electrode is configured to receive the control signal, whose first electrode is coupled to the postsynaptic neuron circuit, and whose second electrode is coupled to the first electrode of the ferroelectric transistor.

10. The electronic synaptic circuit according to claim 9, characterized in that, The input unit at least includes, A second transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is configured to receive the first input signal, and whose second electrode is coupled to the control electrode of the ferroelectric transistor; A third transistor, having a type complementary to that of the second transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is grounded, and whose second electrode is coupled to the control electrode of the ferroelectric transistor; A fourth transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is configured to receive the second input signal, and whose second electrode is coupled to the second electrode of the ferroelectric transistor; A fifth transistor, having a type complementary to that of the fourth transistor, whose control electrode is configured to receive the feedback signal, whose first electrode is grounded, and whose second electrode is coupled to the second electrode of the ferroelectric transistor.

11. The electronic synapse circuit according to any one of claims 8 - 10, characterized in that, The control electrode of the ferroelectric transistor is configured to receive the first input signal, and the second electrode of the ferroelectric transistor is configured to receive the second input signal; The control signal and the second input signal simultaneously transition to the active level, and the first input signal generates an active level when the active level of the second input signal transitions to the inactive level; The active level of the second input signal gradually increases during one pulse, and the active level of the first input signal gradually decreases during one pulse.

12. The electronic synapse circuit according to claim 11, characterized in that, The effective level amplitude of the feedback signal is greater than the maximum amplitude of the effective level of the first or second input signal.

13. An electronic system, characterized in that, Comprising the neural network circuit according to any one of claims 1-7.

14. An electronic device, characterized in that, Comprising the neural network circuit according to any one of claims 1-7.

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