A design method for neural networks and related devices

Abstract

This invention provides a method and related apparatus for designing a neural network. The method includes: obtaining necessary bit data from a bitstream file of an initial neural network to obtain a set of necessary bit data; the necessary bit data is configuration memory data that affects the performance of the initial neural network; flipping each necessary bit data in the set of necessary bit data to obtain updated necessary bit data, and obtaining an updated bitstream file based on the updated necessary bit data; and obtaining a final neural network based on the updated bitstream file. The neural network designed by this method has high accuracy.

Description

Technical Field

[0001] This invention belongs to the field of artificial intelligence, and in particular relates to a design method for neural networks and related devices. Background Technology

[0002] When high-energy particles are incident on SRAM-type FPGAs, they can cause soft errors such as single-event upsets (SEEs) in the internal memory cells. This is especially true as semiconductor manufacturing processes shrink, making SEE events more frequent. Furthermore, with the increasing application of advanced SRAM-type FPGAs in artificial intelligence and neural networks, the impact of SEEs on SRAM-type FPGAs requires close attention. Generally, SEEs are considered to primarily cause errors in computation results, operational halts, and performance degradation in SRAM-type FPGA applications, negatively affecting the system and impacting the accuracy of neural networks. Summary of the Invention

[0003] This application provides a method for designing neural networks and related apparatus, wherein the neural networks designed by this method have high accuracy.

[0004] In a first aspect, the present invention provides a method for designing a neural network, comprising: obtaining necessary bit data from a bitstream file of an initial neural network to obtain a set of necessary bit data; the necessary bit data being configuration memory data that affects the performance of the initial neural network; flipping each of the necessary bit data in the set of necessary bit data to obtain updated necessary bit data, and obtaining an updated bitstream file based on the updated necessary bit data; and obtaining a final neural network based on the updated bitstream file.

[0005] The step of flipping each necessary bit in the necessary bit data set to obtain updated necessary bit data, and obtaining an updated bitstream file based on the updated necessary bit data, includes: flipping each necessary bit in the necessary bit data set one by one to obtain updated necessary bit data, and obtaining an updated bitstream file based on the updated necessary bit data one by one.

[0006] The step of flipping each necessary bit in the necessary bit data set to obtain updated necessary bit data, and obtaining an updated bitstream file based on the updated necessary bit data, includes: flipping the first necessary bit in the necessary bit data set to obtain the first updated necessary bit data; replacing the first necessary bit data with the first updated necessary bit data to obtain the first updated bitstream file; flipping the second necessary bit in the necessary bit data set to obtain the second updated necessary bit data; replacing the second necessary bit data with the second updated necessary bit data to obtain the second updated bitstream file; flipping the Nth necessary bit in the necessary bit data set, loading the bitstream file containing the flipped necessary bits and running a neural network, and obtaining the Nth updated necessary bit data based on the neural network running result; wherein N is greater than or equal to 1 and less than or equal to the total number of bits in the bitstream file; replacing the Nth necessary bit data with the Nth updated necessary bit data to obtain the Nth updated bitstream file.

[0007] The step of obtaining the final neural network based on the updated bitstream file includes: loading the first updated bitstream file in the same system to obtain the first sub-neural network, running the first sub-neural network, obtaining the accuracy of the first sub-neural network, loading the second updated bitstream file to obtain the second sub-neural network, running the second sub-neural network, obtaining the accuracy of the second sub-neural network, loading the Nth updated bitstream file to obtain the Nth sub-neural network, running the Nth sub-neural network, obtaining the accuracy of the Nth sub-neural network, and finally obtaining N sub-neural networks in sequence, and obtaining the accuracy of the N sub-neural networks; obtaining the final neural network based on the accuracy of the N sub-neural networks and the accuracy of the initial neural network.

[0008] The step of obtaining the accuracy of each of the N sub-neural networks includes: processing the same set of test datasets using the N sub-neural networks respectively to obtain processing results; analyzing the accuracy of the processing results to obtain the number of processing results with an accuracy less than a first threshold; and determining the accuracy of the sub-neural network based on the number of test data in the test dataset and the number of processing results with an accuracy less than the first threshold.

[0009] The method further includes: processing the dataset to be tested using the initial neural network to obtain processing results; analyzing the accuracy of the processing results to obtain the number of processing results with an accuracy less than a second threshold; and determining the accuracy of the initial neural network based on the number of data to be tested in the dataset to be tested and the number of processing results with an accuracy less than the second threshold.

[0010] The step of obtaining the final neural network based on the accuracy of the N sub-neural networks and the accuracy of the initial neural network includes: comparing the accuracy of the N sub-neural networks with the accuracy of the initial neural network, and determining the sub-neural networks whose accuracy is greater than or equal to the accuracy of the initial neural network as selected sub-neural networks; recording the necessary update bit data in the selected sub-neural networks, and using the necessary update bit data in the selected sub-neural networks to replace the corresponding necessary bit data in the bitstream file of the initial neural network to obtain the final bitstream file; and obtaining the final neural network based on the final bitstream file.

[0011] Secondly, the present invention also provides a neural network design apparatus, comprising: an acquisition module, configured to acquire necessary bit data from a bitstream file of an initial neural network to obtain a set of necessary bit data; wherein the necessary bit data is data that affects the performance of the initial neural network; a flipping module, configured to flip each of the necessary bit data in the set of necessary bit data to obtain updated necessary bit data, and to obtain an updated bitstream file based on the updated necessary bit data; and a neural network determination module, configured to obtain a final neural network based on the updated bitstream file.

[0012] Thirdly, the present invention also provides an electronic device, including a hardware processor and a memory coupled together, wherein the memory is used to store a bitstream file implementing the method described in any of the preceding claims; and the hardware processor is used to execute the bitstream file stored in the memory.

[0013] Fourthly, the present invention also provides a computer-readable storage medium storing a bitstream file, the bitstream file being executable to implement the method described in any of the preceding claims.

[0014] The beneficial effects of this invention, which differ from the prior art, include the following: The neural network design method of this invention includes:

[0015] Necessary bit data is obtained from the bitstream file of the initial neural network to obtain a necessary bit data set; the necessary bit data is configuration memory data that affects the performance of the initial neural network; each necessary bit data in the necessary bit data set is flipped to obtain updated necessary bit data, and an updated bitstream file is obtained based on the updated necessary bit data; the final neural network is obtained based on the updated bitstream file. The neural network designed by this method has high accuracy.

[0016] Other aspects and features of the invention will become apparent from the following detailed description with reference to the accompanying drawings. However, it should be understood that the drawings are for illustrative purposes only and not as a limitation of the scope of the invention, as reference should be made to the appended claims. It should also be understood that, unless otherwise indicated, the drawings are not necessarily drawn to scale; they are merely intended to conceptually illustrate the structures and processes described herein. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating an embodiment of the neural network design method of the present invention;

[0018] Figure 2 A schematic diagram of an embodiment of a necessary bit file;

[0019] Figure 3 A schematic diagram of one embodiment of a necessary bit data file;

[0020] Figure 4 A schematic diagram of an embodiment of injecting scripts for necessary bit position faults;

[0021] Figure 5 This is a flowchart illustrating an embodiment of the neural network design device of the present invention;

[0022] Figure 6 This is a schematic diagram of the structure of an embodiment of the electronic device of the present invention;

[0023] Figure 7 This is a schematic diagram of an embodiment of the computer-readable storage medium of the present invention. Detailed Implementation

[0024] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of the specific embodiments with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0025] When high-energy particles are incident on SRAM-type FPGAs, they can cause soft errors such as single-event upsets (SEEs) in the internal memory cells. This is especially true as semiconductor manufacturing processes shrink, making SEEs more prevalent. With the increasing application of advanced SRAM-type FPGAs in artificial intelligence and neural networks, the impact of SEEs on SRAM-type FPGAs requires close attention. Generally, SEEs are considered to primarily cause negative consequences for SRAM-type FPGA applications, such as incorrect calculation results, runtime termination, and performance degradation. Previous research has mainly focused on how to efficiently and accurately measure the SEE cross-section caused by different particle incident particles, or how to mitigate the SEE effect. It has neglected the potential positive impacts of some SEEs on SRAM-type FPGA applications, such as improved performance and reduced power consumption. Furthermore, it has not addressed how to improve the performance of SRAM-type FPGA applications based on SEEs. As neural network implementations on SRAM-type FPGAs become more advanced, the impact of SEEs on neural network implementations on SRAM-type FPGAs is also attracting attention. If we continue not to classify and utilize the effects of single-event upsets, but instead process all single-event upsets that affect the design of neural networks on SRAM-type FPGAs, the workload of single-event upset processing will be significantly increased. This will not only affect design performance but also miss the opportunity to make reasonable use of single-event upsets to improve the recognition accuracy of neural networks on SRAM-type FPGAs.

[0026] In particular, SRAM-type FPGAs have reconfigurable features, which allow the configuration memory to be configured multiple times. This greatly facilitates the refinement of the single-event flip effect of the configuration memory and provides a foundation for improving the recognition accuracy of neural network designs on SRAM-type FPGAs based on single-event flips.

[0027] To address the aforementioned realities and problems, this invention proposes a neural network design method that runs on an SRAM-type FPGA. This method achieves improved recognition accuracy of the neural network on the SRAM-type FPGA without requiring complex algorithm design; it only requires flipping necessary bits with a positive impact on the SRAM-type FPGA configuration memory. Furthermore, by comparing and analyzing the changes in recognition accuracy before and after a single-event upset (SE) event, precise classification and identification of SE events on the SRAM-type FPGA can be achieved. Specifically, it clarifies which necessary bits undergoing an SE event will lead to a decrease in recognition accuracy and which will improve it. This application will be further described in conjunction with the accompanying drawings and specific embodiments.

[0028] Please see Figure 1 This is a flowchart illustrating the first embodiment of the neural network design method of the present invention, specifically including:

[0029] Step S11: Obtain necessary bit data from the bitstream file of the initial neural network to obtain a set of necessary bit data; the necessary bit data is configuration memory data that affects the performance of the initial neural network.

[0030] Specifically, the neural network in this application runs on an SRAM-type FPGA. After training the initial neural network using a training sample set, its original bitstream file can be generated. Necessary bit data is selected from the original bitstream file to obtain a set of necessary bit data. It should be noted that this necessary bit data refers to configuration memory data that affects the performance of the initial neural network, and the location of this necessary bit data is considered a fault injection location.

[0031] Please combine Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of the necessary bits in a bitstream file. The position of a "1" in each line indicates that the bit is necessary. Figure 3 The data at the corresponding position is the required bit data. Required bit data can be either "0" or "1". For example... Figure 3 The “1” circled in line 1609 and the “0” circled in line 1610 are both necessary bits.

[0032] Step S12: Flip each of the necessary bits in the necessary bit data set to obtain updated necessary bit data, and obtain an updated bit stream file based on the updated necessary bit data.

[0033] Specifically, the necessary bit position data is subjected to a single-particle flip based on its offset position. It should be noted that in the configuration memory, data is stored in the form of "0"s and "1"s. If the current necessary bit data is "1", flipping it yields an updated necessary bit data of "0"; if the current necessary bit data is "0", flipping it inversely yields an updated necessary bit data of "1". After flipping the target necessary bit position data, the updated necessary bit data is obtained, and the updated bitstream file is generated based on this updated necessary bit data.

[0034] In the first embodiment, a fault injection script is first created based on the necessary bit position data. Please refer to... Figure 4 This is a schematic diagram of a first embodiment of the fault injection script, including the offset Word position and the offset Bit position for fault injection. The necessary bit data is found based on the fault injection script, and then the necessary bit data is flipped.

[0035] In one embodiment of this application, each necessary bit data in the necessary bit data set is flipped one by one to obtain updated necessary bit data, and an updated bit stream file is obtained one by one based on the updated necessary bit data.

[0036] Specifically, the first necessary bit data in the necessary bit data set is flipped to obtain the first updated necessary bit data; the first updated necessary bit data is used to replace the first necessary bit data to obtain the first updated bit stream file.

[0037] The second necessary bit data in the necessary bit data set is flipped to obtain the second updated necessary bit data; the second updated necessary bit data is used to replace the second necessary bit data to obtain the second updated bit stream file.

[0038] The Nth necessary bit in the necessary bit data set is flipped to obtain the Nth updated necessary bit data; wherein N is greater than or equal to 1 and less than or equal to the total number of bits in the bitstream file; the Nth necessary bit data is replaced with the Nth updated necessary bit data to obtain the Nth updated bitstream file.

[0039] If there are 3 necessary bits in the necessary bit data set, then 3 updated bit stream files will be obtained.

[0040] Step S13: Obtain the final neural network based on the updated bitstream file.

[0041] The process involves loading the first updated bitstream file, running the first sub-neural network, obtaining the accuracy of the first sub-neural network, loading the second updated bitstream file, obtaining the second sub-neural network, running the second sub-neural network, obtaining the accuracy of the second sub-neural network, loading the third updated bitstream file, obtaining the third sub-neural network, running the third sub-neural network, obtaining the accuracy of the third sub-neural network, and finally obtaining three sub-neural networks in succession, and obtaining the accuracy of the three sub-neural networks.

[0042] It should be noted that each sub-neural network updates only a single necessary bit data compared to the initial neural network. This means that if the initial neural network has N necessary bits data, then each of these N necessary bits data is flipped, and a sub-neural network is generated for each sub-neural network, resulting in a total of N sub-neural networks.

[0043] After obtaining N sub-neural networks, each of the N sub-neural networks is run, and the accuracy of each of the N sub-neural networks is obtained; the final neural network is obtained based on the accuracy of the N sub-neural networks and the accuracy of the initial neural network.

[0044] Specifically, in one embodiment, the same set of test datasets is processed using N sub-neural networks to obtain processing results; the accuracy of the processing results is analyzed to obtain the number of processing results with an accuracy less than a first threshold; the accuracy of the sub-neural networks is determined based on the number of test data in the test dataset and the number of processing results with an accuracy less than the first threshold.

[0045] In one embodiment, the accuracy of the sub-neural network can be calculated using the following formula:

[0046] σ=(Mm) / M;

[0047] Where M is the number of test data in the test dataset, and m is the number of processing results with an accuracy less than the first threshold.

[0048] Assuming the total amount of data to be tested in the dataset is 6, the dataset is processed using N sub-neural networks to obtain the processing results. Specifically, let the first sub-neural network process the dataset to obtain the processing results (A11, A12, ..., A16), the second sub-neural network process the dataset to obtain the processing results (A21, A22, ..., A26), and the Nth sub-neural network process the dataset to obtain the processing results (AN1, AN2, ..., AN6).

[0049] Analyze the accuracy of the processing results (A11, A12, ..., A16) of the first sub-neural network and obtain the number of processing results with an accuracy less than a first threshold. The first threshold can be customized, for example, it can be defined as 80%, 90%, 95%, etc., without specific limitations. Assuming that the accuracy of processing results A11, A13, and A15 is less than the first threshold, then the number of processing results with an accuracy less than the first threshold is 3, and the accuracy of the first sub-neural network is (6-3) / 6 = 0.5. Analyze the accuracy of the processing results (A21, A22, ..., A26) of the second sub-neural network and obtain the number of processing results with an accuracy less than the first threshold. Assuming that the accuracy of processing results A21 and A23 is less than the first threshold, then the number of processing results with an accuracy less than the first threshold is 2, and the accuracy of the second sub-neural network is (6-2) / 6 = 0.67. Analyze the accuracy of the processing results (AN1, AN2, ..., AN6) of the Nth sub-neural network and obtain the number of processing results with an accuracy less than the first threshold. Assuming that the accuracy of processing results AN1, AN3, AN5, and AN4 is less than the first threshold, then the number of processing results with an accuracy less than the first threshold is 4. Therefore, the accuracy of the Nth sub-neural network is (6-4) / 6 = 0.33.

[0050] Furthermore, this application also needs to determine the accuracy of the initial neural network. Specifically, the initial neural network is used to process the dataset to be tested to obtain processing results; the accuracy of the processing results is analyzed to obtain the number of processing results with an accuracy less than a second threshold; the accuracy of the initial neural network is determined based on the number of data to be tested in the dataset to be tested and the number of processing results with an accuracy less than the second threshold.

[0051] Assuming the number of processing results with an accuracy less than the second threshold is 3, then the accuracy of the initial neural network is (6-3) / 6 = 0.5. It should be noted that the second threshold can be the same as or different from the first threshold, depending on the actual needs.

[0052] The accuracy of the N sub-neural networks is compared with the accuracy of the initial neural network. Sub-neural networks with an accuracy greater than or equal to that of the initial neural network are selected as the chosen sub-neural networks. The necessary bit data for updating in the selected sub-neural networks is recorded. The necessary bit data for updating in the selected sub-neural networks is used to replace the corresponding necessary bit data in the bitstream file of the initial neural network to obtain the final bitstream file. The final neural network is obtained based on the final bitstream file.

[0053] Continuing with the example above, the accuracy of the initial neural network is 0.5; the accuracy of the first sub-neural network is 0.5, the accuracy of the second sub-neural network is 0.67, and the accuracy of the Nth sub-neural network is 0.33. Assuming N is 3, the accuracy of the third sub-neural network is 0.33. Since the accuracy of the first and second sub-neural networks is greater than or equal to the accuracy of the initial neural network, the first and second sub-neural networks are selected as the chosen sub-neural networks.

[0054] Record the necessary bit data for updating obtained after flipping in the first and second sub-neural networks, specifically recording the position of the necessary bit data for updating. At the same time, use the first and second sub-neural networks to replace the corresponding necessary bit data in the bitstream file of the initial neural network to obtain the final bitstream file. Store the final bitstream file in the configuration memory. Loading the final bitstream file will obtain the final neural network.

[0055] The neural network design method of this application realizes a fine classification of single-event flips (SETs) in the configuration memory of SRAM-type FPGAs, and clarifies which SETs can reduce the recognition accuracy of neural networks on SRAM-type FPGAs and which SETs can improve the recognition accuracy of neural networks on SRAM-type FPGAs. It effectively utilizes the SETs that can improve the recognition accuracy of neural networks on SRAM-type FPGAs, and conveniently improves the recognition accuracy of neural networks on SRAM-type FPGAs. It also reduces the workload of SRAM-type FPGAs in processing configuration memory SETs.

[0056] The SRAM-type FPGA involved in this invention can be of different types and can load bitstream files multiple times.

[0057] Please see Figure 5 This is a schematic diagram of the structure of an embodiment of the neural network design device of the present invention, specifically including: an acquisition module 41, a flipping module 42, and a neural network determination module 43.

[0058] The acquisition module 41 is used to acquire necessary bit data from the bit stream file of the initial neural network to obtain a set of necessary bit data; the necessary bit data is data that affects the performance of the initial neural network.

[0059] The flipping module 42 is used to flip each of the necessary bit data in the necessary bit data set to obtain updated necessary bit data, and to obtain an updated bit stream file based on the updated necessary bit data.

[0060] In one embodiment, the flipping module 42 is used to flip each of the necessary bit data in the necessary bit data set one by one to obtain updated necessary bit data, and to obtain an updated bit stream file based on the updated necessary bit data one by one.

[0061] Specifically, the flipping module 42 is used to flip the first necessary bit data in the necessary bit data set to obtain the first updated necessary bit data; replace the first necessary bit data with the first updated necessary bit data to obtain the first updated bit stream file; flip the second necessary bit data in the necessary bit data set to obtain the second updated necessary bit data; replace the second necessary bit data with the second updated necessary bit data to obtain the second updated bit stream file; flip the Nth necessary bit data in the necessary bit data set to obtain the Nth updated necessary bit data; wherein N is greater than or equal to 1 and less than or equal to the total number of bits in the bit stream file; replace the Nth necessary bit data with the Nth updated necessary bit data to obtain the Nth updated bit stream file.

[0062] The neural network determination module 43 is used to obtain the final neural network based on the updated bitstream file.

[0063] In one embodiment, the neural network determination module 43 is used to load and run the first updated bitstream file, the second updated bitstream file, and the Nth updated bitstream file one by one to obtain N sub-neural networks; obtain the accuracy of each of the N sub-neural networks; and obtain the final neural network based on the accuracy of the N sub-neural networks and the accuracy of the initial neural network.

[0064] In one embodiment, the neural network determination module 43 is used to process the dataset to be tested using N sub-neural networks respectively to obtain processing results; analyze the accuracy of the processing results to obtain the number of processing results with an accuracy less than a first threshold; and determine the accuracy of the sub-neural network based on the number of data to be tested in the dataset to be tested and the number of processing results with an accuracy less than the first threshold.

[0065] In one embodiment, the neural network determination module 43 is used to process the dataset to be tested using the initial neural network to obtain a processing result; analyze the accuracy of the processing result to obtain the number of processing results with an accuracy less than a second threshold; and determine the accuracy of the initial neural network based on the number of data to be tested in the dataset to be tested and the number of processing results with an accuracy less than the second threshold.

[0066] In one embodiment, the neural network determination module 43 is used to compare the accuracy of the N sub-neural networks with the accuracy of the initial neural network, determine the sub-neural networks whose accuracy is greater than or equal to the accuracy of the initial neural network as selected sub-neural networks; record the update necessary bit data in the selected sub-neural networks, use the update necessary bit data in the selected sub-neural networks to replace the corresponding necessary bit data in the bitstream file of the initial neural network to obtain the final bitstream file; and obtain the final neural network based on the final bitstream file.

[0067] Please see Figure 6 This is a schematic diagram of an embodiment of the electronic device of the present invention. The electronic device includes a memory 82 and a hardware processor 81 that are interconnected.

[0068] The memory 82 is used to store bitstream files that implement any of the above methods.

[0069] Hardware processor 81 is used to execute bitstream files stored in memory 82.

[0070] The hardware processor 81 can also be referred to as a CPU (Central Processing Unit). The hardware processor 81 may be an integrated circuit chip with signal processing capabilities. The hardware processor 81 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor.

[0071] The memory module 82 can be a RAM stick, TF card, etc., and can store all information in the electronic device, including raw input data, computer programs, intermediate running results, and final running results. It stores and retrieves information according to the location specified by the controller. With memory, the electronic device has a memory function and can ensure normal operation. According to their purpose, the memory of an electronic device can be divided into main memory (RAM) and auxiliary memory (external storage), or it can be classified as external memory and internal memory. External storage is usually magnetic media or optical discs, which can store information for a long time. RAM refers to the storage components on the motherboard, used to store currently executing data and programs, but it is only used for temporary storage of programs and data; the data will be lost when the power is turned off.

[0072] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented by other methods. For example, the apparatus implementation methods described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0073] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this implementation method according to actual needs.

[0074] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0075] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a system server, or a network device, etc.) or a processor to execute all or part of the steps of the various embodiments of this application.

[0076] Please see Figure 7 This is a schematic diagram of the structure of the computer-readable storage medium of the present invention. The storage medium of this application stores a bitstream file 91 capable of implementing all the above methods. This bitstream file 91 can be stored in the storage medium in the form of a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of each embodiment of the present application. The aforementioned storage devices include various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, or terminal devices such as computers, servers, mobile phones, and tablets.

[0077] The above are merely implementation methods of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for designing a neural network, wherein the neural network runs on an SRAM-type FPGA, characterized in that, include: Obtain the necessary bit data from the bitstream file of the initial neural network to obtain the necessary bit data set; The necessary bit data is configuration memory data that affects the performance of the initial neural network, and the location of the necessary bit data is considered to be the fault injection location; Each necessary bit in the necessary bit data set is flipped to obtain updated necessary bit data, and an updated bit stream file is obtained based on the updated necessary bit data; The final neural network is obtained based on the updated bitstream file, which realizes a refined classification of single-particle flips of SRAM-type FPGA configuration memory. Specifically, the necessary bit data in the necessary bit data set is flipped to obtain updated necessary bit data, and an updated bitstream file is obtained based on the updated necessary bit data. Finally, the final neural network is obtained based on the updated bitstream file. The first necessary bit in the necessary bit data set is flipped to obtain the first updated necessary bit data; the first updated necessary bit data is used to replace the first necessary bit data to obtain the first updated bitstream file; the Nth necessary bit in the necessary bit data set is flipped to obtain the Nth updated necessary bit data; wherein N is greater than or equal to 1 and less than or equal to the total number of bits in the bitstream file; the Nth updated necessary bit data is used to replace the Nth necessary bit data to obtain the Nth updated bitstream file; if the initial neural network has N necessary bit data, then each of the N necessary bit data is flipped, and a sub-neural network is generated respectively. The number of sub-neural networks is N. After obtaining N sub-neural networks, each of the N sub-neural networks is run, and the accuracy of each of the N sub-neural networks is obtained. The accuracy of the initial neural network is determined, and the accuracy of the N sub-neural networks is compared with the accuracy of the initial neural network. The sub-neural networks whose accuracy is greater than or equal to the accuracy of the initial neural network are selected as the selected sub-neural networks. The necessary bit data for updating in the selected sub-neural networks is recorded, and the necessary bit data in the bitstream file of the initial neural network is replaced using the necessary bit data for updating in the selected sub-neural networks to obtain the final bitstream file. The final neural network is obtained based on the final bitstream file.

2. The method according to claim 1, characterized in that, The step of obtaining the accuracy of the N sub-neural networks includes: The same set of test datasets is processed using N sub-neural networks respectively to obtain the processing results; Analyze the accuracy of the processing results and obtain the number of processing results with an accuracy less than a first threshold; The accuracy of the sub-neural network is determined based on the number of test data in the test dataset and the number of processing results with an accuracy less than the first threshold.

3. The method according to claim 1, characterized in that, The method further includes: The initial neural network is used to process the dataset to be tested to obtain the processing result; Analyze the accuracy of the processing results and obtain the number of processing results with an accuracy less than the second threshold; The accuracy of the initial neural network is determined based on the number of test data in the test dataset and the number of processing results with an accuracy less than the second threshold.

4. A neural network design device, wherein the neural network runs on an SRAM-type FPGA, characterized in that, include: The acquisition module is used to obtain the necessary bit data from the bitstream file of the initial neural network, and obtain the necessary bit data set; The necessary bit data is configuration memory data that affects the performance of the initial neural network, and the location of the necessary bit data is considered to be the fault injection location; The flipping module is used to flip each of the necessary bit data in the necessary bit data set to obtain updated necessary bit data, and to obtain an updated bit stream file based on the updated necessary bit data; The neural network determination module is used to obtain the final neural network based on the updated bitstream file, and realizes the fine classification of single-particle flips of SRAM-type FPGA configuration memory; Specifically, the necessary bit data in the necessary bit data set is flipped to obtain updated necessary bit data, and an updated bitstream file is obtained based on the updated necessary bit data. Finally, the final neural network is obtained based on the updated bitstream file. The first necessary bit in the necessary bit data set is flipped to obtain the first updated necessary bit data; the first updated necessary bit data is used to replace the first necessary bit data to obtain the first updated bitstream file; the Nth necessary bit in the necessary bit data set is flipped to obtain the Nth updated necessary bit data; wherein N is greater than or equal to 1 and less than or equal to the total number of bits in the bitstream file; the Nth updated necessary bit data is used to replace the Nth necessary bit data to obtain the Nth updated bitstream file; if the initial neural network has N necessary bit data, then each of the N necessary bit data is flipped, and a sub-neural network is generated respectively. The number of sub-neural networks is N. After obtaining N sub-neural networks, each of the N sub-neural networks is run, and the accuracy of each of the N sub-neural networks is obtained. The accuracy of the initial neural network is determined, and the accuracy of the N sub-neural networks is compared with the accuracy of the initial neural network. The sub-neural networks whose accuracy is greater than or equal to the accuracy of the initial neural network are selected as the selected sub-neural networks. The necessary bit data for updating in the selected sub-neural networks is recorded, and the necessary bit data in the bitstream file of the initial neural network is replaced using the necessary bit data for updating in the selected sub-neural networks to obtain the final bitstream file. The final neural network is obtained based on the final bitstream file.

5. An electronic device, characterized in that, This includes interconnected hardware processors and memory, among which, The memory is used to store bitstream files that implement the method as described in any one of claims 1-3; The hardware processor is used to execute the bitstream file stored in the memory.

6. A computer-readable storage medium, characterized in that, A bitstream file is stored, which can be executed to implement the method as described in any one of claims 1-3.

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