Port Testing System

Abstract

The present application provides a port testing system. The port testing system includes: a standard signal generator including a first output end and a second output end; a control unit including a first relay, at least one second relay, a plurality of third relays, and a processor module. The processor module includes a plurality of IO interfaces, which are respectively communicatively connected to the first relay, the second relay, and the third relay in a one-to-one correspondence; the device under test includes a plurality of test ports and a control port, and the plurality of test ports are respectively communicatively connected to the output ends of the plurality of third relays in a one-to-one correspondence. The testing system controls the closing and opening of the first relay, the second relay, and the third relay through the processor module in the control unit, so that any test port can be tested without manual operation, thereby solving the problem of low efficiency in the consistency testing of DisplayPort ports in the prior art.

Description

Technical Field

[0001] This application relates to the field of automatic detection and control, and more particularly, to a port test system. Background Art

[0002] When performing compliance tests on current DisplayPort (display interface) ports, after each physical channel is tested, the SMA cable (Sub Miniature version A, radio frequency coaxial) connected to the channel under test needs to be manually removed, and then the SMA cable is connected to the next physical channel under test. At the same time, the interconnection relationship of three crosstalk channels also needs to be adjusted. Changing the SMA cable during the test process takes a lot of time. Repeatedly changing the SMA cable will additionally increase the risk caused by improper human operation. For example, when changing the SMA cable, it is possible that one of the channels is not firmly installed, resulting in unreliable test results. Frequent removal / installation of the SMA cable will also shorten the service life of the SMA connector and may also affect the true test results.

[0003] Therefore, there is an urgent need for a method to improve the efficiency of DisplayPort port compliance testing.

[0004] The above information disclosed in the background art section is only used to enhance the understanding of the background art of the technology described in this article. Therefore, the background art may contain certain information that is not prior art known to those skilled in the art in this country. Summary of the Invention

[0005] The main object of this application is to provide a port test system to solve the problem of low efficiency in DisplayPort port compliance testing in the prior art.

[0006] To achieve the above object, according to one aspect of the present application, a port test system is provided, including: a standard signal generator, a control unit, and a device under test. Among them, the standard signal generator includes a first output terminal and a second output terminal, and the standard signal generator is used to output test signals; the control unit includes a first relay, at least one second relay, a plurality of third relays, and a processor module. The input terminal of the first relay is communicatively connected to the first output terminal of the standard signal generator, the output terminal of the first relay is electrically connected to the input terminals of at least one of the second relays, the output terminal of each second relay is electrically connected to a part of the input terminals of at least one of the third relays, the other part of the input terminals of each third relay is communicatively connected to the second output terminal of the standard signal generator, and the processor module includes a plurality of IO interfaces, which are respectively communicatively connected to the first relay, the second relay, and the third relay in one-to-one correspondence. The processor module is used to control the closing and opening of the relays so that any one of the third relays is connected to the first output terminal of the standard signal generator; the device under test includes a plurality of test ports and a control port, and the plurality of test ports are communicatively connected to the output terminals of the plurality of third relays in one-to-one correspondence, and the control port is communicatively connected to the output terminal of the processor module.

[0007] Further, when the first relay is electrically connected to two of the second relays, a part of the output terminals of the first relay is electrically connected to the input terminals of one of the second relays, and the other part of the output terminals of the first relay is electrically connected to the input terminals of the other second relay. The first relay is used to communicate with one of the two second relays during testing.

[0008] Further, when each second relay is electrically connected to two of the third relays, a part of the output terminals of one second relay is electrically connected to a part of the input terminals of one of the third relays, and the other part of the output terminals of the second relay is electrically connected to a part of the input terminals of the other third relay. The second relay is used to communicate with one of the two third relays during testing.

[0009] Further, the test system further includes: a controller, communicatively connected to the input terminal of the processor module, for determining the test port to be tested.

[0010] Further, the test system further includes: an ISI (Inter Symbol Interference) channel unit, an input end of the ISI channel unit is communicatively connected to the first output end of the standard signal generator, and an output end of the ISI channel unit is communicatively connected to an input end of the first relay, for generating interference signals.

[0011] Further, the test system further includes: a jitter signal unit, an input end of the jitter signal unit is communicatively connected to the first output end of the standard signal generator, and an output end of the jitter signal unit is communicatively connected to an input end of the ISI channel unit, for generating jitter signals.

[0012] Further, the test system further includes: a power splitter unit, an input end of the power splitter unit is communicatively connected to the second output end of the standard signal generator, and an output end of the power splitter unit is communicatively connected to the other parts of the input ends of the third relays.

[0013] Further, the test system further includes: a DC blocker unit, including a first DC blocker module and a second DC blocker module, an input end of the first DC blocker module is communicatively connected to an output end of the jitter signal unit, an output end of the first DC blocker module is communicatively connected to an input end of the ISI channel unit, an input end of the second DC blocker module is communicatively connected to the second output end of the standard signal generator, and an output end of the second DC blocker module is communicatively connected to an input end of the power splitter unit.

[0014] Further, the signal pattern output from the second output end of the standard signal generator includes one of the following: 1 / 4clock, TPS3, and TPS4.

[0015] Further, the test system further includes: an interface fixture unit, including a plurality of ports, communicatively connected to the output ends of the plurality of third relays and the output end of the processor module in one-to-one correspondence, for accessing the test port and the control port of the device under test.

[0016] Applying the technical solution of the present application, the port test system includes: a standard signal generator, a control unit, and a device under test. Among them, the standard signal generator includes a first output terminal and a second output terminal, and the standard signal generator is used to output a test signal; the control unit includes a first relay, at least one second relay, a plurality of third relays, and a processor module. The input terminal of the first relay is communicatively connected to the first output terminal of the standard signal generator, the output terminal of the first relay is electrically connected to the input terminals of at least one second relay, the output terminal of each second relay is electrically connected to a part of the input terminals of at least one third relay, the other part of the input terminals of each third relay is communicatively connected to the second output terminal of the standard signal generator, and the processor module includes a plurality of IO interfaces, which are respectively communicatively connected to the first relay, the second relay, and the third relay in one-to-one correspondence. The processor module is used to control the closing and opening of the relays so that any one of the third relays is connected to the first output terminal of the standard signal generator; the device under test includes a plurality of test ports and a control port, and the plurality of test ports are communicatively connected to the output terminals of the plurality of third relays in one-to-one correspondence, and the control port is communicatively connected to the output terminal of the processor module. This test system controls the closing and opening of the first relay, the second relay, and the third relay through the processor module in the control unit, so that any one of the third relays is connected to the first output terminal of the standard signal generator, and the third relays correspond to the test ports of the device under test one by one. Therefore, the processor module can control different test ports of the device under test to be connected to the first output terminal of the standard signal generator, so that any test port can be tested without manual operation, thereby solving the problem of low efficiency in the consistency test of DisplayPort ports in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings forming a part of this application are used to provide a further understanding of this application. The schematic embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation to this application. In the drawings:

[0018] Figure 1 FIG. shows a schematic diagram of a port test system according to an embodiment of the present application;

[0019] Figure 2 FIG. shows a schematic diagram of a port test system according to another embodiment of the present application;

[0020] Figure 3 FIG. shows a schematic diagram of a port test system according to still another embodiment of the present application.

[0021] Among them, the above-mentioned drawings include the following reference numerals:

[0022] 10. Standard signal generator; 20. Control unit; 30. Device under test; 40. Controller; 50. ISI channel unit; 60. Jitter signal unit; 70. Power splitter unit; 80. DC blocker unit; 90. Interface fixture unit; 201. First relay; 202. Second relay; 203. Third relay; 204. Processor module; 205. Input interface; 206. Output interface; 301. Test port; 302. Control port; 801. First DC blocker module; 802. Second DC blocker module. Detailed implementation manners

[0023] It should be noted that the following detailed description is exemplary and is intended to provide further description of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs.

[0024] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary implementation manners according to the present application. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0025] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element can be directly on the other element, or a second element may also exist. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element can be "directly connected" to the other element, or "connected" to the other element through a third element.

[0026] For ease of description, some nouns or terms related to the embodiments of the present application are described below:

[0027] DisplayPort, a display interface, is a high-definition digital display interface standard that can connect a computer to a monitor or a computer to a home theater. DisplayPort allows audio and video signals to be transmitted over a single cable and supports multiple high-quality digital audio.

[0028] FPGA, Field Programmable Gate Array, is a programmable logic device that uses a logic cell array for logic editing. In the present application, Xilinx FPGA XC7Z30 is used to test relevant signals.

[0029] As described in the background art, the efficiency of the existing DisplayPort port consistency test is relatively low. To solve the above problems, in a typical implementation manner of the present application, a port test system is provided. As Figure 1 shown, it includes: a standard signal generator 10, a control unit 20, and a device under test 30. Among them, the standard signal generator 10 includes a first output terminal and a second output terminal, and the standard signal generator 10 is used to output test signals; the control unit 20 includes a first relay 201, at least one second relay 202, a plurality of third relays 203, and a processor module 204. The input terminal of the first relay 201 is communicatively connected to the first output terminal of the standard signal generator 10, the output terminal of the first relay 201 is electrically connected to the input terminals of at least one of the second relays 202, the output terminal of each of the second relays 202 is electrically connected to a part of the input terminals of at least one of the third relays 203, the other part of the input terminals of each of the third relays 203 is communicatively connected to the second output terminal of the standard signal generator 10. The processor module 204 includes a plurality of IO interfaces, which are respectively communicatively connected to the first relay 201, the second relay 202, and the third relay 203 in a one-to-one correspondence. The processor module 204 is used to control the closing and opening of the relays so that any one of the third relays 203 is connected to the first output terminal of the standard signal generator 10; the device under test 30 includes a plurality of test ports 301 and a control port 302. The plurality of test ports 301 are communicatively connected to the output terminals of the plurality of third relays 203 in a one-to-one correspondence, and the control port 302 is communicatively connected to the output terminal of the processor module 204.

[0030] The above-mentioned port test system includes: a standard signal generator, a control unit, and a device under test. Among them, the above-mentioned standard signal generator includes a first output terminal and a second output terminal, and the above-mentioned standard signal generator is used to output test signals; the above-mentioned control unit includes a first relay, at least one second relay, a plurality of third relays, and a processor module. The input terminal of the above-mentioned first relay is communicatively connected to the above-mentioned first output terminal of the above-mentioned standard signal generator, the output terminal of the above-mentioned first relay is electrically connected to the input terminals of at least one of the above-mentioned second relays, the output terminal of each of the above-mentioned second relays is electrically connected to a part of the input terminals of at least one of the above-mentioned third relays, the other part of the input terminals of each of the above-mentioned third relays is communicatively connected to the above-mentioned second output terminal of the above-mentioned standard signal generator, the above-mentioned processor module includes a plurality of IO interfaces, which are respectively communicatively connected to the above-mentioned first relay, the above-mentioned second relay, and the above-mentioned third relay in one-to-one correspondence, and the above-mentioned processor module is used to control the closing and opening of the relays so that any one of the above-mentioned third relays is connected to the above-mentioned first output terminal of the above-mentioned standard signal generator; the above-mentioned device under test includes a plurality of test ports and a control port, the plurality of above-mentioned test ports are communicatively connected to the output terminals of the plurality of above-mentioned third relays in one-to-one correspondence, and the above-mentioned control port is communicatively connected to the output terminal of the above-mentioned processor module. This test system controls the closing and opening of the first relay, the second relay, and the third relay through the processor module in the control unit, so that any one of the third relays is connected to the first output terminal of the above-mentioned standard signal generator, and the third relay corresponds to the test port of the device under test one by one. Therefore, the processor module can control different test ports of the device under test to be connected to the first output terminal of the above-mentioned standard signal generator, so that any test port can be tested without manual operation, thus solving the problem of low efficiency in the consistency test of DisplayPort ports in the prior art.

[0031] In practical applications, DisplayPort is one of the current mainstream high-speed digital video interfaces. DisplayPort is mainly used for the connection and communication between a computer host and a display. The currently highest data link rate it can support can reach 20 Gbps / second (single channel). If multiple communication channels are used for communication simultaneously, the communication rate at this time will be very high. For such a high-speed interface, the operation of devices such as the transmitter chip, cable, connector, PCB (Printed Circuit Board), and receiver chip poses no small challenge. Therefore, relevant products of DisplayPort need to undergo some physical layer and link layer tests to measure whether the product meets the requirements of the protocol. Among them, the physical layer test is the most important link, which is the basis of product performance. Currently, the bandwidth of high-speed relays on the market can reach 18 GHz, the insertion loss of transmitting a 10 GHz signal is <0.2 dB, and the Isolation reaches -50 dB@10 GHz, which can meet the performance requirements of DisplayPort1.4 / 2.0. Before starting the DisplayPort compliance test, instrument calibration needs to be carried out first. When running the calibration, the control unit needs to be connected for calibration together. In this way, the DUT (Device Under Test) can compensate for the insertion loss brought by the control unit in advance to ensure the accuracy of the actual test results.

[0032] Specifically, the above-mentioned first relay, the above-mentioned second relay, and the above-mentioned third relay can be equipped with a dual-channel gating switch, which can make any one of the relays connected during the test, so that the above-mentioned test port to be tested is connected to the above-mentioned first output end of the above-mentioned standard signal generator for testing. The above-mentioned processor module can be an FPGA module. The above-mentioned first output end of the above-mentioned standard signal generator can be a Data output end for outputting interference signals, and the above-mentioned second output end of the above-mentioned standard signal generator can be a Crosstalk output end for outputting crosstalk signals. The connection between the above-mentioned standard signal generator, the above-mentioned control unit, and the above-mentioned DUT can use an SMA cable.

[0033] In another embodiment of the present application, when the above-mentioned first relay is electrically connected to two of the above-mentioned second relays, a part of the output ends of the above-mentioned first relay is electrically connected to the input end of one of the above-mentioned second relays, and another part of the output ends of the above-mentioned first relay is electrically connected to the input end of the other of the above-mentioned second relays. The above-mentioned first relay is used to be connected to one of the two above-mentioned second relays during the test. A relay with a dual-channel gating switch can be electrically connected to at most two relays. Through the second relay as an intermediary, more third relays can be connected to the circuit, so that more test ports can be tested subsequently.

[0034] Specifically, the first relay includes a dual-channel selection switch, which has two input terminals and four output terminals, and the two input terminals are communicatively connected to the first output terminal of the standard signal generator.

[0035] In practical applications, two output terminals of one of the first relays are connected to two input terminals of a second relay, and the other two output terminals of the first relay are connected to two input terminals of another second relay. When performing port testing, only one of the two second relays can be connected to the first relay, so that one of the second relays can be connected to the first output terminal of the standard signal generator.

[0036] In order to enable each port of the device under test to be electrically connected to the first output terminal of the standard signal generator, in another embodiment of the present application, as Figure 1 shown, when each of the second relays 202 is electrically connected to two of the third relays 203, a part of the output terminals of one of the second relays 202 is electrically connected to a part of the input terminals of one of the third relays 203, and another part of the output terminals of the second relay 202 is electrically connected to a part of the input terminals of another one of the third relays 203. The second relay 202 is configured to be connected to one of the two third relays 203 during testing. The third relays are in one-to-one correspondence with the test ports of the standard signal generator 10, and by electrically connecting to the third relays, the first output terminal of the signal generator can output signals to the test ports.

[0037] Specifically, two output terminals of one of the second relays are connected to two input terminals of a third relay, and the other two output terminals of the second relay are connected to two input terminals of another third relay. When performing port testing, only one of the two third relays can be connected to the second relay, so that one of the third relays can be connected to the first output terminal of the standard signal generator.

[0038] In still another embodiment of the present application, as Figure 2 shown, the test system further includes: a controller 40 communicatively connected to the input terminal of the processor module 204, and is configured to determine the test port 301 to be tested. The controller can determine which port of the device under test needs to be tested, so that the processor module controls the closing and opening of the first relay, the second relay, and the third relay according to the test port, so that the third relay connected to the test port is connected to the first output terminal of the standard signal generator.

[0039] In practical applications, the above-mentioned controller can be an AUX controller. When starting the test, the signal generator will send a control instruction through the AUX controller to inform the device under test which channel is to be tested currently. The processor module obtains which channel is to be tested currently by listening to the instruction on the AUX, so as to identify which physical channel under test is selected by the current automated test software. Then, the IO of the FPGA controls the relay to switch channels, so as to connect the physical channel under test to the first output terminal of the standard signal generator, and the other three physical channels to the second output terminal of the standard signal generator.

[0040] In order to add interference to the signal output from the first output terminal of the standard signal generator, in another embodiment of the present application, as Figure 2 shown, the above-mentioned test system further includes: an ISI channel unit 50, the input end of the above-mentioned ISI channel unit 50 is communicatively connected to the above-mentioned first output terminal of the above-mentioned standard signal generator 10, and the output end of the above-mentioned ISI channel unit 50 is communicatively connected to the input end of the above-mentioned first relay 201, and is used for generating an interference signal.

[0041] In order to be able to test the signal jitter reception ability of the device under test, in another embodiment of the present application, as Figure 2 shown, the above-mentioned test system further includes: a jitter signal unit 60, which is communicatively connected to the above-mentioned first output terminal of the above-mentioned standard signal generator 10, and is used for generating a jitter signal.

[0042] In another embodiment of the present application, as Figure 2 shown, the above-mentioned test system further includes: a power splitter unit 70, the input end of the above-mentioned power splitter unit 70 is communicatively connected to the above-mentioned second output terminal of the above-mentioned standard signal generator 10, and the output end of the above-mentioned power splitter unit 70 is communicatively connected to the other part of the input ends of each of the above-mentioned third relays 203. The power splitter unit divides the energy of one input signal into two or more outputs with equal energy, so that the signal energy received by each third relay is equal.

[0043] In practical applications, in the case of having two second relays and four third relays, the above-mentioned power splitter unit can include two 1:4 power splitters. The four output terminals of one 1:4 power splitter are respectively electrically connected to one of the remaining two output terminals of the four third relays, and the four output terminals of the other 1:4 power splitter are respectively electrically connected to the last output terminal of the four third relays. So that the four third relays are all electrically connected to the second output terminal of the standard signal generator.

[0044] In order to block the DC signal, in another embodiment of the present application, as Figure 2As shown in the figure, the above test system further includes: a DC blocker unit 80, including a first DC blocker module 801 and a second DC blocker module 802. The input end of the first DC blocker module 801 is communicatively connected to the output end of the jitter signal unit 60, the output end of the first DC blocker module 801 is communicatively connected to the input end of the ISI channel unit 50, the input end of the second DC blocker module 802 is communicatively connected to the second output end of the standard signal generator 10, and the output end of the second DC blocker module 802 is communicatively connected to the input end of the power splitter unit 70.

[0045] In another embodiment of the present application, the signal pattern output by the second output end of the above standard signal generator includes one of the following: 1 / 4clock, TPS3, and TPS4. The second output end outputs a signal with a pattern of 1 / 4clock, TPS3, or TPS4 to add crosstalk signals to the channels to be tested.

[0046] In order to enable each of the above third relays to be conveniently connected to the ports of the device under test, in another embodiment of the present application, as Figure 2 shown in the figure, the above test system further includes: an interface fixture unit 90, including a plurality of ports, which are communicatively connected to the output ends of a plurality of the above third relays 203 and the output ends of the processor module 204 in one-to-one correspondence, and are used to access the test port 301 and the control port 302 of the above device under test 30.

[0047] In practical applications, the above control unit may further include a plurality of input interfaces and a plurality of output interfaces. The two input ends of the first input interface are communicatively connected to the two output ends of the ISI channel unit, the two output ends of the first input interface are communicatively connected to the two input ends of the first relay, the two input ends of the last input interface are communicatively connected to the two output ends of the controller, and the two output ends of the last output interface are communicatively connected to the two input ends of the processor module. Among the remaining input interfaces, one input end of each input interface is communicatively connected to the multiple output ends of one power splitter in one-to-one correspondence, and the other input end of each input interface is communicatively connected to the multiple output ends of another power splitter in one-to-one correspondence. The input end of the last output interface is communicatively connected to the two output ends of the processor module and is connected to the control port through the interface fixture unit. The two input ends of the remaining output interfaces are communicatively connected to the two output ends of a plurality of third relays in one-to-one correspondence and are connected to a plurality of test ports in one-to-one correspondence through the interface fixture unit.

[0048] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the technical solution of the present application will be described in detail below with reference to specific embodiments.

[0049] Embodiment

[0050] The port test system in this embodiment includes:

[0051] As Figure 3 shown, a standard signal generator 10, including a first output end and a second output end, and the above-mentioned standard signal generator 10 is used to output test signals;

[0052] A control unit 20, including a first relay 201, two second relays 202, four third relays 203, and a processor module 204. The above-mentioned processor module 204 includes seven IO interfaces, which are respectively in one-to-one correspondence communication connection with the above-mentioned first relay 201, the above-mentioned second relay 202, and the above-mentioned third relay 203 (not shown in the figure). The above-mentioned processor module 204 is used to control the closing and opening of the relays, so that any one of the above-mentioned third relays 203 is communicated with the above-mentioned first output end of the standard signal generator 10;

[0053] A device under test 30, including four test ports 301 and a control port 302. The four test ports 301 are in one-to-one correspondence communication connection with the output ends of the four above-mentioned third relays 203, and the above-mentioned control port 302 is in communication connection with the output end of the above-mentioned processor module 204;

[0054] A controller 40, in communication connection with the input end of the above-mentioned processor module 204, is used to determine the above-mentioned test port 301 that needs to be tested;

[0055] An ISI channel unit 50, the input end of the above-mentioned ISI channel unit 50 is in communication connection with the above-mentioned first output end of the standard signal generator 10, and the output end of the above-mentioned ISI channel unit 50 is in communication connection with the input end of the above-mentioned first relay 201, and is used to generate interference signals;

[0056] A jitter signal unit 60, in communication connection with the above-mentioned first output end of the standard signal generator 10, and is used to generate jitter signals;

[0057] A power splitter unit 70, the input end of the above-mentioned power splitter unit 70 is in communication connection with the above-mentioned second output end of the standard signal generator 10, and the output end of the above-mentioned power splitter unit 70 is in communication connection with the other part of the input ends of each of the above-mentioned third relays 203;

[0058] An interface fixture unit 90, including multiple ports, in one-to-one correspondence communication connection with the output ends of the four above-mentioned third relays 203 and the output end of the processor module 204, and is used to access the above-mentioned test port 301 and the control port 302 of the above-mentioned device under test 30.

[0059] Specifically, the first relay 201, the second relay 202, and the third relay 203 may be equipped with dual-channel gating switches. The first relay 201 and the second relay 202 have two input terminals and four output terminals, and the third relay 203 has four input terminals and two output terminals. The two input terminals of the first relay 201 are communicatively connected to the first output terminal of the standard signal generator 10. The two output terminals of the first relay 201 are electrically connected to the two input terminals of the first of the two second relays 202, and the other two output terminals of the first relay 201 are electrically connected to the two input terminals of the second of the two second relays 202. During port testing, only one of the two second relays 202 can be connected to the first relay 201, so that one of the second relays 202 can be connected to the first output terminal of the standard signal generator 10.

[0060] The two output terminals of the first of the two second relays 202 are electrically connected to the two input terminals of the first of the four third relays 203, the other two output terminals of the first of the two second relays 202 are electrically connected to the two input terminals of the second of the four third relays 203, the two output terminals of the second of the two second relays 202 are electrically connected to the two input terminals of the third of the four third relays 203, and the other two output terminals of the second of the two second relays 202 are electrically connected to the two input terminals of the fourth of the four third relays 203. The second relay 202 is used to connect to one of the two third relays 203 during testing. The third relay 203 corresponds one-to-one with the test port 301 of the standard signal generator 10. By being electrically connected to the third relay 203, the first output terminal of the signal generator can output a signal to the test port 301.

[0061] The power splitter unit 70 includes two 1:4 power splitters. The four output terminals of one 1:4 power splitter are respectively electrically connected to one of the remaining two output terminals of the four third relays 203, and the four output terminals of the other 1:4 power splitter are respectively electrically connected to the last output terminal of the four third relays 203. This enables the four third relays 203 to be electrically connected to the second output terminal of the standard signal generator 10.

[0062] The above control unit 20 may further include six input interfaces 205 and five output interfaces 206. The two input terminals of the first input interface are communicatively connected to the two output terminals of the ISI channel unit 50, and the two output terminals of the first input interface are communicatively connected to the two input terminals of the first relay 201. One input terminal of the second to fifth input interfaces is communicatively connected to the four output terminals of a 1:4 power divider, and the other input terminal of the second to fifth input interfaces is communicatively connected to the four output terminals of another 1:4 power divider. The two input terminals of the sixth input interface are communicatively connected to the two output terminals of the controller 40, and the two output terminals of the sixth output interface are communicatively connected to the two input terminals of the processor module 204. The two input terminals of the first to fourth output interfaces are respectively communicatively connected to the two output terminals of four third relays 203. The input terminal of the fifth output interface is communicatively connected to the two output terminals of the processor module 204. The output terminals of the five output interfaces are respectively communicatively connected to the interface fixture unit 90. The first to fourth output interfaces are connected to the test port 301 through the interface fixture unit, and the fifth output interface is connected to the control port 302 through the interface fixture unit.

[0063] In the above embodiments of the present invention, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0064] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0065] The above-mentioned port test system of the present application includes: a standard signal generator, a control unit, and a device under test. Among them, the above-mentioned standard signal generator includes a first output terminal and a second output terminal, and the above-mentioned standard signal generator is used to output a test signal; the above-mentioned control unit includes a first relay, at least one second relay, a plurality of third relays, and a processor module. The input terminal of the above-mentioned first relay is communicatively connected to the above-mentioned first output terminal of the above-mentioned standard signal generator, the output terminal of the above-mentioned first relay is electrically connected to the input terminals of at least one of the above-mentioned second relays, the output terminal of each of the above-mentioned second relays is electrically connected to a part of the input terminals of at least one of the above-mentioned third relays, the other part of the input terminals of each of the above-mentioned third relays is communicatively connected to the above-mentioned second output terminal of the above-mentioned standard signal generator, and the above-mentioned processor module includes a plurality of IO interfaces, which are respectively communicatively connected to the above-mentioned first relay, the above-mentioned second relay, and the above-mentioned third relay one by one. The above-mentioned processor module is used to control the closing and opening of the relays so that any one of the above-mentioned third relays is connected to the above-mentioned first output terminal of the above-mentioned standard signal generator; the above-mentioned device under test includes a plurality of test ports and a control port, and the plurality of above-mentioned test ports are communicatively connected to the output terminals of the plurality of above-mentioned third relays one by one, and the above-mentioned control port is communicatively connected to the output terminal of the above-mentioned processor module. This test system controls the closing and opening of the first relay, the second relay, and the third relay through the processor module in the control unit, so that any one of the third relays is connected to the first output terminal of the above-mentioned standard signal generator, and the third relay corresponds to the test port of the device under test one by one. Therefore, the processor module can control different test ports of the device under test to be connected to the first output terminal of the above-mentioned standard signal generator, so that any test port can be tested without manual operation, thus solving the problem of low efficiency in the consistency test of the DisplayPort port in the prior art.

[0066] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A port testing system, characterized in that, Comprising: A standard signal generator, including a first output terminal and a second output terminal, the standard signal generator being configured to output a test signal; A control unit, including a first relay, at least one second relay, a plurality of third relays, and a processor module. The input terminal of the first relay is communicatively connected to the first output terminal of the standard signal generator. The output terminal of the first relay is electrically connected to the input terminals of at least one of the second relays. The output terminal of each second relay is electrically connected to a part of the input terminals of at least one of the third relays. The other part of the input terminals of each third relay is communicatively connected to the second output terminal of the standard signal generator. The processor module includes a plurality of IO interfaces, which are respectively communicatively connected to the first relay, the second relay, and the third relay in a one-to-one correspondence. The processor module is configured to control the closing and opening of the relays so that any one of the third relays is connected to the first output terminal of the standard signal generator; A device under test, including a plurality of test ports and a control port. The plurality of test ports are communicatively connected to the output terminals of the plurality of third relays in a one-to-one correspondence. The control port is communicatively connected to the output terminal of the processor module; An ISI channel unit, the input terminal of the ISI channel unit is communicatively connected to the first output terminal of the standard signal generator, and the output terminal of the ISI channel unit is communicatively connected to the input terminal of the first relay, for generating interference signals; A jitter signal unit, the input terminal of the jitter signal unit is communicatively connected to the first output terminal of the standard signal generator, and the output terminal of the jitter signal unit is communicatively connected to the input terminal of the ISI channel unit, for generating jitter signals.

2. The test system according to claim 1, wherein When the first relay is electrically connected to two of the second relays, a part of the output terminals of the first relay is electrically connected to the input terminal of one of the second relays, and the other part of the output terminals of the first relay is electrically connected to the input terminal of the other second relay. The first relay is configured to be connected to one of the two second relays during testing.

3. The test system according to claim 1, wherein When each second relay is electrically connected to two of the third relays, a part of the output terminals of one of the second relays is electrically connected to a part of the input terminals of one of the third relays, and the other part of the output terminals of the second relay is electrically connected to a part of the input terminals of the other third relay. The second relay is configured to be connected to one of the two third relays during testing.

4. The test system according to claim 1, wherein The test system further includes: A controller, communicatively connected to the input terminal of the processor module, for determining the test port to be tested.

5. The test system according to claim 1, characterized in that, The test system further includes: A power splitter unit, the input terminal of the power splitter unit is communicatively connected to the second output terminal of the standard signal generator, and the output terminal of the power splitter unit is communicatively connected to the other part of the input terminals of each of the third relays.

6. The test system according to claim 5, wherein The test system further includes: The DC-blocking unit includes a first DC-blocking module and a second DC-blocking module. The input end of the first DC-blocking module is communicatively connected to the output end of the jitter signal unit, the output end of the first DC-blocking module is communicatively connected to the input end of the ISI channel unit, the input end of the second DC-blocking module is communicatively connected to the second output end of the standard signal generator, and the output end of the second DC-blocking module is communicatively connected to the input end of the power splitter unit.

7. The test system according to any one of claims 1 to 6, characterized in that, The signal pattern output by the second output end of the standard signal generator includes one of the following: 1 / 4clock, TPS3, and TPS4.

8. The test system according to any one of claims 1 to 6, characterized in that, The test system further includes: The interface fixture unit includes a plurality of ports, which are communicatively connected to the output ends of a plurality of the third relays and the output end of the processor module in one-to-one correspondence, and is used to access the test port and the control port of the device under test.

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