Light emission control circuit and light emission control driver

Abstract

The application discloses a light-emitting control circuit and a light-emitting control driver. The light-emitting control circuit comprises a node control module, at least two output modules and at least one shift module; the node control module is used for forming a control signal according to an input signal, a first clock signal and a first power signal; the output module comprises a clamping unit and an output unit; the clamping unit of the first output module is connected with the node control module, the clamping unit is used for clamping the control signal, the output unit is connected with the clamping unit, and the output unit is used for outputting a light-emitting control signal according to the control signal; the clamping unit of the i-th output module is connected with the output unit of the (i-1)-th output module through a shift module, the shift module is used for shifting an input signal and then outputting the shifted signal to a next output module; wherein i is an integer greater than or equal to 2. The light-emitting control circuit can occupy less space, which is beneficial to the narrow frame design of a display panel.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of display, and in particular to a light emitting control circuit and a light emitting control driver. Background Art

[0002] A display panel includes a light-emission control circuit that provides light-emission control signals to pixel units, controlling the light-emitting devices in the pixel units to emit light and achieve display on the display panel. In the prior art, this light-emission control circuit is typically located in the border area of ​​the display panel. The light-emission control circuit includes multiple transistors and multiple capacitors, which occupies a relatively large area of ​​the display panel's border. This results in a larger border on the display panel, hindering the narrow-border design of the display panel. Summary of the Invention

[0003] The present invention provides a light emitting control circuit and a light emitting control driver, so as to reduce the occupied area of ​​the light emitting control circuit, thereby facilitating a narrow frame design of a display panel.

[0004] In a first aspect, an embodiment of the present invention provides a light emitting control circuit, comprising a node control module, at least two output modules, and at least one shift module;

[0005] The node control module is used to form a control signal based on an input signal, a first clock signal and a first power supply signal; the output module includes a clamping unit and an output unit; the clamping unit of the first output module is connected to the node control module, the clamping unit is used to clamp the control signal, and the output unit is connected to the clamping unit, and the output unit is used to output a light-emitting control signal according to the control signal; the clamping unit of the i-th output module is connected to the output unit of the i-1-th output module through a shift module, and the shift module is used to shift the input signal and output it to the next output module; wherein i is an integer greater than or equal to 2.

[0006] Optionally, the clamping unit includes a pull-up subunit and a pull-down subunit, and the output unit includes a first output subunit and a second output subunit;

[0007] The first end of the pull-up subunit of the first clamping unit and the control end of the first output subunit of the first output unit are connected to the first output end of the node control module, the first end of the pull-up subunit of the i-th clamping unit and the control end of the first output subunit of the i-th output unit are connected to the control end of the first output subunit of the i-1-th output unit via the shift module; the second end of the pull-up subunit and the first end of the first output subunit are connected to the first power input end, the second end of the first output subunit is connected to the second end of the second output subunit, and serve as the output end of the output module;

[0008] The first end and the control end of the pull-down subunit of the first clamping unit and the control end of the second output subunit of the first output unit are connected to the second output end of the node control module, the second end of the pull-down subunit of the first clamping unit is connected to the second clock signal input end, and the first end and the control end of the pull-down subunit of the i-th clamping unit and the control end of the second output subunit of the i-th output unit are connected to the output end of the (i-1)-th output module via a shift module;

[0009] When i is an even number, the second end of the pull-down subunit of the i-th clamping unit is connected to the first clock signal input end, and when i is an odd number, the second end of the pull-down subunit of the i-th clamping unit is connected to the second clock signal input end; wherein the timing sequence of the first clock signal provided by the first clock signal input end is opposite to the timing sequence of the second clock signal provided by the second clock signal input end;

[0010] The first end of the second output subunit is connected to the second power input end.

[0011] Optionally, the pull-up subunit includes a first capacitor, the pull-down subunit includes a second capacitor and a first transistor, the first output subunit includes a first output transistor, and the second output subunit includes a second output transistor;

[0012] The first electrode of the first capacitor serves as the first end of the pull-up subunit, and the second electrode of the first capacitor serves as the second end of the pull-up subunit; the first electrode of the second capacitor serves as the first end of the pull-down subunit, and the second electrode of the second capacitor is connected to the first electrode of the first transistor, the control electrode of the first transistor serves as the control end of the pull-down subunit, and the second electrode of the first transistor serves as the second end of the pull-down subunit;

[0013] The control electrode of the first output transistor serves as the control terminal of the first output sub-unit, the first electrode of the first output transistor serves as the first terminal of the first output sub-unit, and the second electrode of the first output transistor serves as the second terminal of the first output sub-unit;

[0014] The control electrode of the second output transistor serves as the control terminal of the second output subunit, the first electrode of the second output transistor serves as the first terminal of the second output subunit, and the second electrode of the second output transistor serves as the second terminal of the second output subunit.

[0015] Optionally, the capacitance value of the first capacitor in the i-th output module is smaller than the capacitance value of the first capacitor in the (i-1)-th output module.

[0016] Optionally, the shift module includes a first shift unit and a second shift unit;

[0017] The first end of the first shift unit is connected to the control end of the first output subunit of the i-1th output module, the second end of the first shift unit is connected to the control end of the i-th first output subunit, the first end of the second shift unit is connected to the output end of the i-1th output module, and the second end of the second shift unit is connected to the control end of the second output subunit of the i-th output module; when i is an even number, the control end of the first shift unit and the control end of the second shift unit are connected to the second clock signal input end, and when i is an odd number, the control end of the first shift unit and the control end of the second shift unit are connected to the first clock signal input end.

[0018] Optionally, the first shift unit includes a second transistor, and the second shift unit includes a third transistor;

[0019] The first electrode of the second transistor serves as the first end of the first shift unit, the second electrode of the second transistor serves as the second end of the first shift unit, and the control electrode of the second transistor serves as the control end of the first shift unit;

[0020] The first electrode of the third transistor serves as the first end of the second shift unit, the second electrode of the third transistor serves as the second end of the second shift unit, and the control electrode of the third transistor serves as the control end of the second shift unit.

[0021] Optionally, the output module further includes a fourth transistor;

[0022] The fourth transistor of the first output module is connected between the node control module and the clamping unit of the first output module, the fourth transistor of the i-th output module is connected between the shift module and the clamping unit of the i-th output module, and the control electrode of the fourth transistor is connected to the second power supply input terminal.

[0023] Optionally, the node control module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third capacitor;

[0024] The first electrode of the fifth transistor is used to input the input signal, the second electrode of the fifth transistor is connected to the control electrode of the sixth transistor and serves as the second output terminal of the node control module; the control electrode of the fifth transistor is used to input the first clock signal;

[0025] The first electrode of the sixth transistor is used to input the first power supply signal, and the second electrode of the sixth transistor is connected to the second electrode of the seventh transistor and serves as the first output terminal of the node control module;

[0026] The first electrode of the seventh transistor and the first electrode of the third capacitor are used to input the first clock signal, and the control electrode of the seventh transistor and the second electrode of the third capacitor are connected to the second electrode of the eighth transistor;

[0027] The first electrode of the eighth transistor is used to input the first power supply signal, and the control electrode of the eighth transistor is used to input the input signal.

[0028] Optionally, the node control module further includes a ninth transistor; and the pull-down subunit includes a second capacitor and a first transistor;

[0029] The first electrode of the ninth transistor is used to input the first power supply signal, the second electrode of the ninth transistor is connected to the second electrode of the second capacitor, and the control electrode of the ninth transistor is connected to the first output end of the node control module.

[0030] In a second aspect, an embodiment of the present invention further provides a light emitting control driver, comprising at least two stages of the light emitting control circuits described in the first aspect, wherein the at least two stages of the light emitting control circuits are cascaded.

[0031] The technical solution of an embodiment of the present invention is to provide a light-emitting control circuit including at least two output modules and at least one shift module. Adjacent output modules are connected by the shift module. After the previous output module outputs a light-emitting control signal, the shift module shifts the input signal and outputs it to the next output module, so that the next output module outputs a signal after the previous light-emitting control signal is shifted. This enables the light-emitting control circuit to output cascaded light-emitting control signals. This is equivalent to at least two light-emitting control circuits in the prior art, used to drive different rows of pixel units in a display panel, thereby reducing the number of components in the light-emitting control circuit when the display panel has multiple rows of pixel units. Moreover, at least two output modules reuse the same node control module, which is equivalent to at least two light-emitting control circuits in the prior art reuse the same node control module. This can reduce the number of components required for the light-emitting control circuit compared to the prior art, and further reduce the space occupied by the light-emitting control circuit, which is conducive to the narrow-frame design of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the structure of a light-emitting control circuit provided by the prior art;

[0033] Figure 2 for Figure 1 A timing diagram corresponding to the light emitting control circuit;

[0034] Figure 3 A schematic structural diagram of a light emitting control circuit provided by an embodiment of the present invention;

[0035] Figure 4 A schematic structural diagram of another light-emitting control circuit provided by an embodiment of the present invention;

[0036] Figure 5 A schematic structural diagram of another light-emitting control circuit provided by an embodiment of the present invention;

[0037] Figure 6 A schematic structural diagram of another light-emitting control circuit provided by an embodiment of the present invention;

[0038] Figure 7 A schematic structural diagram of another light-emitting control circuit provided by an embodiment of the present invention;

[0039] Figure 8 A schematic structural diagram of another light-emitting control circuit provided by an embodiment of the present invention;

[0040] Figure 9 A schematic structural diagram of another light-emitting control circuit provided by an embodiment of the present invention;

[0041] Figure 10 for Figure 9A timing diagram corresponding to the provided light emitting control circuit;

[0042] Figure 11 A light emitting control driver is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0044] Figure 1 This is a schematic diagram of the structure of a light-emitting control circuit provided by the prior art. Figure 1As shown, the light emitting control circuit includes 13T3C, specifically including a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, an eighth thin film transistor M8, a ninth thin film transistor M9, a tenth thin film transistor M10, an eleventh thin film transistor M11, a twelfth thin film transistor M12, a thirteenth thin film transistor M13, a first storage capacitor Cs1, a second storage capacitor Cs2 and a pull-down capacitor Cp. Among them, the gate of the first thin film transistor M1, the gate of the second thin film transistor M2, and the first electrode of the third thin film transistor M3 are connected to the first clock signal input terminal ECK1, the first electrode of the first thin film transistor M1 is connected to the initialization signal input terminal EIN, the second electrode of the first thin film transistor M1 is connected to the first electrode of the eighth thin film transistor M8, the gate of the third thin film transistor M3, and the gate of the fourth thin film transistor M4, the second electrode of the third thin film transistor M3 is connected to the first electrode of the fourth thin film transistor M4, the second electrode of the fourth thin film transistor M4 is connected to the second electrode of the second thin film transistor M2, the gate of the fifth thin film transistor M5, and the first electrode of the sixth thin film transistor M6, the first electrode of the second thin film transistor M2, the gate of the sixth thin film transistor M6, the gate of the eighth thin film transistor M8, and the first electrode of the twelfth thin film transistor M12 are connected to the first power signal input terminal VGL, and the second electrode of the sixth thin film transistor M6 is connected to the first storage A first electrode of the storage capacitor Cs1 is electrically connected to the gate of the seventh thin film transistor M7, a first electrode of the seventh thin film transistor M7, a gate of the ninth thin film transistor M9, and a first electrode of the tenth thin film transistor M10 are connected to the second clock signal input terminal ECK2, a second electrode of the seventh thin film transistor M7 is connected to the second electrode of the first storage capacitor Cs1 and the first electrode of the ninth thin film transistor M9, a second electrode of the ninth thin film transistor M9 is connected to the second electrode of the second storage capacitor Cs2, the gate of the thirteenth thin film transistor M13, and the second electrode of the eleventh thin film transistor M11, a first electrode of the second storage capacitor Cs2, a first electrode of the thirteenth thin film transistor M13, a first electrode of the eleventh thin film transistor M11, and a first electrode of the fifth thin film transistor M5 are connected to the second power signal input terminal VGH, a second electrode of the thirteenth thin film transistor M13 is connected to the second electrode of the twelfth thin film transistor M12, and serve as the output terminal EMOUT of the light emitting control circuit. The second electrode of the eighth thin film transistor M8 is connected to the second electrode of the pull-down capacitor Cp, the gate of the tenth thin film transistor M10, the gate of the eleventh thin film transistor M11 and the gate of the twelfth thin film transistor M12, and the first electrode of the pull-down capacitor Cp is connected to the second electrode of the fifth thin film transistor M5 and the second electrode of the tenth thin film transistor M10.

[0045] Figure 2 for Figure 1A timing diagram corresponding to the light emitting control circuit. Among them, the first power signal provided by the first power signal input terminal VGL is a low level, and the second power signal provided by the second power signal input terminal VGH is a high level. Eck1 is the timing of the first clock signal provided by the first clock signal input terminal ECK1, Eck2 is the timing of the second clock signal provided by the second clock signal input terminal ECK2, Ein is the timing of the initialization signal provided by the initialization signal input terminal EIN, and EMout is the timing of the light emitting control signal output terminal EMOUT. Figure 2 The provided timing can enable the light emitting control circuit to shift the initialization signal and then output it, so as to drive the pixel circuit in the pixel unit to operate.

[0046] Depend on Figure 1 and Figure 2 It can be seen that the light-emitting control circuit requires a large number of transistors and capacitors, which takes up a relatively large space. In addition, each light-emitting control circuit outputs only one light-emitting control signal for driving a row of pixel units in the display panel. When the display panel has multiple rows of pixel units, multiple cascaded light-emitting control circuits are required to drive different rows of pixel units, which multiplies the number of transistors and capacitors required for the overall light-emitting control circuit, further increasing the space and area occupied by the light-emitting control circuit, which is not conducive to the narrow-frame design of the display panel. For example, when the light-emitting control circuit needs to control two rows of pixel units, a total of two cascaded light-emitting control circuits are required, each light-emitting control circuit including 13T3C. In this case, the two cascaded light-emitting control circuits require a total of 26T6C, which makes the light-emitting control circuit occupy a relatively large space, which is not conducive to the narrow-frame design of the display panel.

[0047] In response to the above technical problems, an embodiment of the present invention provides a light emitting control circuit. Figure 3 FIG1 is a structural diagram of a light emitting control circuit provided by an embodiment of the present invention. Figure 3 As shown, the light-emitting control circuit includes a node control module 110, at least two output modules 120 and at least one shift module 130; the node control module 110 is used to form a control signal according to an input signal, a first clock signal and a first power supply signal; the output module 120 includes a clamping unit 121 and an output unit 122; the clamping unit 121 of the first output module 120 is connected to the node control module 110, and the clamping unit 121 is used to clamp the control signal, and the output unit 122 is connected to the clamping unit 121, and the output unit 122 is used to output a light-emitting control signal according to the control signal; the clamping unit 121 of the i-th output module 120 is connected to the output unit 122 of the i-1-th output module 120 through a shift module 130, and the shift module 130 is used to shift the input signal and output it to the next output module 120; wherein i is an integer greater than or equal to 2.

[0048] Specifically, the light-emitting control circuit can be applied to a display panel to control the light-emitting time of a pixel unit in the display panel. The light-emitting control circuit also includes a first power input terminal VGH, an input signal terminal IN, a second power input terminal VGL, a first clock signal input terminal CK1, and a second clock signal input terminal CK2, which are used to provide a drive signal to the light-emitting control circuit to drive the light-emitting control circuit to output a light-emitting control signal. The first power signal provided by the first power signal input terminal VGH can be a high level, the second power signal provided by the second power signal input terminal VGL can be a low level, and the first clock signal provided by the first clock signal input terminal CK1 and the second clock signal provided by the second clock signal input terminal CK2 can be clock signals with opposite phases. The node control module 110 can form a control signal based on the input signal, the first clock signal, and the first power signal, so that the level of the control signal is high or low as needed. The clamping unit 121 is used to clamp the control signal. When the control signal is at a high level, the clamping unit 121 in the first output module 120 can clamp the control signal to maintain a high level. When the control signal is at a low level, the clamping unit 121 in the first output module 120 can clamp the control signal to maintain a low level. The input end of the output unit 122 is used to input the first power signal and the second power signal. In the first output module 120, the control end of the output unit 122 is connected to the clamping unit 121. The output unit 122 in the first output module 120 receives the clamped control signal. The output unit 122 in the first output module 120 can output the first power signal or the second power signal in response to the control signal, so that the output unit 122 in the first output module 120 can output the light control signal according to the control signal.

[0049] The clamping unit 121 in the i-th output module 120 is connected to the output unit 122 in the i-1-th output module 120 via the shifting module 130. That is, between two adjacent output modules 120, the shifting module 130 receives the signal of the previous output module 120 and shifts the signal of the previous output module 120. The signal is then output to the clamping unit 121 in the next output module 120, so that the clamping unit 121 clamps the shifted signal. The output unit 122 in the next output module 120 outputs the first power signal or the second power signal based on the clamped signal. This allows the output unit 122 in the next output module 120 to shift and output the next light control signal after the previous output module 120 outputs the light control signal. This enables different output modules 120 to output cascaded light control signals, which is equivalent to at least two light control circuits in the prior art for driving different rows of pixel units in a display panel. This reduces the number of light control circuits when the display panel has multiple rows of pixel units. Moreover, at least two output modules 120 reuse the same node control module 110, which is equivalent to at least two light-emitting control circuits in the prior art reusing the same node control module 110. This can reduce the components required for the light-emitting control circuit compared to the prior art, and further reduce the space occupied by the light-emitting control circuit, which is beneficial to the narrow-frame design of the display panel.

[0050] For example, Figure 3 The light-emitting control circuit includes two output modules 120 and a shift module 130. The clamping unit 121 in the second output module 120 is connected to the output unit 122 in the first output module 120 through the shift module 130. The shift module 130 receives the signal of the first output module 120, shifts the signal, and then outputs it to the clamping unit 121 in the second output module 120, so that the clamping unit 121 clamps the shifted signal and then outputs it to the output unit 122 in the second output module 120. The output unit 122 in the second output module 120 outputs the first power supply signal or the second power supply signal according to the clamped signal, so that the output unit 122 in the second output module 120 can shift and output the second light-emitting control signal after the first output module 120 outputs the light-emitting control signal, thereby realizing that different output modules 120 output cascaded light-emitting control signals.

[0051] It should be noted that Figure 3The figure exemplarily shows that the light-emitting control circuit includes two output modules 120 and a shift module 130. In other embodiments, multiple output modules 120 and at least two shift modules 130 may be provided, and two adjacent output modules 120 are connected via a shift module 130. By providing multiple output modules 120, the light-emitting control circuit can output multiple cascaded light-emitting control signals, which is equivalent to multiple light-emitting control circuits in the prior art. Moreover, multiple output modules 120 reuse the same node control module 110, which is equivalent to multiple light-emitting control circuits sharing the same node control module 110 in the prior art. Compared with the prior art, the number of components required for the light-emitting control circuit can be further reduced, and the space occupied by the light-emitting control circuit can be further reduced, which is conducive to the narrow-frame design of the display panel.

[0052] The technical solution of this embodiment is to provide a light-emitting control circuit, which includes at least two output modules and at least one shift module. Adjacent output modules are connected by the shift module. After the previous output module outputs a light-emitting control signal, the shift module shifts the input signal and outputs it to the next output module, so that the next output module outputs the signal after the previous light-emitting control signal is shifted. This enables the light-emitting control circuit to output cascaded light-emitting control signals. This is equivalent to at least two light-emitting control circuits in the prior art, used to drive different rows of pixel units in a display panel, thereby reducing the number of light-emitting control circuits required when the display panel has multiple rows of pixel units. Moreover, at least two output modules reuse the same node control module, which is equivalent to at least two light-emitting control circuits in the prior art reuse the same node control module. This can reduce the number of components required for the light-emitting control circuit compared to the prior art, and further reduce the space occupied by the light-emitting control circuit, which is conducive to the narrow-frame design of the display panel.

[0053] Figure 4 FIG1 is a structural diagram of another light emitting control circuit provided by an embodiment of the present invention. Figure 4As shown, the clamping unit 121 includes a pull-up subunit 1211 and a pull-down subunit 1212, and the output unit 122 includes a first output subunit 1221 and a second output subunit 1222; the first end of the pull-up subunit 1211 of the first clamping unit 121 and the control end of the first output subunit 1221 of the first output unit 122 are connected to the first output end of the node control module 110, and the first end of the pull-up subunit 1211 of the i-th clamping unit 121 and the control end of the first output subunit 1221 of the i-th output unit 122 are connected to the first output end of the node control module 110. The control end of the subunit 1221 is connected to the control end of the first output subunit 1221 of the i-1th output unit 122 through a shift module 130; the second end of the pull-up subunit 1211 and the first end of the first output subunit 1221 are connected to the first power input terminal VGH, and the second end of the first output subunit 1221 is connected to the second end of the second output subunit 1222, and serves as the output terminal OUT of the output module 120; the first end of the pull-down subunit 1212 of the first clamping unit 121, the control end The first terminal and the control terminal of the second output subunit 1222 of the first output unit 122 are connected to the second output terminal of the node control module 110, the second terminal of the pull-down subunit 1212 of the first clamping unit 121 is connected to the second clock signal input terminal CK2, and the first terminal and the control terminal of the pull-down subunit 1212 of the i-th clamping unit 121 and the control terminal of the second output subunit 1222 of the i-th output unit 122 are connected to the output terminal OUT of the i-1-th output module 120 through a shift module 130; When i is an even number, the second end of the pull-down subunit 1212 of the i-th clamping unit 121 is connected to the first clock signal input terminal CK1; when i is an odd number, the second end of the pull-down subunit 1212 of the i-th clamping unit 121 is connected to the second clock signal input terminal CK2; wherein, the timing of the first clock signal provided by the first clock signal input terminal CK1 and the second clock signal provided by the second clock signal input terminal CK2 are opposite; the first end of the second output subunit 1222 is connected to the second power supply input terminal VGL.

[0054] Specifically, the j-th clamping unit 121 may be a clamping unit in the j-th output module 120, and the j-th output unit 122 may be an output unit in the j-th output module 120; wherein j is an integer greater than or equal to 1 and less than i. The first end of the pull-up subunit 1211 of the first clamping unit 121 and the control end of the first output subunit 1221 of the first output unit 122 are connected to the first output terminal of the node control module 110. When the first control signal output from the first output terminal of the node control module 110 is at an active level, the first output subunit 1221 can be controlled to be in a conductive state. The first output subunit 1221 can transmit the first power signal provided by the first power input terminal VGH to the output terminal OUT of the output module 120, so that the output module 120 can output the first power signal. In this case, the light-emitting control signal is the first power signal. When the first control signal output from the first output terminal of the node control module 110 is at an inactive level, the first output subunit 1221 can be controlled to be in an open circuit state, and the first output subunit 1221 stops outputting the first power signal to the output terminal OUT of the output module 120. Furthermore, when the first output terminal of the node control module 110 stops outputting the signal, the pull-up subunit 1211 can maintain the level of the first control signal output from the first output terminal of the node control module 110 in the previous stage, so that the first output subunit 1221 maintains the state of the previous stage until the first output terminal of the node control module 110 outputs the first control signal again. Similarly, when the second control signal output from the second output terminal of the node control module 110 is at an active level, the second output subunit 1222 can be controlled to be in a closed circuit state, and the second output subunit 1222 can transmit the second power signal provided by the second power input terminal VGL to the output terminal OUT of the output module 120, so that the output module 120 can output the second power signal. In this case, the light-emitting control signal is the second power signal. When the second control signal outputted by the second output terminal of the node control module 110 is at an invalid level, the second output subunit 1222 can be controlled to be in an open circuit state, and the second output subunit 1222 stops outputting the second power signal to the output terminal OUT of the output module 120. When the second output terminal of the node control module 110 stops outputting the signal, the pull-down subunit 1212 can maintain the second control signal outputted by the second output terminal of the node control module 110 in the previous stage, so that the second output subunit 1222 maintains the state of the previous stage until the second output terminal of the node control module 110 outputs the second control signal again.

[0055] In addition, the first end of the pull-up subunit 1211 of the i-th clamping unit 121 and the control end of the first output subunit 1221 of the i-th output unit 122 are connected to the control end of the first output subunit 1221 of the i-1-th output unit 122 via a shift module 130. That is, the first control signal output from the first output end of the node control module 110 is shifted by the shift module 130 and then transmitted to the first end of the next pull-up subunit 1211 and the next first output subunit 1221. When the first control signal output from the first output end of the node control module 110 is at a valid level, after the first output module 120 outputs the light-emitting control signal, the next first output subunit 1221 can be controlled to be in a conductive state. The next first output subunit 1221 can transmit the first power signal provided by the first power input terminal VGH to the output terminal OUT of the next output module 120, so that the next output module 120 can output the first power signal. In this case, the next light-emitting control signal is the first power signal. When the first control signal output from the first output terminal of the node control module 110 is at an invalid level, after the first output module 120 outputs the light-emitting control signal, the next first output subunit 1221 can be controlled to be in an open circuit state, and the next first output subunit 1221 stops outputting the first power signal to the output terminal OUT of the output module 120. When the first output terminal of the node control module 110 stops outputting the signal, the next pull-up subunit 1211 can maintain the level of the first control signal output from the first output terminal of the node control module 110 in the previous stage, so that the next first output subunit 1221 maintains the state of the previous stage until the first output terminal of the node control module 110 outputs the first control signal again.

[0056] Similarly, the first terminal and control terminal of the pull-down subunit 1212 of the i-th clamping unit 121, and the control terminal of the second output subunit 1222 of the i-th output unit 122 are connected to the output terminal OUT of the (i-1)-th output module 120 via a shift module 130. That is, the light-emission control signal output from the output terminal OUT of the previous output module 120 is shifted by the shift module 130 and transmitted to the first terminal and control terminal of the next pull-down subunit 1212 and the control terminal of the next second output subunit 1222. When the light-emission control signal output from the output terminal OUT of the previous output module 120 is at a valid level, the shift module 130 shifts the light-emission control signal and controls the next second output subunit 1222 to be in a conductive state. The next second output subunit 1222 transmits the second power signal provided by the second power input terminal VGL to the output terminal OUT of the next output module 120, allowing the next output module 120 to output the second power signal. In this case, the next light-emission control signal is the second power signal. When the light control signal outputted from the output terminal OUT of the previous output module 120 is at an invalid level, the shift module 130 shifts the light control signal and controls the next second output sub-unit 1222 to be in an open circuit state. The next second output sub-unit 1222 stops outputting the second power signal to the output terminal OUT of the next output module 120. The next pull-down sub-unit 1212 can also maintain the level of the light control signal at the previous stage, so that the next second output sub-unit 1222 maintains the state of the previous stage until the output terminal OUT of the previous output module 120 outputs the light control signal again.

[0057] Furthermore, when i is an even number, the second end of the pull-down subunit 1212 of the i-th clamping unit 121 is connected to the first clock signal input terminal CK1, and when i is an odd number, the second end of the pull-down subunit 1212 of the i-th clamping unit 121 is connected to the second clock signal input terminal CK2. When the second control signal output from the second output terminal of the node control module 110 is at an active level, the level of the clock signal input to the second end of each pull-down subunit 1212 and the active level are in phase with each other, thereby enabling the pull-down subunit 1212 to couple the active level of the second control signal, thereby better maintaining the active level of the second control signal, and thereby improving the reliability of controlling the second output subunit 1222 to be in the on state. The in-phase level can be when the active level of the second control signal and the level of the clock signal input to the second end of the pull-down subunit 1212 are both high or low.

[0058] It should be noted that the first control signal output from the first output terminal and the second control signal output from the second output terminal of the node control module 110 are related to the levels of the input signal, the first clock signal, and the second clock signal. For example, if the low level of the first control signal and the second control signal is valid, during the operation of the light-emitting control circuit, when the input signal provided by the input signal terminal IN is high, the first clock signal provided by the first clock signal input terminal CK1 is low, and the second clock signal provided by the second clock signal input terminal CK2 is high, the first control signal formed by the node control module 110 based on the input signal, the first power signal, and the first clock signal can be low, and the second control signal can be high. When the input signal provided by the input signal terminal IN is at a high level, the first clock signal provided by the first clock signal input terminal CK1 is at a high level, and the second clock signal provided by the second clock signal input terminal CK2 is at a low level, the node control module 110 stops outputting the first control signal and the second control signal based on the input signal, the first power signal, and the first clock signal. At this time, the pull-up subunit 1211 and the pull-up subunit 1212 respectively maintain the levels of the first control signal and the second control signal of the previous stage, so that the output module 120 maintains the output state of the previous stage. When the input signal provided by the input signal terminal IN is at a low level, the first clock signal provided by the first clock signal input terminal CK1 is at a low level, and the second clock signal provided by the second clock signal input terminal CK2 is at a high level, the first control signal formed by the node control module 110 based on the input signal, the first power signal, and the first clock signal can be at a high level, and the second control signal can be at a low level. When the input signal provided by the input signal terminal IN is at a low level, the first clock signal provided by the first clock signal input terminal CK1 is at a high level, and the second clock signal provided by the second clock signal input terminal CK2 is at a low level, the node control module 110 stops outputting the first control signal and the second control signal according to the input signal, the first power supply signal and the first clock signal. At this time, the pull-up sub-unit 1211 and the pull-up sub-unit 1212 respectively maintain the level of the first control signal and the second control signal of the previous stage, so that the output module 120 maintains the output state of the previous stage.

[0059] Figure 5 FIG1 is a structural diagram of another light emitting control circuit provided by an embodiment of the present invention. Figure 5As shown, the pull-up subunit 1211 includes a first capacitor C1, the pull-down subunit 1212 includes a second capacitor C2 and a first transistor T1, the first output subunit 1221 includes a first output transistor TO1, and the second output subunit 1222 includes a second output transistor TO2; the first electrode of the first capacitor C1 serves as the first end of the pull-up subunit 1211, and the second electrode of the first capacitor C1 serves as the second end of the pull-up subunit 1211; the first electrode of the second capacitor C2 serves as the first end of the pull-down subunit 1212, the second electrode of the second capacitor C2 is connected to the first electrode of the first transistor T1, and the control electrode of the first transistor T1 serves as the control electrode of the pull-down subunit 1212 The control terminal of the first transistor T1 serves as the second terminal of the pull-down sub-unit 1212; the control terminal of the first output transistor TO1 serves as the control terminal of the first output sub-unit 1221, the first terminal of the first output transistor TO1 serves as the first terminal of the first output sub-unit 1221, and the second terminal of the first output transistor TO1 serves as the second terminal of the first output sub-unit 1221; the control terminal of the second output transistor TO2 serves as the control terminal of the second output sub-unit 1222, the first terminal of the second output transistor TO2 serves as the first terminal of the second output sub-unit 1222, and the second terminal of the second output transistor TO2 serves as the second terminal of the second output sub-unit 1222.

[0060] Specifically, Figure 5 , it is exemplarily shown that the first transistor T1, the first output transistor TO1, and the second output transistor TO2 are all P-type transistors. At this time, the effective levels of the first control signal and the second control signal are low, so that the first output transistor TO1 and the second output transistor TO2 are turned on. The specific process is: when the first control signal output by the first output terminal of the node control module 110 is low, the first output transistor TO1 is in the on state, and the first power signal is transmitted to the output terminal OUT through the first output transistor TO1. At this time, the light-emitting control signal is the first power signal. When the first control signal output by the first output terminal of the node control module 110 is high, the first output transistor TO1 is in the off state, and the first output transistor TO1 stops transmitting the first power signal to the output terminal OUT. At the same time, the first capacitor C1 can maintain the first control signal so that when the first output terminal of the node control module 110 stops outputting the first control signal, the control pole of the first output transistor TO1 is maintained at the first control signal level of the previous stage, thereby ensuring that the state of the first output transistor TO1 maintains the state of the previous stage.

[0061] Similarly, when the second control signal output from the second output terminal of the node control module 110 is at a low level, the second output transistor TO2 is in an on state, and the second power signal is transmitted to the output terminal OUT through the second output transistor TO2. At this time, the light-emitting control signal is the second power signal. Moreover, the first transistor T1 is in an on state. When the second control signal output from the second output terminal of the node control module 110 is at a high level, the second output transistor TO2 is in an off state, and the second output transistor TO2 stops transmitting the second power signal to the output terminal OUT. Moreover, the first transistor T1 is in an off state. At the same time, the second capacitor C2 can maintain the second control signal so that when the second output terminal of the node control module 110 stops outputting the second control signal, the control pole of the second output transistor TO2 is maintained at the second control signal level of the previous stage, thereby ensuring that the state of the second output transistor TO2 maintains the state of the previous stage. Moreover, the second electrode of the first transistor T1 in the even-numbered pull-down sub-unit 1212 is connected to the first clock signal input terminal CK1, and the second electrode of the first transistor T1 in the odd-numbered pull-down sub-unit 1212 is connected to the second clock signal input terminal CK2, so that when the first transistor T1 is in the on state, the clock signal input by the second electrode of the first transistor T1 can pull down the first electrode potential of the second capacitor C2, thereby ensuring that the control electrode potential of the second output transistor TO2 is sufficiently low, ensuring the reliability of the conduction of the second output transistor TO2, and at the same time making the second power supply signal output by the second output transistor TO2 output at full amplitude, thereby improving the stability of the light-emitting control circuit.

[0062] Continue to refer Figure 5 , the capacitance value of the first capacitor C1 in the i-th output module 120 is smaller than the capacitance value of the first capacitor C1 in the (i-1)-th output module 120 .

[0063] Specifically, when the capacitance value of the first capacitor C1 in the previous output module 120 is greater than the capacitance value of the first capacitor C1 in the next output module 120, the first capacitor C1 in the previous output module 120 stores more electrical energy. When the first control signal is shifted by the shift module 130 and output to the first capacitor C1 in the next output module 120, the potential of the first electrode of the first capacitor C1 in the previous output module 120 decreases, causing the potential of the control electrode of the first output transistor TO1 in the next output module 120 to be sufficiently low to ensure that the first output transistor TO1 in the next output module 120 is in the on state. Moreover, when the capacitance value of the first capacitor C1 in the previous output module 120 is greater than the capacitance value of the first capacitor C1 in the next output module 120, the charging rate of the first electrode of the first capacitor C1 in the previous output module 120 to the first electrode of the first capacitor C1 in the next output module 120 through the shift module 130 can be increased, which facilitates the rapid transfer of power between different output modules 120 and improves the efficiency of the light-emitting control circuit.

[0064] For example, Figure 5 exemplarily shows that the light emitting control module includes two output modules 120, and the capacitance value of the first capacitor C1 in the first output module 120 can be set to be greater than the capacitance value of the first capacitor C1 in the second output module 120. In other embodiments, the light emitting control circuit may further include multiple output modules 120 and at least two shift modules 130. Figure 6 FIG1 is a structural diagram of another light emitting control circuit provided by an embodiment of the present invention. Figure 6 As shown, Figure 6The light-emitting control circuit exemplarily shows that it includes three output modules 120. The capacitance value of the first capacitor C1 in the first output module 120 can be set to be greater than the capacitance value of the first capacitor C1 in the second output module 120. This can ensure that the control electrode potential of the first output transistor TO1 in the second output module 120 is sufficiently low, thereby ensuring that the first output transistor TO1 in the second output module 120 is in the on state. Furthermore, the charging rate of the first electrode of the first capacitor C1 in the first output module 120 to the first electrode of the first capacitor C1 in the second output module 120 via the shift module 130 can be increased. At the same time, the capacitance value of the first capacitor C1 in the second output module 120 is greater than the capacitance value of the first capacitor C1 in the third output module 120. This can ensure that the control electrode potential of the first output transistor TO1 in the third output module 120 is sufficiently low, thereby ensuring that the first output transistor TO1 in the third output module 120 is in the on state. Furthermore, the charging rate of the first electrode of the first capacitor C1 in the second output module 120 to the first electrode of the first capacitor C1 in the third output module 120 through the shift module 130 can be increased.

[0065] Figure 7 FIG1 is a structural diagram of another light emitting control circuit provided by an embodiment of the present invention. Figure 7 As shown, the shift module 130 includes a first shift unit 131 and a second shift unit 132; the first end of the first shift unit 131 is connected to the control end of the first output subunit 1221 of the i-1th output module 120, the second end of the first shift unit 131 is connected to the control end of the i-th first output subunit 1221, the first end of the second shift unit 132 is connected to the output end OUT of the i-1th output module 120, and the second end of the second shift unit 132 is connected to the control end of the second output subunit 1222 of the i-th output module 120; when i is an even number, the control end of the first shift unit 131 and the control end of the second shift unit 132 are connected to the second clock signal input end CK2, and when i is an odd number, the control end of the first shift unit 131 and the control end of the second shift unit 132 are connected to the first clock signal input end CK1.

[0066] Specifically, when the first clock signal provided by the first clock signal input terminal CK1 and the second clock signal provided by the second clock signal input terminal CK2 are at a valid level, the first shift unit 131 and the second shift unit 132 are in a conducting state, thereby enabling signal transmission. Moreover, the first clock signal and the second clock signal are clock signals with opposite phases, so that the stage in which the first shift unit 131 and the second shift unit 132 in the previous shift module 130 are in a conducting state differs by one timing stage from the stage in which the first shift unit 131 and the second shift unit 132 in the next shift module 130 are in a conducting state, thereby enabling the shifting action of the shift module 130 to be realized, so that the next output module 120 outputs a light-emitting control signal under the shifting action of the shift module 130, thereby enabling the light-emitting control circuit to output a cascaded light-emitting control signal. For example, Figure 7 exemplarily shows that the light emitting control circuit includes three output modules 120 and two shift modules 130. The first shift unit 131 and the second shift unit 132 in the shift module 130 between the first output module 120 and the second output module 120 are connected to the second clock signal input terminal CK2, and the first shift unit 131 and the second shift unit 132 in the shift module 130 between the second output module 120 and the third output module 120 are connected to the first clock signal input terminal CK1. When the active level is low, the first clock signal provided by the first clock signal input terminal CK1 is high, and the second clock signal provided by the second clock signal input terminal CK2 is low, then the first shift unit 131 and the second shift unit 132 in the shift module 130 between the first output module 120 and the second output module 120 are in a conducting state. The first control signal provided by the first output module 120 is transmitted via the first shift unit 131 to the control terminal of the first output subunit 1221 of the second output module 120, thereby controlling the state of the first output subunit 1221 of the second output module 120. Simultaneously, the light emission control signal provided by the first output module 120 is transmitted via the second shift unit 132 to the control terminal of the second output subunit 1222 of the second output module 120, thereby controlling the state of the second output subunit 1222 of the second output module 120, thereby causing the second output module 120 to output the second light emission control signal based on the first control signal and the first light emission control signal. In the current stage, the first shift unit 131 and the second shift unit 132 in the shift module 130 between the second output module 120 and the third output module 120 are in an off state.

[0067] In the next phase, when the first clock signal provided by the first clock signal input terminal CK1 is at a low level, the second clock signal provided by the second clock signal input terminal CK2 is at a high level. At this time, the first shift unit 131 and the second shift unit 132 in the shift module 130 between the first output module 120 and the second output module 120 are in the off state. The first shift unit 131 and the second shift unit 132 in the shift module 130 between the second output module 120 and the third output module 120 are in the on state. The first control signal provided by the second output module 120 is transmitted via the first shift unit 131 to the control terminal of the first output subunit 1221 of the third output module 120, thereby controlling the state of the first output subunit 1221 of the third output module 120. At the same time, the light-emitting control signal provided by the second output module 120 is transmitted to the control end of the second output subunit 1222 of the third output module 120 through the second shift unit 132, controlling the state of the second output subunit 1222 of the third output module 120, so that the third output module 120 outputs a third light-emitting control signal according to the first control signal and the second light-emitting control signal.

[0068] Continue to refer Figure 7 The first shift unit 131 includes a second transistor T2, and the second shift unit 132 includes a third transistor T3; the first electrode of the second transistor T2 serves as the first end of the first shift unit 131, the second electrode of the second transistor T2 serves as the second end of the first shift unit 131, and the control electrode of the second transistor T2 serves as the control end of the first shift unit 131; the first electrode of the third transistor T3 serves as the first end of the second shift unit 132, the second electrode of the third transistor T3 serves as the second end of the second shift unit 132, and the control electrode of the third transistor T3 serves as the control end of the second shift unit 132.

[0069] Specifically, Figure 7 It is exemplarily shown that the second transistor T2 and the third transistor T3 are P-type transistors. At this time, the effective levels of the first clock signal and the second clock signal are low levels, and the first clock signal and the second clock signal alternately output low levels in turn, so that the second transistor T2 and the third transistor T3 in different shift modules 130 are alternately turned on in turn, so that the signal provided by the previous output module 120 can be shifted by the shift module 130 and output to the next output module 120, so that the next output module 120 outputs a cascaded light-emitting control signal according to the first control signal and the previous light-emitting control signal.

[0070] It should be noted that, in other embodiments, the second transistor T2 and the third transistor T3 can also be N-type transistors. In this case, the effective levels of the first clock signal and the second clock signal are high levels. The specific working process is similar to the above process and will not be repeated here.

[0071] Figure 8 FIG1 is a structural diagram of another light emitting control circuit provided by an embodiment of the present invention. Figure 8 As shown, the output module 120 also includes a fourth transistor T4; the fourth transistor T4 of the first output module 120 is connected between the node control module 110 and the clamping unit 121 of the first output module 120, the fourth transistor T4 of the i-th output module 120 is connected between the shift module 130 and the clamping unit 121 of the i-th output module 120, and the control electrode of the fourth transistor T4 is connected to the second power input terminal VGL.

[0072] Specifically, the second power signal provided by the second power input terminal VGL is a constant voltage signal, and by setting the second power signal to the effective level of the fourth transistor T4, the fourth transistor T4 can be kept in the on state. Figure 8 As shown, Figure 8 In the example shown in FIG, the fourth transistor T4 is a P-type transistor. In this case, the second power supply signal can be at a low level, causing the fourth transistor T4 to remain in the on state. By providing the fourth transistor T4 between the clamping unit 121 and the other modules, the output unit 122 and the shifting module 130 can be isolated. This prevents the potential drop at the output terminal of the shifting module 130 when the potential at the control terminal of the output unit 122 drops due to the action of the clamping unit 121. This prevents damage to the shifting module 130 caused by a large voltage difference between the control terminal and the output terminal of the shifting module 130.

[0073] Exemplarily, when the clamping unit 121 includes a pull-down subunit 1212, the pull-down subunit 1212 includes a second capacitor C2 and a first transistor T1, the output unit 122 includes a first output subunit 1221 and a second output subunit 1222, the first output subunit 1221 includes a first output transistor TO1, the second output subunit 1222 includes a second output transistor TO2, the shifting module 130 includes a second shifting unit 132, and the second shifting unit 132 includes a third transistor T3, when the second control signal output by the node control module 110 is at a low level, the first transistor T1 is turned on, and when the clock signal pulls down the second electrode potential of the second capacitor C2, the control electrode potential of the second output transistor TO2 can be made very low through the coupling effect of the second capacitor C2. At this time, by providing the fourth transistor T4, it is possible to prevent the control electrode potential of the second output transistor TO2 from being too low, thereby preventing the second electrode potential of the third transistor T3 from being too low, thereby preventing the third transistor T3 from being damaged due to a large voltage difference between the second electrode and the control electrode potentials of the third transistor T3.

[0074] It should be noted that Figure 8 The fourth transistor T4 is shown as a P-type transistor for example. In other embodiments, the fourth transistor T4 may also be an N-type transistor. Here, the second power signal provided by the second power input terminal VGL may be at a high level, so that the fourth transistor T4 is always in the on state.

[0075] Figure 9 FIG1 is a structural diagram of another light emitting control circuit provided by an embodiment of the present invention. Figure 9 As shown, the node control module 110 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a third capacitor C3; the first electrode of the fifth transistor T5 is used to input the input signal in, the second electrode of the fifth transistor T5 is connected to the control electrode of the sixth transistor T6, and serves as the second output end of the node control module 110; the control electrode of the fifth transistor T5 is used to input the first clock signal ck1; the first electrode of the sixth transistor T6 is used to input the first power supply signal Vgh, the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7, and serves as the first output end of the node control module 110; the first electrode of the seventh transistor T7 and the first electrode of the third capacitor C3 are used to input the first clock signal ck1, the control electrode of the seventh transistor T7 and the second electrode of the third capacitor C3 are connected to the second electrode of the eighth transistor T8; the first electrode of the eighth transistor T8 is used to input the first power supply signal Vgh, and the control electrode of the eighth transistor T8 is used to input the input signal in.

[0076] Specifically, Figure 9, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors. When the first power signal Vgh is at a high level and the second power signal Vgl is at a low level, the node control module 110 can generate the first control signal and the second control signal according to the input signal in, the first power signal Vgh, and the first clock signal ck1 to control the light emission control signal output by the output module 120. By way of example, Figure 10 for Figure 9 A timing diagram corresponding to the light emitting control circuit is provided. In which, in is the timing of the input signal provided by the input signal terminal IN, ck1 is the timing of the first clock signal provided by the first clock signal input terminal CK1, ck2 is the timing of the second clock signal provided by the second clock signal input terminal CK2, em1 is the timing of the light emitting control signal output by the output terminal OUT of the first output module 120, and em2 is the timing of the light emitting control signal output by the output terminal OUT of the second output module 120. Figure 9 and Figure 10 Explain the working process of the light-emitting control circuit.

[0077] In the first phase t11, the input signal in is at a high level, the first clock signal ck1 is at a low level, the second clock signal ck2 is at a high level, the fifth transistor T5 is turned on, and the eighth transistor T8 is turned off. The input signal in is transmitted to the second output terminal of the node control module 110 via the fifth transistor T5, causing the second control signal of the node control module 110 to be high. The second control signal is transmitted to the first second output transistor T02 via the fourth transistor T4, controlling the first second output transistor T02 to be turned off. Simultaneously, the second control signal controls the sixth transistor T6 to be turned off. Furthermore, the coupling effect of the third capacitor C3 can couple the low level of the first clock signal ck1 to the control electrode of the seventh transistor T7, causing the seventh transistor T7 to be turned on and transmit the first clock signal ck1 to the first output terminal of the node control module 110, causing the first control signal of the node control module 110 to be low. The first control signal controls the first first output transistor T01 to be turned on, and the first first output transistor T01 outputs the first power supply signal Vgh to the output terminal OUT of the first output module 120, causing the light emission control signal of the first output module 120 to be high. At the same time, the second clock signal ck2 controls the second transistor T2 and the third transistor T3 to be in the off state. The control electrode of the first output transistor TO1 in the second output module 120 is maintained at the high level of the previous stage by the first capacitor C1 in the second output module 120, turning off the first output transistor TO1 in the second output module 120. The control electrode of the second output transistor TO2 in the second output module 120 is maintained at the low level of the previous stage by the second capacitor C2 in the second output module 120, turning on the second output transistor TO2 in the second output module 120. The second output transistor TO2 outputs the second power supply signal Vgl to the output terminal OUT of the second output module 120, causing the light-emission control signal of the second output module 120 to be in the low level at this time.

[0078] In the second phase t12, the input signal in is at a high level, the first clock signal ck1 is at a high level, the second clock signal ck2 is at a low level, the fifth transistor T5 is turned off, and the eighth transistor T8 is turned off. The input signal in cannot be transmitted to the second output terminal of the node control module 110 through the fifth transistor T5, causing the node control module 110 to be unable to output the second control signal. At this time, the holding effect of the second capacitor C2 can maintain the control electrode of the first second output transistor TO2 at a high level, controlling the first second output transistor TO2 to be in an off state. At the same time, the coupling effect of the third capacitor C3 couples the low level of the first clock signal ck1 to the control electrode of the seventh transistor T7, causing the seventh transistor T7 to be turned off, preventing the node control module 110 from outputting the first control signal. The holding effect of the first first capacitor C1 can maintain the control electrode of the first first output transistor TO1 at a low level, controlling the first first output transistor TO1 to be in an on state. The first first output transistor TO1 outputs the first power supply signal Vgh to the output terminal OUT of the first output module 120, causing the light emission control signal of the first output module 120 to be high. At the same time, the second clock signal ck2 turns on the second transistor T2 and the third transistor T3. The control electrode potential of the first first output transistor TO1 is transmitted to the control electrode of the second first output transistor TO1 via the second transistor T2, turning on the second first output transistor TO1. The second first output transistor TO1 then outputs the first power supply signal Vgh to the output terminal OUT of the second output module 120, causing the light emission control signal of the second output module 120 to be high. Furthermore, the light emission control signal output by the first output module 120 is transmitted to the control electrode of the second second output transistor TO2 via the third transistor T3, turning off the second second output transistor TO2.

[0079] In the third phase t13, the input signal in is at a high level, the first clock signal ck1 is at a low level, the second clock signal ck2 is at a high level, the fifth transistor T5 is turned on, and the eighth transistor T8 is turned off. The input signal in is transmitted to the second output terminal of the node control module 110 via the fifth transistor T5, causing the second control signal of the node control module 110 to be high. The second control signal is transmitted to the first second output transistor T02 via the fourth transistor T4, controlling the first second output transistor T02 to be turned off. Simultaneously, the second control signal controls the sixth transistor T6 to be turned off. Furthermore, the coupling effect of the third capacitor C3 can couple the low level of the first clock signal ck1 to the control electrode of the seventh transistor T7, causing the seventh transistor T7 to be turned on and transmit the first clock signal ck1 to the first output terminal of the node control module 110, causing the first control signal of the node control module 110 to be low. The first control signal controls the first first output transistor T01 to be turned on, and the first first output transistor T01 outputs the first power supply signal Vgh to the output terminal OUT of the first output module 120, causing the light emission control signal of the first output module 120 to be high. At the same time, the second clock signal ck2 controls the second transistor T2 and the third transistor T3 to be in the off state. The control electrode of the first output transistor TO1 in the second output module 120 is maintained at the low level of the previous stage by the first capacitor C1 in the second output module 120, so that the first output transistor TO1 in the second output module 120 is in the on state. The second first output transistor TO1 outputs the first power supply signal Vgh to the output terminal OUT of the second output module 120, so that the light-emitting control signal of the second output module 120 is now at a high level. The control electrode of the second output transistor TO2 in the second output module 120 is maintained at the high level of the previous stage by the second capacitor C2 in the second output module 120, controlling the second second output transistor TO2 to be in the off state.

[0080] In the fourth phase t14, the input signal in is at a high level, the first clock signal ck1 is at a high level, the second clock signal ck2 is at a low level, the fifth transistor T5 is turned off, and the eighth transistor T8 is turned off. The input signal in cannot be transmitted to the second output terminal of the node control module 110 through the fifth transistor T5, causing the node control module 110 to be unable to output the second control signal. At this time, the holding effect of the second capacitor C2 can maintain the control electrode of the first second output transistor TO2 at a high level, controlling the first second output transistor TO2 to be in an off state. At the same time, the coupling effect of the third capacitor C3 couples the low level of the first clock signal ck1 to the control electrode of the seventh transistor T7, causing the seventh transistor T7 to be turned off, preventing the node control module 110 from outputting the first control signal. The holding effect of the first first capacitor C1 can maintain the control electrode of the first first output transistor TO1 at a low level, controlling the first first output transistor TO1 to be in an on state. The first first output transistor TO1 outputs the first power supply signal Vgh to the output terminal OUT of the first output module 120, causing the light emission control signal of the first output module 120 to be high. At the same time, the second clock signal ck2 turns on the second transistor T2 and the third transistor T3. The control electrode potential of the first first output transistor TO1 is transmitted to the control electrode of the second first output transistor TO1 via the second transistor T2, turning on the second first output transistor TO1. The second first output transistor TO1 then outputs the first power supply signal Vgh to the output terminal OUT of the second output module 120, causing the light emission control signal of the second output module 120 to be high. Furthermore, the light emission control signal output by the first output module 120 is transmitted to the control electrode of the second second output transistor TO2 via the third transistor T3, turning off the second second output transistor TO2.

[0081] In the fifth phase t15, the input signal in is at a low level, the first clock signal ck1 is at a low level, the second clock signal ck2 is at a high level, the fifth transistor T5 is turned on, and the eighth transistor T8 is turned on. The input signal in is transmitted to the second output terminal of the node control module 110 via the fifth transistor T5, causing the second control signal of the node control module 110 to be at a low level. The second control signal is transmitted to the first second output transistor TO2 via the fourth transistor T4, controlling the first second output transistor TO2 to be in a conductive state. The first second output transistor TO2 transmits the second power signal Vgl to the output terminal OUT of the first second output module 120, causing the light emission control signal of the first output module 120 to be at a low level. At the same time, the second control signal controls the sixth transistor T6 to be conductive, and the first power signal Vgh is transmitted to the first output terminal of the node control module 110 via the sixth transistor T6, causing the first control signal to be at a high level. The first control signal controls the first first output transistor TO1 to be in a cut-off state. The eighth transistor T8 can transmit the first power signal Vgh to the gate of the seventh transistor T7, controlling the seventh transistor T7 to be in a cut-off state. At the same time, the second clock signal ck2 controls the second transistor T2 and the third transistor T3 to be in the off state. The control electrode of the first output transistor TO1 in the second output module 120 is maintained at the low level of the previous stage by the first capacitor C1 in the second output module 120, controlling the second first output transistor TO1 to be in the on state. The second first output transistor TO1 outputs the first power supply signal Vgh to the output terminal OUT of the second output module 120, causing the light-emitting control signal of the second output module 120 to be in the high level at this time. The control electrode of the second output transistor TO2 in the second output module 120 is maintained at the high level of the previous stage by the second capacitor C2 in the second output module 120, controlling the second second output transistor TO2 to be in the off state.

[0082] In the sixth phase t16, the input signal in is at a low level, the first clock signal ck1 is at a high level, the second clock signal ck2 is at a low level, the fifth transistor T5 is turned off, and the eighth transistor T8 is turned on. The input signal in cannot be transmitted to the second output terminal of the node control module 110 through the fifth transistor T5, so that the node control module 110 cannot output the second control signal. At this time, the maintaining effect of the second capacitor C2 can keep the control terminal of the first second output transistor TO2 at a low level, controlling the first second output transistor TO2 to be in a conductive state. The first second output transistor TO2 transmits the second power supply signal Vgl to the output terminal OUT of the first second output module 120, causing the light emission control signal of the first output module 120 to be low. At the same time, the second control signal controls the sixth transistor T6 to be conductive, and the first power supply signal Vgh is transmitted to the first output terminal of the node control module 110 through the sixth transistor T6, causing the first control signal to be high, and the first control signal controls the first first output transistor TO1 to be in a cut-off state. In addition, the second control signal controls the first first transistor T1 to be turned on, and the clock signal input to the second electrode of the first first transistor T1 jumps from a high level to a low level, and through the coupling effect of the second capacitor C2, the control electrode potential of the first second output transistor TO2 is pulled down, thereby ensuring the conduction reliability of the first second output transistor TO2.

[0083] At the same time, the second clock signal ck2 turns on the second transistor T2 and the third transistor T3. The control electrode potential of the first first output transistor TO1 is transmitted via the second transistor T2 to the control electrode of the second first output transistor TO1, turning off the second first output transistor TO1. The light emission control signal output by the first output module 120 is transmitted via the third transistor T3 to the control electrode of the second second output transistor TO2, turning on the second second output transistor TO2. The second second output transistor TO2 then transmits the second power supply signal Vgl to the output terminal OUT of the second second output module 120, causing the light emission control signal of the second output module 120 to be low.

[0084] In the seventh phase t17, the input signal in is at a low level, the first clock signal ck1 is at a low level, the second clock signal ck2 is at a high level, the fifth transistor T5 is turned on, and the eighth transistor T8 is turned on. The input signal in is transmitted to the second output terminal of the node control module 110 via the fifth transistor T5, causing the second control signal of the node control module 110 to be at a low level. The second control signal is transmitted to the first second output transistor TO2 via the fourth transistor T4, controlling the first second output transistor TO2 to be in a conductive state. The first second output transistor TO2 transmits the second power signal Vgl to the output terminal OUT of the first second output module 120, causing the light emission control signal of the first output module 120 to be at a low level. At the same time, the second control signal controls the sixth transistor T6 to be conductive, and the first power signal Vgh is transmitted to the first output terminal of the node control module 110 via the sixth transistor T6, causing the first control signal to be at a high level. The first control signal controls the first first output transistor TO1 to be in a cut-off state. The eighth transistor T8 can transmit the first power signal Vgh to the gate of the seventh transistor T7, controlling the seventh transistor T7 to be in a cut-off state. At the same time, the second clock signal ck2 turns the second transistor T2 and the third transistor T3 off. The control electrode of the first output transistor TO1 in the second output module 120 is maintained at a high level from the previous stage by the first capacitor C1 in the second output module 120, turning the second first output transistor TO1 off. The control electrode of the second output transistor TO2 in the second output module 120 is maintained at a low level from the previous stage by the second capacitor C2 in the second output module 120, turning the second second output transistor TO2 on. The second second output transistor TO2 transmits the second power supply signal Vgl to the output terminal OUT of the second second output module 120, causing the light-emission control signal of the second output module 120 to be low.

[0085] In addition, the second first transistor T1 is turned on, and the clock signal input to the second electrode of the second first transistor T1 jumps from a high level to a low level, and through the coupling effect of the first second capacitor C2, the control electrode potential of the second second output transistor TO2 is pulled down, thereby ensuring the conduction reliability of the second second output transistor TO2.

[0086] In the eighth stage t18, the input signal in is at a low level, the first clock signal ck1 is at a high level, the second clock signal ck2 is at a low level, the fifth transistor T5 is turned off, and the eighth transistor T8 is turned on. The input signal in cannot be transmitted to the second output terminal of the node control module 110 through the fifth transistor T5, so that the node control module 110 cannot output the second control signal. At this time, the maintaining effect of the second capacitor C2 can keep the control terminal of the first second output transistor TO2 at a low level, controlling the first second output transistor TO2 to be in a conductive state. The first second output transistor TO2 transmits the second power supply signal Vgl to the output terminal OUT of the first second output module 120, causing the light emission control signal of the first output module 120 to be low. At the same time, the second control signal controls the sixth transistor T6 to be conductive, and the first power supply signal Vgh is transmitted to the first output terminal of the node control module 110 through the sixth transistor T6, causing the first control signal to be high, and the first control signal controls the first first output transistor TO1 to be in a cut-off state. At the same time, the second clock signal ck2 turns on the second transistor T2 and the third transistor T3. The control electrode potential of the first first output transistor TO1 is transmitted via the second transistor T2 to the control electrode of the second first output transistor TO1, turning off the second first output transistor TO1. The light emission control signal output by the first output module 120 is transmitted via the third transistor T3 to the control electrode of the second second output transistor TO2, turning on the second second output transistor TO2. The second second output transistor TO2 then transmits the second power supply signal Vgl to the output terminal OUT of the second second output module 120, causing the light emission control signal of the second output module 120 to be low.

[0087] It should be noted that Figure 9 The light emitting control circuit exemplarily includes two output modules 120 and one shift module 130. In other embodiments, the light emitting control circuit may further include multiple output modules 120 and at least two shift modules 130. When the light emitting control circuit includes multiple output modules 120 and at least two shift modules 130, the operating process of the mth output module 120 and the nth shift module 130 may repeat the above-described fifth stage t15 to eighth stage t18, which will not be further described here. m is an integer greater than or equal to 3, and n is an integer greater than or equal to 2.

[0088] Continue to refer Figure 9, the node control module 110 also includes a ninth transistor T9; when the pull-down subunit 1212 includes a second capacitor C2 and a first transistor T1; the first electrode of the ninth transistor T9 is used to input the first power supply signal, the second electrode of the ninth transistor T9 is connected to the second electrode of the second capacitor C2, and the control electrode of the ninth transistor T9 is connected to the first output end of the node control module 110.

[0089] Specifically, Figure 9 The ninth transistor T9 is exemplarily shown as a P-type transistor. When the potential of the first output terminal of the node control module 110 is low, the potential of the second output terminal of the node control module 110 is high. At this time, the ninth transistor T9 is turned on, and the first power supply signal can be transmitted to the second electrode of the second capacitor C2 through the ninth transistor T9, so that the second electrode of the second capacitor C2 is at a high level. At the same time, the first electrode of the second capacitor C2 is at a high level, which can maintain the potential of the first electrode of the second capacitor C2 at a high level, avoid misleading conduction of the second output transistor T02, and improve the reliability of the light-emitting control circuit.

[0090] An embodiment of the present invention further provides a light emitting control driver. Figure 11 A light emitting control driver is provided in an embodiment of the present invention. Figure 11 As shown, the light emitting control driver includes at least two stages of light emitting control circuits 100 provided by any embodiment of the present invention, and the at least two stages of light emitting control circuits 100 are cascaded.

[0091] Specifically, if Figure 11 As shown, an exemplary embodiment includes N (N is a positive integer) stages of light emitting control circuits 100. The light emitting control circuit 100 includes an input signal terminal IN, a first power input terminal VGH, a second power input terminal VGL, a first clock signal input terminal CK1, a second clock signal input terminal CK2, and at least two output terminals OUT. The input signal terminal IN of the first stage light emitting control circuit 100 is used to input an input signal, and the input signal terminal IN of the q+1th (q is an integer greater than or equal to 1 and less than N) stage light emitting control circuit 100 is electrically connected to the last output terminal OUT of the previous stage light emitting control circuit 100. The first clock signal and the second clock signal are respectively input to the first clock signal and the second clock signal. It can be seen from this that the same-level light-emitting control circuit 100 can output at least two light-emitting control signals step by step, and the input signal of the next-level light-emitting control circuit 100 is the last light-emitting control signal output by the previous-level light-emitting control circuit 100. When the previous-level light-emitting control circuit 100 outputs the last light-emitting control signal, the next-level light-emitting control circuit 100 is started to work, and then the light-emitting control signal is output, thereby realizing the light-emitting control driver outputting the light-emitting control signal step by step.

[0092] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A light emitting control circuit, characterized in that: It includes a node control module, at least two output modules and at least one shift module; The node control module is configured to generate a control signal based on an input signal, a first clock signal, and a first power supply signal; the output module includes a clamping unit and an output unit; the clamping unit of the first output module is connected to the node control module, the clamping unit is configured to clamp the control signal, and the output unit is connected to the clamping unit, the output unit is configured to output a light-emitting control signal based on the control signal; the clamping unit of the i-th output module is connected to the output unit of the i-1-th output module via a shifting module, the shifting module is configured to shift the input signal and output it to the next output module; wherein i is an integer greater than or equal to 2; The node control module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third capacitor; The first electrode of the fifth transistor is used to input the input signal, the second electrode of the fifth transistor is connected to the control electrode of the sixth transistor and serves as the second output terminal of the node control module; the control electrode of the fifth transistor is used to input the first clock signal; The first electrode of the sixth transistor is used to input the first power supply signal, and the second electrode of the sixth transistor is connected to the second electrode of the seventh transistor and serves as the first output terminal of the node control module; The first electrode of the seventh transistor and the first electrode of the third capacitor are used to input the first clock signal, and the control electrode of the seventh transistor and the second electrode of the third capacitor are connected to the second electrode of the eighth transistor; The first electrode of the eighth transistor is used to input the first power supply signal, and the control electrode of the eighth transistor is used to input the input signal; The clamping unit includes a pull-up subunit and a pull-down subunit, and the output unit includes a first output subunit and a second output subunit; The first end of the pull-up subunit of the first clamping unit and the control end of the first output subunit of the first output unit are connected to the first output end of the node control module, the first end of the pull-up subunit of the i-th clamping unit and the control end of the first output subunit of the i-th output unit are connected to the control end of the first output subunit of the i-1-th output unit via the shift module; the second end of the pull-up subunit and the first end of the first output subunit are connected to the first power input end, the second end of the first output subunit is connected to the second end of the second output subunit, and serve as the output end of the output module; When i is an even number, the second end of the pull-down subunit of the i-th clamping unit is connected to the first clock signal input end, and when i is an odd number, the second end of the pull-down subunit of the i-th clamping unit is connected to the second clock signal input end; wherein the timing sequence of the first clock signal provided by the first clock signal input end is opposite to the timing sequence of the second clock signal provided by the second clock signal input end; The first end of the second output subunit is connected to the second power input end; The shift module includes a first shift unit and a second shift unit; The first end of the first shift unit is connected to the control end of the first output subunit of the i-1th output module, the second end of the first shift unit is connected to the control end of the i-th first output subunit, the first end of the second shift unit is connected to the output end of the i-1th output module, and the second end of the second shift unit is connected to the control end of the second output subunit of the i-th output module; when i is an even number, the control end of the first shift unit and the control end of the second shift unit are connected to the second clock signal input end, and when i is an odd number, the control end of the first shift unit and the control end of the second shift unit are connected to the first clock signal input end.

2. The light emitting control circuit according to claim 1, characterized in that: The first end and the control end of the pull-down subunit of the first clamping unit and the control end of the second output subunit of the first output unit are connected to the second output end of the node control module, the second end of the pull-down subunit of the first clamping unit is connected to the second clock signal input end, and the first end and the control end of the pull-down subunit of the i-th clamping unit and the control end of the second output subunit of the i-th output unit are connected to the output end of the (i-1)-th output module through a shift module.

3. The light emitting control circuit according to claim 2, characterized in that: The pull-up subunit includes a first capacitor, the pull-down subunit includes a second capacitor and a first transistor, the first output subunit includes a first output transistor, and the second output subunit includes a second output transistor; The first electrode of the first capacitor serves as the first end of the pull-up sub-unit, and the second electrode of the first capacitor serves as the second end of the pull-up sub-unit; The first electrode of the second capacitor serves as the first end of the pull-down subunit, the second electrode of the second capacitor is connected to the first electrode of the first transistor, the control electrode of the first transistor serves as the control end of the pull-down subunit, and the second electrode of the first transistor serves as the second end of the pull-down subunit; The control electrode of the first output transistor serves as the control terminal of the first output sub-unit, the first electrode of the first output transistor serves as the first terminal of the first output sub-unit, and the second electrode of the first output transistor serves as the second terminal of the first output sub-unit; The control electrode of the second output transistor serves as the control terminal of the second output subunit, the first electrode of the second output transistor serves as the first terminal of the second output subunit, and the second electrode of the second output transistor serves as the second terminal of the second output subunit.

4. The light emitting control circuit according to claim 3, characterized in that: The capacitance value of the first capacitor in the i-th output module is smaller than the capacitance value of the first capacitor in the (i-1)-th output module.

5. The light emitting control circuit according to claim 1, wherein: The first shift unit includes a second transistor, and the second shift unit includes a third transistor; The first electrode of the second transistor serves as the first end of the first shift unit, the second electrode of the second transistor serves as the second end of the first shift unit, and the control electrode of the second transistor serves as the control end of the first shift unit; The first electrode of the third transistor serves as the first end of the second shift unit, the second electrode of the third transistor serves as the second end of the second shift unit, and the control electrode of the third transistor serves as the control end of the second shift unit.

6. The light emitting control circuit according to claim 1, wherein: The output module further includes a fourth transistor; The fourth transistor of the first output module is connected between the node control module and the clamping unit of the first output module, the fourth transistor of the i-th output module is connected between the shift module and the clamping unit of the i-th output module, and the control electrode of the fourth transistor is connected to the second power supply input terminal.

7. The light emitting control circuit according to claim 1, characterized in that: The node control module further includes a ninth transistor; and the pull-down subunit includes a second capacitor and a first transistor; The first electrode of the ninth transistor is used to input the first power supply signal, the second electrode of the ninth transistor is connected to the second electrode of the second capacitor, and the control electrode of the ninth transistor is connected to the first output end of the node control module.

8. A light emitting control driver, characterized in that: The light emitting control circuit comprises at least two stages as described in any one of claims 1 to 7, wherein the at least two stages of the light emitting control circuit are cascaded.

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