Mac array based on resistive random access memory and mac array operation method

Abstract

The application provides a MAC array based on a resistive memory, 1T1R resistive memory cells storing the same bit with different weights are distributed on adjacent and continuous multiple bit lines; 1T1R resistive memory cells storing different bits with the same weight are distributed on the same bit line and are spaced by 2 n bit lines; each 1T1R resistive memory cell comprises a transistor-resistive memory; the resistive memory comprises a resistor connected with the transistor; a word line is used for transmitting an input signal; a source line applies a voltage to the resistor to form a bias current on the bit line; an ADC module converts the bias current in the bit line to form a digital product operation result; and a shift adder is used for summing the digital product operation result to obtain a MAC operation result; in this way, only one row of word lines is opened each time, multiple bit lines are connected to the same ADC, analog-digital conversion and summation operation are realized, and therefore the influence of parasitic parameters is greatly reduced when calculating their current sum.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and more particularly to a MAC array based on resistive random access memory and a MAC array operating method. Background Art

[0002] Multiplication and addition (MAC) is the most important calculation method of neural network, which represents the sum of the products of two groups of numbers (A0, A1, A2…) (B0, B1, B2…) (A0·B0+A1·B1+A2·B2+…). Resistive random access memory (RRAM), as a non-volatile memory, uses the resistance state of the device to store information. When voltage is applied to both ends of the device, the input voltage and the device resistance represent 1-bit signals respectively, and the multiplication operation is realized in the form of output current. The sum of multiple output currents represents the sum of the products of multiple 1-bit input signals and 1-bit stored information, that is, the MAC operation. The MAC array based on resistive random access memory (RRAM) has the characteristics of high density, low cost and high energy efficiency. The present invention proposes a MAC operation array architecture based on resistive random access memory, which significantly improves the calculation speed by utilizing the time domain distinction of the input signal while ensuring high calculation accuracy.

[0003] However, because the actual size of a resistive random access memory array typically exceeds 1Mb, the long WL / BL wiring leads to a large amount of parasitic resistance / capacitance. This results in significant current drift when calculating the same product between the memory cells and the WL input signals at different locations in the array. This further reduces the distinction between the sums of the different products and the corresponding total currents. In severe cases, it can even cause the different products and corresponding current ranges to overlap, resulting in read errors. In a 1Mb RRAM MAC array using a 28nm process, the traditional method of reading the current difference between the best / worst WL / BL parasitic positions causes the MAC summed current range to overlap significantly in the best / worst cases, leading to read errors. To address this problem, each ADC needs to be individually modulated. However, given the demand for high computing power and large arrays, this greatly increases the difficulty of circuit design and testing costs, and severely reduces the accuracy of MAC operations.

[0004] Therefore, there is an urgent need for a MAC array and operation method based on resistive random access memory that significantly reduces the calculation result error caused by the resistance value difference of resistive random access memory devices and large array parasitic parameters, and minimizes the accuracy loss. Summary of the Invention

[0005] In view of the above-mentioned problems, the present invention aims to provide a MAC array based on resistive random access memory (RRAM) to solve the problem that, because the actual size of RRAM arrays typically exceeds 1 Mb, the long WL / BL wiring leads to a large amount of parasitic resistance / capacitance. As a result, when calculating, the currents of memory cells and WL input signals at different locations in the array will drift significantly even when the products are the same. This further reduces the differentiation between the sums of different products and the corresponding total currents. In severe cases, the ranges of different products and corresponding currents may even overlap, resulting in read errors. The ranges of MAC summed currents also overlap significantly, leading to read errors, increasing the difficulty of circuit design and testing costs, and seriously reducing the accuracy of MAC operations.

[0006] The present invention provides a MAC array based on resistive memory, comprising a 1T1R resistive memory cell, a word line, a source line, a bit line, an ADC module and a shift adder, characterized in that:

[0007] 1T1R resistive memory cells storing the same bit with different weights are distributed on a plurality of adjacent and continuous bit lines; wherein the interval between the bit lines is less than or equal to 8;

[0008] 1T1R resistive memory cells storing different bits with the same weight are distributed on the same bit line and are arranged in a 2 n The word lines are spaced; n is less than or equal to 5;

[0009] Each 1T1R resistive memory cell includes a transistor-resistive memory;

[0010] The resistive memory includes a resistor, the resistor is connected to the transistor, and the resistance can be high or low;

[0011] The word line is connected to the gate terminal of the transistor, the word line is controlled by a decoder, and the word line is used to transmit an input signal;

[0012] The source line and the 1T1R resistive memory cell, wherein the source line is used to apply a voltage to the resistor to form a bias current on the bit line;

[0013] The ADC module is connected to the bit line, and all the bit lines share one ADC module, and the ADC module is used to convert the bias current in the bit line to form a digital product operation result;

[0014] The shift adder is used to sum the digital product operation results to obtain a MAC operation result.

[0015] Preferably, the bias current is generated based on the input signal and the voltage, reflecting a product of the input signal and the resistance.

[0016] Preferably, the control unit is further included,

[0017] The control unit is used to simultaneously open a row of word lines and multiple bit lines to perform MAC operation.

[0018] Preferably, the control unit is further used to perform a set operation and a reset operation on the row of word lines before simultaneously opening the row of word lines.

[0019] Preferably, the set operation is that the bit lines and the word lines are applied with high voltage, and the source lines are grounded.

[0020] The reset operation is that the word lines and the source lines are applied with high voltage, and the bit lines are grounded.

[0021] Preferably, the voltage value of the word lines in the set operation is less than half of the voltage value in the reset operation.

[0022] The application further provides a MAC array operation method based on resistive random access memory, which is implemented based on the MAC array based on resistive random access memory as described above, and includes:

[0023] Simultaneously opening a row of word lines, bit lines with a preset interval, and source lines in the MAC array based on resistive random access memory;

[0024] Transmitting an input signal based on the word lines, and applying voltage to resistors in the MAC array based on resistive random access memory based on the source lines to form a bias current on the bit lines;

[0025] Converting the bias current in the bit lines by an ADC module in the MAC array based on resistive random access memory to form a digital product operation result;

[0026] Summing the digital product operation result by a shift adder in the MAC array based on resistive random access memory to obtain a MAC operation result.

[0027] Preferably, a set operation and a reset operation are performed on the row of word lines before simultaneously opening the row of word lines.

[0028] The set operation is that the bit lines and the word lines are applied with high voltage, and the source lines are grounded.

[0029] The reset operation is that the word lines and the source lines are applied with high voltage, and the bit lines are grounded.

[0030] As can be seen from the above technical solution, the MAC array based on resistive memory provided by the present invention includes 1T1R resistive memory cells, word lines, source lines, bit lines, ADC modules and shift adders, wherein the 1T1R resistive memory cells storing the same bits with different weights are distributed on a plurality of adjacent continuous bit lines; wherein the interval between the bit lines is less than or equal to 8; the 1T1R resistive memory cells storing different bits with the same weight are distributed on the same bit line, and ... n The resistive memory comprises a transistor-resistive memory; the resistive memory comprises a resistor, the resistor is connected to the transistor, and the resistor can be high or low; the word line is connected to the gate end of the transistor, the word line is controlled by a decoder, and the word line is used to transmit an input signal; the source line is connected to the 1T1R resistive memory cell, and the source line is used to apply a voltage to the resistor to form a bias current on the bit line, the ADC module is connected to the bit line, and all the bit lines share one ADC module, the ADC module is used to convert the bias current in the bit line to form a digital product operation result, and the shift adder is used to sum the digital product operation result to obtain MAC operation results, thus, there is enough space to configure a higher-precision ADC module. At the same time, the use of a high-precision ADC module can achieve better optimization of area and power consumption. In addition, during actual operation, only one row of WL (word line) is opened at a time, and multiple BL (bit line) is connected to the same ADC to achieve analog-to-digital conversion and summation operations. A larger-scale summation is performed on the periphery through an adder tree, thereby having the advantage of high parallelism of analog summation and can effectively limit the error to an allowable range. At the same time, for all 1T1R units in the same WL, their BL parasitic parameters are basically the same. Therefore, when calculating their current sum, the impact of the parasitic parameters is greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] By referring to the following description in conjunction with the accompanying drawings, and with a more complete understanding of the present invention, other objects and results of the present invention will become more apparent and easier to understand. In the accompanying drawings:

[0032] Figure 1 A schematic diagram of a MAC array based on a resistive random access memory according to an embodiment of the present invention;

[0033] Figure 2 Flowchart of a MAC array operating method based on resistive random access memory according to an embodiment of the present invention; DETAILED DESCRIPTION

[0034] Due to the actual size of the resistance change memory array is usually more than 1Mb, wherein the longer WL / BL wiring leads to a large amount of parasitic resistance / capacitance, resulting in the calculation, the different locations of the storage unit in the array and the WL input signal have a large drift at the same product, and further reduce the different product and the corresponding total current of the sum of the degree of distinction, in serious case, even cause the different product and the corresponding current range overlap, produce reading error; in the 1Mb RRAM MAC array of 28nm process, the current reading difference of the traditional method in the optimal / worst position of WL / BL parasitic is in the optimal / worst case, the range of MAC summation current occurs serious overlap, resulting in reading error; in order to solve this problem, it is necessary to modulate each ADC individually, but this greatly increases the difficulty and test cost of circuit design under the demand of large algorithmic large array, seriously reduces the precision of MAC operation. In view of the above problems, the present application provides a MAC array based on resistance change memory, which will be described in detail below in combination with the accompanying drawings.

[0035] In order to illustrate the MAC array based on resistance change memory and the operation method provided by the present application, Figure 1 The MAC array based on resistance change memory of the embodiment of the present application is exemplarily indicated; Figure 2 The operation method of the MAC array based on resistance change memory of the embodiment of the present application is exemplarily indicated.

[0036] The following exemplary embodiment description is actually merely illustrative, by no means as any limitation on the present application and its application or use. The technology and equipment known to those skilled in the relevant art may not be discussed in detail, but in appropriate cases, the technology and equipment should be regarded as part of the specification.

[0037] As Figure 1 The MAC array based on resistance change memory of the embodiment of the present application, as shown in the figure, comprises 1T1R resistance change memory unit, word line, source line, bit line, ADC module and shift adder, wherein the 1T1R resistance change memory unit storing the same bit with different weights is distributed on the adjacent continuous bit line; wherein the interval of the bit line is less than or equal to 8; the 1T1R resistance change memory unit storing the different bit with the same weight is distributed on the same bit line, and the interval of the bit line is 2 nIn this embodiment, 1T1R cells storing the same bit with different weights are distributed on adjacent BLs (bit lines). That is, 1T1R resistive memory cells storing the same bit with different weights are distributed on multiple adjacent, continuous bit lines. In this way, when performing MAC operations on the same bit, the parasitic parameters between the 1T1R cells are very close, which can avoid summation errors of the products of the same bit. Different bits of the same weight are distributed on the same BL, not continuously, but at intervals of 4 / 8 / 16 / 32 WLs. In this embodiment, the interval between bit lines is less than or equal to 8. Taking 4 WLs as an example, WL0 connects to the cell corresponding to weight B00, WL4 connects to the cell corresponding to weight B01, and WL8 connects to the cell corresponding to weight B02. By distributing different bits of the same weight, the accuracy of high-bit operations is effectively improved. In AI operations, low-bit operation errors are usually negligible. Therefore, this method can effectively improve overall operation accuracy.

[0038] exist Figure 1 In the illustrated embodiment, each 1T1R resistive memory cell comprises a transistor-resistive memory; the resistive memory includes a resistor, which is connected to the transistor and has a resistance that can be high or low. A word line is connected to the gate terminal of the transistor, controlled by a decoder, and used to transmit an input signal. A source line is connected to the 1T1R resistive memory cell, and the source line is used to apply a voltage to the resistor to form a bias current on the bit line. An ADC module is connected to the bit line and is used to convert the bias current in the bit line to form a digital product operation result. The shift adder is used to sum the digital product operation results to obtain a MAC operation result. In this embodiment, all bit lines are connected to the same ADC, and multiple BLs are connected to the same ADC to implement analog-to-digital conversion of multi-bit product sums of multiple weights and multiple input signals, and a larger-scale summation is performed peripherally through an adder tree. This can reduce the occupied space, improve space utilization, and increase operation speed.

[0039] In actual operations, only one row of WLs is opened at a time, and multiple BLs are connected to the same ADC to perform analog-to-digital conversion and summation. A larger summation is then performed on the periphery via an adder tree. This method offers the advantage of high parallelism in analog summation and effectively limits errors to within an acceptable range.

[0040] Specifically, each transistor-resistive random access memory (1T1R) unit is used to store one bit of weight, which represents 0 when the R resistance is high and represents 1 when the R resistance is low; the WL (word line) is controlled by a decoder and is used to transmit the input signal; the SL (source line) is used to apply a fixed read voltage and form a bias current on the BL (bit line), which is then processed by the ADC to produce a MAC operation result; when the WL of the 1T1R unit is set to a high level, it indicates that the input signal is 1; since the current is large when the 1T1R unit stores 1, it indicates that the product of the input signal and the 1T1R unit is 1; when the 1T1R unit stores 0 or the WL is not selected, the BL current where the unit is located is very low, indicating that the product of the input signal and the 1T1R unit is 0; in this embodiment, the bias current is generated based on the input signal and the voltage, reflecting the product of the input signal and the resistance. By simultaneously turning on a row of WLs, these currents representing the products can be formed into a total current, thereby achieving the summation of the products.

[0041] In this embodiment, a control unit is further included, which is used to simultaneously open a row of word lines and multiple bit lines at preset intervals to perform a subsequent MAC operation and complete the sum operation of the product of the input signal and the resistance; the control unit is also used to perform a set operation and a reset operation on a row of word lines before simultaneously opening a row of word lines; wherein the set operation is: applying a high voltage to the bit line and the word line, and grounding the source line; the reset operation is: applying a high voltage to the word line and the source line, and grounding the bit line; wherein the voltage value of the word line in the set operation is less than half of the voltage value in the reset operation.

[0042] In a specific embodiment, during the calculation operation, a row of WL is opened at the same time each time, the WL interval is 4, and the BL interval is 8. The actual situation can be adjusted to 4, 8, 16, 32, etc. as needed, and calculated as int8 (can be adjusted according to the actual application). The 0th bit of B0-B7 is distributed on WL0, and the 0th to 7th bits of B0 are distributed on BL0, and are located on WL0, WL4, WL8, WL12, WL16, WL20, WL24, WL28. The rest of the weights are deduced by analogy. Each time a calculation is performed, a certain WL (such as WL0) is opened, and BL0-BL7 input the 0th to 7th bits of A0-A7 in sequence, and then the output currents of multiple BLs are converted into product sums through ADC. Figure 1 As shown, since the ADC converts the current sum of the results of multiple BLs, a current mode ADC is required, but the ADC density is relatively low. Figure 1 The significant reduction is beneficial to the layout and wiring design. At the same time, for all 1T1R units in the same WL, the BL parasitic parameters are basically the same. Therefore, when calculating their current sum, the impact of the parasitic parameters is greatly reduced.

[0043] And, since the ADC module is shared by multiple BLs, the space in the lateral length of the ADC module is greatly expanded, and the space utilization is greatly improved Figure 1 The design shown in the prior art corresponds to one ADC for one BL, and the space utilization of the present application has greater advantages. Therefore, an ADC module with higher precision and larger area can be configured to implement the summation of more BLs, effectively improving the parallelism, that is, the overall operation speed.

[0044] As described above, the MAC array based on the resistive memory provided by the present application comprises 1T1R resistive memory cells, word lines, source lines, bit lines, ADC modules and shift adders, and the 1T1R resistive memory cells storing the same bit with different weights are distributed on multiple adjacent and continuous bit lines; wherein the interval of the bit lines is less than or equal to 8; the 1T1R resistive memory cells storing different bits with the same weight are distributed on the same bit line, and the interval is 2 n word lines; each 1T1R resistive memory cell comprises a transistor-resistive memory; the resistive memory comprises a resistor connected to the transistor, and the resistor can be high or low; the word line is connected to the gate end of the transistor, and the word line is controlled by a decoder, and the word line is used to transmit an input signal; the source line is connected to the 1T1R resistive memory cell, and the source line is used to apply a voltage to the resistor to form a bias current on the bit line; the ADC module is connected to the bit line, and all the bit lines share one ADC module; the ADC module is used to convert the bias current in the bit line to form a digital product operation result; the shift adder is used to sum the digital product operation result to obtain a MAC operation result; in this way, there is enough space to configure a higher precision ADC module, and using a high precision ADC module can achieve better optimization of area and power consumption, and in actual operation, only one row of WL (word line) is opened each time, multiple BLs (bit lines) are connected to the same ADC, analog-to-digital conversion and summation operation are realized, and a larger scale summation is realized through an addition tree in the periphery, thereby having the advantages of high parallelism of analog summation, and the error can be effectively limited within the allowable range; at the same time, for all 1T1R units of the same WL, the BL parasitic parameters of the 1T1R units are basically consistent, so the influence of the parasitic parameters is greatly reduced when calculating their current and.

[0045] As shown in Figure 2 The present application also provides a MAC array operation method based on resistive memory, which is realized based on the MAC array based on resistive memory as described above, comprising:

[0046] S1: simultaneously opening a row of word lines, a predetermined interval of bit lines and source lines in the MAC array based on resistive memory;

[0047] S2: transmitting an input signal based on the word line, applying a voltage to the resistors in the MAC array based on the resistive memory based on the source line, so as to form a bias current on the bit line;

[0048] S3: converting the bias current in the bit line by an ADC module in the MAC array based on the resistive memory to form a digital product operation result;

[0049] S4: summing the digital product operation results through the shift adder in the MAC array based on the resistive random access memory to obtain a MAC operation result.

[0050] Before simultaneously opening a row of word lines, performing a set operation and a reset operation on the row of word lines;

[0051] The set operation is as follows: a high voltage is applied to the bit line and the word line, and the source line is grounded;

[0052] The reset operation is as follows: a high voltage is applied to the word line and the source line, and the bit line is grounded.

[0053] Specifically, during operation, all bit lines are connected to the same ADC, and multiple BLs are connected to the same ADC to realize the analog-to-digital conversion of multi-bit products and sums of multiple weights and multiple input signals, and perform larger-scale summation through the addition tree on the periphery, which can reduce the occupied space, improve space utilization, and increase the operation speed.

[0054] In actual operations, only one row of WLs is opened at a time, and multiple BLs are connected to the same ADC to perform analog-to-digital conversion and summation. A larger summation is then performed on the periphery via an adder tree. This method offers the advantage of high parallelism in analog summation and effectively limits errors to within an acceptable range.

[0055] In a specific embodiment, during the calculation operation, a row of WL is opened at the same time each time, the WL interval is 4, and the BL interval is 8. The actual situation can be adjusted to 4, 8, 16, 32, etc. as needed, and calculated as int8 (can be adjusted according to the actual application). The 0th bit of B0-B7 is distributed on WL0, and the 0th to 7th bits of B0 are distributed on BL0, and are located on WL0, WL4, WL8, WL12, WL16, WL20, WL24, WL28. The rest of the weights are deduced by analogy. Each time a calculation is performed, a certain WL (such as WL0) is opened, and BL0-BL7 input the 0th to 7th bits of A0-A7 in sequence, and then the output currents of multiple BLs are converted into product sums through ADC. Figure 1 As shown, since the ADC converts the current sum of the results of multiple BLs, a current mode ADC is required, but the ADC density is relatively low. Figure 1The significant reduction is beneficial to the layout and wiring design. At the same time, for all 1T1R units in the same WL, the BL parasitic parameters are basically the same. Therefore, when calculating their current sum, the impact of the parasitic parameters is greatly reduced.

[0056] Moreover, since the ADC module is shared by multiple BLs, the horizontal length of the ADC module is greatly expanded. Figure 1 The design shown here corresponds to one ADC per BL, which has a greater advantage in space utilization. Therefore, a higher-precision, larger-area ADC module can be configured to achieve the summation of more BLs, effectively improving the degree of parallelism, that is, the overall computing speed.

[0057] It can be seen from the above embodiments that the MAC array operation method based on resistive memory provided by the present invention is implemented based on the MAC array based on resistive memory as described above. First, a row of word lines, bit lines and source lines at preset intervals in the MAC array based on resistive memory are simultaneously opened; then, input signals are transmitted based on the word lines, and voltages are applied to resistors in the MAC array based on resistive memory based on the source lines to form bias currents on the bit lines; then, the bias currents in the bit lines are converted by the ADC module in the MAC array based on resistive memory to form digital product operation results; finally, the ADC module in the MAC array based on resistive memory is used to generate digital product operation results. The shift adder in the MAC array based on the resistive random access memory sums the digital product operation results to obtain the MAC operation result. In this way, during actual operation, only one WL (word line) row is opened at a time, and multiple BLs (bit lines) are connected to the same ADC to achieve analog-to-digital conversion and summation operations. A larger-scale summation is performed in the periphery through an adder tree, thereby achieving the advantage of high parallelism of analog summation and effectively limiting errors to within an allowable range. At the same time, for all 1T1R cells in the same WL, their BL parasitic parameters are basically consistent, so the impact of the parasitic parameters is greatly reduced when calculating their current sum.

[0058] The above description of the resistive random access memory (RRAM)-based MAC array and operating method according to the present invention is described by way of example with reference to the accompanying drawings. However, those skilled in the art will appreciate that various improvements may be made to the RRAM-based MAC array and operating method according to the present invention without departing from the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A MAC array based on resistive memory, comprising a 1T1R resistive memory cell, a word line, a source line, a bit line, an ADC module and a shift adder, characterized in that: 1T1R resistive memory cells storing the same bit with different weights are distributed on a plurality of adjacent and continuous bit lines; wherein the interval between the bit lines is less than or equal to 8; 1T1R resistive memory cells storing different bits with the same weight are distributed on the same bit line and are arranged in a 2 n The word lines are spaced; n is less than or equal to 5; Each 1T1R resistive memory cell includes a transistor-resistive memory; The resistive memory includes a resistor, the resistor is connected to the transistor, and the resistance can be high or low; The word line is connected to the gate terminal of the transistor, the word line is controlled by a decoder, and the word line is used to transmit an input signal; The source line and the 1T1R resistive memory cell, wherein the source line is used to apply a voltage to the resistor to form a bias current on the bit line; The ADC module is connected to the bit line, and all the bit lines share one ADC module, and the ADC module is used to convert the bias current in the bit line to form a digital product operation result; The shift adder is used to sum the digital product operation results to obtain a MAC operation result.

2. The MAC array based on resistive random access memory according to claim 1, wherein: The bias current is generated based on the input signal and the voltage, reflecting a product of the input signal and the resistance.

3. The MAC array based on resistive random access memory according to claim 2, wherein: Also includes a control unit, The control unit is used to simultaneously open a row of word lines and a plurality of bit lines to perform MAC operations.

4. The MAC array based on resistive random access memory according to claim 3, wherein: The control unit is further configured to perform a set operation and a reset operation on a row of word lines before simultaneously opening the row of word lines.

5. The MAC array based on resistive random access memory according to claim 4, wherein: The set operation is as follows: a high voltage is applied to the bit line and the word line, and the source line is grounded; The reset operation is as follows: a high voltage is applied to the word line and the source line, and the bit line is grounded.

6. The MAC array based on resistive random access memory according to claim 5, wherein: The voltage value of the word line in the set operation is less than half of the voltage value in the reset operation.

7. A method for operating a MAC array based on a resistive random access memory, implemented based on the MAC array based on a resistive random access memory according to any one of claims 1 to 6, comprising: Simultaneously turning on a row of word lines, bit lines at preset intervals, and source lines in a MAC array based on a resistive random access memory; Transmitting an input signal based on the word line, applying a voltage to a resistor in the MAC array based on the resistive memory based on the source line to form a bias current on the bit line; Converting the bias current in the bit line by an ADC module in the MAC array based on the resistive memory to form a digital product operation result; The digital product operation results are summed by a shift adder in the MAC array based on the resistive random access memory to obtain a MAC operation result.

8. The method for operating a MAC array based on a resistive random access memory according to claim 7, wherein: Before simultaneously opening a row of word lines, performing a set operation and a reset operation on the row of word lines; The set operation is as follows: a high voltage is applied to the bit line and the word line, and the source line is grounded; The reset operation is as follows: a high voltage is applied to the word line and the source line, and the bit line is grounded.

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