Semiconductor structure and method of manufacturing the same
By forming metal silicides on the drain or source regions of the transistor, the problem of insufficient gate current drive capability of VGAA transistors is solved, realizing efficient current drive of transistors, which is suitable for new types of memory such as MRAM, PCRAM and FeRAM.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-06-24
- Publication Date
- 2026-06-05
AI Technical Summary
In the prior art, the gate current driving capability of vertically all-encompassing gate (VGAA) transistors is insufficient, which cannot meet the driving requirements of new non-volatile memories such as MRAM, PCRAM and FeRAM.
Metal silicides are formed on the drain or source region of a transistor and reacted with semiconductor pillars through heat treatment to reduce the contact resistance between the transistor drain region and the storage structure, thereby improving the gate current drive capability.
It effectively reduces the contact resistance between the transistor drain region and the memory structure, improves the gate current driving capability of the transistor, and meets the driving requirements of new memory.
Smart Images
Figure CN115274415B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] Vertically all-enclosed gate (VGAA) transistors are an emerging technology that continues the existing semiconductor technology roadmap, further enhancing gate control capabilities and overcoming the physical scaling and performance limitations of current technologies. However, enhancing the transistor's gate current drive capability remains a significant challenge. Summary of the Invention
[0003] Based on this, embodiments of this application provide a semiconductor structure and its fabrication method to improve the gate current driving capability of a transistor.
[0004] A method for fabricating a semiconductor structure, comprising:
[0005] A transistor structure is formed, the transistor structure including a transistor and a first dielectric layer, the transistor including a semiconductor pillar and a gate structure at least partially surrounding the semiconductor pillar, a source region or a drain region being formed at the top of the semiconductor pillar, the first dielectric layer surrounding the transistor, and the upper surface of the first dielectric layer being flush with the top surface of the semiconductor pillar.
[0006] A metal material layer is formed on the upper surface of the first dielectric layer and the top surface of the semiconductor pillar;
[0007] The metal material layer is heat-treated to react with the top of the semiconductor pillar to form a metal silicide;
[0008] Remove the unreacted layer of the metallic material;
[0009] A storage structure is formed on the metal silicide.
[0010] In one embodiment, prior to forming the memory structure on the metal silicide, the method further includes:
[0011] The upper surface of the first dielectric layer and the upper surface of the metal silicide are planarized.
[0012] In one embodiment, before forming a metal material layer on the upper surface of the first dielectric layer and the top surface of the semiconductor pillar, the process includes:
[0013] The top of the semiconductor pillar is patterned to form a convex structure.
[0014] In one embodiment, before forming a metal material layer on the upper surface of the first dielectric layer and the top surface of the semiconductor pillar, the process includes:
[0015] The top of the semiconductor pillar is patterned to form a concave structure.
[0016] In one embodiment, the projected area of the memory structure on a projection plane parallel to the top surface of the semiconductor pillar accounts for more than 75% of the projected area of the semiconductor pillar.
[0017] In one embodiment, the projected area of the storage structure is greater than or equal to the projected area of the semiconductor pillar.
[0018] In one embodiment, after forming the memory structure on the metal silicide, the method further includes:
[0019] An isolation and protective layer is formed covering the storage structure and the first medium layer;
[0020] A second dielectric layer is formed on the isolation and protective layer;
[0021] An interconnecting via is formed that penetrates the second dielectric layer and the isolation protective layer, and a conductive plug is formed within the interconnecting via;
[0022] A metal layer is formed on the second dielectric layer, and the metal layer is connected to the conductive plug.
[0023] A semiconductor structure, comprising:
[0024] A transistor structure includes a transistor and a first dielectric layer, the transistor including a semiconductor pillar and a gate structure at least partially surrounding the semiconductor pillar, a source region or a drain region being formed at the top of the semiconductor pillar, and the first dielectric layer surrounding the transistor;
[0025] A metal silicide is located at the top of the semiconductor pillar and is connected to the first dielectric layer;
[0026] The storage structure is located on the metal silicide.
[0027] In one embodiment, the upper surface of the first dielectric layer is flush with the upper surface of the metal silicide.
[0028] In one embodiment, the top of the semiconductor pillar has an upwardly convex structure.
[0029] In one embodiment, a recessed structure is formed at the top of the semiconductor pillar.
[0030] In one embodiment, the projected area of the memory structure on a projection plane parallel to the top surface of the semiconductor pillar accounts for more than 75% of the projected area of the semiconductor pillar.
[0031] In one embodiment, the projected area of the storage structure is greater than or equal to the projected area of the semiconductor pillar.
[0032] In one embodiment, the semiconductor structure further includes:
[0033] An isolation and protective layer covers the storage structure and the first medium layer;
[0034] The second dielectric layer is located on the isolation and protective layer;
[0035] A conductive plug penetrates the second dielectric layer and the isolation protection layer, and connects to the top of the storage structure;
[0036] A metal layer is located on the second dielectric layer and is connected to the conductive plug.
[0037] In one embodiment, the storage structure includes any one or more of magnetic random access memory (MRAM), phase-change random access memory (PCM), ferroelectric random access memory (FRAM), and resistive random access memory (RRAM).
[0038] The aforementioned semiconductor structure and its fabrication method effectively reduce the contact resistance between the transistor's drain region (or source region) and the storage structure by forming metal silicide on the drain region (or source region) of the transistor, thereby improving the transistor's gate current driving capability.
[0039] Furthermore, in this embodiment, the upper surface of the first dielectric layer is flush with the top surface of the semiconductor pillar before forming the metal material layer. The formed metal material layer covers both the top surface of the semiconductor pillar and the upper surface of the first dielectric layer, ensuring that all locations on the top surface of the semiconductor pillar react with the metal material layer. This allows for good contact between the semiconductor pillar and the metal silicide, effectively reducing the contact resistance between them. Therefore, the total contact resistance between the transistor drain (or source) region and the memory structure can be effectively reduced, thereby significantly improving the transistor's gate current drive capability. Attached Figure Description
[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0041] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;
[0042] Figures 2-9This is a schematic cross-sectional view of the semiconductor structure fabrication process provided in one embodiment;
[0043] Figures 10 to 13 These are schematic diagrams of the semiconductor structures prepared in different embodiments;
[0044] Figure 14 A cross-sectional structural schematic diagram of the semiconductor structure fabrication process provided in another embodiment;
[0045] Figure 15 A cross-sectional structural diagram of the semiconductor structure fabrication process provided in another embodiment.
[0046] Explanation of reference numerals in the attached figures:
[0047] 100 - Transistor structure, 110 - Transistor, 111 - Semiconductor pillar, 112 - Gate structure, 120 - First dielectric layer, 200 - Metal material layer, 300 - Metal silicide, 400 - Storage structure, 500 - Isolation protection layer, 600 - Second dielectric layer, 700 - Conductive plug, 800 - Metal layer. Detailed Implementation
[0048] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0050] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.
[0051] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0052] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0053] The embodiments of this application should not be limited to the specific shape of the area shown in the accompanying drawings, but should include shape deviations due to, for example, manufacturing techniques.
[0054] As mentioned in the background section, the gate current drive capability of VGAA transistors still needs to be improved.
[0055] Specifically, for example, Magnetic Random Access Memory (MRAM) is a new type of non-volatile random access memory that operates on the principle of modulating magnetoresistive magnitude. As a non-volatile memory, MRAM's read and write speeds are comparable to those of volatile memory DRAM. Moreover, MRAM's standby power consumption is far lower than that of DRAM, giving it the potential to replace DRAM in the future.
[0056] MRAM memory cells typically consist of a transistor and a magnetic tunnel junction (MTJ). To implement DRAM-like applications, the transistor needs to be small in size and have a high drive current to drive the magnetic tunnel junction to flip.
[0057] For example, various emerging technologies, such as Phase Change Random Access Memory (PCRAM), have attracted widespread attention due to their high integration and low power consumption. In particular, PCRAM, with its non-volatile and byte-addressable characteristics, possesses the potential to function as both main memory and secondary storage. Under its influence, the boundary between main memory and secondary storage is gradually blurring, potentially even bringing about significant changes to future memory architectures. Therefore, PCRAM is considered one of the most promising emerging technologies and most likely to completely replace DRAM.
[0058] PCRAM data storage requires a certain amount of drive current. However, with the miniaturization of semiconductor devices, the transistor drive current has decreased, making it impossible to maintain the original drive capability.
[0059] For example, to achieve high-density architecture requirements for ferroelectric random access memory (FeRAM) and resistive random access memory (RRAM), the feature size of semiconductor processes must be continuously reduced. At this point, the dimensions of the gate, source, and drain active regions of the transistors in the memory cell will also shrink accordingly, thus limiting the increase in transistor drive current and potentially causing the memory to fail to operate.
[0060] Based on this, this application provides a semiconductor structure and its fabrication method to improve the gate current driving capability of a transistor. The semiconductor structure may include, but is not limited to, magnetic memory, phase-change memory, ferroelectric memory, or resistive switching memory. The transistor may include, but is not limited to, a VGAA transistor.
[0061] In one embodiment, see Figure 1A method for fabricating a semiconductor structure is provided, comprising the following steps:
[0062] For step S100, please refer to... Figure 3 A transistor structure 100 is formed, which includes a transistor 110 and a first dielectric layer 120. The transistor includes a semiconductor pillar 111 and a gate structure 112 that at least partially surrounds the semiconductor pillar 111. A source region or a drain region is formed on the top of the semiconductor pillar 111. The first dielectric layer surrounds the transistor, and the upper surface of the first dielectric layer 120 is flush with the top surface of the semiconductor pillar 111.
[0063] For step S300, please refer to... Figure 3 A metal material layer 200 is formed on the upper surface of the first dielectric layer 120 and the top surface of the semiconductor pillar 111;
[0064] For step S500, please refer to [link / reference]. Figure 4 The metal material layer 200 is heat-treated to react with the top of the semiconductor pillar 111 to form metal silicide 300.
[0065] For step S700, please refer to... Figure 4 Remove the unreacted metal material layer 200;
[0066] For step S900, please refer to... Figure 7 A memory structure 400 is formed on the metal silicide 300.
[0067] In step S100, please refer to Figure 2 In the formation of transistor structure 100, a semiconductor substrate may be provided first. The substrate may include, but is not limited to, silicon (Si) substrates, germanium (Ge) substrates, or silicon-on-insulator (SOI) substrates. The substrate may be a P-type substrate or an N-type substrate. Then, a vertical semiconductor pillar 111 is formed on the substrate. Next, a gate structure 112 is formed, either fully or partially surrounding the semiconductor pillar 111. At this point, the gate structure 112 either fully surrounds the semiconductor pillar 111 or partially surrounds it. That is, the gate structure 112 at least partially surrounds the semiconductor pillar 111. The top and bottom of the semiconductor pillar 111 are heavily doped to form source and drain regions, respectively. Specifically, the top of the semiconductor pillar 111 may form either a source region or a drain region.
[0068] It is understood here that the gate structure 112 may include a gate dielectric layer and a gate conductive layer. The gate dielectric layer may be a conventional dielectric layer or formed of a material with a high k dielectric constant. Materials with a high k dielectric constant may include, for example, aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3).
[0069] The gate conductive layer may include, but is not limited to, any one or more of titanium nitride (TiN), titanium (Ti), tungsten silicide (Si2W), and tungsten (W).
[0070] Simultaneously, during the formation of the transistor structure 100, a first dielectric layer 120 can also be formed. Please refer to... Figure 2 The initially formed first dielectric layer 120 can fill the spaces between the semiconductor pillars 111 and completely cover the transistor 110. See then... Figure 3 The first dielectric layer 120 above the semiconductor pillar 111 can be removed by chemical mechanical polishing and / or etching, so that the upper surface of the first dielectric layer 120 is flush with the top surface of the semiconductor pillar 111.
[0071] Specifically, the first dielectric layer 120 may include, but is not limited to, a silicon oxide (SiO2) layer, a silicon nitride (Si3N4) layer, an aluminum oxide (Al2O3) layer, or a silicon oxynitride (SiON) layer.
[0072] As an example, the first dielectric layer 120 may include multiple film layers made of the same or different materials. These multiple film layers may be formed in different process steps.
[0073] In step S300, please refer to Figure 3 A metal material layer 200 can be formed on the upper surface of the planarized first dielectric layer 120 and the top surface of the semiconductor pillar 111 by means of magnetron sputtering or electroplating.
[0074] The metallic material layer 200 may include, but is not limited to, Ti, Co, or NiPt.
[0075] In step S500, the metal material layer 200 can be heat-treated by annealing. In the heat-treated device, atoms in the metal material layer 200 and the top of the semiconductor pillar 111 diffuse and react to form a metal silicide 300. At this time, the formed metal silicide 300 extends from the interface between the metal material layer 200 and the semiconductor pillar 111 before annealing to both sides of the metal material layer 200 and the semiconductor pillar 111. Simultaneously, since metal material layers 200 are formed at each position on the top of the semiconductor pillar 111, reactions occur at each position on the top of the semiconductor pillar 111 with the metal material layers to form metal silicide 300. At this time, the finally formed metal silicide 300 connects to the first dielectric layer 120, and the semiconductor pillar 111 and the metal silicide 300 can make good contact, effectively reducing the contact resistance between them.
[0076] In step S700, please refer to Figure 4 As an example, the unreacted metal material layer 200 can be removed by chemical mechanical polishing (CMP). Specifically, CMP can be stopped on the first dielectric layer 120, so that the unreacted metal material layer 200 can be completely removed.
[0077] At this point, after CMP treatment, the upper surface of the metal silicide 300 can be flush with the upper surface of the first dielectric layer 120.
[0078] Of course, this is not a limitation. The unreacted metal material layer 200 can also be removed by other methods (such as wet etching). After removing the unreacted metal material layer 200, the upper surface of the metal silicide 300 can also be higher than the upper surface of the first dielectric layer 120.
[0079] In step S900, the storage structure 400 may include, but is not limited to, a magnetic random access memory structure (see [link to documentation]). Figure 10 Phase-change random access memory (see Phase-change random access memory structure) Figure 11 Ferroelectric random access memory (see ) Figure 12 ), resistive random access memory structure (see [link]) Figure 13 Any one or more of the following.
[0080] During the formation of the memory structure 400, the materials of each film layer of the memory structure 400 can first be formed on the upper surface of the metal silicide 300 and the upper surface of the first dielectric layer 120. Then, the materials of each film layer are patterned to form the memory structure 400 on the metal silicide 300.
[0081] For example, when storage structure 400 includes a magnetic random access memory structure, it includes a magnetic tunnel junction. In this case, please refer to... Figure 5First, a pinned layer material 411 can be formed on the upper surface of the metal silicide 300 and the upper surface of the first dielectric layer 120. Then, a tunnel barrier material 421 can be formed on the surface of the pinned layer material. Then, a free layer material 431 can be formed on the tunnel barrier material.
[0082] Please refer to the following: Figure 6 A mask material 10 can be formed on the free layer material, and a patterned photoresist 20 can be formed on the mask material 10. Then, the mask material 10 is patterned using photolithography, etching, and other processes to form a mask layer. Next, the patterned photoresist 20 is removed, and based on the mask layer, the free layer material, the tunnel junction material, and the plug layer material are etched sequentially to form the free layer 430, the tunnel junction 420, and the plug layer 410. (See [link to relevant documentation]). Figure 7 The free layer 430, the tunnel junction 420, and the tether layer 410 constitute a magnetic tunnel junction.
[0083] In this embodiment, by forming a metal silicide 300 on the drain region (or source region) of transistor 110, the contact resistance between the drain region (or source region) of transistor 110 and the storage structure 400 is effectively reduced, thereby improving the gate current driving capability of the transistor.
[0084] Furthermore, in this embodiment, the upper surface of the first dielectric layer 120 is flush with the top surface of the semiconductor pillar 111 before forming the metal material layer 200. The formed metal material layer 200 covers both the top surface of the semiconductor pillar 111 and the upper surface of the first dielectric layer 120, thereby ensuring that all locations on the top surface of the semiconductor pillar 111 react with the metal material layer. At this time, the semiconductor pillar and the metal silicide 300 can make good contact, and the contact resistance between them can be effectively reduced. Therefore, the total contact resistance between the drain region (or source region) of the transistor 110 and the memory structure 400 can be effectively reduced, thereby effectively improving the gate current driving capability of the transistor.
[0085] In one embodiment, prior to step S900, the method further includes:
[0086] In step S800, the upper surface of the first dielectric layer 120 and the upper surface of the metal silicide 300 are planarized.
[0087] Specifically, after step S700, if the upper surface of the metal silicide 300 is higher than the upper surface of the first dielectric layer 120, the upper surface of the first dielectric layer 120 and the upper surface of the metal silicide 300 can be planarized so that their upper surfaces are flush.
[0088] At this point, during the subsequent formation of the storage structure 400, the materials of each film layer can be formed on a flat surface, which is conducive to making the thickness of the relevant film layers of the final storage structure 400 more uniform.
[0089] Of course, in other embodiments, as before, the unreacted metal material layer 200 can be removed directly by CMP in step S700, so that the upper surface of the metal silicide 300 can be flush with the upper surface of the first dielectric layer 120.
[0090] Alternatively, in other embodiments, the deposition of each film layer material of the storage structure 400 may be performed with the upper surface of the metal silicide 300 being higher than the upper surface of the first dielectric layer 120, and there is no limitation on this.
[0091] In one embodiment, prior to step S300, the method further includes:
[0092] Step S210: The top of the semiconductor pillar 111 is patterned to form a convex structure. Please refer to [link to relevant documentation]. Figure 14 .
[0093] Specifically, photoresist can be coated on the upper surface of the first dielectric layer 120 and the top surface of the semiconductor pillar 111, and a patterned photoresist layer can be formed through a series of steps such as exposure and development. Then, based on the patterned photoresist layer, the top of the semiconductor pillar 111 (drain region or source region) is etched to form a convex structure. Then, the photoresist layer is removed.
[0094] The shape and size of the convex structure can be set according to requirements. For example, the cross-sectional shape of the convex structure can be rectangular. In this case, as an example, it is possible to remove the opposite two sides (such as the front and back edges or the left and right edges) of the top of the semiconductor pillar 111, or it is possible to remove all four edges of the top of the semiconductor pillar 111. As another example, the cross-sectional shape of the convex structure can be circular. In this case, the edge portions other than the circle can be removed.
[0095] At this point, the exposed surface area of the semiconductor pillar 111 can be effectively increased, thereby allowing the metal material layer 200 formed in step S300 to have a larger contact area with the semiconductor pillar 111, which in turn allows the subsequently formed metal silicide 300 to have a larger contact surface. This further reduces the contact resistance.
[0096] In one embodiment, prior to step S300, the method further includes:
[0097] Step S220: The top of the semiconductor pillar 111 is patterned to form a recessed structure. Please refer to [link / reference]. Figure 15 .
[0098] Specifically, photoresist can be coated on the upper surface of the first dielectric layer 120 and the top surface of the semiconductor pillar 111, and a patterned photoresist layer can be formed through a series of steps such as exposure and development. Then, based on the patterned photoresist layer, the top of the semiconductor pillar 111 (drain region or source region) is etched to form a recessed structure. Then, the photoresist layer is removed.
[0099] The shape and size of the recessed structure can be set according to requirements. For example, the cross-sectional shape of the recessed structure can be rectangular or circular. As an example, the central portion of the semiconductor pillar 111 can be removed, resulting in a recess in the center of the semiconductor pillar 111, thus forming a recessed structure.
[0100] At this time, the exposed surface area of the semiconductor pillar 111 can also be effectively increased, so that the metal material layer 200 formed in step S300 and the semiconductor pillar 111 have a larger contact area, which in turn makes the subsequently formed metal silicide 300 have a larger contact surface, thereby further reducing the contact resistance.
[0101] In one embodiment, on a projection plane parallel to the top surface of the semiconductor pillar 111, the projected area of the memory structure 400 accounts for more than 75% of the projected area of the semiconductor pillar 111.
[0102] At this point, the storage structure 400 and the metal silicide 300 that can be formed on the semiconductor pillar 111 have a sufficiently large contact area, thereby effectively reducing the contact resistance between them.
[0103] As an example, the projected area of the storage structure 400 can be set to be greater than or equal to the projected area of the semiconductor pillar 111.
[0104] At this point, the entire upper surface of the metal silicide 300 can be in contact with the storage structure 400, thereby further reducing the contact resistance between the two.
[0105] In one embodiment, after step S900, the method further includes:
[0106] Step S11, please refer to Figure 8 This forms an isolation and protective layer 500 covering the storage structure 400 and the first dielectric layer 120;
[0107] Step S12, please refer to Figure 9 A second dielectric layer 600 is formed on the isolation and protective layer 500;
[0108] Step S13, please refer to Figure 9 An interconnecting via is formed that penetrates the second dielectric layer 600 and the isolation protective layer 500, and a conductive plug 700 is formed in the interconnecting via.
[0109] Step S14, please refer to Figure 10 A metal layer 800 is formed on the second dielectric layer 600, and the metal layer 800 is connected to the conductive plug 700.
[0110] In step S11, since the surface of the previously formed storage structure 400 is higher than the surface of the first dielectric layer 120, the isolation protection layer 500 can specifically cover the upper surface of the first dielectric layer 120, the upper surface of the storage structure 400, and the sidewall surface of the storage structure 400.
[0111] The protective isolation layer 500 may include, but is not limited to, a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), an aluminum oxide layer (Al2O3), or a silicon oxynitride layer (SiON). The protective isolation layer 500 can be formed by chemical vapor deposition. Specific chemical vapor deposition methods may include atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD).
[0112] In step S12, a second dielectric material can be deposited on the isolation protective layer 500. Since the surface of the previously formed storage structure 400 is higher than the surface of the first dielectric layer 120, the surface of the deposited second dielectric material may be uneven. Therefore, after forming the second dielectric material, it can be planarized to form the second dielectric layer 600. At this time, the second dielectric layer 600 has a flat surface.
[0113] In step S13, interconnect vias can first be formed within the second dielectric layer 600 using processes such as photolithography and etching. Specifically, a patterned photoresist layer can first be formed on the surface of the second dielectric layer 600 using photolithography. Then, based on the patterned photoresist layer, dry etching is performed on the second dielectric layer 600 to form the interconnect vias. The dry etching includes at least one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-concentration plasma etching (HDP).
[0114] Next, conductive material is deposited within the interconnect vias. The conductive material may protrude above the interconnect vias. The conductive material is then planarized to form conductive plugs 700 within the interconnect vias.
[0115] Specifically, the conductive plug 700 may be made of metals such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanide (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).
[0116] In step S14, a metal layer material can be formed on the flat surface of the second dielectric layer 600 by sputtering or other methods. Then, the metal layer material is patterned to form the metal layer 800.
[0117] The metal layer 800 connects to the conductive plug 700, allowing signals to be applied to the conductive plug 700 through the metal layer 800. Multiple conductive plugs 700 can be connected to the same metal layer 800, thereby simplifying the circuit.
[0118] The material of the metal layer 800 can also include metals such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanide (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al). The material of the metal layer 800 can be the same as or different from that of the conductive plug 700.
[0119] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0120] In one embodiment, a semiconductor structure is also provided. See also... Figures 10 to 13 In any of the diagrams, the semiconductor structure includes transistor structure 100, metal silicide 300, and memory structure 400.
[0121] Transistor structure 100 includes transistor 110 and a first dielectric layer 120. Transistor 110 includes a semiconductor pillar 111 and a gate structure 112. Gate structure 112 at least partially surrounds semiconductor pillar 111. A source or drain region is formed on top of semiconductor pillar 111. First dielectric layer 120 surrounds transistor 110. Metal silicide 300 is located on top of semiconductor pillar 111 and is connected to first dielectric layer 120. Storage structure 400 is located on metal silicide 300.
[0122] In this embodiment, a metal silicide 300 is formed on the drain region (or source region) of transistor 110, thereby effectively reducing the contact resistance between the drain region (or source region) of transistor 110 and the storage structure 400, thereby improving the gate current driving capability of the transistor.
[0123] Simultaneously, the metal silicide 300 is connected to the first dielectric layer 120. At this time, the semiconductor pillar 111 and the metal silicide 300 can make good contact, and the contact resistance between them can be effectively reduced. Therefore, the total contact resistance between the drain region (or source region) of the transistor 110 and the memory structure 400 can be effectively reduced, thereby effectively improving the gate current driving capability of the transistor.
[0124] In one embodiment, the upper surface of the first dielectric layer 120 is flush with the upper surface of the metal silicide 300.
[0125] In one embodiment, a convex structure is formed on the top of the semiconductor pillar 111.
[0126] At this point, the metal silicide 300 has a larger contact surface, which can further reduce the contact resistance.
[0127] In one embodiment, a recessed structure is formed at the top of the semiconductor pillar 111.
[0128] At this point, the metal silicide 300 also has a larger contact surface, which can further reduce the contact resistance.
[0129] In one embodiment, on a projection plane parallel to the top surface of the semiconductor pillar, the projected area of the memory structure 400 accounts for more than 75% of the projected area of the semiconductor pillar 111.
[0130] At this point, the storage structure 400 and the metal silicide 300 that can be formed on the semiconductor pillar 111 have a sufficiently large contact area, thereby effectively reducing the contact resistance between them.
[0131] In one embodiment, the projected area of the storage structure 400 is greater than or equal to the projected area of the semiconductor pillar 111.
[0132] At this point, the entire upper surface of the metal silicide 300 can be in contact with the storage structure 400, thereby further reducing the contact resistance between the two.
[0133] In one embodiment, the semiconductor structure further includes an isolation protective layer 500, a second dielectric layer 600, a conductive plug 700, and a metal layer 800.
[0134] An isolation layer 500 covers the storage structure 400 and the first dielectric layer 120. A second dielectric layer 600 is located on the isolation layer 500. A conductive plug 700 penetrates the second dielectric layer 600 and the isolation layer 500, and connects to the top of the storage structure 400. A metal layer 800 is located on the second dielectric layer 120 and connects to the conductive plug 700.
[0135] In one embodiment, the storage structure includes any one or more of magnetic random access memory (MRAM), phase-change random access memory (PCM), ferroelectric random access memory (FRAM), and resistive random access memory (RRAM).
[0136] For specific limitations on semiconductor structures, please refer to the limitations on semiconductor structure fabrication methods mentioned above, which will not be elaborated further here.
[0137] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0138] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A transistor structure is formed, the transistor structure including a transistor and a first dielectric layer, the transistor including a semiconductor pillar and a gate structure at least partially surrounding the semiconductor pillar, a source region or a drain region being formed at the top of the semiconductor pillar, the first dielectric layer surrounding the transistor, and the upper surface of the first dielectric layer being flush with the top surface of the semiconductor pillar. A metal material layer is formed on the upper surface of the first dielectric layer and the top surface of the semiconductor pillar; The metal material layer is heat-treated to react with the top of the semiconductor pillar to form a metal silicide; Remove the unreacted layer of the metallic material; A storage structure is formed on the metal silicide.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before forming the memory structure on the metal silicide, the method further includes: The upper surface of the first dielectric layer and the upper surface of the metal silicide are planarized.
3. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before forming a metal material layer on the upper surface of the first dielectric layer and the top surface of the semiconductor pillar, the process includes: The top of the semiconductor pillar is patterned to form a convex structure.
4. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before forming a metal material layer on the upper surface of the first dielectric layer and the top surface of the semiconductor pillar, the process includes: The top of the semiconductor pillar is patterned to form a concave structure.
5. The method for preparing a semiconductor structure according to claim 1, characterized in that, On a projection plane parallel to the top surface of the semiconductor pillar, the projected area of the memory structure accounts for more than 75% of the projected area of the semiconductor pillar.
6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The projected area of the storage structure is greater than or equal to the projected area of the semiconductor pillar.
7. The method for preparing a semiconductor structure according to any one of claims 1-6, characterized in that, After forming the storage structure on the metal silicide, the method further includes: An isolation and protective layer is formed covering the storage structure and the first medium layer; A second dielectric layer is formed on the isolation and protective layer; An interconnecting via is formed that penetrates the second dielectric layer and the isolation protective layer, and a conductive plug is formed within the interconnecting via; A metal layer is formed on the second dielectric layer, and the metal layer is connected to the conductive plug.
8. A semiconductor structure, characterized in that, include: A transistor structure includes a transistor and a first dielectric layer, the transistor including a semiconductor pillar and a gate structure at least partially surrounding the semiconductor pillar, a source region or a drain region being formed at the top of the semiconductor pillar, and the first dielectric layer surrounding the transistor; A metal silicide is located at the top of the semiconductor pillar and is connected to the first dielectric layer; The storage structure is located on the metal silicide.
9. The semiconductor structure according to claim 8, characterized in that, The upper surface of the first dielectric layer is flush with the upper surface of the metal silicide.
10. The semiconductor structure according to claim 8, characterized in that, The top of the semiconductor pillar has an upwardly convex structure.
11. The semiconductor structure according to claim 8, characterized in that, The top of the semiconductor pillar has a recessed structure.
12. The semiconductor structure according to claim 8, characterized in that, On a projection plane parallel to the top surface of the semiconductor pillar, the projected area of the memory structure accounts for more than 75% of the projected area of the semiconductor pillar.
13. The semiconductor structure according to claim 12, characterized in that, The projected area of the storage structure is greater than or equal to the projected area of the semiconductor pillar.
14. The semiconductor structure according to any one of claims 8-13, characterized in that, The semiconductor structure also includes: An isolation and protective layer covers the storage structure and the first medium layer; The second dielectric layer is located on the isolation and protective layer; A conductive plug penetrates the second dielectric layer and the isolation protection layer, and connects to the top of the storage structure; A metal layer is located on the second dielectric layer and is connected to the conductive plug.
15. The semiconductor structure according to any one of claims 8-13, characterized in that, The storage structure includes any one or more of the following: magnetic random access memory, phase change random access memory, ferroelectric random access memory, and resistive random access memory.