Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a channel structure on the substrate, the channel structure including one or more stacked channel stacks, the channel stack including a sacrificial layer and a channel layer located on the sacrificial layer, the sacrificial layer including two first sacrificial layers and a second sacrificial layer sandwiched between the two first sacrificial layers, and along the extension direction of the channel structure, the channel structure includes a channel region, wherein the etching resistance of the second sacrificial layer is less than that of the first sacrificial layer; etching and removing the sacrificial layer in the channel region; after etching and removing the sacrificial layer in the channel region, forming a gate structure in the channel region, including a gate dielectric layer surrounding and covering the channel layer, and a gate electrode layer located on the gate dielectric layer. In the process of etching and removing the sacrificial layer, the second sacrificial layer is easily removed first, exposing the surface of the first sacrificial layer in the horizontal direction, increasing the contact area between the first sacrificial layer and the etching medium, and facilitating the etching rate of the first sacrificial layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also shortened accordingly. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, so the control ability of the gate structure over the channel becomes worse, and the difficulty of pinching off the channel by the gate voltage becomes increasingly greater, making subthreshold leakage, the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better adapt to the requirements of device size reduction, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a metal-all-around transistor, the gate surrounds the channel area from all sides. Compared with planar transistors, the gate of a metal-all-around transistor has a stronger control ability over the channel and can better suppress the short channel effect. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a channel structure on the substrate, the channel structure comprising one or more stacked channel stacks, the channel stack comprising a sacrificial layer and a channel layer located on the sacrificial layer, the sacrificial layer comprising two first sacrificial layers and a second sacrificial layer sandwiched between the two first sacrificial layers, along the extension direction of the channel structure, the channel structure comprises a channel region, wherein the etching resistance of the second sacrificial layer is less than the etching resistance of the first sacrificial layer; etching and removing the sacrificial layer in the channel region; after etching and removing the sacrificial layer in the channel region, forming a gate structure in the channel region, the gate structure comprising a gate dielectric layer surrounding and covering the channel layer, and a gate electrode layer located on the gate dielectric layer.

[0006] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0007] In the formation method provided by the embodiment of the present invention, the sacrificial layer includes two first sacrificial layers and a second sacrificial layer sandwiched between the two first sacrificial layers, wherein the etching resistance of the second sacrificial layer is less than that of the first sacrificial layer, and the sacrificial layer in the channel region is etched away; in the embodiment of the present invention, the sacrificial layer includes two first sacrificial layers and a second sacrificial layer sandwiched between the two first sacrificial layers, wherein the etching resistance of the second sacrificial layer is less than that of the first sacrificial layer, then in the process of etching away the sacrificial layer in the channel region, the second sacrificial layer is easy to be removed first, and accordingly, the first sacrificial layer can protect the channel layer in the process of removing the second sacrificial layer, and at the same time, after removing the second sacrificial layer, the surface of the first sacrificial layer in the horizontal direction can be exposed, thereby increasing the contact area between the first sacrificial layer and the etching medium, which is conducive to accelerating the etching rate of the first sacrificial layer, and can also etch the first sacrificial layer along the thickness direction of the first sacrificial layer, correspondingly improving the uniformity of the etching rate of the first sacrificial layer, and is conducive to reducing the influence of the width of the channel structure on the etching rate of the first sacrificial layer, thereby reducing the damage to the channel layer in the process of removing the first sacrificial layer, and correspondingly is conducive to improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 4 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0009] Figures 5 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0010] The performance of the current semiconductor structure needs to be improved. The reasons why the performance needs to be improved are analyzed in combination with a method for forming a semiconductor structure.

[0011] Figures 1 to 4 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0012] refer to Figure 1 , providing a substrate 10, wherein the substrate 10 includes a first device region 10A for forming a first device, and a second device region 10B for forming a second device, wherein the channel width of the first device is smaller than the channel width of the second device, and a channel structure 40 is formed on the substrate 10, wherein the channel structure 40 includes one or more stacked channel stacks 31, wherein the channel stack 31 includes a sacrificial layer 21 and a channel layer 30 located on the sacrificial layer 21.

[0013] Combined with reference Figure 2 and Figure 3 , remove the sacrificial layer 21.

[0014] The sacrificial layer 21 is removed so that all surfaces of the channel layer 30 are exposed, so that the gate structure formed subsequently can surround and cover all surfaces of the channel layer 30 .

[0015] refer to Figure 4 After removing the sacrificial layer 21 , a gate structure 50 surrounding and covering the channel layer 30 is formed.

[0016] However, in the process of removing the sacrificial layer 21, only the side surface of the sacrificial layer 21 can contact the etching medium, so the contact area between the sacrificial layer 21 and the etching medium is small, and the lateral depth of etching is relatively large, so a longer etching time is required. In particular, for a channel structure 40 with a larger width, the etching time required to etch the sacrificial layer 21 is longer than that of a channel structure 40 with a smaller width. Usually, in the channel release process, the sacrificial layer 21 between the channel layers 30 of different widths is removed at the same time. Therefore, after the sacrificial layer 21 of the first device area 10A with a smaller channel width is completely removed, the sacrificial layer 21 of the second device area 10B with a larger channel width has not been completely removed (e.g., Figure 2 shown).

[0017] In order to ensure that the sacrificial layer 21 in different regions is completely removed, the etching time needs to be extended to ensure that the sacrificial layer 21 in the second device region 10B does not remain, thereby causing over-etching of the channel layer 30 in the first device region 10A. Figure 3 As shown, Figure 3 The dotted box in the middle indicates the initial outline of the channel layer 30 of the first device area 10A. If the channel layer 30 of the first device area 10A is over-etched, it is easy to cause the channel layer 30 of the first device area 10A to be damaged and the thickness to be reduced. The channel layer 30 is a key structure of the device, and the dimensional stability of the channel layer 30 has a great influence on the performance of the semiconductor structure. In addition, a gate structure 50 covering the channel layer 30 needs to be formed subsequently. If the thickness of the channel layer 30 is reduced, the gap size between adjacent channel layers 30 will increase. Therefore, when the gate structure 50 is filled between the channel layers 30, the performance of the final device will deviate greatly from the expected design, thereby affecting the performance of the semiconductor structure.

[0018] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a channel structure on the substrate, the channel structure comprising one or more stacked channel stacks, the channel stack comprising a sacrificial layer and a channel layer located on the sacrificial layer, the sacrificial layer comprising two first sacrificial layers and a second sacrificial layer sandwiched between the two first sacrificial layers, along the extension direction of the channel structure, the channel structure comprises a channel region, wherein the etching resistance of the second sacrificial layer is less than the etching resistance of the first sacrificial layer; etching and removing the sacrificial layer in the channel region; after etching and removing the sacrificial layer in the channel region, forming a gate structure in the channel region, the gate structure comprising a gate dielectric layer surrounding and covering the channel layer, and a gate electrode layer located on the gate dielectric layer.

[0019] In the formation method provided by the embodiment of the present invention, the sacrificial layer includes two first sacrificial layers and a second sacrificial layer sandwiched between the two first sacrificial layers, wherein the etching resistance of the second sacrificial layer is less than that of the first sacrificial layer, and the sacrificial layer in the channel region is etched away; in the embodiment of the present invention, the sacrificial layer includes two first sacrificial layers and a second sacrificial layer sandwiched between the two first sacrificial layers, wherein the etching resistance of the second sacrificial layer is less than that of the first sacrificial layer, then in the process of etching away the sacrificial layer in the channel region, the second sacrificial layer is easy to be removed first, and accordingly, the first sacrificial layer can protect the channel layer in the process of removing the second sacrificial layer, and at the same time, after removing the second sacrificial layer, the surface of the first sacrificial layer in the horizontal direction can be exposed, thereby increasing the contact area between the first sacrificial layer and the etching medium, which is conducive to accelerating the etching rate of the first sacrificial layer, and can also etch the first sacrificial layer along the thickness direction of the first sacrificial layer, correspondingly improving the uniformity of the etching rate of the first sacrificial layer, and is conducive to reducing the influence of the width of the channel structure on the etching rate of the first sacrificial layer, thereby reducing the damage to the channel layer in the process of removing the first sacrificial layer, and correspondingly is conducive to improving the performance of the semiconductor structure.

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0021] Figures 5 to 10 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0022] refer to Figure 5 , providing a substrate 100.

[0023] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure, wherein the semiconductor structure includes a gate-all-around (GAA) transistor and a forksheet transistor.

[0024] The base 100 includes a substrate (not shown).

[0025] In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0026] In this embodiment, taking the semiconductor structure as a fully enclosed gate transistor as an example, the substrate 100 includes a first device region 100A for forming a first device and a second device region 100B for forming a second device, and the channel width of the first device is smaller than the channel width of the second device.

[0027] Combined with reference Figures 5 to 7 , a channel structure 400 (such as Figure 6 As shown), the channel structure 400 includes one or more stacked channel stacks 310 (as shown Figure 6 As shown), the channel stack 310 includes a sacrificial layer 200 (as shown Figure 6 ) and a channel layer 300 (as shown) located on the sacrificial layer 200 Figure 6 As shown), the sacrificial layer 200 includes two first sacrificial layers 210 (as shown Figure 6 ) and a second sacrificial layer 220 (as shown) sandwiched between the two first sacrificial layers 210 Figure 6 As shown), along the extension direction of the channel structure 400, the channel structure 400 includes a channel region 400c (as shown Figure 7 As shown), wherein the etching resistance of the second sacrificial layer 220 is less than the etching resistance of the first sacrificial layer 210.

[0028] The channel layer 300 in the channel structure 400 is used to provide a channel of the transistor, and the sacrificial layer 200 is used to provide a process basis for the subsequent realization of the suspended setting of the channel layer 300, and is also used to occupy a space position for the gate structure formed subsequently. In the subsequent process, the sacrificial layer 200 of the channel area 400c is removed, so that the channel layer 300 of the channel area 400c is suspended, and a gate structure is formed between the channel layer 300 and the substrate 100, and between adjacent channel layers 300, so that the gate structure surrounds and covers the channel layer 300 of the channel area 400c.

[0029] The top and side walls of the channel layer 300 covered by the gate structure are used as a channel. In this embodiment, the top, bottom and side walls of the channel layer 300 can all be used as a channel, increasing the area of ​​the channel layer 300 used as a channel, thereby increasing the operating current of the semiconductor structure.

[0030] Combined with reference Figure 7 , Figure 7 4 is a top view of any channel structure 400. Along the extension direction of the channel structure 400, the channel structure 400 includes a channel region 400c. The channel layer 300 of the channel region 400c is used as a channel of a transistor.

[0031] In this embodiment, the material of the channel layer 300 includes silicon, germanium, silicon germanium or III-V semiconductor material. As an example, the material of the channel layer 300 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0032] It should be noted that, in this embodiment, the channel layer 300 and the substrate 100 are made of the same material. In other embodiments, the channel layer and the substrate may be made of different materials.

[0033] In this embodiment, the sacrificial layer 200 is a stacked structure, including two first sacrificial layers 210 and a second sacrificial layer 220 sandwiched between the two first sacrificial layers 210. The etching resistance of the second sacrificial layer 220 is less than that of the first sacrificial layer 210. In the subsequent process of removing the sacrificial layer 200, it is easy to remove the second sacrificial layer 220 first to expose the surface of the first sacrificial layer 210 in the horizontal direction, thereby easily accelerating the etching rate of the first sacrificial layer 210 and reducing the damage to the channel layer 300 caused by the process of removing the sacrificial layer 200.

[0034] It should be noted that in the subsequent step of removing the sacrificial layer 200 , there is a high etching selectivity ratio between the sacrificial layer 200 and the channel layer 300 . Accordingly, there is a high etching selectivity ratio between the first sacrificial layer 210 and the channel layer 300 .

[0035] In this embodiment, the material of the channel layer 300 is silicon, and therefore the material of the first sacrificial layer 210 is silicon germanium.

[0036] The silicon germanium and silicon can form a larger etching selectivity ratio, which is beneficial to the subsequent removal of the first sacrificial layer 210 and reduces damage to the channel layer 300 .

[0037] In other embodiments, a suitable material having an etching selectivity ratio with the channel layer may be selected according to the material of the channel layer, so as to reduce damage to the channel layer when the first sacrificial layer is subsequently removed.

[0038] Similarly, the second sacrificial layer 220 and the channel layer 300 also have a high etching selectivity ratio.

[0039] Moreover, the etching resistance of the second sacrificial layer 220 is smaller than that of the first sacrificial layer 210 .

[0040] In this embodiment, the material of the first sacrificial layer 210 includes silicon germanium, and therefore, the material of the second sacrificial layer 220 includes germanium or silicon germanium. When the material of the second sacrificial layer 220 also includes silicon germanium, the atomic percentage content of germanium in the second sacrificial layer 220 is greater than the atomic percentage content of germanium in the first sacrificial layer 210.

[0041] In the silicon germanium layer, the higher the atomic percentage of germanium is, the faster the etching rate of the silicon germanium layer is. That is to say, while the silicon germanium has a high etching selectivity to silicon, the higher the germanium content in the silicon germanium is, the faster the silicon germanium is removed.

[0042] Moreover, in the present embodiment, in the etching process of channel release, an etching process capable of achieving a high etching selectivity ratio between silicon germanium and silicon needs to be adopted, and the etching rate of the second sacrificial layer 220 with a higher germanium content is faster in the etching process.

[0043] Therefore, in this embodiment, the material of the second sacrificial layer 220 includes germanium or silicon germanium. Compared with the sacrificial layer only including silicon germanium in the prior art, the sacrificial layer 200 in this embodiment has a higher germanium content, which increases the etching rate of the sacrificial layer 200.

[0044] In this embodiment, the material of the channel layer 300 is silicon. Therefore, the material of the second sacrificial layer 220 is germanium, which is more conducive to making the etching resistance of the second sacrificial layer 220 lower than that of the first sacrificial layer 210 .

[0045] The germanium and silicon can form a larger etching selectivity ratio, which is beneficial to the subsequent removal of the second sacrificial layer 220 and reduces the damage to the channel layer 300. At the same time, the etching resistance of the germanium is lower than that of silicon germanium, which is beneficial to remove the second sacrificial layer 220 first and expose the surface of the first sacrificial layer 210 in the horizontal direction, thereby easily accelerating the etching rate of the first sacrificial layer 210 and reducing the damage of the etching process to the channel layer 300.

[0046] In other embodiments, the material of the first sacrificial layer having an etching selectivity ratio with the channel layer can be selected according to the material of the channel layer, and a suitable material having an etching selectivity ratio with the channel layer and having a lower etching resistance than the first sacrificial layer can be selected to reduce damage to the channel layer when the second sacrificial layer is subsequently removed.

[0047] It should be noted that the ratio of the thickness d of the second sacrificial layer 220 to the total thickness d0 of the sacrificial layer 200 cannot be too large or too small. If the thickness d of the second sacrificial layer 220 accounts for too large a proportion of the total thickness d0 of the sacrificial layer 200, and the second sacrificial layer 220 is formed by epitaxial growth, the epitaxial quality of the second sacrificial layer 220 is easily affected by the lattice size adaptation, and additional stress problems are generated. Moreover, the thickness d of the second sacrificial layer 220 accounts for too large a proportion of the total thickness d0 of the sacrificial layer 200, which correspondingly causes the thickness of the first sacrificial layer 210 to account for too small a proportion of the total thickness d0 of the sacrificial layer 200. In this embodiment, the material of the channel layer 300 is silicon, the material of the first sacrificial layer 210 is silicon germanium, and the material of the second sacrificial layer 220 is germanium. When the channel structure 400 is formed, the concentration gradient of the germanium content between the channel layer 300 and the second sacrificial layer 220 is too large, and it is difficult to form the channel structure 400 with higher quality. At the same time, the thickness of the first sacrificial layer 210 accounts for too large a proportion of the total thickness d0 of the sacrificial layer 200. If the thickness d of the second sacrificial layer 220 is too small, the germanium element in the second sacrificial layer 220 is easily diffused into the channel layer 300, affecting the quality of the channel layer 300; if the ratio of the thickness d of the second sacrificial layer 220 to the total thickness d0 of the sacrificial layer 200 is too small, the ratio of the thickness d of the first sacrificial layer 210 to the total thickness d0 of the sacrificial layer 200 is correspondingly too large, and after the second sacrificial layer 220 is subsequently removed, it is difficult to increase the rate of removing the first sacrificial layer 210, and it still takes a long time to remove the first sacrificial layer 210, thereby increasing the probability of over-etching of the channel layer 300 in some areas, and if the thickness d of the second sacrificial layer 220 is too small, after the second sacrificial layer 220 is removed, the gap between the two first sacrificial layers 210 is too small, and it is difficult for the etching medium to completely enter the gap and completely contact with the exposed surface of the first sacrificial layer 210, thereby increasing the rate of removing the first sacrificial layer 210. Therefore, in this embodiment, the ratio of the thickness d of the second sacrificial layer 220 to the total thickness d0 of the sacrificial layer 200 is 10% to 90%.

[0048] Specifically, refer to Figure 5The step of forming the channel structure 400 includes: forming a channel structure material layer 401 on the substrate 100, the channel structure material layer 401 includes one or more stacked channel stack material layers 311, the channel stack material layer 311 includes a sacrificial material layer 201 and a channel material layer 301 located on the sacrificial material layer 201, the sacrificial material layer 201 includes two first sacrificial material layers 211 and a second sacrificial material layer 221 sandwiched between the two first sacrificial material layers 211, wherein the etching resistance of the second sacrificial material layer 221 is less than the etching resistance of the first sacrificial material layer 211.

[0049] The channel structure material layer 401 is used to form a channel structure 400. In this embodiment, the channel structure material layer 401 is used to form multiple channel structures 400 in multiple regions at the same time, which simplifies the process flow, improves the process efficiency, and saves the process cost.

[0050] Among them, the channel stack material layer 311 is used to form a channel stack 310, the sacrificial material layer 201 is used to form a sacrificial layer 200, the channel material layer 301 is used to form a channel layer 300, the first sacrificial material layer 201 is used to form a first sacrificial layer 210, and the second sacrificial material layer 221 is used to form a second sacrificial layer 220.

[0051] The channel material layer 301 includes silicon, germanium, silicon germanium or III-V semiconductor material, and is used to directly form the channel layer 300. The material of the first sacrificial layer 211 includes silicon germanium, and is used to directly form the first sacrificial layer 210. The material of the second sacrificial layer 221 includes germanium, and is used to directly form the second sacrificial layer 220. The etching resistance of the second sacrificial material layer 221 is less than that of the first sacrificial material layer 211, so that the etching resistance of the second sacrificial layer 220 is less than that of the first sacrificial layer 210.

[0052] In this embodiment, the channel structure material layer 401 is formed in the same process, which simplifies the process flow, improves the process efficiency, and saves the process cost.

[0053] Specifically, forming the channel structure material layer 401 in the same process means that the formation of the channel structure material layer 401 is completed in the same machine of the same process, and no new process needs to be added.

[0054] In this embodiment, the channel structure material layer 401 is formed by an epitaxial growth process.

[0055] The epitaxial growth process can better control the process parameters, has high process controllability, and is easy to obtain a more accurate film thickness size. Moreover, the epitaxial growth process is easy to form a film layer with fewer impurities, so that the quality of the channel structure material layer 401 is higher. In addition, the material of the first sacrificial material layer 211 is silicon, the material of the second sacrificial material layer 221 is germanium, and the material of the channel material layer 301 is silicon. Through the above material settings, the epitaxial growth process can be used to grow the first sacrificial material layer 211 on the channel material layer 301, grow the second sacrificial material layer 221 on the first sacrificial material layer 211, grow the first sacrificial material layer 211 on the second sacrificial material layer 221, and grow the channel material layer 301 on the first sacrificial material layer 211, so that the channel structure material layer 401 is formed in the same process.

[0056] refer to Figure 6 , patterning the channel structure material layer 401 to form a channel structure 400 on the substrate 100 .

[0057] The channel structure material layer 401 is patterned so that the channel structure 400 is formed in the first device region 100A and the second device region 100B at the same time, which simplifies the process flow, improves the process efficiency, and saves the process cost.

[0058] In the present embodiment, during the process of forming the channel structure 400 on the substrate 100, the channel structure 400 is formed on the substrate 100 in the first device region 100A and the second device region 100B, and in a direction perpendicular to the extension direction of the channel structure 400, a width w1 of the channel structure 400 in the first device region 100A is smaller than a width w2 of the channel structure 400 in the second device region 100B.

[0059] The channel width of the first device is smaller than the channel width of the second device. The channel width refers to the width of the channel structure 400 in the direction perpendicular to the extension direction of the channel structure 400. In the direction perpendicular to the extension direction of the channel structure 400, the width w1 of the channel structure 400 in the first device area 100A is smaller than the width w2 of the channel structure 400 in the second device area 100B.

[0060] It should be noted that the channel width affects the rate of removing the sacrificial layer 200. If the width w1 of the channel structure 400 in the first device area 100A is smaller than the width w2 of the channel structure 400 in the second device area 100B, the volume of the sacrificial layer 200 in the first device area 100A is smaller than the volume of the sacrificial layer 200 in the second device area 100B. Therefore, in the subsequent process of removing the sacrificial layer 200, the time for removing the sacrificial layer 200 in the first device area 100A is less than the time for removing the sacrificial layer 200 in the second device area 100B. In other words, the sacrificial layer 200 in the first device area 100A is removed faster.

[0061] It should also be noted that after patterning the channel structure material layer 401 , the following step may be further included: continuing to pattern the substrate 100 to form a fin portion (not shown) protruding from the remaining substrate 100 .

[0062] In this embodiment, after forming the channel structure 400 and the fin, the method further includes: forming an isolation layer (not shown) on the remaining substrate 100 exposed from the channel structure 400 and the fin, wherein the isolation layer covers the entire sidewall or a portion of the sidewall of the fin.

[0063] The isolation layer is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, an isolation layer is usually formed between an NMOS transistor and a PMOS transistor.

[0064] refer to Figure 8 After forming the channel structure 400 , the method further includes: forming a dummy gate structure 600 across the channel structure 400 on the substrate 100 , wherein the dummy gate structure 600 covers the top and sidewalls of the channel structure 400 in the channel region 400 c .

[0065] Specifically, after forming the isolation layer, the dummy gate structure 600 is formed.

[0066] The dummy gate structure 600 is used to occupy a space for the subsequent formation of a gate structure.

[0067] Specifically, the dummy gate structure 600 is a stacked structure, including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) covering the dummy gate oxide layer.

[0068] The dummy gate layer may be a single-layer structure or a stacked-layer structure, and the material of the dummy gate layer includes one or both of amorphous silicon and polycrystalline silicon. In other embodiments, the material of the dummy gate layer may also include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon nitride oxide, or amorphous carbon.

[0069] In this embodiment, the dummy gate layer is a single-layer structure, and the material of the dummy gate layer is amorphous silicon. Amorphous silicon has no crystal orientation, so the etching rate uniformity and etching effect uniformity of amorphous silicon are better, thereby improving the subsequent removal effect of the dummy gate layer.

[0070] As an example, the material of the dummy gate oxide layer is silicon oxide.

[0071] refer to Fig. 9 The formation method further includes: forming an interlayer dielectric layer 610 covering the channel structure 400 on the substrate 100, wherein the interlayer dielectric layer 610 also covers the sidewalls of the dummy gate structure 600 and exposes the top of the dummy gate structure 600.

[0072] The interlayer dielectric layer 610 is used to isolate adjacent devices, and is also used to provide a process basis for subsequently removing the dummy gate structure 600 to form a gate opening.

[0073] The material of the interlayer dielectric layer 610 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0074] refer to Fig.10 The formation method further includes: removing the dummy gate structure 600 , and forming a gate opening 620 in the interlayer dielectric layer 610 , wherein the gate opening 620 exposes the channel structure 400 in the channel region 400 c .

[0075] The gate opening 620 provides a space for subsequently forming a gate structure, and the gate opening 620 exposes the channel structure 400 in the channel region 400 c to prepare for the subsequent removal of the sacrificial layer 200 .

[0076] Combined with reference Fig.11 and Fig.12 , the sacrificial layer 200 in the channel region 400 c is etched away.

[0077] In the embodiment of the present invention, the sacrificial layer 200 includes two first sacrificial layers 210 and a second sacrificial layer 220 sandwiched between the two first sacrificial layers 210. The etching resistance of the second sacrificial layer 220 is less than that of the first sacrificial layer 210. In the process of removing the sacrificial layer 200, the second sacrificial layer 220 is easy to be removed first. Accordingly, the first sacrificial layer 210 can protect the channel layer 200 in the process of removing the second sacrificial layer 220. At the same time, after removing the second sacrificial layer 220, the surface 212 (such as Fig.11As shown), the contact area between the first sacrificial layer 210 and the etching medium is increased, which is beneficial to speed up the etching rate of the first sacrificial layer 210, and the first sacrificial layer 210 can also be etched along the thickness direction of the first sacrificial layer 210, which correspondingly improves the uniformity of the etching rate of the first sacrificial layer 210, and is beneficial to reduce the influence of the width of the channel structure 400 on the etching rate of the first sacrificial layer 210, thereby reducing the damage to the channel layer 300 in the process of removing the first sacrificial layer 210, which is correspondingly beneficial to improve the performance of the semiconductor structure.

[0078] Specifically in this embodiment, the etching rate of the sacrificial layer 200 in the second region 100B is increased, thereby greatly reducing the probability of over-etching of the channel layer 300 in the first device region 100A.

[0079] In this embodiment, in the process of etching and removing the sacrificial layer 200 in the channel area 400c, the second sacrificial layer 220 and the first sacrificial layer 210 are removed in sequence. After removing the second sacrificial layer 220, the thickness of the remaining first sacrificial layer 210 in the first device area 100A and the second device area 100B that needs to be etched in a direction perpendicular to the substrate surface is consistent, thereby helping to reduce the probability of over-etching of the channel layer 300 in the first device area 100A during the process of removing the first sacrificial layer 210.

[0080] In this embodiment, the sacrificial layer 200 of the channel region 400 c is removed by etching through the gate opening 620 , so as to realize the suspended arrangement of the channel layer 300 , and also provide a spatial position for the gate structure to be formed subsequently.

[0081] In this embodiment, in the step of etching away the sacrificial layer 200 in the channel region 400c, the second sacrificial layer 220 and the first sacrificial layer 210 are removed in sequence in the same process, which simplifies the process flow, improves process efficiency, and saves process costs.

[0082] Specifically, in the same process, removing the second sacrificial layer 220 and the first sacrificial layer 210 in sequence means: removing the second sacrificial layer 220 and the first sacrificial layer 210 in the same process and on the same machine without additionally changing the process or adding a new process.

[0083] In this embodiment, the sacrificial layer 200 is etched away by an isotropic dry etching process.

[0084] The isotropic etching process is beneficial to completely removing the sacrificial layer 200 .

[0085] In this embodiment, the isotropic etching process includes a Certas etching process or a SiCoNi etching process.

[0086] The Certas etching process or the SiCoNi etching process has good isotropic characteristics, which is conducive to completely removing the sacrificial layer 200 , and the Certas etching process or the SiCoNi etching process has a good etching selectivity ratio for the sacrificial layer 200 and the channel layer 300 .

[0087] In this embodiment, the isotropic etching process is a Certas etching process, and the etching gas of the Certas etching process includes HF gas.

[0088] In other embodiments, the sacrificial layer may also be removed by etching using a wet etching process.

[0089] It should be noted that, in this embodiment, the second sacrificial layer 220 and the first sacrificial layer 210 are removed in the same etching step, but because the second sacrificial layer 220 has a lower etching resistance, the second sacrificial layer 220 is removed first, thereby achieving the effect of removing the second sacrificial layer 220 and the first sacrificial layer 210 in sequence.

[0090] refer to Fig.13 After the sacrificial layer 200 of the channel region 400 c is removed by etching, a gate structure 500 is formed in the channel region 400 c . The gate structure 500 includes a gate dielectric layer 510 surrounding and covering the channel layer 300 , and a gate electrode layer 520 located on the gate dielectric layer 510 .

[0091] The gate structure 500 is used to control the opening and closing of the channel of the transistor.

[0092] The gate structure 500 surrounds and covers the channel layer 300 , so the top, bottom and sidewalls of the channel layer 300 can all serve as channels, increasing the area of ​​the channel layer 300 used as a channel, thereby increasing the operating current of the semiconductor structure.

[0093] In this embodiment, a gate structure 500 is formed in the gate opening 620 .

[0094] The gate dielectric layer 510 is used to isolate the gate electrode layer 520 from the channel layer 300 .

[0095] The material of the gate dielectric layer 510 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0096] In this embodiment, the gate structure 500 is a metal gate structure, and therefore, the gate dielectric layer 510 includes a high-k gate dielectric layer (not shown), and the material of the high-k gate dielectric layer includes a high-k dielectric material. Among them, the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. As an example, the material of the high-k gate dielectric layer is HfO2.

[0097] In this embodiment, the gate dielectric layer 510 may further include a gate oxide layer (not shown) located between the high-k gate dielectric layer and the channel layer 300. As an example, the material of the gate oxide layer is silicon oxide.

[0098] The gate electrode layer 520 is used to electrically lead out the metal gate structure.

[0099] In this embodiment, in the step of forming the gate electrode layer 520 , the gate electrode layer 520 surrounds and covers the gate dielectric layer 510 , so that the gate electrode layer 520 surrounds and covers the channel layer 300 .

[0100] In this embodiment, the material of the gate electrode layer 520 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0101] In this embodiment, the gate structure 500 is a metal gate structure, so the gate electrode layer 520 includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer, or the gate electrode layer 520 may also only include the work function layer. The work function layer is used to adjust the threshold voltage of the transistor.

[0102] It should be noted that, in some other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

[0103] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A channel structure is formed on the substrate, wherein the channel structure comprises one or more stacked channel stacks, wherein the channel stack comprises a sacrificial layer and a channel layer located on the sacrificial layer, wherein the sacrificial layer comprises two first sacrificial layers and a second sacrificial layer sandwiched between the two first sacrificial layers, and along the extension direction of the channel structure, the channel structure comprises a channel region, wherein the etching resistance of the second sacrificial layer is less than the etching resistance of the first sacrificial layer; Etching and removing the sacrificial layer in the channel region; In the step of etching away the sacrificial layer in the channel region, the second sacrificial layer and the first sacrificial layer are etched using the same etching medium in the same process to sequentially remove the second sacrificial layer and the first sacrificial layer; After the sacrificial layer in the channel region is removed by etching, a gate structure is formed in the channel region. The gate structure includes a gate dielectric layer surrounding and covering the channel layer, and a gate electrode layer located on the gate dielectric layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing a substrate, the substrate includes a first device region for forming a first device, and a second device region for forming a second device, and a channel width of the first device is smaller than a channel width of the second device; In the process of forming the channel structure on the substrate, the channel structure is formed on the substrate of the first device region and the second device region, and in a direction perpendicular to the extension direction of the channel structure, the width of the channel structure in the first device region is smaller than the width of the channel structure in the second device region.

3. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the channel structure comprises: forming a channel structure material layer on the substrate, the channel structure material layer comprising one or more stacked channel stack material layers, the channel stack material layer comprising a sacrificial material layer and a channel material layer located on the sacrificial material layer, the sacrificial material layer comprising two first sacrificial material layers and a second sacrificial material layer sandwiched between the two first sacrificial material layers, wherein the etching resistance of the second sacrificial material layer is less than the etching resistance of the first sacrificial material layer; The channel structure material layer is patterned to form a channel structure on the substrate.

4. The method for forming a semiconductor structure according to claim 3, wherein: The channel structure material layer is formed in the same process.

5. The method for forming a semiconductor structure according to claim 3, wherein: The channel structure material layer is formed by an epitaxial growth process.

6. The method for forming a semiconductor structure according to claim 1, wherein: The sacrificial layer in the channel region is etched away by an isotropic dry etching process.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first sacrificial layer includes silicon germanium, and the material of the second sacrificial layer includes germanium; Alternatively, the material of the first sacrificial layer includes silicon germanium, the material of the second sacrificial layer includes silicon germanium, and the atomic percentage content of germanium in the second sacrificial layer is greater than the atomic percentage content of germanium in the first sacrificial layer.

8. The method for forming a semiconductor structure according to claim 1, wherein: The material of the channel layer includes silicon, germanium, silicon germanium or III-V group semiconductor material.

9. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the second sacrificial layer accounts for 10% to 90% of the total thickness of the sacrificial layer.

10. The method for forming a semiconductor structure according to claim 1, wherein: After forming the channel structure, before sequentially removing the second sacrificial layer and the first sacrificial layer in the channel region, the method further includes: forming a dummy gate structure across the channel structure on the substrate, wherein the dummy gate structure covers the top and sidewalls of the channel structure in the channel region; forming an interlayer dielectric layer covering the channel structure on the substrate, wherein the interlayer dielectric layer also covers the sidewalls of the dummy gate structure and exposes the top of the dummy gate structure; Removing the dummy gate structure, forming a gate opening in the interlayer dielectric layer, wherein the gate opening exposes the channel structure of the channel region; Etching and removing the sacrificial layer in the channel region through the gate opening; After the sacrificial layer in the channel region is removed by etching, a gate structure is formed in the gate opening.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

12. The method for forming a semiconductor structure according to claim 1, wherein: The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

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