Bare chip packaging assembly and preparation method thereof

Abstract

The present application discloses a bare chip package assembly and a method for preparing the same. The bare chip package assembly includes: a bare chip and a package substrate, wherein the first surface of the bare chip is soldered to the package substrate; wherein the bare chip includes a first surface and a second surface disposed opposite each other, and a bump is formed on the first surface; a first heat sink, wherein the first heat sink is mounted on the package substrate; wherein the first heat sink has a recess disposed in a reverse direction to accommodate the bare chip; a second heat sink, wherein the second heat sink is disposed on a side surface of the first heat sink away from the bare chip; a plastic package, wherein the plastic package fills the remaining space between the bare chip, the first heat sink, the second heat sink, and the package substrate; and a third heat sink, wherein the third heat sink is disposed on a side surface of the second heat sink away from the first heat sink. Through the above-mentioned method, the present application can quickly dissipate heat from the bare chip.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a bare chip packaging assembly and a preparation method thereof. Background Art

[0002] With the development of 5G and microelectronics, PCBs are becoming increasingly miniaturized and denser. Chips are becoming smaller, yet their computing speeds are increasing. Consequently, the heat generated by these chips is also increasing. Any chip must operate within a certain operating range. To maintain this operating range, the heat generated by the chip must be quickly conducted away; otherwise, its performance will be limited.

[0003] In the prior art, a heat dissipation housing is generally mounted on the surface of the chip to dissipate heat from the chip through the heat dissipation housing. However, the heat dissipation area of ​​the heat dissipation housing is small and the chip cannot be quickly cooled. Summary of the Invention

[0004] The main technical problem solved by the present application is to provide a bare chip packaging assembly and a preparation method thereof, and to solve the problem of being unable to quickly dissipate heat for the bare chip by setting up multiple heat sinks.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is to provide a bare chip packaging assembly, including: a bare chip and a packaging substrate, wherein the first surface of the bare chip is welded to the packaging substrate; wherein the bare chip includes a first surface and a second surface arranged opposite to each other, and a planting ball is formed on the first surface; a first heat sink, wherein the first heat sink is mounted on the packaging substrate; wherein the first heat sink has a groove arranged in a back direction to accommodate the bare chip; a second heat sink, wherein the second heat sink is arranged on a side surface of the first heat sink away from the bare chip; a plastic package, wherein the plastic package fills the remaining space between the bare chip, the first heat sink, the second heat sink and the packaging substrate; and a third heat sink, wherein the third heat sink is arranged on a side surface of the second heat sink away from the first heat sink.

[0006] The bare chip packaging assembly further includes at least one surface packaging component, which is arranged on the packaging substrate around the bare chip.

[0007] The materials of the first heat sink, the second heat sink and the third heat sink include copper, aluminum or copper-aluminum alloy.

[0008] The second surface of the bare chip is connected to the groove through non-conductive glue.

[0009] The surface of the second heat sink is connected to the surface of the first heat sink away from the die through non-conductive adhesive, and the third heat sink is connected to the surface of the second heat sink away from the first heat sink through non-conductive adhesive.

[0010] To solve the above technical problems, another technical solution adopted in the present application is to provide a method for preparing a bare chip packaging assembly, including: obtaining a bare chip and a packaging substrate, and soldering the first surface of the bare chip to the packaging substrate; wherein the bare chip includes a first surface and a second surface arranged opposite to each other, and a planting ball is formed on the first surface; obtaining a first heat sink, and mounting the first heat sink on the packaging substrate; wherein the first heat sink has a groove arranged in a back direction, and the bare chip is accommodated in the groove; obtaining a second heat sink, and setting the second heat sink on a side surface of the first heat sink away from the bare chip; using a plastic package to plastic-seal the bare chip, the first heat sink, and the remaining space between the second heat sink and the packaging substrate; obtaining a third heat sink, and setting the third heat sink on a side surface of the second heat sink away from the first heat sink.

[0011] The steps of obtaining a bare chip and a packaging substrate and soldering the first surface of the bare chip to the packaging substrate further include obtaining at least one surface packaging component and arranging the surface packaging component around the bare chip on the packaging substrate.

[0012] Among them, a first heat sink is obtained and mounted on a packaging substrate; wherein the first heat sink has a groove arranged in a back direction, and before the step of placing the bare chip in the groove includes: setting the size of the groove of the first heat sink according to the size of the bare chip so that the size of the groove matches the size of the bare chip; wherein the size of the groove is not less than the size of the bare chip, and the size of the bare chip includes the length, width and height of the bare chip.

[0013] Among them, a first heat sink is obtained and mounted on a packaging substrate; wherein the first heat sink has a groove arranged in a back direction, and the step of placing the bare chip in the groove includes: applying non-conductive glue on the second surface of the bare chip and covering the groove on the second surface of the bare chip; applying non-conductive glue on the surface of the first heat sink including the groove to mount the first heat sink on the packaging substrate.

[0014] The step of using the plastic package to plastic-package the bare chip, the first heat sink, and the remaining space between the second heat sink and the package substrate further includes: after the plastic packaging is completed, polishing the surface of the second heat sink away from the first heat sink to expose the surface.

[0015] The present application has the following beneficial effects: Different from the prior art, the die package assembly provided by the present application includes a first heat sink, a second heat sink, and a third heat sink. The first heat sink includes a groove to accommodate the die and dissipate heat from the die, thereby quickly reducing the operating temperature of the electronic components in the die. The second heat sink is disposed on a side of the first heat sink away from the die, thereby accelerating the heat dissipation of the first heat sink. The third heat sink is disposed on a side of the second heat sink away from the first heat sink, thereby conducting heat generated by the die to the outside of the plastic cover, thereby further improving heat dissipation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 This is a schematic structural diagram of an embodiment of a bare chip packaging assembly of the present application;

[0018] Figure 2 It is a structural schematic diagram of another embodiment of the bare chip packaging assembly of the present application;

[0019] Figure 3 It is a flow chart of an embodiment of a method for preparing a bare chip package assembly of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0021] The terms used in the examples of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a," "the," and "the" used in the examples of this application and the appended claims are also intended to include plural forms. Unless otherwise clearly indicated above, "a plurality" generally includes at least two, but does not exclude the inclusion of at least one.

[0022] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0023] It should be understood that the terms "comprises," "comprising," or any other variations used herein are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0024] With the development of 5G and microelectronics, PCBs are becoming increasingly miniaturized and denser. Chips are becoming smaller, yet their computing speeds are increasing. Consequently, the heat generated by these chips is also increasing. Any chip must operate within a certain operating range. To maintain this operating range, the heat generated by the chip must be quickly conducted away; otherwise, its performance will be limited.

[0025] In the prior art, a heat sink is generally mounted on the surface of the chip to dissipate heat from the chip through the heat sink. However, the heat dissipation area of ​​the heat sink is small, and the air inside the heat sink has poor thermal conductivity, which cannot quickly dissipate heat from the chip.

[0026] Based on the above situation, the present application provides a bare chip packaging assembly and a preparation method thereof, which solves the problem of being unable to quickly dissipate heat from the chip by providing multiple heat sinks.

[0027] To illustrate the specific structure of the bare chip package assembly of this application, please refer to Figure 1 , Figure 1 This is a schematic structural diagram of an embodiment of a bare chip packaging assembly of the present application. Figure 1 As shown, in this embodiment, the bare chip package assembly 10 includes: a bare chip 2 and a package substrate 1, wherein the first surface 21 of the bare chip 2 is soldered to the package substrate 1; wherein the bare chip 2 includes a first surface 21 and a second surface 22 arranged opposite to each other, and a planting ball 211 is formed on the first surface 21; a first heat sink 3, wherein the first heat sink 3 is mounted on the package substrate 1; wherein the first heat sink 3 has a groove 31 arranged in a back direction to accommodate the bare chip 2; a second heat sink 4, wherein the second heat sink 4 is arranged on a side surface of the first heat sink 3 away from the bare chip 2; a plastic package 6, wherein the plastic package 6 fills the remaining space between the bare chip 2, the first heat sink 3, the second heat sink 4 and the package substrate 1; and a third heat sink 5, wherein the third heat sink 5 is arranged on a side surface of the second heat sink 4 away from the first heat sink 3.

[0028] In this embodiment, the bare die 2 refers to a silicon wafer used for manufacturing silicon semiconductor integrated circuits, and is generally called a wafer due to its circular shape.

[0029] In this embodiment, the first heat sink 3, the second heat sink 4, and the third heat sink 5 are made of copper, aluminum, or a copper-aluminum alloy. Since copper, aluminum, or a copper-aluminum alloy have excellent thermal conductivity, the heat generated by the die 2 can be quickly transferred to the outside of the die package assembly 10 through the first heat sink 3, the second heat sink 4, and the third heat sink 5.

[0030] The first heat sink 3 and the second heat sink 4 include copper blocks.

[0031] The copper block of the first heat sink 3 has a grid structure, and the size of the groove 31 is not smaller than that of the die 2 , so as to facilitate the filling of the plastic package 6 , thereby effectively protecting the die 2 through the plastic package 6 .

[0032] In a preferred embodiment, the size of the groove 31 is larger than the size of the die 2 .

[0033] In this embodiment, the second surface 22 of the bare chip 2 is connected to the surface 311 inside the groove 31 of the first heat sink 3 away from the packaging substrate 1 through non-conductive adhesive, the surface 312 of the first heat sink 3 with the groove 31 is attached to the packaging substrate 1 through non-conductive adhesive, and the second heat sink 4 is attached to the side surface of the first heat sink 3 away from the bare chip 2 through non-conductive adhesive.

[0034] Among them, the non-conductive glue is a glue with strong thermal conductivity. The bare chip 2 is tightly fitted to the surface 311 of the first heat sink 3 through the non-conductive glue, and can quickly conduct the heat generated by itself to the first heat sink 3 with a larger surface area. Since the second heat sink 4 is also tightly fitted to the first heat sink 3 through the non-conductive glue, it can quickly conduct the heat emitted from the outer shell of the first heat sink 3 to the plastic cover 61, thereby effectively reducing the operating temperature of the electronic components.

[0035] Furthermore, the third heat sink 5 comprises copper and is connected to the surface of the second heat sink 4 facing away from the first heat sink 3 via a non-conductive adhesive. The large area of ​​copper provided on the surface of the second heat sink 4 facing away from the first heat sink 3 effectively covers the entire plastic cover 61, further increasing the heat dissipation area. Heat conducted from the second heat sink 4 is then directly transferred to the external environment of the die package assembly 10, thereby rapidly dissipating heat from the die 2.

[0036] In other embodiments, the third heat sink 5 may further include a heat sink. Since the heat sink is a stacked thin plate structure, the area of ​​the heat sink is much larger than that of a single copper sheet. During the heat transfer process, the heat exchange area can be more effectively increased, accelerating the heat dissipation of the bare chip 2.

[0037] In this embodiment, the balls 211 on the first surface 21 of the die 2 are distributed in an array. The balls 211 can conduct part of the heat generated by the die 2 to the package substrate 1, thereby further optimizing the heat dissipation effect and greatly improving the thermal performance and reliability of the product.

[0038] In this embodiment, the plastic package 6 includes powdered molding materials such as epoxy resin molding compound and epoxy molding compound, which usually have high-quality properties such as chemical resistance, moisture resistance, electrical properties, mechanical properties, thermal properties and water solubility. It is filled in the remaining space between the bare chip 2, the first heat sink 3 and the second heat sink 4 and the packaging substrate 1, and can effectively protect the integrated circuit on the bare chip 2 from physical damage and adverse effects of the external environment.

[0039] Unlike existing technologies, the die package assembly of this embodiment includes a first heat sink, a second heat sink, and a third heat sink. The first heat sink includes a groove to accommodate and dissipate heat from the die, rapidly reducing the operating temperature of the electronic components within the die. The second heat sink is located on the side of the first heat sink facing away from the die, accelerating heat dissipation from the first heat sink. The third heat sink, located on the side of the second heat sink facing away from the first heat sink, conducts heat generated by the die to the exterior of the plastic cover, further enhancing heat dissipation. Furthermore, a bump is provided on the surface of the die that contacts the package substrate, which conducts some of the heat generated by the die to the package substrate, further optimizing heat dissipation.

[0040] See also Figure 2 , Figure 2 This is a structural diagram of another embodiment of the bare chip packaging component of the present application. Figure 2 As shown, in this embodiment, the bare chip package assembly 20 includes: a bare chip 2 and a package substrate 1, wherein the first surface 21 of the bare chip 2 is soldered to the package substrate 1; wherein the bare chip 2 includes a first surface 21 and a second surface 22 arranged opposite to each other, and a planting ball 211 is formed on the first surface 21; at least one surface-mounted component 7, wherein the surface-mounted component 7 is arranged on the package substrate 1 around the bare chip 2; a first heat sink 3, wherein the first heat sink 3 is mounted on the package substrate 1; wherein the first heat sink 3 has a groove 31 arranged in a reverse direction to accommodate the bare chip 2; a second heat sink 4, wherein the second heat sink 4 is arranged on a side surface of the first heat sink 3 away from the bare chip 2; a plastic package 6, wherein the plastic package 6 fills the remaining space between the bare chip 2, the first heat sink 3, the second heat sink 4 and the package substrate 1; and a third heat sink 5, wherein the third heat sink 5 is arranged on a side surface of the second heat sink 4 away from the first heat sink 3.

[0041] In this embodiment, the surface mount components 7 include electronic components such as resistors, capacitors, resistor arrays, capacitor arrays, inductors, diodes, transistors, IC pins, and fuses.

[0042] Specifically, surface mount components 7 offer advantages such as high reliability, small size, light weight, strong vibration resistance, automated production, high installation reliability, and a very low rate of defective solder joints. As electronic products pursue miniaturization, previously used through-hole plug-in components cannot be scaled down and are no longer suitable for use on miniature PCBs (printed circuit boards). The inclusion of surface mount components 7 on the bare chip package assembly 20 ensures a low rate of solder joint defects in electronic products.

[0043] Different from the prior art, the bare chip packaging assembly of this embodiment includes a first heat sink, a second heat sink, a third heat sink and surface mount components, and the first heat sink includes a groove to accommodate the bare chip and dissipate heat from the bare chip, which can quickly reduce the operating temperature of the electronic components in the bare chip; the second heat sink is arranged on the side surface of the first heat sink away from the bare chip, which can accelerate the heat dissipation of the first heat sink; the third heat sink is arranged on the side surface of the second heat sink away from the first heat sink, which can conduct the heat generated by the bare chip to the outside of the plastic cover to further enhance heat dissipation. Furthermore, the surface where the bare chip contacts the packaging substrate is also provided with a planting ball, which can conduct part of the heat generated by the bare chip to the packaging substrate through the planting ball to further optimize the heat dissipation effect. In addition, the surface mount components can ensure that the solder joint defect rate of the bare chip packaging assembly is low.

[0044] Correspondingly, the present application provides a method for preparing a bare chip packaging assembly.

[0045] Specifically, see Figure 3 , Figure 3 FIG. 1 is a flow chart of an embodiment of a method for preparing a bare chip package assembly of the present application. Figure 3 As shown, in this embodiment, the preparation method includes:

[0046] S31: Obtain a bare chip and a packaging substrate, and solder a first surface of the bare chip to the packaging substrate; wherein the bare chip includes a first surface and a second surface opposite to each other, and a planting ball is formed on the first surface.

[0047] In this embodiment, the bare chip is soldered to the package substrate using SMT (Surface Mounted Technology), which refers to the technology of soldering the chip to the substrate using solder paste.

[0048] Specifically, SMT does not require drilling insertion holes on the package substrate, but directly mounts the first surface of the bare chip on the package substrate through solder paste.

[0049] In this embodiment, the balls on the first surface of the die are metal balls implanted by a conventional ball implantation process.

[0050] Among them, the planting balls are distributed in an array.

[0051] Specifically, ball implantation can transfer part of the heat generated by the die to the package substrate, thereby further optimizing the heat dissipation effect and greatly improving the thermal performance and reliability of the product.

[0052] In this embodiment, only SMT is used to mount the bare chip on the package substrate.

[0053] In other embodiments, at least one surface mount component is obtained and disposed on a packaging substrate around the bare chip, which is not limited in this application.

[0054] Specifically, since surface mount components have the advantages of high reliability, small size, light weight, strong vibration resistance, automated production, high installation reliability and extremely low defective solder joint rate, using SMT to mount bare chips and surface mount components at the same time can ensure a low solder joint defect rate for electronic products.

[0055] S32: Obtain a first heat sink, and mount the first heat sink on the packaging substrate; wherein the first heat sink has a groove arranged in a back direction, and the bare chip is accommodated in the groove.

[0056] In this embodiment, the size of the groove of the first heat sink is first set according to the size of the die so that the size of the groove matches the size of the die; wherein the size of the groove is not less than the size of the die, and the size of the die includes the length, width and height of the die.

[0057] The first heat sink is a copper block, and the copper block of the first heat sink has a grid structure, so as to facilitate the subsequent filling of the plastic package.

[0058] In a preferred embodiment, the size of the recess is larger than the size of the die.

[0059] In this embodiment, non-conductive glue is coated on the second surface of the bare chip, and a groove is covered on the second surface of the bare chip so that the bare chip is accommodated in the groove; non-conductive glue is coated on the surface of the first heat sink including the groove to mount the first heat sink on the packaging substrate.

[0060] Among them, the non-conductive glue is a glue with strong thermal conductivity. The bare chip is tightly attached to the surface of the first heat sink through the non-conductive glue, and can quickly conduct the heat generated by itself to the first heat sink with a larger surface area to reduce the operating temperature of the electronic component.

[0061] S33: Obtain a second heat sink, and dispose the second heat sink on a surface of the first heat sink that is away from the die.

[0062] In this embodiment, non-conductive glue is coated on the surface of the second heat sink, and the surface coated with the non-conductive glue is mounted on a side of the first heat sink away from the bare chip.

[0063] Since the second heat sink is also tightly attached to the first heat sink through the non-conductive adhesive, the heat emitted by the first heat sink shell can be quickly conducted to the plastic cover formed after plastic sealing, thereby effectively reducing the operating temperature of the electronic components.

[0064] S34: Using a plastic package to plastic-package the bare chip, the first heat sink, and the remaining space between the second heat sink and the packaging substrate.

[0065] In this embodiment, the plastic encapsulation comprises a powdered molding compound, such as epoxy resin molding compound or epoxy molding compound, which typically exhibits excellent properties, including chemical and moisture resistance, electrical properties, mechanical properties, thermal properties, and water solubility. By filling the remaining space between the bare die, the first and second heat sinks, and the package substrate with the plastic encapsulation, the integrated circuit on the bare die can be effectively protected from physical damage and adverse environmental influences.

[0066] In this embodiment, after the plastic packaging is completed, the surface of the second heat dissipation element away from the first heat dissipation element is polished to expose the surface.

[0067] Specifically, the surface of the second heat sink away from the first heat sink is polished because a layer of plastic packaging material will also be applied to the surface of the second heat sink away from the first heat sink during plastic packaging. If this layer of plastic packaging material is not polished, the subsequently mounted third heat sink will not be able to make good contact with the second heat sink, and the heat dissipation effect will be greatly reduced.

[0068] S35: Obtain a third heat dissipation element, and dispose the third heat dissipation element on a side surface of the second heat dissipation element away from the first heat dissipation element.

[0069] In this embodiment, a third heat sink with a larger surface area is provided on the surface of the second heat sink away from the first heat sink, which can further increase the heat dissipation area and directly conduct the heat conducted by the second heat sink to the external environment of the bare chip packaging assembly, thereby quickly dissipating the heat of the bare chip.

[0070] Unlike existing technologies, this embodiment rapidly reduces the operating temperature of the electronic components within the die by providing a first heat sink, a second heat sink, and a third heat sink on the die package assembly. The first heat sink includes a groove to accommodate and dissipate heat from the die, accelerating heat dissipation from the first heat sink. The third heat sink, located on the side of the second heat sink away from the first, conducts heat generated by the die to the exterior of the plastic cover, further enhancing heat dissipation. Furthermore, a bump is provided on the surface of the die that contacts the package substrate, transferring some of the heat generated by the die to the package substrate, further optimizing heat dissipation.

[0071] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A bare chip package assembly, characterized in that: include: A bare chip and a packaging substrate, wherein the first surface of the bare chip is soldered to the packaging substrate; wherein the bare chip includes the first surface and the second surface arranged opposite to each other, and a planting ball is formed on the first surface; a first heat sink mounted on the package substrate; wherein the first heat sink has a recess disposed in a reverse direction to accommodate the die; and the second surface of the die is connected to the recess via a non-conductive adhesive; a second heat sink, the second heat sink being disposed on a surface of the first heat sink away from the die; a surface of the second heat sink being connected to a surface of the first heat sink away from the die via the non-conductive adhesive; a plastic package body, the plastic package body filling the remaining space between the bare chip, the first heat sink, the second heat sink, and the packaging substrate; A third heat sink is arranged on a side surface of the second heat sink away from the first heat sink; the third heat sink is connected to the surface of the second heat sink away from the first heat sink through the non-conductive adhesive; the materials of the first heat sink, the second heat sink and the third heat sink include copper, aluminum or copper-aluminum alloy.

2. The bare chip package assembly according to claim 1, wherein: The bare chip packaging assembly further includes at least one surface packaging component, which is disposed on the packaging substrate surrounding the bare chip.

3. A method for preparing a bare chip package assembly, characterized in that: include: Obtain a bare chip and a packaging substrate, and solder the first surface of the bare chip to the packaging substrate; wherein the bare chip includes the first surface and the second surface arranged opposite to each other, and a planting ball is formed on the first surface; Obtain a first heat sink and attach the first heat sink to the package substrate; wherein the first heat sink has a groove disposed in a reverse direction, and the die is accommodated in the groove; the second surface of the die is connected to the groove via a non-conductive adhesive; Obtain a second heat sink, and dispose the second heat sink on a surface of the first heat sink away from the die; the surface of the second heat sink is connected to the surface of the first heat sink away from the die via the non-conductive adhesive; Using a plastic package to plastic-encapsulate the bare chip, the first heat sink, the remaining space between the second heat sink and the packaging substrate; Obtain a third heat sink and set the third heat sink on a side surface of the second heat sink away from the first heat sink; the third heat sink is connected to the surface of the second heat sink away from the first heat sink through the non-conductive adhesive; the materials of the first heat sink, the second heat sink, and the third heat sink include copper, aluminum, or copper-aluminum alloy.

4. The preparation method according to claim 3, characterized in that The step of obtaining a bare chip and a packaging substrate, and soldering the first surface of the bare chip to the packaging substrate further comprises: At least one surface packaging component is obtained, and the surface packaging component is disposed on the packaging substrate around the bare chip.

5. The preparation method according to claim 3, characterized in that The step of obtaining a first heat sink and attaching the first heat sink to the package substrate, wherein the first heat sink has a groove disposed in a reverse direction, and the step of placing the die in the groove includes: The size of the groove of the first heat sink is set according to the size of the die so that the size of the groove matches the size of the die; wherein the size of the groove is not less than the size of the die, and the size of the die includes the length, width and height of the die.

6. The preparation method according to claim 5, characterized in that The step of obtaining a first heat sink and mounting the first heat sink on the package substrate, wherein the first heat sink has a groove arranged in a back direction, and accommodating the die in the groove comprises: Applying non-conductive glue on the second surface of the die, and covering the groove on the second surface of the die; The non-conductive adhesive is coated on the surface of the first heat dissipation member including the groove, so as to mount the first heat dissipation member on the packaging substrate.

7. The preparation method according to claim 3, characterized in that The step of using a plastic package to plastic-encapsulate the bare chip, the first heat sink, the remaining space between the second heat sink and the packaging substrate further comprises: After the plastic packaging is completed, the surface of the second heat dissipation member away from the first heat dissipation member is polished to expose the surface.

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