A low on-resistance double-trench gate SOI-LDMOS layout structure and a forming method thereof

Abstract

The application provides a low-conduction-resistance double-trench-gate SOI-LDMOS layout structure and a forming method thereof, and the structure at least comprises an SOI substrate and a plurality of array-arranged hexagonal LDMOS units formed in a top layer of silicon of the SOI substrate. The LDMOS power module is formed by splicing the hexagonal units, and since two trench gates are formed, there are two longitudinal conductive channels in the module, so that the current conduction resistance is reduced, the device current density is increased, and the device performance is obviously improved. The hexagonal ring-shaped trench gate makes the current channel also have six directions, and the current processing capacity is doubled compared with the traditional strip-shaped gate device. The hexagonal array-distributed LDMOS units can make the chip area utilization reach the optimum, and there is no area waste, which is obviously superior to the traditional circular array distribution.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a low on-resistance double trench gate SOI-LDMOS layout structure and its formation method. Background Technology

[0002] SOI (Silicon on Insulator) refers to silicon-on-insulator technology. SOI is a fully dielectric isolation technology where devices such as MOS are fabricated on a top silicon film, with an oxide layer acting as an isolation layer between the top silicon film and the substrate. This technology completely eliminates the latch-up effect of traditional bulk silicon processes, resulting in low parasitic capacitance and advantages such as high speed, low power consumption, high integration density, and high reliability. LDMOS (Lateral Double Diffused Metal Oxide Semiconductor Field Effect Transistor) has high gain, a wide linear range, and low intermodulation distortion, and is widely used in wireless communication, medical electronics, and other fields. LDMOS, fabricated based on SOI technology, combines all these advantages as a high-voltage, high-power device, exhibiting significant strengths.

[0003] However, conventional power LDMOS currently uses a planar gate distribution and a single channel, which limits the effective improvement of current density. Meanwhile, conventional high-power LDMOS uses a strip or circular array distribution, which cannot effectively utilize chip area. If power performance can be maintained while miniaturizing the power LDMOS which occupies a large chip area, the competitiveness of the BCD process platform can be significantly improved.

[0004] Therefore, providing a novel low on-resistance dual-trench gate SOI-LDMOS layout structure and its formation method is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a low on-resistance dual trench gate SOI-LDMOS layout structure and its formation method, so as to solve the problem of large chip area occupied by high power LDMOS in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a low on-resistance dual-trench-gate SOI-LDMOS layout structure, the structure comprising at least an SOI substrate and a plurality of arrayed hexagonal LDMOS cells formed in the top silicon layer of the SOI substrate, wherein the hexagonal LDMOS cells include:

[0007] The active region is hexagonal;

[0008] The first trench oxide layer, in the form of a hexagonal ring, is formed in the active region;

[0009] The well region, which is hexagonal in shape, is formed on the periphery of the first trench oxide layer, and the well region is lower than the surface of the active region;

[0010] The second trench oxide layer is hexagonal and is formed around the first trench oxide layer and penetrates the well region;

[0011] The first gate layer, which is hexagonal in shape, is formed in the first trench oxide layer;

[0012] The second gate layer, which is hexagonal in shape, is formed in the second trench oxide layer;

[0013] The drain doped region is hexagonal and is formed in the annular surrounding region of the first trench oxide layer;

[0014] The source doped region, in the form of a hexagonal ring, is formed above the well region;

[0015] The bulk doped region, in the form of a hexagonal ring, is formed in the source doped region above the well region.

[0016] Preferably, the first gate layer is located near the outer edge of the first trench oxide layer.

[0017] Preferably, the depth of the second trench oxide layer is greater than the depth of the first trench oxide layer.

[0018] Preferably, the active region, the first trench oxide layer, the well region, the second trench oxide layer, the first gate layer, the second gate layer, the drain doped region, the source doped region, and the body doped region are concentric structures with a common axis of symmetry.

[0019] The present invention also provides a method for forming a low on-resistance dual trench gate SOI-LDMOS layout structure, the method comprising at least: firstly providing an SOI substrate; and then forming a plurality of arrayed hexagonal LDMOS cells in the top silicon layer of the SOI substrate, wherein the method for forming the hexagonal LDMOS cells includes:

[0020] A hexagonal active region is formed in the top silicon layer of the SOI substrate;

[0021] A first trench oxide layer is formed in the active region, and the first trench oxide layer is hexagonal.

[0022] A trap region is formed around the first trench oxide layer. The trap region is hexagonal and lower than the surface of the active region.

[0023] A second trench oxide layer is formed around the first trench oxide layer, the second trench oxide layer being hexagonal and penetrating the well region;

[0024] A first gate layer is formed in the first trench oxide layer, and the first gate layer is hexagonal;

[0025] A second gate layer is formed in the second trench oxide layer, and the second gate layer is hexagonal;

[0026] A hexagonal drain doped region is formed in the annular surrounding region of the first trench oxide layer;

[0027] A source doped region is formed above the well region, and the source doped region layer is hexagonal;

[0028] A bulk doped region is formed in the source doped region above the well region, and the bulk doped region is hexagonal.

[0029] Preferably, an etching and deposition process is used to form a first gate layer in the first trench oxide layer, and the first gate layer is close to the outer edge of the first trench oxide layer.

[0030] Preferably, a second gate layer is formed in the second trench oxide layer using etching and deposition processes, wherein the depth of the second trench oxide layer is greater than the depth of the first trench oxide layer.

[0031] Preferably, the active region, the first trench oxide layer, the well region, the second trench oxide layer, the first gate layer, the second gate layer, the drain doped region, the source doped region, and the body doped region are concentric structures with a common axis of symmetry.

[0032] As described above, the low on-resistance dual trench gate SOI-LDMOS layout structure and its formation method of the present invention have the following beneficial effects: The present invention forms an LDMOS power module by splicing hexagonal cells. Since two trench gates are formed, there are two longitudinal conductive channels in the module, which can reduce the on-resistance, increase the device current density, and significantly improve the device performance; Since the present invention forms a hexagonal ring trench gate, the current channel is also in 6 directions, which doubles the current handling capability compared to the traditional strip gate device; In the present invention, the LDMOS cells are distributed in a hexagonal array, which can optimize the chip area utilization and eliminate area waste, which is significantly better than the traditional circular array distribution. Attached Figure Description

[0033] Figures 1-10 This is a schematic diagram illustrating the various steps of the method for forming a low on-resistance dual trench gate SOI-LDMOS layout structure according to the present invention. Figure 9 and Figure 10This is the low on-resistance dual trench gate SOI-LDMOS layout structure of the present invention;

[0034] Figure 11 This is a metal lead diagram of the layout structure of the present invention;

[0035] Figure 12 This is a top view of the overall layout structure of a low on-resistance dual trench gate SOI-LDMOS.

[0036] Component designation explanation

[0037] 10 SOI substrate

[0038] 101 Underlying Silicon

[0039] 102 Buried Oxygen Layer

[0040] 103 Top-layer silicon

[0041] 20 LDMOS cells

[0042] 201 Active Zone

[0043] 202 First trench oxide layer

[0044] 203 Tunnel Area

[0045] 204 Second trench oxide layer

[0046] 205 First gate layer

[0047] 206 Second gate layer

[0048] 207 Drain Doped Region

[0049] 208 source doped region

[0050] 209 bulk doped region Detailed Implementation

[0051] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] Please refer to the accompanying drawings. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] This embodiment provides a method for forming a low on-resistance dual-trench-gate SOI-LDMOS layout structure, such as Figures 1-10 As shown, the formation method includes at least the following steps: first, providing an SOI substrate 10; then forming a plurality of arrayed hexagonal LDMOS cells 20 in the top silicon layer of the SOI substrate 10, wherein the method for forming the hexagonal LDMOS cells 20 includes the following steps:

[0054] First, please refer to Figure 1 and Figure 2 A hexagonal active area 201 is formed in the top silicon 103 of the SOI substrate 10.

[0055] The SOI substrate 1 includes a bottom silicon layer 101, an intermediate buried oxide layer (BOX) 102, and a top silicon layer 103. The hexagonal LDMOS cell 20 is formed in the top silicon layer 103.

[0056] in, Figure 1 This is a top view. Figure 2 For along Figure 1 The accompanying diagram shows a cross-sectional view along the AA' direction. All cross-sectional views in the diagram are along the AA' direction and will not be explained further below. In this step, the location of the active region 201 is defined in the top silicon layer 103.

[0057] Then, please refer to Figure 3 and Figure 4 A first trench oxide layer 202 is formed in the active region 201, and the first trench oxide layer 202 is hexagonal.

[0058] The first trench oxide layer 202 can be formed by etching followed by deposition. The etching can include one or a combination of dry etching or wet etching, and the deposition step can be thermal oxidation or chemical vapor deposition, etc., which are not limited here.

[0059] in, Figure 3 This is a top view. Figure 4 This is a cross-sectional view.

[0060] Then, please refer to Figure 4 A trap region 203 is formed on the periphery of the first trench oxide layer 202. The trap region 203 is hexagonal and lower than the surface of the active region 201.

[0061] The well region 203 is ion implanted and doped according to the specific device type. In this embodiment, the well region 203 is a P-type well region (PW).

[0062] Next, please refer to Figure 5 and Figure 6A second trench oxide layer 204 is formed on the periphery of the first trench oxide layer 202. The second trench oxide layer 204 is hexagonal and penetrates the well region 203.

[0063] As an example, the depth of the second trench oxide layer 204 is greater than the depth of the first trench oxide layer 202.

[0064] in, Figure 5 This is a top view. Figure 6 This is a cross-sectional view.

[0065] Next, please refer to Figure 7 and Figure 8 A first gate layer 205 is formed in the first trench oxide layer 202, and the first gate layer 205 is hexagonal. A second gate layer 206 is formed in the second trench oxide layer 204, and the second gate layer 206 is hexagonal.

[0066] Preferably, an etching and deposition process is used to form a first gate layer 205 in the first trench oxide layer 202, and the first gate layer 205 is close to the outer edge of the first trench oxide layer 202.

[0067] Preferably, an etching and deposition process is used to form a second gate layer 206 in the second trench oxide layer 204, and the depth of the second gate layer 206 is greater than the depth of the first gate layer 205.

[0068] in, Figure 7 This is a top view. Figure 8 This is a cross-sectional view.

[0069] It should be noted that, since the width of the second gate layer 206 is almost the same as the width of the second trench oxide layer 204, for ease of illustration, Figure 7 The second trench oxide layer 204 is not shown in the top view.

[0070] Next, please refer to Figure 9 and Figure 10 A hexagonal drain doped region 207 is formed in the annular surrounding region of the first trench oxide layer 202. A source doped region 208 is formed above the well region 203, and the source doped region 208 layer is hexagonal. A body doped region 209 is formed in the source doped region 208 above the well region 203, and the body doped region 209 is hexagonal.

[0071] in, Figure 9 This is a top view. Figure 10 This is a cross-sectional view.

[0072] As an example, the hexagonal drain doped region 207 is formed into an N+ doped region by ion implantation as needed, the source doped region 208 is also formed into an N+ doped region by ion implantation, and the bulk doped region 209 is formed into a P+ doped region by ion implantation.

[0073] In addition, a metal lead layer needs to be fabricated to bring out the electrical properties of the device; specifically, such as... Figure 11 As shown, the drain doped region (N+) 207 is led out through metal leads (D), the source doped region (N+) 208 is led out through metal leads (S), the body doped region (P+) 209 is led out through metal leads (B), and the first gate layer 205 and the second gate layer 206 are led out in parallel through metal leads (G).

[0074] Finally, as Figure 12 The top view shown shows that hexagonal LDMOS cells 20 are combined and spliced ​​into an array to form an LDMOS power module.

[0075] This module features two trench gates, a first gate layer 205 and a second gate layer 206, with two longitudinal conductive channels. This reduces on-resistance, increases current density, and significantly improves device performance. Furthermore, the hexagonal annular trench gate provides current channels in six directions, enhancing current handling capability. Additionally, the hexagonal LDMOS cell 20 fully utilizes the chip area, reducing wasted space.

[0076] As an example, the active region 201, the first trench oxide layer 202, the well region 203, the second trench oxide layer 204, the first gate layer 205, the second gate layer 206, the drain doped region 207, the source doped region 208, and the body doped region 209 are concentric structures with a common axis of symmetry.

[0077] like Figures 9-12 As shown, this embodiment also provides a low on-resistance dual trench gate SOI-LDMOS layout structure, which includes, but is not limited to, the structure formed using the above methods. The structure includes at least an SOI substrate 10 and a plurality of arrayed hexagonal LDMOS cells 20 formed in the top silicon layer of the SOI substrate 10. The hexagonal LDMOS cells 20 include: an active region 201, a first trench oxide layer 202, a well region 203, a second trench oxide layer 204, a first gate layer 205, a second gate layer 206, a drain doped region 207, a source doped region 208, and a body doped region 209.

[0078] The active region 201 is hexagonal;

[0079] The first trench oxide layer 202 is hexagonal and is formed in the active region 201;

[0080] The well region 203 is hexagonal and is formed on the periphery of the first trench oxide layer 202, and the well region 203 is lower than the surface of the active region 201.

[0081] The second trench oxide layer 204 is hexagonal and is formed on the periphery of the first trench oxide layer 202 and penetrates the well region 203;

[0082] The first gate layer 205 is hexagonal and is formed in the first trench oxide layer 202;

[0083] The second gate layer 206 is hexagonal and is formed in the second trench oxide layer 204;

[0084] The drain doped region 207 is hexagonal and is formed in the annular surrounding region of the first trench oxide layer 202;

[0085] The source doped region 208 is hexagonal and is formed above the well region 203;

[0086] The bulk doped region 209 is hexagonal and is formed in the source doped region 208 above the well region 203.

[0087] As an example, the first gate layer is located near the outer edge of the first trench oxide layer 202.

[0088] As an example, the depth of the second trench oxide layer 204 is greater than the depth of the first trench oxide layer 202.

[0089] As an example, the active region 201, the first trench oxide layer 202, the well region 203, the second trench oxide layer 204, the first gate layer 205, the second gate layer 206, the drain doped region 207, the source doped region 208, and the body doped region 209 are concentric structures with a common axis of symmetry.

[0090] Other features and beneficial effects of this map structure have been described in the embodiments of the formation method and will not be repeated here.

[0091] In summary, this invention provides a low on-resistance dual-trench-gate SOI-LDMOS layout structure and its formation method. The structure includes at least an SOI substrate 10 and a plurality of arrayed hexagonal LDMOS cells 20 formed in the top silicon layer of the SOI substrate 10. This invention forms an LDMOS power module by splicing hexagonal cells. Because two trench gates are formed, the module has two longitudinal conductive channels, which reduces on-resistance, increases current density, and significantly improves device performance. The hexagonal annular trench gate also provides six current channels, doubling the current handling capability compared to traditional strip-gate devices. The hexagonal array of LDMOS cells optimizes chip area utilization with no wasted area, significantly superior to traditional circular array distributions.

[0092] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A low on-resistance double-trench gate SOI-LDMOS layout structure, characterized in that, The structure comprises at least an SOI substrate and a plurality of arrayed hexagonal LDMOS cells formed in a top silicon layer of the SOI substrate, the hexagonal LDMOS cell comprising: an active region in a hexagonal shape; a first trench oxide layer in a hexagonal ring shape formed in the active region; a well region in a hexagonal ring shape formed at a periphery of the first trench oxide layer and lower than a surface of the active region; a second trench oxide layer in a hexagonal ring shape formed at a periphery of the first trench oxide layer and penetrating through the well region; a first gate layer in a hexagonal ring shape formed in the first trench oxide layer; a second gate layer in a hexagonal ring shape formed in the second trench oxide layer; a drain doped region in a hexagonal shape formed in a ring-enclosed area of the first trench oxide layer; a source doped region in a hexagonal ring shape formed above the well region; a body doped region in a hexagonal ring shape formed in the source doped region above the well region; the active region, the first trench oxide layer, the well region, the second trench oxide layer, the first gate layer, the second gate layer, the drain doped region, the source doped region and the body doped region are concentric structures with a common symmetry axis. 2.The low on-resistance double-trench gate SOI-LDMOS layout structure according to claim 1, characterized in that: the first gate layer is close to an outer edge of the first trench oxide layer. 3.The low on-resistance double-trench gate SOI-LDMOS layout structure according to claim 1, characterized in that: a depth of the second trench oxide layer is greater than a depth of the first trench oxide layer.

4. A forming method of a low on-resistance double-trench gate SOI-LDMOS layout structure, characterized in that, The forming method comprises at least: firstly providing an SOI substrate; and then forming a plurality of arrayed hexagonal LDMOS cells in a top silicon layer of the SOI substrate, wherein the method of forming the hexagonal LDMOS cell comprises: forming a hexagonal active region in the top silicon layer of the SOI substrate; forming a first trench oxide layer in the active region, the first trench oxide layer being in a hexagonal ring shape; forming a well region at a periphery of the first trench oxide layer, the well region being in a hexagonal ring shape and lower than a surface of the active region; forming a second trench oxide layer at a periphery of the first trench oxide layer, the second trench oxide layer being in a hexagonal ring shape and penetrating through the well region; forming a first gate layer in the first trench oxide layer, the first gate layer being in a hexagonal ring shape; forming a second gate layer in the second trench oxide layer, the second gate layer being in a hexagonal ring shape; forming a hexagonal drain doped region in a ring-enclosed area of the first trench oxide layer; forming a source doped region above the well region, the source doped region being in a hexagonal ring shape; forming a body doped region in the source doped region above the well region, the body doped region being in a hexagonal ring shape; the active region, the first trench oxide layer, the well region, the second trench oxide layer, the first gate layer, the second gate layer, the drain doped region, the source doped region and the body doped region are concentric structures with a common symmetry axis.

5. The forming method of low on-resistance double-trench gate SOI-LDMOS layout structure according to claim 4, characterized in that: forming the first gate layer in the first trench oxide layer by etching and depositing processes, the first gate layer being close to an outer edge of the first trench oxide layer.

6. The forming method of low on-resistance double-trench gate SOI-LDMOS layout structure according to claim 4, characterized in that: forming the second gate layer in the second trench oxide layer by etching and depositing processes, a depth of the second trench oxide layer being greater than a depth of the first trench oxide layer.

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