Memory device, manufacturing method thereof, and electronic device including the memory device

Abstract

Disclosed are a memory device, a method for manufacturing the same, and an electronic device including the memory device. According to an embodiment, the memory device may include: first to fourth connection line layers arranged sequentially in a vertical direction, the connection line layers adjacent to each other respectively including conductive lines extending in directions intersecting each other; a plurality of memory cells, each including a stacked first transistor and a second transistor. The first active layer of the first transistor includes a first source / drain region electrically connected to a corresponding conductive line in the first connection line layer and a second source / drain region electrically connected to a corresponding conductive line in the second connection line layer. The second active layer of the second transistor includes a first source / drain region electrically connected to a gate conductor layer of the first transistor and a second source / drain region electrically connected to a corresponding conductive line in a third connection line layer. The gate conductor layer of the second transistor of each memory cell is electrically connected to a corresponding conductive line in the fourth connection line layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular, to a memory device and a method for manufacturing the same, as well as an electronic device including the memory device. Background Art

[0002] Dynamic random access memory (DRAM) often uses capacitors as storage elements. For example, in a common 1T1C configuration, there is one (1) transistor (T) as a switching device and one (1) capacitor (C) as a storage element. However, as the size of memory devices continues to shrink, the area used to make capacitors also becomes smaller, making it difficult to ensure that the capacitor has a large enough capacitance to retain data.

[0003] A 2T0C DRAM configuration that doesn't use capacitors has been proposed. This configuration has a read transistor and a write transistor, and the gate capacitance of the read transistor can be used as a storage element instead of a capacitor. However, the 2T0C configuration occupies a relatively large area. Summary of the Invention

[0004] In view of this, an object of the present disclosure is at least partially to provide a memory device capable of saving area, a method for manufacturing the same, and an electronic device including the memory device.

[0005] According to one aspect of the present disclosure, a memory device is provided, comprising: a first connection line layer, a second connection line layer, and a third connection line layer sequentially arranged in a vertical direction relative to a substrate, wherein the first connection line layer comprises a plurality of first conductive lines extending parallel to each other along a first direction, the second connection line layer comprises a plurality of second conductive lines extending parallel to each other along a second direction intersecting the first direction, and the third connection line layer comprises a plurality of third conductive lines extending parallel to each other along the first direction; a plurality of memory cells, wherein each memory cell vertically extends from a corresponding first conductive line in the first connection line layer through a corresponding second conductive line in the second connection line layer and a corresponding third conductive line in the third connection line layer, and comprises a first transistor and a second transistor stacked on each other in the vertical direction, wherein the first transistor comprises: a first active layer comprising a first active layer electrically connected to the corresponding first conductive line in the first connection line layer; a source / drain region, a second source / drain region electrically connected to a corresponding second conductive line in a second connecting line layer, and a channel region between the first source / drain region and the second source / drain region; a first gate dielectric layer on the first active layer; and a first gate conductor layer on the first gate dielectric layer, the second transistor comprising: a second active layer, comprising a first source / drain region electrically connected to the first gate conductor layer, a second source / drain region electrically connected to a corresponding third conductive line in a third connecting line layer, and a channel region between the first source / drain region and the second source / drain region, wherein adjacent portions of the first active layer and the second active layer are substantially aligned in a vertical direction; a second gate dielectric layer on the second active layer; and a second gate conductor layer on the second gate dielectric layer; a fourth connecting line layer, above the memory cell, comprising a plurality of fourth conductive lines extending along a second direction, wherein the second gate conductor layer of each memory cell is electrically connected to a corresponding fourth conductive line in the fourth connecting line layer.

[0006] According to another aspect of the present disclosure, a method for manufacturing a memory device is provided, comprising: providing a first isolation layer on a substrate; forming a first connection line layer on the first isolation layer, and patterning the first connection line layer into a plurality of first conductive lines extending parallel to each other along a first direction; forming a second isolation layer on the first isolation layer and the first connection line layer; forming a second connection line layer on the second isolation layer, and patterning the second connection line layer into a plurality of second conductive lines extending parallel to each other along a second direction intersecting the first direction; forming a third isolation layer on the second isolation layer and the second connection line layer; forming a third connection line layer on the third isolation layer, and patterning the third connection line layer into a plurality of third conductive lines extending parallel to each other along the first direction; forming a fourth isolation layer on the third isolation layer and the third connection line layer; forming a plurality of openings, each opening passing through the fourth isolation layer, a corresponding third conductive line in the third connection line layer, the third isolation layer, a corresponding second conductive line in the second connection line layer, the second isolation layer, and entering a corresponding first conductive line in the first connection line layer; first crystals stacked vertically on each other in each opening; A body transistor and a second transistor are used to form a memory cell, wherein the first transistor comprises: a first active layer, comprising a first source / drain region electrically connected to a corresponding first conductive line in a first connecting line layer, a second source / drain region electrically connected to a corresponding second conductive line in a second connecting line layer, and a channel region between the first source / drain region and the second source / drain region; a first gate dielectric layer on the first active layer; and a first gate conductor layer on the first gate dielectric layer; the second transistor comprises: a second active layer, comprising a first source / drain region electrically connected to the first gate conductor layer, a second source / drain region electrically connected to a corresponding third conductive line in a third connecting line layer, and a channel region between the first source / drain region and the second source / drain region, wherein adjacent portions of the first active layer and the second active layer are substantially aligned in a vertical direction; a second gate dielectric layer on the second active layer; and a second gate conductor layer on the second gate dielectric layer; a fourth connecting line layer is formed on the fourth isolation layer, the fourth connecting line layer comprising a plurality of fourth conductive lines extending along the second direction, wherein the second gate conductor layer of each memory cell is electrically connected to a corresponding fourth conductive line in the fourth connecting line layer.

[0007] According to another aspect of the present disclosure, an electronic device is provided, comprising the above-mentioned memory device.

[0008] According to an embodiment of the present disclosure, a memory device is provided in which transistors constituting a memory cell are stacked on top of each other, thereby saving area. In particular, the stacked transistors in each memory cell can be self-aligned in the vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figures 1(a) to 10(c) A schematic diagram showing some stages in a process of manufacturing a memory device according to an embodiment of the present disclosure is shown;

[0011] Figures 11(a) to 14(b) A schematic diagram showing some stages in a process of manufacturing a memory device according to another embodiment of the present disclosure is shown;

[0012] Figure 15 Schematically shows an equivalent circuit diagram of a memory cell according to an embodiment of the present disclosure,

[0013] in, Figure 1(a) 、 3(a) , 6(a), 9(a), and 10(a) are top views, and FIG1(a) shows the positions of the AA′ and BB′ lines.

[0014] Figure 1(b) 、 3(b) , 4(a), 5(a), 6(b), 9(b), 10(b), 11(a), 12(a), 13(a), 14(a) are cross-sectional views along line AA′,

[0015] Figure 1(c) 、 2 , 4(b), 5(b), 6(c), 7, 8, 9(c), 9(d), 10(c), 11(b), 12(b), 13(b), and 14(b) are cross-sectional views along line BB′.

[0016] Throughout the drawings, the same or similar reference numerals refer to the same or similar parts. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0018] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0019] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0020] The memory device according to the embodiments of the present disclosure is based on a vertical device. The vertical device may include a vertical active region relative to the substrate, including source / drain regions at the top and bottom ends and a channel region located between the source / drain regions. A conductive channel may be formed between the source / drain regions through the channel region.

[0021] According to an embodiment of the present disclosure, the position of the source / drain region can be defined in the active area by an electrode. For example, the active area can be defined by a semiconductor layer (taking into account the manufacturing process, there may be a laterally extending bottom, as described below) that extends substantially in a vertical direction (a direction roughly perpendicular to the substrate surface). The region in the semiconductor layer that is connected to the electrode (for example, the conductive line or gate length control pad described below) (for example, the region at the upper and lower ends of the semiconductor layer) can form a source / drain region, and the region between the source / drain region can form a channel region. The gate conductor layer can face the channel region through the gate dielectric layer to control the channel region.

[0022] The memory device according to an embodiment of the present disclosure may be a dynamic random access memory (DRAM) and may have a capacitor-free configuration, such as a 2T0C configuration. In the 2T0C configuration, each memory cell of the memory device may have two transistors, i.e., a first transistor (e.g., a read transistor) and a second transistor (e.g., a write transistor). As described above, the two transistors may be vertical devices and may therefore be easily stacked on top of each other, thereby saving area. The two transistors may be defined by corresponding active regions (in combination with corresponding gate stacks) respectively, and may be self-aligned as described below. For example, adjacent portions of the active layers of the two transistors (e.g., the vertically extending semiconductor layers) may be substantially aligned in the vertical direction. In addition, an isolation portion may be provided between the two transistors (active regions) to achieve electrical isolation. As described below, such an isolation portion may also be self-aligned. The self-aligned configuration may further save area.

[0023] The electrodes may include bit lines and word lines of the memory device. According to an embodiment of the present disclosure, a plurality of connection line layers at different levels may be provided to define source / drain regions at different heights of the active area. For example, a first connection line layer, a second connection line layer, and a third connection line layer may be provided, which include conductive materials and may be patterned as first conductive lines, second conductive lines, and third conductive lines, respectively. To facilitate the manufacture of the array, the conductive lines in the connection line layers adjacent in the vertical direction may extend in directions that intersect (e.g., perpendicularly) with each other, so that they may intersect with each other, and the memory cells may be formed at the intersections. The first connection line layer may be provided at a vertical height of the lower end of the active area of ​​the first transistor to define the source / drain region of the lower end of the first transistor, and the second connection line layer may be provided at a vertical height of the upper end of the active area of ​​the first transistor to define the source / drain region of the upper end of the first transistor. The third connection line layer may be provided at a vertical height of the upper end of the active area of ​​the second transistor to define the source / drain region of the upper end of the second transistor. In the case of a 2T0C configuration, the gate of the first transistor can be electrically connected to a source / drain region of the second transistor (for example, the source / drain region at the lower end), so for the second transistor, the source / drain region at the lower end thereof can be defined by the gate conductor layer of the first transistor without the need to separately provide a corresponding connection line layer. In addition, a fourth connection line layer including a fourth conductive line can be provided to achieve electrical connection to the gate of each second transistor. In the 2T0C configuration, the first conductive line can be one of a read bit line (RBL) and a read word line (RWL), the second conductive line can be the other of the read bit line (RBL) and the read word line (RWL), the third conductive line can be a write bit line (WBL), and the fourth conductive line can be a write word line (WWL).

[0024] Each memory cell can be formed to pass through the connection line layers used to define the source / drain regions (for the first through third connection line layers described above, the bottommost first connection line layer may only pass through a portion of its thickness). That is, each memory cell can be formed within an opening where the conductive lines intersect. The semiconductor layer serving as the active region of the first transistor (hereinafter referred to as the "first active layer") can be formed along the sidewalls of the opening and, due to the manufacturing process, can also extend along the bottom wall of the opening. Thus, the first active layer can have a cup shape. The first gate dielectric layer of the first transistor can extend along the inner wall of the cup-shaped first active layer, and the first gate conductor layer can fill the inner space of the first gate dielectric layer. Similarly, the semiconductor layer serving as the active region of the second transistor (hereinafter referred to as the "second active layer") can be formed along the sidewalls of the opening and, due to the manufacturing process, can also extend along the top of the first transistor. Thus, the second active layer can also have a cup shape. The second gate dielectric layer of the second transistor can extend along the inner wall of the cup-shaped second active layer, and the second gate conductor layer can fill the inner space of the second gate dielectric layer. The two transistors can be formed in an opening formed based on the same mask and can thus be self-aligned with each other. For example, adjacent portions of the outer sidewalls of the two transistors can be substantially coplanar in the vertical direction (defined by the inner sidewalls of the opening).

[0025] The first transistor and the second transistor may be in substantially the same or similar form: a cup-shaped active layer; a gate stack (including a gate dielectric layer and a gate conductor layer) provided on the inner side of the cup-shaped active layer; and a connecting line layer provided on the outer side of the cup-shaped active layer to define the source / drain region. Their respective active layers and gate stacks may have the same configuration, or may have different configurations to further optimize device performance. For example, when used as a read transistor, the first active layer of the first transistor may include a semiconductor material with relatively high mobility to reduce the read time (or increase the read speed); and when used as a write transistor, the second active layer of the second transistor may include a semiconductor material with relatively low leakage or a relatively large bandgap to increase data retention capability.

[0026] In order to achieve electrical isolation between the first active layer and the second active layer, an isolation portion can be provided between them. This isolation portion can be implemented as a sidewall formed on the sidewall of the opening, and can therefore be self-aligned between the first active layer and the second active layer. Here, the isolation portion can expose the first gate conductor layer to achieve electrical connection between the lower source / drain region of the second transistor and the gate electrode of the first transistor as described above. For example, the second active layer can be in direct physical contact with the first gate conductor layer. On the one hand, due to the presence of the first gate conductor layer, the lower source / drain region is defined at the corresponding position of the second active layer; on the other hand, the direct physical contact between them achieves electrical connection between the lower source / drain region of the second transistor and the gate electrode of the first transistor. Alternatively, a connection portion, such as a metal, can be further provided between the second active layer and the first gate conductor layer to reduce the contact resistance between the two.

[0027] Such a memory device can be manufactured, for example, as follows.

[0028] Multiple isolation layers and multiple connection line layers can be alternately arranged on the substrate, for example, a first isolation layer, a first connection line layer, a second isolation layer, a second connection line layer, a third isolation layer, a third connection line layer, and a fourth isolation layer. As described above, each connection line layer can be patterned into a corresponding conductive line. Openings can be formed at the intersection of each conductive line, so that these openings can vertically pass through each connection line layer (for the bottom first connection line layer, these openings can only pass through part of its thickness). Memory cells can be formed in each opening. As described above, each memory cell can include a first transistor and a second transistor stacked on top of each other. Transistors can be formed by sequentially forming corresponding active layers, gate dielectric layers, and gate conductor layers into the openings. After forming the first transistor and before forming the second transistor, an isolation portion can be formed on the sidewalls of the opening using a sidewall process to shield the top of the first active layer. In addition, after forming the isolation portion and before forming the second transistor, a connection portion (for example, metal) can be formed on the first transistor in the opening to physically contact the first gate conductor layer. In addition, a fourth connection line layer including fourth conductive lines may be formed on the fourth isolation layer to achieve electrical connection to the gates of the second transistors.

[0029] The present disclosure can be presented in various forms, some of which are described below. In the following description, reference is made to the selection of various materials. In addition to considering its function (for example, semiconductor materials are used to form active areas, dielectric materials are used to form electrical isolation, conductive materials are used to form electrodes, interconnect structures, etc.), the selection of materials also takes into account etching selectivity. In the following description, the required etching selectivity may or may not be indicated. It should be clear to those skilled in the art that when the following mentions etching a certain material layer, if it is not mentioned that other layers are also etched or it is not shown in the figure that other layers are also etched, then such etching can be selective, and the material layer can have etching selectivity relative to other layers exposed to the same etching recipe.

[0030] Figures 1(a) to 10(c) A schematic diagram illustrating some stages in a process of manufacturing a memory device according to an embodiment of the present disclosure is shown.

[0031] like Figure 1(a) 、 1(b) As shown in FIG1( c ), a substrate 1001 is provided. The substrate 1001 may be a substrate of various forms, including but not limited to a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, etc. In the following description, for convenience of explanation, a bulk Si substrate such as a Si wafer is used as an example.

[0032] On the substrate 1001, a first isolation layer 1003 and a first connection line layer 1005 can be formed by, for example, deposition. The first isolation layer 1003 can include a dielectric material such as an oxide (e.g., silicon oxide) to achieve electrical isolation, and its thickness can be, for example, approximately 20 nm to 200 nm. The first connection line layer 1005 can include a conductive material such as a metal such as molybdenum (Mo) or ruthenium (Ru), and its thickness can be, for example, approximately 5 nm to 100 nm. As described below, the first connection line layer 1005 can define an RBL or RWL. As bit lines or word lines, they can be multiple conductive lines extending in parallel along a certain direction.

[0033] To this end, as shown in the figure, a photoresist 1007 can be formed on the first connection line layer 1005 and patterned by photolithography into lines extending along a first direction (the horizontal direction within the paper in FIG. 1( a )). The line width of these lines can be approximately 20 nm to 500 nm, and the interval W1 between them can be approximately 10 nm to 50 nm.

[0034] like Figure 2As shown, the patterned photoresist 1007 can be used as a mask to selectively etch the first connection line layer 1005, such as by vertical reactive ion etching (RIE). The RIE can stop at the underlying first isolation layer 1003. The first connection line layer 1005 can then be patterned into a pattern corresponding to the photoresist 1007, namely, first conductive lines extending parallel in a first direction. The photoresist 1007 can then be removed.

[0035] A second isolation layer 1009 may be formed on the first connection line layer 1005, for example, by deposition. The second isolation layer 1009 may include a dielectric material such as an oxide, a nitride (e.g., silicon nitride), or a carbide (e.g., silicon carbide) to achieve electrical isolation. The deposition thickness of the second isolation layer 1009 may be controlled to be greater than W1 / 2 to fill the gaps between the first conductive lines in the first connection line layer 1005 and to achieve a sufficiently flat top surface, thereby avoiding the need for a planarization process such as chemical mechanical polishing (CMP). Avoiding a planarization process allows for better control of the thickness of the second isolation layer 1009 (particularly on the first connection line layer 1005), as this thickness will subsequently define the gate length (or channel length) of the read transistor. For example, the thickness of the second isolation layer 1009 (on the first connection line layer 1005) may be approximately 10 nm to 100 nm.

[0036] like Figure 3(a) and 3(b) As shown, a second connection line layer 1015 can be formed on the second isolation layer 1009 by, for example, deposition. Similarly, the second connection line layer 1015 can include a conductive material, such as a metal such as Mo, Ru, etc., with a thickness of, for example, about 5 nm to 20 nm. As described below, the second connection line layer 1015 can define an RWL (when the first connection line layer 1005 defines an RBL) or an RBL (when the first connection line layer 1005 defines an RWL). To facilitate the formation of an array of memory cells, the RWL or RBL defined by the second connection line layer 1015 can be formed as a conductive line extending in a direction that intersects (e.g., is perpendicular to) the RBL or RWL defined by the first connection line layer 1015.

[0037] To this end, as shown in the figure, a photoresist 1017 can be formed on the second connection line layer 1015 and patterned by photolithography into lines extending along a second direction (the vertical direction within the paper in FIG. 3( a) ) that intersects (e.g., is perpendicular) the first direction. The line width of these lines can be approximately 20 nm to 500 nm, and the interval W2 between them can be approximately 10 nm to 50 nm.

[0038] like Figure 4(a) and 4(b)As shown, the patterned photoresist 1017 can be used as a mask to selectively etch the second connection line layer 1015, such as by vertical RIE. The RIE can stop at the second isolation layer 1009 below. The second connection line layer 1015 can then be patterned into a pattern corresponding to the photoresist 1017, namely, second conductive lines extending parallel to the second direction. The photoresist 1017 can then be removed.

[0039] On the second connection line layer 1015, a third isolation layer 1019 can be formed by, for example, deposition. The third isolation layer 1019 can include dielectric materials such as oxides, nitrides, carbides, etc. to achieve electrical isolation. Similarly, the deposition thickness of the third isolation layer 1019 can be controlled to be greater than W2 / 2 to fill the gaps between the second conductive lines in the second connection line layer 1015 and to achieve a sufficiently flat top surface to avoid the use of a planarization process. Avoiding the use of a planarization process can better control the thickness of the third isolation layer 1019 (especially the thickness on the second connection line layer 1015) because the thickness will subsequently define the gate length (or channel length) of the write transistor. For example, the thickness of the third isolation layer 1019 (on the second connection line layer 1015) can be approximately 20nm to 200nm.

[0040] like Figure 5(a) and 5(b) As shown, a third connection line layer 1021 and a fourth isolation layer 1023 may be formed on the third isolation layer 1019. The third connection line layer 1021 may include a conductive material, such as a metal such as Mo or Ru, and may have a thickness of, for example, approximately 5 nm to 20 nm. As described below, the third connection line layer 1021 may define a write bit line (WBL). Here, the write bit line may be a conductive line extending in a direction that intersects (e.g., perpendicular to) a conductive line in an adjacent conductive layer (e.g., the second conductive line in the second connection line layer 1015).

[0041] In this example, the third connection line layer 1021 is shown as having substantially the same composition as the first connection line layer 1005, for example, the same mask can be used. Therefore, regarding the composition of the third connection line layer 1021, reference can be made to the above description in conjunction with FIG. Figure 1(a) 、 1(b) and 1(c) and Figure 2 However, the present disclosure is not limited thereto. As long as the conductive lines in each connection line layer have overlapping portions in the vertical direction, openings can be formed in these overlapping portions as described below and storage cells can be formed in the openings.

[0042] The fourth isolation layer 1023 may include dielectric materials such as oxide, nitride, carbide, etc. to achieve electrical isolation. The fourth isolation layer 1023 may be formed using the same process as the second isolation layer 1009, as described above. Figure 2 The description is not repeated here.

[0043] Through the above process, intersecting conductive lines (bit lines or word lines) are formed, and memory cells can be formed at the intersections of these conductive lines. More specifically, the intersecting conductive lines define areas arranged in an array on the substrate, and memory cells can be formed in these areas (in a 2TOC configuration, two transistors can be formed).

[0044] Space for the active areas of transistors in the memory cells may be defined in these regions.

[0045] For example, Figure 6(a) 、 6(b) As shown in Figures 6(c), a photoresist 1025 can be formed on the fourth isolation layer 1023. The photoresist 1025 can be patterned by photolithography to have a series of openings to expose areas where the conductive lines intersect with each other. Although the openings in the photoresist 1025 are shown as square, the shape of the openings is not limited thereto and can include various other shapes suitable for manufacturing, such as rectangular, circular, etc.

[0046] Using the thus-patterned photoresist 1025 as a mask, the underlying layers are selectively etched, such as by vertical RIE. RIE can proceed into the first connection line layer 1005 (but not to its base. Retaining a certain thickness of the first connection line layer 1005 here can increase the contact area between the first transistor to be formed later and the first connection line layer 1005, thereby reducing contact resistance). Thus, a series of openings arranged in an array are formed. The photoresist 1025 can then be removed.

[0047] Thus, each conductive line in the first connection line layer 1005, the second connection line layer 1015, and the third connection line layer 1021 has an opening corresponding to the photoresist 1025. In this example, each conductive line continues to extend continuously along the first direction or the second direction, and is not completely interrupted by such an opening. In particular, each conductive line has material that extends continuously around the periphery of the opening. However, the present disclosure is not limited to this. For example, at least some conductive lines, the opening may not be completely surrounded by the corresponding conductive line (for example, the corresponding conductive line may be biased to one side of the opening, thereby only surrounding a portion of the sidewall of the opening).

[0048] In each opening, two vertical transistors may be formed stacked on top of each other.

[0049] For example, Figure 7As shown, the first active layer 1027 can be formed in a substantially conformal manner by deposition methods such as direct current (DC) magnetron sputtering, radio frequency (RF) magnetron sputtering, atomic layer deposition (ALD), etc. The first active layer 1027 can include a semiconductor material to define an active region of a first transistor (e.g., a read transistor). For example, the first active layer 1027 can include an oxide semiconductor, such as indium gallium zinc oxide (IGZO), and have a thickness of approximately 5 nm to 100 nm.

[0050] A first gate dielectric layer 1029 may be formed on the first active layer 1027 by deposition in a substantially conformal manner. For example, the first gate dielectric layer 1029 may include an oxide dielectric such as aluminum oxide (Al2O3) with a thickness of about 2 nm to 30 nm.

[0051] Then, a first gate conductor layer 1031 can be formed by deposition. The first gate conductor layer 1031 can fill the remaining space in each opening. The first gate conductor layer 1031 can include a conductor, such as a conductive nitride such as titanium nitride (TiN), a metal such as tungsten (W), or a conductive oxide such as zinc-doped indium oxide (IZO). The first gate conductor layer 1031 can be etched back by wet etching, RIE, atomic layer etching (ALE), etc., so that its top surface is lowered to near the top surface of the second connection line layer 1015.

[0052] like Figure 8 As shown, the etched-back first gate conductor layer 1031 can be used as a mask to selectively etch the first gate dielectric layer 1029 and the first active layer 1027 by, for example, wet etching, dry etching, ALE, etc. The top surface of the first active layer 1027 may not exceed the top surface of the second connection line layer 1015.

[0053] Thus, a first transistor (eg, a read transistor) is formed in each opening. Figure 8 As shown, each first transistor may include a first active layer 1027. The first active layer 1027 may extend along the sidewalls and bottom wall of the opening, thereby forming a cup shape. The regions of the first active layer 1027 that are connected to the first connection line layer 1005 and the second connection line layer 1015 may respectively define the source / drain regions of the first transistor, while the portion between the source / drain regions is the channel region, which is controlled by the first gate conductor layer 1031 (via the first gate dielectric layer 1029). The channel length or gate length is determined by the spacing between the first connection line layer 1005 and the second connection line layer 1015 (or, in other words, the thickness of the second isolation layer 1009 therebetween).

[0054] A second transistor (e.g., a write transistor) may be formed above the first transistor in the opening. To achieve isolation between the two transistors, in particular isolation between the active regions, an isolation portion 1037 may be formed. Here, considering that the first active layer 1027 is along the sidewalls of the opening, an isolation portion 1037 in the form of a spacer may be formed on the sidewalls of the opening. For example, a layer of dielectric may be deposited in a roughly conformal manner and then the deposited dielectric may be anisotropically etched, such as by RIE in the vertical direction, to remove the lateral extension of the deposited dielectric and leave its vertical extension, thereby forming a sidewall. Taking into account the etching selectivity, for example, in the case where the isolation layers previously formed include oxides, the isolation portion 1037 may be seen to include nitrides.

[0055] Here, the isolation portion 1037 is arranged along the sidewall of the opening and exposes the first gate conductor layer 1031 in the middle of the opening, so that the first gate conductor layer 1031 is subsequently electrically connected to the second transistor.

[0056] The second transistor can be formed similarly. Figure 9(a) 、 9(b) As shown in FIG9( c ), a second active layer 1041, a second gate dielectric layer 1043 and a second gate conductor layer 1045 may be sequentially formed above the first transistor in the opening. The formation methods thereof may be combined as described above. Figure 7 Regarding the first active layer 1027, the first gate dielectric layer 1029, and the first gate conductor layer 1031, the difference is that a planarization process, such as CMP, can be performed after the deposition of the second gate conductor layer 1045, so that they can remain within the opening. The materials and thicknesses of the second active layer 1041, the second gate dielectric layer 1043, and the second gate conductor layer 1045 can be the same as those of the first active layer 1027, the first gate dielectric layer 1029, and the first gate conductor layer 1031, but can also be different. In particular, the second active layer 1041 can include a semiconductor material with relatively low leakage or a relatively large bandgap (e.g., relative to silicon) to enhance data retention, while the first active layer 1027 can include a semiconductor material with relatively high mobility (e.g., relative to silicon) to reduce read time (or increase read speed).

[0057] Thus, a second transistor (e.g., a write transistor) is formed in each opening. As shown in the figure, each second transistor may include a second active layer 1041. The second active layer 1041 may extend along the sidewalls of the opening and the top surface of the first transistor (and the isolation portion 1037), thereby forming a cup shape. The portion of the second active layer 1041 that is connected to the third connection line layer 1021 may define a source / drain region of the second transistor, and the portion of the second active layer 1041 that is connected to the first gate conductor layer 1031 may define another source / drain region of the second transistor. The portion between the source / drain region is a channel region, which is controlled by the second gate conductor layer 1045 (via the second gate dielectric layer 1043). The channel length or gate length is mainly determined by the thickness of the third isolation layer 1019.

[0058] According to another embodiment of the present disclosure, as shown in FIG9( d ), before forming the second transistor, a connection portion 1041 ′ may be formed in each opening. For example, the connection portion 1041 ′ may be formed by depositing a conductive material such as a metal, performing a planarization process such as CMP on the deposited conductive material, and etching back the planarized conductive material. The connection portion 1041 ′ may reduce the contact resistance with the first gate conductor layer 1031. In addition, the position of the bottom of the second gate conductor layer 1045 of the second transistor may also be adjusted through the connection portion 1041 ′, which may be beneficial for controlling the gate length of the second transistor as described below.

[0059] In addition, a fourth connection line layer may be formed on the fourth isolation layer 1023. Figure 10(a) 、 10(b) As shown in Figures 10 and 10 (c), a fifth isolation layer 1047 can be formed by, for example, deposition. The fifth isolation layer 1047 can include dielectric materials such as oxides, nitrides, carbides, etc. to achieve electrical isolation. In the fifth isolation layer 1047, openings corresponding to the second gate conductor layers 1045 of each second transistor and grooves extending in a direction (e.g., a second direction) that intersects (e.g., is perpendicular to) the conductive lines in the adjacent connection line layer (e.g., the third conductive lines in the third connection line layer 1021) can be formed by, for example, a dual damascene process. In the openings and grooves thus formed in the fifth isolation layer 1047, conductive material can be filled by, for example, deposition and then planarization. The conductive material filled in the openings of the fifth isolation layer 1047 can form contact plugs 1049, and the conductive material filled in the grooves of the fifth isolation layer 1047 can form fourth conductive lines 1051.

[0060] In this way, the memory cell according to this embodiment is obtained.

[0061] like Figure 15As shown, the first transistor serving as the read transistor TR can be connected between the first conductive line (e.g., one of RBL and RWL) in the first connection line layer 1005 and the second conductive line (e.g., the other of RBL and RWL) in the second connection line layer 1015, and the second transistor serving as the write transistor TW can be connected between the third conductive line (e.g., WBL) in the third connection line layer 1021 and the gate of the read transistor TR, and its gate is electrically connected to the fourth conductive line 1051 (e.g., WWL) in the fourth connection line layer.

[0062] In this memory cell, a separate storage element such as a capacitor may not be provided. Instead, the gate capacitance of the read transistor TR may serve as the storage element. The node between the write transistor and the read transistor is the storage node SN. Thus, a 2T0C configuration is obtained.

[0063] For example, a voltage of 0V can be applied to RWL, and a voltage of 0.8V can be applied to RBL. A voltage of 1V can be applied to WWL, and a voltage of 1V can be applied to WBL to store charge in the gate capacitance of the read transistor TR, thereby writing data "1". After writing the data, a voltage of -2V can be applied to WWL, and a voltage of 0V can be applied to WBL to turn off the write transistor TW. In addition, during the read operation, for example, the drain current of the read transistor TR can be monitored through RBL, and the change in the voltage at the storage node SN over time can be indirectly inferred based on the monitored current, thereby obtaining whether charge is stored in the gate capacitance of the read transistor TR (that is, whether data "0" or data "1" is stored).

[0064] In the above embodiment, the gate length of the second transistor is mainly, but not completely, determined by the thickness of the third isolation layer 1019, and thus may be subject to large process fluctuations. According to the embodiments of the present disclosure, the gate length of the second transistor can be more accurately controlled.

[0065] Figures 11(a) to 14(b) A schematic diagram illustrating some stages in a process of manufacturing a memory device according to another embodiment of the present disclosure is shown. The following mainly describes the differences between this embodiment and the above-mentioned embodiment.

[0066] Can be combined as above Figures 1(a) to 4(b) As described above, a first isolation layer 1003, a first connection line layer 1005, a second isolation layer 1009, and a second connection line layer 1015 are sequentially formed on the substrate 1001. Similarly, a third isolation layer 1019' can be formed on the second connection line layer 1015, except that a gate length control layer 1201 can be inserted into the third isolation layer 1019'. Figure 11(a) and 11(b)As shown. For example, the lower portion of the third isolation layer 1019′ can be formed on the second connection line layer 1015 in the same manner as the third isolation layer 1019 is formed above. On the lower portion of the third isolation layer 1019′, a gate length control layer 1201 can be formed by, for example, deposition. The gate length control layer 1201 may include a conductive material, such as a metal such as Mo, Ru, etc., with a thickness of, for example, about 10 nm to 150 nm. The gate length control layer 1201 can be patterned into gate length control pads corresponding to each memory cell by selective etching such as RIE. For example, the gate length control layer 1201 can be patterned based on a combined pattern of the mask for patterning the first connection line layer and the mask for patterning the second connection line layer (the pattern shown in FIG. 1( a) + the pattern shown in FIG. 3( a)), so that the resulting gate length control pad can be located where the first conductive line in the first connection line layer and the second conductive line in the second connection line layer intersect each other (for example, see the approximately square area surrounded by dotted lines shown in FIG. 6( a)). Then, an upper portion of the third isolation layer 1019 ′ may be formed on the gate length control layer 1201 in the same manner as the above formation of the third isolation layer 1019 .

[0067] Next, the process can be carried out as in the above embodiment. Figure 12(a) and 12(b) As shown in FIG. 1 , the space for the active area of ​​the transistor in the memory cell can be defined, that is, a series of openings arranged in an array can be formed. Similarly, these openings also pass through the corresponding gate length control pads in the gate length control layer 1201. Then, as shown in FIG. Figure 13(a) and 13(b) A first transistor may be formed in these openings as shown, and as Figure 14(a) and 14(b) As shown, a second transistor may be formed above the first transistor in these openings.

[0068] Here, a connection portion 1041′ is provided to better define the lower end of the channel region of the second transistor. More specifically, the top surface of the connection portion 1041′ can be between the top surface and the bottom surface of the gate length control layer 1201 (and therefore connected to the gate length control layer 1201), so that the lower portion of the second active layer 1041 is surrounded by a conductive material such as metal (the connection portion 1041′, the gate length control pad in the gate length control layer 1201), and is therefore defined as the source / drain region at the lower end. The top of the lower end source / drain region is defined by the top surface of the gate length control layer 1201. On the other hand, the bottom of the upper end source / drain region is defined by the bottom surface of the third connection line layer 1021. Therefore, the length of the channel region (or gate length) between the upper source / drain region and the lower source / drain region can be determined by the distance between the top surface of the gate length control layer 1201 and the bottom surface of the third connection line layer 1021, that is, the thickness of the upper portion of the third isolation layer 1019' (the thickness above the gate length control layer 1201). Here, the bottom surface of the gate conductor layer 1045 is located between the top and bottom surfaces of the gate length control layer 1201 so as to cover the entire vertical range of the distance or thickness.

[0069] In this example, the top surface of the connecting portion 1041′ is shown to be substantially flat and is located between the top and bottom surfaces of the gate length control layer 1201. However, the present disclosure is not limited to this. The top surface of the connecting portion 1041′ may not be flat, but may have a shape such as being lower in the middle of the opening and higher near the sidewalls of the opening, especially when the opening is thinner. Alternatively, the connecting portion 1041′ may not be provided. In these cases, the bottom of the second active layer 1041 may also extend non-flatly on the lower structure, for example, on the connecting portion 1041′ (low in the middle and high on both sides), or, in the case where the connecting portion 1041′ is not provided, on the gate conductor layer 1031 and the isolation portion 1037 as in the above embodiment. At this time, the bottom surface of the gate conductor layer 1045 may not be flat, and its lowest point may be lower than the top surface of the gate length control pad so as to cover the entire vertical range of the spacing or the thickness.

[0070] The memory device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, the memory device can store various programs, applications, and data required for the operation of the electronic device. The electronic device may also include a processor that cooperates with the memory device. For example, the processor can operate the electronic device by running the program stored in the memory device. Such electronic devices include smart phones, personal computers (PCs), tablet computers, artificial intelligence devices, wearable devices, or mobile power supplies.

[0071] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0072] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A storage device comprising: a first connection line layer, a second connection line layer, and a third connection line layer sequentially arranged in a vertical direction relative to a substrate, wherein the first connection line layer includes a plurality of first conductive lines extending parallel to one another along a first direction, the second connection line layer includes a plurality of second conductive lines extending parallel to one another along a second direction intersecting the first direction, and the third connection line layer includes a plurality of third conductive lines extending parallel to one another along the first direction; a plurality of memory cells, wherein each memory cell vertically extends from a corresponding first conductive line in the first connection line layer through a corresponding second conductive line in the second connection line layer and a corresponding third conductive line in the third connection line layer, and includes a first transistor and a second transistor stacked on each other in a vertical direction, wherein The first transistor includes: a first active layer comprising a first source / drain region electrically connected to a corresponding first conductive line in the first connection line layer, a second source / drain region electrically connected to a corresponding second conductive line in the second connection line layer, and a channel region between the first source / drain region and the second source / drain region; a first gate dielectric layer on the first active layer; and a first gate conductor layer on the first gate dielectric layer, The second transistor includes: a second active layer comprising a first source / drain region electrically connected to the first gate conductor layer, a second source / drain region electrically connected to a corresponding third conductive line in the third connection line layer, and a channel region between the first source / drain region and the second source / drain region, wherein adjacent portions of the first active layer and the second active layer are substantially aligned in a vertical direction; a second gate dielectric layer on the second active layer; and a second gate conductor layer on the second gate dielectric layer; A fourth connection line layer, above the memory cells, includes a plurality of fourth conductive lines extending along the second direction, wherein the second gate conductor layer of each memory cell is electrically connected to a corresponding fourth conductive line in the fourth connection line layer.

2. The memory device according to claim 1, wherein The outer sidewall of the first active layer and an adjacent portion of the outer sidewall of the second active layer are substantially coplanar in a vertical direction.

3. The memory device according to claim 1 or 2, wherein: The first active layer has a bottom and a vertical extension extending vertically upward from the bottom, wherein the bottom is in physical contact with the corresponding first conductive line in the first connection line layer, and the vertical extension is in physical contact with the corresponding second conductive line in the second connection line layer.

4. The memory device according to claim 3, wherein: The first gate dielectric layer extends along the inner wall of the first active layer, and the first gate conductor layer fills the inner space of the first gate dielectric layer.

5. The memory device according to claim 3, wherein: The second active layer has a bottom and a vertical extension portion extending vertically upward from the bottom, wherein the bottom is electrically connected to the first gate conductor layer, and the vertical extension portion is in physical contact with a corresponding third conductive line in the third connection line layer. The memory device according to claim 5 , wherein: A bottom of the second active layer is in physical contact with the first gate conductor layer.

7. The memory device according to claim 5, wherein: The storage unit further includes: A connecting portion is provided between the first transistor and the second transistor, wherein a bottom portion of the second active layer is electrically connected to the first gate conductor layer through the connecting portion.

8. The memory device according to claim 5, wherein The second gate dielectric layer extends along the inner wall of the second active layer, and the second gate conductor layer fills the inner space of the second gate dielectric layer.

9. The memory device according to claim 5, wherein: The vertically extending portion of the first active layer is substantially aligned with the vertically extending portion of the second active layer in a vertical direction.

10. The memory device according to claim 5, further comprising: A gate length control layer is provided between the second connection line layer and the third connection line layer, wherein the gate length control layer includes a gate length control pad arranged around the storage unit, and the lowest point of the bottom surface of the second gate conductor layer is lower than the top surface of the gate length control pad.

11. The memory device according to claim 7, further comprising: a gate length control layer between the second connecting line layer and the third connecting line layer, wherein the gate length control layer includes a gate length control pad arranged around the storage unit, the bottom surface of the second gate conductor layer is at a vertical height between the top surface and the bottom surface of the gate length control pad, and the top surface of the connecting portion is not lower than the bottom surface of the gate length control pad.

12. The memory device according to claim 5, wherein The storage unit further includes: An isolation portion in the form of a sidewall is located between the first active layer and the second active layer.

13. The memory device according to claim 12, wherein: The vertical extension portion of the first active layer, the vertical extension portion of the second active layer, and the outer sidewall of the isolation portion are substantially coplanar in a vertical direction.

14. The memory device according to claim 1 or 2, wherein: At least one of the first active layer and the second active layer includes indium gallium zinc oxide.

15. The memory device according to claim 1 or 2, wherein: The first active layer includes a semiconductor material having relatively high mobility compared to silicon, and the second active layer includes a semiconductor material having relatively low leakage or a relatively large bandgap compared to silicon.

16. The memory device according to claim 1 or 2, wherein: The first active layer and the second active layer are self-aligned in a vertical direction.

17. The memory device according to claim 16, wherein: The storage unit further includes: An isolation portion in the form of a sidewall is located between the first active layer and the second active layer, The first active layer, the second active layer and the isolation portion are self-aligned in a vertical direction.

18. The memory device according to claim 1 or 2, wherein: The memory device is a dynamic random access memory device, the first conductive line corresponds to one of a read word line and a read bit line, the second conductive line corresponds to the other of the read word line and the read bit line, the third conductive line corresponds to a write bit line, and the fourth conductive line corresponds to a write word line.

19. A method of manufacturing a memory device, comprising: forming a first isolation layer on the substrate; forming a first connection line layer on the first isolation layer, and patterning the first connection line layer into a plurality of first conductive lines extending parallel to each other along a first direction; forming a second isolation layer on the first isolation layer and the first connection line layer; forming a second connection line layer on the second isolation layer, and patterning the second connection line layer into a plurality of second conductive lines extending parallel to each other along a second direction intersecting the first direction; forming a third isolation layer on the second isolation layer and the second connection line layer; forming a third connection line layer on the third isolation layer, and patterning the third connection line layer into a plurality of third conductive lines extending parallel to each other along the first direction; forming a fourth isolation layer on the third isolation layer and the third connection line layer; forming a plurality of openings, each opening passing through the fourth isolation layer, a corresponding third conductive line in the third connection line layer, the third isolation layer, a corresponding second conductive line in the second connection line layer, the second isolation layer, and entering a corresponding first conductive line in the first connection line layer; A first transistor and a second transistor are formed in each of the openings to overlap each other in a vertical direction to form a memory cell, wherein: The first transistor includes: a first active layer comprising a first source / drain region electrically connected to a corresponding first conductive line in the first connection line layer, a second source / drain region electrically connected to a corresponding second conductive line in the second connection line layer, and a channel region between the first source / drain region and the second source / drain region; a first gate dielectric layer on the first active layer; and a first gate conductor layer on the first gate dielectric layer, The second transistor includes: a second active layer comprising a first source / drain region electrically connected to the first gate conductor layer, a second source / drain region electrically connected to a corresponding third conductive line in the third connection line layer, and a channel region between the first source / drain region and the second source / drain region, wherein adjacent portions of the first active layer and the second active layer are substantially aligned in a vertical direction; a second gate dielectric layer on the second active layer; and a second gate conductor layer on the second gate dielectric layer; A fourth connection line layer is formed on the fourth isolation layer, wherein the fourth connection line layer includes a plurality of fourth conductive lines extending along the second direction, wherein the second gate conductor layer of each memory cell is electrically connected to a corresponding fourth conductive line in the fourth connection line layer.

20. The method according to claim 19, wherein Forming a first transistor includes: forming a first active layer in the opening in a conformal manner; forming a first gate dielectric layer on the first active layer in a conformal manner; filling a first gate conductor layer in the opening where the first active layer and the first gate dielectric layer are formed; Etching back the first gate conductor layer so that a top surface thereof is vertically located near a top surface of the second connection line layer; The first gate dielectric layer and the first active layer are selectively etched using the etched-back first gate conductor layer as a mask.

21. The method according to claim 20, wherein Forming the second transistor includes: forming a second active layer on the first transistor in the opening in a conformal manner; forming a second gate dielectric layer on the second active layer in a conformal manner; filling a second gate conductor layer in the opening where the second active layer and the second gate dielectric layer are formed; A planarization process is performed to leave the second active layer, the second gate dielectric layer and the second active layer in the opening.

22. The method according to claim 20, further comprising: An isolation portion in the form of a sidewall is formed on a sidewall of the opening, and the isolation portion shields a top end of the first active layer.

23. The method of claim 21, further comprising: A connecting portion is formed on the first transistor in the opening, wherein the connecting portion is in physical contact with the first gate conductor layer.

24. The method according to claim 21 or 23, further comprising: A gate length control layer is formed in the third isolation layer. The gate length control layer includes a gate length control pad disposed around the opening. The lowest point of the bottom surface of the second gate conductor layer is lower than the top surface of the gate length control pad.

25. The method according to claim 19, wherein At least one of the following is true: (a) forming the second isolation layer includes depositing a dielectric material on the first isolation layer and the first connection line layer, wherein the deposition thickness of the dielectric material is greater than half of the interval between the first conductive lines in the first connection line layer, and no planarization process is required for the deposited dielectric material; (b) forming the third isolation layer includes depositing a dielectric material on the second isolation layer and the second connection line layer, wherein the deposition thickness of the dielectric material is greater than half of the interval between the second conductive lines in the second connection line layer, and no planarization process is required for the deposited dielectric material; (c) forming the fourth isolation layer includes depositing a dielectric material on the third isolation layer and the third connection line layer, wherein the deposition thickness of the dielectric material is greater than half of the interval between the third conductive lines in the third connection line layer, and the deposited dielectric material does not need to be planarized.

26. An electronic device comprising the memory device according to any one of claims 1 to 18.

27. The electronic device according to claim 26, wherein The electronic device includes a smart phone, a personal computer, an artificial intelligence device, a wearable device or a mobile power supply.

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