Display panel, manufacturing method thereof, and display device

Abstract

This application discloses a display panel, a method for manufacturing the same, and a display device, including a thin-film transistor disposed on a substrate. The thin-film transistor includes a gate electrode, a gate insulating layer, and an active layer sequentially disposed on the substrate. The active layer is provided with a first source-drain electrode, a second source-drain electrode, and a drain-source electrode on a side away from the substrate. The first source-drain electrode and the second source-drain electrode are the same source or drain electrode, and the drain-source electrode is the other of the source or drain electrode. This application optimizes the channel design by symmetrically arranging the first and second source-drain electrodes relative to the drain-source electrode, thereby reducing the resistance and capacitance on the source-drain gate electrode, increasing the pixel charge saturation rate, and improving the display effect and reducing the power consumption of the product by symmetrically arranging the signal uniformity across the entire surface.

Description

Technical Field

[0001] The present application generally relates to the field of display technology, and specifically relates to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] With the development of information technology, electronic devices are widely used in people's daily lives. Liquid crystal displays, as one of the most widely used flat panel displays, occupy an important position in display panels.

[0003] Currently, people are very interested in ultra-high refresh rate gaming products (gaming display products). For example, there are already QHD (Quarter High Definition, a type of screen resolution) 240Hz and FHD (Full High Definition, a type of screen resolution) 360Hz gaming products on the market. However, most current gaming products use oxide technology, and a-Si products have low electron mobility (less than 1cm 2 / vs) and high refresh rate products have short pixel charging time and it is difficult to achieve excellent image quality. Even if the product can display normally, power consumption is also a major pain point. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a display panel and its preparation method, and a display device, which can reduce the resistance and capacitance loads on the gate and drain-source metal wiring of the pixel, effectively improve the charging saturation rate of the pixel, and reduce the power consumption of the product.

[0005] In a first aspect, the present application provides a display panel, comprising:

[0006] substrate;

[0007] a thin film transistor disposed on the substrate, the thin film transistor comprising a gate, a gate insulating layer, and an active layer sequentially disposed on the substrate; the active layer being provided with a first source-drain electrode, a second source-drain electrode, and a drain-source electrode on a side away from the substrate; the first source-drain electrode and the second source-drain electrode being the same as either the source or the drain, and the drain-source being the other of the source or the drain;

[0008] The orthographic projection of the drain and source electrodes on the base substrate does not overlap with the orthographic projection of the first source and drain electrodes on the base substrate and the orthographic projection of the second source and drain electrodes on the base substrate;

[0009] A pixel electrode is connected to the first source and drain through a first via hole and to the second source and drain through a second via hole.

[0010] Optionally, the pixel electrodes are arranged in an array on the base substrate to define a plurality of sub-pixel regions, the thin film transistor is located on one side of the sub-pixel region, and the middle position of the thin film transistor is close to the center line of the sub-pixel region.

[0011] Optionally, the first source and drain electrode and the second source and drain electrode are respectively located on both sides of a midline of the sub-pixel region, and the source and drain electrode are located on a midline of the sub-pixel region.

[0012] Optionally, the thin film transistor further includes a planar layer located above the first source / drain electrode, the second source / drain electrode, and the source / drain electrode, and the first via hole and the second via hole are provided on the planar layer.

[0013] Optionally, a common electrode is further included on the planar layer, and an insulating layer is provided between the common electrode and the pixel electrode.

[0014] Optionally, a common electrode wiring electrically connected to the common electrode is further included, the common electrode wiring is located at an edge of the sub-pixel area, and the common electrode is provided in the same layer as the first source and drain and the second source and drain.

[0015] Optionally, along the center line direction of the sub-pixel area, the drain and source electrodes corresponding to two adjacent sub-pixel areas are connected by a drain-source wiring, and the orthographic projection of the drain-source wiring on the substrate is located within the orthographic projection range of the sub-pixel area on the substrate.

[0016] Optionally, the pixel electrode includes a plurality of strip electrodes arranged in an array, the drain-source electrode wiring has the same shape as the strip electrodes, and the drain-source electrode wiring is located at an interval between two adjacent strip electrodes.

[0017] In a second aspect, the present application provides a method for manufacturing a display panel, for forming any of the above display panels, the method comprising:

[0018] providing a substrate;

[0019] forming a gate, a gate insulating layer, and an active layer in sequence on the base substrate;

[0020] forming a source-drain metal layer on the active layer, and patterning the source-drain metal layer to form a first source-drain electrode, a second source-drain electrode, and a drain-source electrode, wherein the orthographic projection of the drain-source electrode on the base substrate does not overlap with the orthographic projection of the first source-drain electrode on the base substrate and the orthographic projection of the second source-drain electrode on the base substrate;

[0021] forming a planar layer on the source / drain metal layer and patterning the planar layer to form a first via hole and a second via hole;

[0022] A pixel electrode is formed on the planar layer, and the pixel electrode is connected to the first source and drain electrode through a first via hole and is connected to the second source and drain electrode through a second via hole.

[0023] In a third aspect, the present application provides a display device comprising any display panel as described above.

[0024] The technical solutions provided by the embodiments of the present application may have the following beneficial effects:

[0025] The display panel provided in the embodiment of the present application optimizes the channel design by symmetrically arranging the first source-drain and the second source-drain about the drain-source, thereby reducing the resistance and capacitance on the source-drain gate, improving the pixel charging saturation rate, and improving the display effect and reducing the power consumption of the product by symmetrically arranging the uniformity of the signal across the entire surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0027] Figure 1 A schematic diagram of a pixel charging saturation rate provided in an embodiment of the present application;

[0028] Figure 2 A schematic structural diagram of a display panel provided in an embodiment of the present application;

[0029] Figure 3 A schematic structural diagram of a thin film transistor provided in an embodiment of the present application;

[0030] Figure 4 for Figure 3 Schematic diagram of the cross section at DD in the middle;

[0031] Figure 5 is a schematic structural diagram of a display panel in the prior art;

[0032] Figure 6 is a schematic structural diagram of a thin film transistor in the prior art;

[0033] Figure 7 A table showing comparison results between the display panels of the embodiment of the present application and those of the prior art;

[0034] Figure 8 A flow chart of a method for manufacturing a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. It should also be noted that, for ease of description, only portions relevant to the invention are shown in the accompanying drawings.

[0036] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0037] Whether the existing display panel meets the image quality requirements is generally evaluated by the pixel charge saturation rate AR, AR = actual pixel voltage / pixel design voltage (i.e. Data voltage). The relevant principles and processes can be found in the following. Figure 1 Generally, based on experience, when AR is greater than or equal to 98.5%, it can be considered that the product can display normally without abnormalities such as horizontal stripes. t1 is the Data voltage rise time, which is mainly determined by the thrust of the Source IC (data driver chip) and the resistance R and capacitance C on the Data line; t2 is the pixel voltage write time. During this period, the pixel write voltage speed is mainly limited by the W / L (width-to-length ratio) of the TFT (Thin Film Transistor). The larger the W / L of the TFT, the faster the charging rate and the higher the AR. In fact, the pixel also starts to write voltage at t1, but the write voltage is mainly limited by the rise speed of the Source voltage itself; t3 is the GOE (Gate Output Enable, that is, the delay time of the Data signal relative to the Gate signal) time. To ensure that the pixel writes the correct voltage, the Gate voltage must be turned off before the Data voltage. In theory, the GOE time should be greater than the Gate voltage fall time. The GOE time is mainly determined by the TFT size of the GOA (Gate Driver On Array, integrated gate driver) and the resistance R and capacitance C on the Gate line; t4 is the 1H time, 1H = 1 / refresh rate / vertical resolution.

[0038] High refresh rate products have a very short 1H time, making it difficult to achieve pixel charge saturation rates using a-Si processes. Consequently, most products use oxide processes with higher electron mobility, leading to increased product costs. Research has shown that to increase the pixel charge saturation rate (AR), it is necessary to reduce t1 and t3, increase t2 and the W / L ratio of the TFT. The larger the W / L ratio of the TFT, the larger the resistance R and capacitance C on the Gate and Data lines. Therefore, reducing the resistance R and capacitance C on the Gate and Data lines while maintaining the same TFT W / L ratio is a key issue. The smaller the resistance R and capacitance C, the lower the product's power consumption.

[0039] Please see Figure 2-4 , the present application provides a display panel, comprising:

[0040] Base substrate 10;

[0041] A thin film transistor 20 is provided on the base substrate 10, and the thin film transistor 20 includes a gate 21, a gate insulating layer, and an active layer 23 provided in sequence on the base substrate 10; the active layer 23 is provided with a first source-drain electrode 24, a second drain electrode 25, and a drain-source electrode 26 on a side away from the base substrate 10; the first source-drain electrode 24 and the second source-drain electrode 25 are the same type of source electrode or drain electrode, and the drain-source electrode 26 is the other type of source electrode or drain electrode;

[0042] The orthographic projection of the drain and source electrodes 26 on the base substrate 10 does not overlap with the orthographic projection of the first source and drain electrodes 24 on the base substrate 10 and the orthographic projection of the second source and drain electrodes 25 on the base substrate 10;

[0043] The pixel electrode 30 is connected to the first source-drain electrode 24 through a first via hole 50 and is connected to the second source-drain electrode 25 through a second via hole 60 .

[0044] It should be noted that the present application does not limit the type of thin-film transistor 20; different configurations can be used depending on the device or application scenario. Low-temperature polysilicon (LTPS) thin-film transistor 20 uses polysilicon deposition to form the active layer 23. LTPS has high electron mobility, fast response speed, high brightness, high resolution, and low power consumption.

[0045] The oxide thin-film transistor 20 (oxide TFT) uses, for example, an oxide semiconductor as its active layer 23, such as indium gallium zinc oxide (IGZO). Oxide semiconductors have high electron mobility and good off-state characteristics. Compared to LTPS, oxide semiconductors have a simpler manufacturing process and are more compatible with amorphous silicon processes. Of course, the oxide thin-film transistor 20 can also be other metal oxide semiconductors, such as indium zinc tin oxide (IZTO) or indium gallium zinc tin oxide (IGZTO).

[0046] It can be understood that the source and drain of the thin film transistor 20 can be interchanged when used. Therefore, in the embodiment of the present application, the first source-drain electrode 24 and the second source-drain electrode 25 can be the source electrode, and the drain-source electrode 26 can be the drain electrode; or, the first source-drain electrode 24 and the second source-drain electrode 25 can be the drain electrode, and the drain-source electrode 26 can be the source electrode.

[0047] In the embodiment of the present application, the first source-drain electrode 24 and the second source-drain electrode 25 can be source electrodes, and the drain-source electrode 26 can be drain electrodes for exemplary description. The corresponding thin-film transistor 20 is connected in such a manner that the gate 21 is connected to the scan line, the first source-drain electrode 24 (source electrode) and the second source-drain electrode 25 (source electrode) are respectively connected to the pixel electrode 30, and the drain-source electrode 26 (drain electrode) is connected to the data line. The thin-film transistor 20 is configured to charge and discharge the data line at the drain electrode to the pixel at the source electrode through the semiconductor channel under the control of the gate 21.

[0048] In the embodiment of the present application, the pixel electrodes 30 are arranged in an array along a first direction X and a second direction Y on the base substrate 10 , and the pixel electrodes 30 define and form a plurality of sub-pixel regions.

[0049] It should be noted that in the embodiments of the present application, the first direction X and the second direction Y may be perpendicular to each other or nearly perpendicular to each other, and the present application does not limit the specific directions of the first direction X and the second direction Y. In the present application, the arrangement direction of pixel columns is exemplarily taken as the first direction X, and the arrangement direction of pixel rows is taken as the second direction Y. Of course, in other embodiments, the first direction X and the second direction Y may be interchangeable, such that the first direction X may be the arrangement direction of pixel rows, and the second direction Y may be the arrangement direction of pixel columns.

[0050] The shape of the pixel electrode 30 is not limited in the embodiments of the present application. In different embodiments, the pixel electrode 30 can be a planar electrode or a strip electrode 33, and the shape of the strip electrode 33 can be an inclined strip, a zigzag shape, an X shape, a Y shape, etc. The shape of the pixel electrode 30 can be selected as needed depending on the device and application scenario. In the embodiments of the present application, the shape and position of the pixel electrode 30 are defined as the shape and position of the sub-pixel area.

[0051] In the embodiments of the present application, a multi-domain sub-pixel region is used as an example for illustrative description. For example, the sub-pixel region includes a first domain 31 and a second domain 32 arranged along a first direction X. Therefore, the first domain 31 and the second domain 32 are symmetrically arranged about a center line arranged along a second direction Y. The first domain 31 includes a first center line that forms an area bisector, and the direction in which the first center line extends is the same as the shape of the strip electrodes 33 in the first domain 31 along the first direction X. The second domain 32 includes a second center line that forms an area bisector, and the direction in which the first center line extends is the same as the shape of the strip electrodes 33 in the first domain 31 along the first direction X. The first center line and the second center line together form the center line of the sub-pixel region described in this application.

[0052] In the embodiment of the present application, the thin film transistor 20 is located on one side of the sub-pixel region, and the middle position of the thin film transistor 20 is close to the midline of the sub-pixel region. In the embodiment of the present application, the overall position direction of the thin film transistor 20 is extended along the first direction X and the second direction Y. Since the midline of the sub-pixel region in this embodiment is a broken line formed by the first midline and the second midline, the straight line in the first direction X where the midline is close to the end point of the thin film transistor 20 can be used as the axis of the thin film transistor 20.

[0053] It should be understood that the absolute positional relationship between the thin-film transistor 20 and the sub-pixel region is not limited in the embodiments of the present application and can be appropriately adjusted based on the positional relationship of various components on the array substrate. The thin-film transistor 20 can be positioned as close as possible to the centerline of the sub-pixel region. By ensuring maximum symmetry, the parasitic capacitance generated between the various conductive structures can be more uniform across the sub-pixel region, thereby improving the uniformity of the display panel.

[0054] In the embodiment of the present application, the thin film transistor 20 further includes a planar layer 27 located above the first source / drain electrode 24 , the second source / drain electrode 25 and the drain / source electrode 26 . The first via hole 50 and the second via hole 60 are provided on the planar layer 27 .

[0055] The first source / drain electrode 24 and the second source / drain electrode 25 include a main source / drain portion located on the upper layer of the active layer 23 and a transverse extension extending from one side of the main source / drain portion along the second direction Y toward the edge of the thin film transistor 20. The transverse extension conformally covers the upper surface of the gate insulating layer. The transverse extension is configured to electrically connect to the first via hole 50 or the second via hole 60 formed in the pixel electrode 30.

[0056] In a preferred embodiment of the present application, the first source-drain electrode 24 and the second source-drain electrode 25 are respectively located on both sides of the midline of the sub-pixel region, and the drain-source electrode 26 is located on the midline of the sub-pixel region.

[0057] In this embodiment, the centerline of the drain and source electrodes 26 corresponds to the centerline of the region where the thin-film transistor 20 is located. That is, the drain and source electrodes 26 are arranged on the centerline of the region where the thin-film transistor 20 is located, and the first source and drain electrodes 24 and the second source and drain electrodes 25 are arranged symmetrically about the centerline. In this application, the gate electrode 21 of the thin-film transistor 20 is also symmetrical about the centerline of the region where the thin-film transistor 20 is located. It is understood that the positional relationship in this application may allow for certain process errors due to manufacturing factors.

[0058] In this embodiment, the source-drain main body portion of the first source-drain electrode 24 and the source-drain main body portion of the second source-drain electrode 25 are symmetrical about the centerline of the drain-source electrode 26. The lateral extension portion of the first source-drain electrode 24 and the lateral extension portion of the second source-drain electrode 25 are symmetrical about the centerline of the drain-source electrode 26. The first via 50 and the second via 60 are symmetrical about the centerline of the drain-source electrode 26. In this embodiment, the first via 50 and the second via 60 are respectively located near the edges of the pixel electrode 30 on both sides.

[0059] In the thin film transistor 20, the drain is used to connect to the corresponding data line, the gate 21 is used to connect to the corresponding gate line 80, and the source is used to connect to the corresponding pixel electrode 30. Pixel units in the same row are connected to the same gate line through corresponding thin film transistors 20, while pixel units in different rows are connected to different gate lines. Pixel units in the same column are connected to the same data line through corresponding thin film transistors 20, while pixel units in different columns are connected to different data lines.

[0060] In the prior art, the data line extends along a first direction X, the gate line 80 extends along a second direction Y, and the data line and the gate line 80 intersect to define a sub-pixel area. In the present application, a symmetrically designed first source and drain electrode 24 and a second source and drain electrode 25 and a drain source electrode 26 located in the middle are adopted. In the direction along the center line of the sub-pixel area (that is, the first direction X in this embodiment), the drain and source electrodes 26 corresponding to two adjacent sub-pixel areas are connected by a drain-source electrode wiring 90, and the orthographic projection of the drain-source wiring 90 on the base substrate 10 is located within the orthographic projection range of the sub-pixel area on the base substrate 10.

[0061] The drain-source wiring 90 in the present application is located in a wiring segment within the sub-pixel region. The drain-source wiring 90 replaces the data line in the prior art. The drain-source wiring 90 is used to provide data voltage to the drain-source electrode 26 .

[0062] Specifically, the pixel electrode 30 includes a plurality of strip electrodes 33 arranged in an array. The drain-source electrode trace 90 has the same shape as the strip electrodes 33 and is located between two adjacent strip electrodes 33. In this embodiment, the drain-source electrode trace 90 is generally in the shape of a zigzag line, extending in the same direction as the pixel electrode 30. By maximizing symmetry, the parasitic capacitance generated between the various conductive structures can be made more uniform across the sub-pixel region, thereby improving the uniformity of the display panel.

[0063] It can be understood that in the embodiment of the present application, the first source and drain electrode 24, the second source and drain electrode 25, and the drain source and drain electrode 26 can be formed by the same metal layer. In the present application, the drain-source electrode wiring 90 is arranged on the same layer as the source and drain metal layer, and there is no need to set the drain-source electrode wiring 90 separately. The drain-source electrode wiring 90 can be formed by the same conductive layer and the same process as the source and drain metal layer. The manufacturing process is simple and the cost is low. Since there is no need to add an additional conductive layer to form the data line, the thickness of the array substrate is thin.

[0064] In an embodiment of the present application, the display panel further includes a common electrode 40 located on the upper layer of the flat layer 27, and an insulating layer 28 is provided between the common electrode 40 and the pixel electrode 30. The shape of the common electrode 40 is not limited in the embodiment of the present application. In different embodiments, the common electrode 40 may be a planar electrode or a strip electrode 33, etc. The shape of the strip electrode 33 may be an inclined bar, a sawtooth shape, an X shape, a Y shape, etc. The shape of the common electrode 40 may be selected as needed depending on the device and the application scenario. In addition, the coupling between the common electrode 40 and the pixel electrode 30 may also affect the VCOM signal. In the present application, the common electrode 40 and the pixel electrode 30 are isolated by an insulating layer 28.

[0065] In an embodiment of the present application, at the position corresponding to the thin film transistor 20, the orthographic projection of the common electrode 40 on the base substrate 10 does not overlap with the orthographic projection of the pixel electrode 30 on the base substrate 10, thereby preventing the occurrence of a short circuit. In this embodiment, the common electrode 40 is provided with an etching area at the position corresponding to the first via hole 50 and the second via hole 60, and the orthographic projections of the first via hole 50 and the second via hole 60 on the base substrate 10 are located within the orthographic projection range of the etching area on the base substrate 10.

[0066] In the embodiment of the present application, exemplarily, the pixel electrode 30 is arranged above the common electrode layer. It can be understood that the relative position relationship between the common electrode 40 and the pixel electrode 30 is described exemplarily in the embodiment of the present application. However, the specific positions of the common electrode layer and the pixel electrode layer are not limited in the present application. The IPS driving mode display panel in which the common electrode 40 and the pixel electrode 30 are arranged on the same layer can also be an IPS driving mode display panel, a TN driving mode display panel, a VA driving mode display panel, or an FFS driving mode display panel.

[0067] The common electrode 40 can usually be made of transparent conductive indium tin oxide (ITO) material, which makes the common electrode 40 itself have a relatively large resistance. Therefore, when a common voltage is applied to the common electrode 40 through the common electrode wiring 70, due to the large resistance of the common electrode 40, it will cause problems such as signal delay. In order to further reduce the RC delay of the common electrode 40 VCOM signal. In addition, the drain-source wiring 90 used as the data line in this application is set in the middle position of the sub-pixel area. By adding the common electrode wiring 70, the pulling effect of the drain-source wiring 90 signal on VCOM can be reduced, thereby avoiding flickering and greenish image quality problems.

[0068] Optionally, a common electrode wiring 70 electrically connected to the common electrode 40 is further included. The common electrode wiring 70 is located at the edge of the sub-pixel area. The common electrode 40 is provided in the same layer as the first source-drain 24 and the second source-drain 25 .

[0069] The common electrode routing 70 includes a first common routing segment 71 arranged between the sub-pixel areas and a second common routing segment 72 located between the thin film transistors 20 and the thin film transistors 20. The first common routing segment 71 has the same shape and routing trend as the strip electrode 33 of the pixel electrode 30. The first common routing segment 71 and the drain-source routing 90 are formed together on the source-drain metal layer; the extension direction of the second common routing segment 72 can be parallel to the first direction X.

[0070] The extension direction of the first common electrode trace 70 is the same as the extension direction of the strip electrode 33 in the pixel electrode 30. The same pixel row corresponds to one common electrode trace 70, and the common electrodes 40 of all the pixel units in the same pixel row are electrically connected to the same common electrode trace 70 to prevent the pixel load of the pixel unit from being too large. For any row of pixel units, the first common electrode trace 70 is located on the same side as the gate line electrically connected to the pixel unit. In the present application, the common electrode trace 70 provides a common signal VCOM to the common electrode 40. The common electrode trace 70 is connected to the common electrode 40 through a third via 73. The setting position of the third via 73 is not limited in the present application. In some embodiments, the third via 73 can be set at the intersection of the first common trace segment 71 and the second common trace segment 72.

[0071] It can be understood that in the embodiment of the present application, the first source-drain electrode 24, the second source-drain electrode 25, and the drain-source electrode 26 can be formed from the same metal layer. In this application, the common electrode trace 70 is provided on the same layer as the source-drain metal layer, eliminating the need for a separate layer of material to form the common electrode trace 70. The common electrode trace 70 can be formed from the same conductive layer and process as the source-drain metal layer, resulting in a simple manufacturing process and low cost. Moreover, since no additional conductive layer is required to form the common electrode trace 70, the thickness of the array substrate can be reduced. This design is applied to medium and large-sized products and greatly ensures the uniformity of the VCOM signal across the entire surface.

[0072] It can be understood that the hierarchical structure of the thin film transistor 20 provided in the present application does not constitute a limitation on the thin film transistor 20. Those skilled in the art can improve the hierarchical structure of the thin film transistor 20 provided in the present application, including more or fewer hierarchical structures mentioned above, or combining certain hierarchical structures, or arranging different hierarchical structures.

[0073] In the embodiment of the present application, since the thin film transistor 20 adopts the method of two sources and one drain (two drains and one source), the parasitic capacitance and RC load value of the thin film transistor 20 can be reduced while ensuring the channel width-to-length ratio.

[0074] It is particularly important to note that the semiconductor active layer 23 between the source and drain electrodes can form a conductive channel. The distance between the source and drain electrodes is called the channel length L, and the conductive direction perpendicular to L is the width W of the drain-source electrode 26. The channel width-to-length ratio of the thin film transistor 20, that is, the ratio of the channel width W to the channel length L of the thin film transistor 20, is an important factor in determining the output capability of the thin film transistor 20.

[0075] In this application, the channel length L and width W of the thin film transistor 20 are represented as follows: Figure 3As shown, since the present application adopts a symmetrical arrangement of two sources and one drain (two drains and one source), the channel length L in the figure is L = 2A, and W = B. Therefore, compared with the prior art, the overlapping area of ​​the gate 21 and the source and drain electrodes can be greatly reduced while ensuring the channel width-to-length ratio, which can effectively reduce the capacitance C and resistance R on the gate line 80 and the drain-source electrode line 90. When the resistance R and the capacitance C have the following advantages: the pixel charging saturation rate AR is improved, and the product image quality is effectively guaranteed; the product power consumption is highly correlated with the resistance R and the capacitance C. When the two are reduced, the product power consumption will be reduced accordingly, which can greatly improve the product life and thus enhance the product competitiveness.

[0076] In existing panel designs, common TFT shapes include I-type, L-type, and U-type. I-type TFTs have a smaller W / L ratio, resulting in lower resistance and capacitance; L-type TFTs have an intermediate W / L ratio, resulting in intermediate resistance and capacitance; and U-type TFTs have the largest W / L ratio, resulting in the largest resistance and capacitance. The capacitance on gate line 80 primarily includes the capacitance between the TFT gate 21 and the source, the capacitance between the TFT gate 21 and the drain, and the capacitance between the TFT gate 21 and the VCOM electrode. The capacitance on data lines primarily includes the capacitance between the TFT drain and gate 21, and the capacitance between the TFT drain and the VCOM electrode.

[0077] The following data is explained based on the basic conditions of 16.0 inches, 1920*1200 resolution, 165Hz refresh rate, and TFT W / L of 27 / 3.6um. Under the same conditions (such as line width and line spacing, film thickness, etc.), the U-shaped pixel structure (such as Figure 5-6 As shown) and the capacitance and resistance between the gate line 80 and the source signal line of the display panel provided by the embodiment of the present application, and data simulation is performed to obtain t1, t3 and AR data, see Figure 7 . Figure 6 In FIG, the U-shaped TFT pixel structure includes a common electrode 01', a pixel electrode 02', a gate electrode 03', a source electrode 04', and a drain electrode 05'. Figure 7It can be seen that under the same conditions, the gate 21R*C of the thin-film transistor 20 in this application decreased by 16.85% compared to the U-type, and the parameter t3, which is mainly determined by the gate 21R*C, decreased by about 0.3us; its drain R*C even decreased by 42.73% compared to the U-type, and the parameter t1, which is mainly determined by the drain R*C, decreased by about 0.59us. Therefore, thanks to the significant reduction in t1 and t3, the charging time t2 is increased. When the charging rate of the thin-film transistor 20 in this application reaches 98.5%, the pixel charging rate of the U-shaped structure is only 94.05%. Obviously, according to the rule that AR is greater than or equal to 98.5%, products using the thin-film transistor 20 of this application will not have display abnormalities and other problems, while products using the existing U-shaped pixel structure have a great risk of abnormal display.

[0078] like Figure 8 As shown, the present application provides a method for preparing a display panel, for forming any of the above-described display panels, the method comprising:

[0079] S01. Provide a base substrate 10. The base substrate 10 may be made of glass, quartz, organic polymer or other applicable materials.

[0080] S02 , forming a gate 21 , a gate insulating layer, and an active layer 23 in sequence on the base substrate 10 .

[0081] Specifically, the method includes:

[0082] S201. Form a gate metal layer on the base substrate 10 and pattern the gate 21; wherein the gate metal layer may include at least one metal selected from, for example, molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), tungsten (W) and copper (Cu).

[0083] S202 , forming a gate insulating layer on the gate metal layer. The material of the gate insulating layer may be silicon oxide (SiOx), silicon nitride (SiNx) or the like.

[0084] S203: Patterning a semiconductor material layer on the gate insulating layer to form an active layer 23; wherein the semiconductor material layer can be a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), or indium gallium zinc tin oxide (IGZTO). It can also be an amorphous silicon (a-Si) semiconductor layer, a polycrystalline silicon (p-Si) semiconductor layer, or an organic semiconductor layer.

[0085] S03. Form a source-drain metal layer on the active layer 23, and pattern the source-drain metal layer to form a first source-drain electrode 24, a second source-drain electrode 25, and a drain-source electrode 26, wherein the orthographic projection of the drain-source electrode 26 on the base substrate 10 does not overlap with the orthographic projection of the first source-drain electrode 24 on the base substrate 10 and the orthographic projection of the second source-drain electrode 25 on the base substrate 10.

[0086] In the embodiment of the present application, the patterned source-drain metal layer further includes a gate line 80 , a drain-source wiring 90 , and a common electrode wiring 70 formed on the same layer as the source-drain metal layer.

[0087] S04. A flat layer 27 is formed on the source / drain metal layer and patterned to form a first via 50 and a second via 60. The flat layer 27 may be made of an organic material or an inorganic material, such as a hybrid resin material such as polysiloxane or polysilazane called spin-on glass (SOG), or an inorganic material such as silicon nitride, silicon oxide, or aluminum oxide.

[0088] S05 , forming a pixel electrode 30 on the planar layer 27 , wherein the pixel electrode 30 is connected to the first source-drain electrode 24 through a first via hole 50 and is connected to the second source-drain electrode 25 through a second via hole 60 .

[0089] Specifically, the method includes:

[0090] S501. A common electrode layer is formed on the planar layer 27 and patterned to form a common electrode 40. The common electrode layer may be made of a transparent metal oxide conductive material or other suitable materials, such as (but not limited to): indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide or other suitable materials.

[0091] S502: Form an insulating layer 28 on the common electrode layer and pattern a first via 50 and a second via 60. In the embodiment of the present application, the first via 50 and the second via 60 are formed by patterning the planar layer, the common electrode layer, and the second via layer. The insulating layer 28 can be made of an organic material or an inorganic material, such as a hybrid resin material such as polysiloxane or polysilazane known as spin-on glass (SOG), or an inorganic material such as silicon nitride, silicon oxide, or aluminum oxide.

[0092] S503: Form a pixel electrode layer on the insulating layer 28 and pattern the pixel electrode 30. The pixel electrode layer may be made of a transparent metal oxide conductive material or other suitable materials, such as (but not limited to): indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or other suitable materials.

[0093] It should be noted that in the embodiments of this application, "same-layer arrangement" refers to two layers, components, members, elements, or parts being located on the same horizontal plane. In this embodiment, the bottom surfaces of the two layers are on the same horizontal plane. In the field of display technology, a patterning process may include only photolithography, or may include photolithography and etching steps, and may also include other processes such as printing and inkjet printing to form a predetermined pattern. Photolithography refers to a process that uses photoresist, a mask, an exposure machine, and other processes to form a pattern, including film formation, exposure, and development. The corresponding patterning process can be selected based on the structure formed in this invention.

[0094] Based on the same inventive concept, the present application provides a display device comprising any of the above-described display panels. The display device may be a television, or may be a display terminal device with a display function, such as a PC, a smartphone, a tablet computer, an e-book reader, an MP3 (Moving Picture Experts Group Audio Layer III) player, an MP4 (Moving Picture Experts Group Audio Layer IV) player, or a portable computer.

[0095] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0096] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0097] Unless otherwise defined, the technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present invention. The terms used herein are only for describing specific implementation purposes and are not intended to limit the present invention. Terms such as "setting" appearing in this article can mean that one component is directly attached to another component, or that one component is attached to another component through an intermediate component. Features described in this article in one embodiment can be applied to another embodiment alone or in combination with other features, unless the feature is not applicable in the other embodiment or otherwise specified.

[0098] The present invention has been described through the above embodiments, but it should be understood that the above embodiments are for illustrative and illustrative purposes only and are not intended to limit the present invention to the described embodiments. Those skilled in the art will appreciate that various variations and modifications may be made based on the teachings of the present invention, and such variations and modifications fall within the scope of protection claimed in the present invention.

Claims

1. A display panel, characterized in that: include: substrate; A thin film transistor is provided on the base substrate, wherein the thin film transistor includes a gate, a gate insulating layer, and an active layer which are sequentially provided on the base substrate; The active layer is provided with a first source-drain electrode, a second source-drain electrode, and a drain-source electrode on a side away from the base substrate; the first source-drain electrode and the second source-drain electrode are the same type of source or drain electrode, and the drain-source electrode is the other type of source or drain electrode; The orthographic projection of the drain and source electrodes on the base substrate does not overlap with the orthographic projection of the first source and drain electrodes on the base substrate and the orthographic projection of the second source and drain electrodes on the base substrate; A pixel electrode, wherein the pixel electrode is connected to the first source and drain through a first via hole and to the second source and drain through a second via hole; the drain and source are connected to a data line, the drain and source are arranged on the center line of the area where the thin film transistor is located, and the first source and drain and the second source and drain are symmetrically arranged about the center line.

2. The display panel according to claim 1, wherein: The pixel electrodes are arranged in an array on the base substrate to define a plurality of sub-pixel regions. The thin film transistor is located on one side of the sub-pixel region, and the middle position of the thin film transistor is close to the center line of the sub-pixel region.

3. The display panel according to claim 2, wherein: The first source and drain electrode and the second source and drain electrode are respectively located on both sides of the midline of the sub-pixel region, and the drain and source electrode are located on the midline of the sub-pixel region.

4. The display panel according to claim 2, wherein: The thin film transistor further includes a planar layer located above the first source / drain electrode, the second source / drain electrode, and the source / drain electrode, and the first via hole and the second via hole are provided on the planar layer.

5. The display panel according to claim 4, wherein: It also includes a common electrode located on the upper layer of the planar layer, and an insulating layer is provided between the common electrode and the pixel electrode.

6. The display panel according to claim 5, wherein: It also includes a common electrode wiring electrically connected to the common electrode, the common electrode wiring is located at the edge of the sub-pixel area, and the common electrode is arranged in the same layer as the first source and drain and the second source and drain.

7. The display panel according to claim 2, wherein: In the midline direction of the sub-pixel area, the drain and source electrodes corresponding to two adjacent sub-pixel areas are connected by a drain-source wiring, and the orthographic projection of the drain-source wiring on the substrate is located within the orthographic projection range of the sub-pixel area on the substrate.

8. The display panel according to claim 7, wherein: The pixel electrode includes a plurality of strip electrodes arranged in an array. The drain-source electrode wiring has the same shape as the strip electrodes, and the drain-source electrode wiring is located at an interval between two adjacent strip electrodes.

9. A method for preparing a display panel, characterized in that: For forming the display panel according to any one of claims 1 to 8, the method comprises: providing a substrate; forming a gate, a gate insulating layer, and an active layer in sequence on the base substrate; forming a source-drain metal layer on the active layer, and patterning the source-drain metal layer to form a first source-drain electrode, a second source-drain electrode, and a drain-source electrode, wherein the orthographic projection of the drain-source electrode on the base substrate does not overlap with the orthographic projection of the first source-drain electrode on the base substrate and the orthographic projection of the second source-drain electrode on the base substrate; forming a planar layer on the source / drain metal layer and patterning the planar layer to form a first via hole and a second via hole; A pixel electrode is formed on the planar layer, and the pixel electrode is connected to the first source and drain electrode through a first via hole and is connected to the second source and drain electrode through a second via hole.

10. A display device, characterized in that: The display panel comprises the display panel as described in any one of claims 1 to 8.

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