A display panel

Abstract

The present application relates to a kind of display panel.The display panel of the present application includes a plurality of arrayed display blocks, each display block has a driving layer, the driving layer has a plurality of arrayed conductive regions, by arranging pixel units on the conductive regions of display block, the first pixel pitch of adjacent two pixel units arranged along the first direction is adjusted to L1 and the second pixel pitch of adjacent two pixel units arranged along the second direction is adjusted to L2, in turn, so that the display panel can be suitable for different use scenarios, meet the demand of user for the use of display panel in multiple scenarios.The present application is packaged to form independent display block, and then a plurality of display blocks are arrayed to form a display panel, which is beneficial to realize the integration and miniaturization of the package of display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] As flat-panel display technology matures, numerous display companies are investing in the development of next-generation displays. Light-emitting diodes (LEDs), with their advantages of high reliability, compact size, and high brightness, have become a research hotspot in the display industry. Within the display industry, fine-pitch RGB LED direct displays are experiencing a growing market share, as they offer an excellent viewing experience. Active-mode (AM) LEDs, suitable for applications with high resolution (PPI), high brightness, and high transmittance, are also becoming a research hotspot in the industry.

[0003] Currently, there are two main ways to achieve AM drive: one is to use a silicon-based microchip (Si-μIC) to drive a single-pixel R / G / B LED, that is, the microchip and RGB LED are bonded to a passive driver (PM) wiring substrate by bonding to achieve an electrical connection between the LED and the driver circuit; the other is to bond the R / G / B LED to an active driver (AM) substrate to achieve an electrical connection between the LED and the driver circuit.

[0004] Regarding the microchip active drive solution, microchips have great application prospects in the fields of RGBLED direct display and backlight because they can simplify the peripheral drive circuit and realize PWM drive. The current mainstream solution uses silicon-based complementary metal oxide semiconductor (CMOS) to drive microchips. Due to the limited size of the wafer, the number of microchips cut out is limited. The resolution of the display screen is getting higher and higher. Since each pixel requires a microchip, the cost of the microchip is also greatly increased. In addition, the existing light-driven integrated package usually bonds the microchip and RGB LED to a package carrier before packaging, which is not conducive to the integration and miniaturization of the package. Under the premise of the same resolution, the pixel pitch of the large-size display panel is larger than that of the small-size display panel. The current display panel cannot adjust the pixel pitch to meet the needs of using the display panel in multiple scenarios. Summary of the Invention

[0005] The purpose of the present invention is to provide a display panel and a display device, which can solve the problems existing in the prior art, such as the inability to integrate and miniaturize the integrated lamp and driver package and the inability to meet users' needs for multi-scenario use of the display panel.

[0006] In order to solve the above problems, the present invention provides a display panel, which includes a plurality of display blocks arranged in an array; each of the display blocks includes: a driving layer, which has a plurality of conductive areas arranged in an array, each of the conductive areas is provided with a conductive block group; and at least one pixel unit, arranged in the conductive area of ​​the driving layer and electrically connected to the conductive block group; each of the conductive areas is provided with at most one pixel unit, and the projection of each pixel unit on the driving layer falls within the projection of its corresponding conductive area on the driving layer; the length of the first side of each conductive area parallel to the first direction is P1, and the length of the second side of each conductive area parallel to the second direction is P2; the first pixel spacing between two adjacent pixel units arranged along the first direction is L1, L1=j*P1, j≥1; the second pixel spacing between two adjacent pixel units arranged along the second direction is L2, L2=k*P2, k≥1.

[0007] Furthermore, each of the conductive areas is provided with one pixel unit, L1 = P1, L2 = P2.

[0008] Furthermore, there is one conductive block group between two adjacent pixel units arranged along the first direction in the same display block, and L1 = 2P1.

[0009] Furthermore, there is one conductive block group between two adjacent pixel units arranged along the second direction in the same display block, L2=2P2.

[0010] Furthermore, there are two conductive block groups between two adjacent pixel units arranged along the first direction in the same display block, and L1 = 3P1.

[0011] Furthermore, there are two conductive block groups between two adjacent pixel units arranged along the second direction in the same display block, L2=3P2.

[0012] Furthermore, each of the display blocks includes one pixel unit, and there are three conductive block groups between two adjacent pixel units arranged along the first direction, where L1 = 4P1.

[0013] Furthermore, there are three conductive block groups between two adjacent pixel units arranged along the second direction, L2=4P2.

[0014] Furthermore, each of the display blocks further includes a first signal connection block and a second signal connection block which are arranged on a side of the driving layer away from the pixel unit.

[0015] Furthermore, the signal transmitted by the first signal connection block includes a scan control signal, and the signal transmitted by the second signal connection block includes a common signal.

[0016] The advantages of the present invention are as follows: the display panel of the present invention includes a plurality of display blocks arranged in an array, each display block comprises a drive layer, and the drive layer has a plurality of conductive areas arranged in an array. By arranging pixel units on the conductive areas of the display blocks, the first pixel pitch between two adjacent pixel units arranged along the first direction is adjusted to L1, and the second pixel pitch between two adjacent pixel units arranged along the second direction is adjusted to L2, thereby making the display panel suitable for different usage scenarios and meeting user needs for multi-scenario use of the display panel. The present invention encapsulates independent display blocks and then arranges multiple display blocks in an array to form a display panel, which facilitates the integration and miniaturization of the display panel package. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a schematic plan view of a display panel according to embodiment 1 of the present invention;

[0019] Figure 2 is a schematic plan view of a display block of a display panel according to embodiment 1 of the present invention;

[0020] Figure 3 yes Figure 2 AA cross-section of

[0021] Figure 4 is a schematic diagram of a first signal connection block and a second first signal connection block of a display block of a display panel according to embodiment 1 of the present invention;

[0022] Figure 5 is a schematic plan view of a display panel according to Example 2 of the present invention;

[0023] Figure 6 is a schematic plan view of a display block of a display panel according to embodiment 2 of the present invention;

[0024] Figure 7 yes Figure 6 BB cross-section diagram;

[0025] Figure 8 is a schematic diagram of a first signal connection block and a second first signal connection block of a display block of a display panel according to embodiment 2 of the present invention;

[0026] Figure 9 is a schematic plan view of a display panel according to Example 3 of the present invention;

[0027] Figure 10 is a schematic plan view of a display block of a display panel according to embodiment 3 of the present invention;

[0028] Figure 11 yes Figure 10 CC cross-section diagram;

[0029] Figure 12 is a schematic diagram of a first signal connection block and a second first signal connection block of a display block of a display panel according to embodiment 3 of the present invention;

[0030] Figure 13 is a schematic plan view of a display panel according to embodiment 4 of the present invention;

[0031] Figure 14 is a schematic plan view of a display block of a display panel according to a fourth embodiment of the present invention;

[0032] Figure 15 yes Figure 14 DD cross-section diagram;

[0033] Figure 16 4 is a schematic diagram of a first signal connection block and a second first signal connection block of a display block of a display panel according to a fourth embodiment of the present invention.

[0034] Description of reference numerals:

[0035] 100. Display panel; 101. Display block;

[0036] 1. Driving layer; 2. Pixel unit;

[0037] 3. First signal connection block; 4. Second signal connection block;

[0038] 11. conductive area; 111. conductive block group;

[0039] 1111, a first conductive block pair; 1112, a second conductive block pair;

[0040] 1113, third conductive block pair;

[0041] 21. Red LED; 22. Green LED;

[0042] 23. Blue LED. DETAILED DESCRIPTION

[0043] The following describes in detail preferred embodiments of the present invention in conjunction with the accompanying drawings to fully introduce the technical content of the present invention to those skilled in the art, to illustrate that the present invention can be implemented, to make the technical content disclosed in the present invention clearer, and to make it easier for those skilled in the art to understand how to implement the present invention. However, the present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments described herein. The description of the embodiments below is not intended to limit the scope of the present invention.

[0044] The directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only directions in the drawings. The directional terms used in this article are used to explain and illustrate the present invention, and are not used to limit the scope of protection of the present invention.

[0045] In the accompanying drawings, components with the same structure are represented by the same numerical labels, and components with similar structures or functions are represented by similar numerical labels. In addition, for ease of understanding and description, the size and thickness of each component shown in the accompanying drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component.

[0046] Example 1

[0047] like Figure 1 As shown, this embodiment provides a display panel 100. The display panel 100 includes a plurality of display blocks 101 arranged in an array. In this embodiment, the display panel 100 includes 8 display blocks 101 arranged in 2 rows and 4 columns. In other embodiments, the display panel 100 may also include 12 display blocks 101 arranged in 3 rows and 4 columns, or 15 display blocks 101 arranged in 5 rows and 3 columns, which are not limited in this embodiment.

[0048] In this embodiment, independent display blocks 101 are packaged and then a plurality of display blocks 101 are arranged in an array to form a display panel 100 , which is conducive to achieving integration and miniaturization of the package of the display panel 100 .

[0049] like Figure 2 and Figure 3 As shown, each of the display blocks 101 includes: a driving layer 1 , at least one pixel unit 2 , a first signal connection block 3 and a second signal connection block 4 .

[0050] like Figure 2 As shown, the driving layer 1 has a plurality of conductive areas 11 arranged in an array. Specifically, each display block 101 includes the conductive areas 11 arranged in m rows and n columns, where m ≥ 1 and n ≥ 1. In this embodiment, m = n = 4, i.e., each display block 101 includes 16 conductive areas 11 arranged in 4 rows and 4 columns. In other embodiments, m may not be equal to n.

[0051] like Figure 2 As shown, each conductive area 11 is provided with a conductive block group 111. In this embodiment, each conductive block group 111 includes a first conductive block pair 1111 for electrically connecting to a red LED, a second conductive block pair 1112 for electrically connecting to a green LED, and a third conductive block pair 1113 for electrically connecting to a blue LED.

[0052] like Figure 2 and Figure 3 As shown, the pixel unit 2 is disposed in the conductive region 11 of the driving layer 1 and is electrically connected to the conductive block group 111. In this embodiment, each pixel unit 2 includes a red LED 21, a green LED 22, and a blue LED 23.

[0053] like Figure 2 As shown, at most one pixel unit 2 is provided in each conductive area 11 , and the projection of each pixel unit 2 on the driving layer 1 falls within the projection of its corresponding conductive area 11 on the driving layer 1 .

[0054] like Figure 2 As shown, the length of the first side of each conductive area 11 parallel to the first direction X is P1, and the length of the second side of each conductive area 11 parallel to the second direction Y is P2.

[0055] like Figure 2 As shown, the first pixel pitch between two adjacent pixel units 2 arranged along the first direction X is L1, L1=j*P1, j≥1; the second pixel pitch between two adjacent pixel units 2 arranged along the second direction Y is L2, L2=k*P2, k≥1.

[0056] like Figure 2 As shown, in this embodiment, one pixel unit 2 is provided in each conductive area 11 , so that L1 = P1 and L2 = P2 , thereby meeting the user's demand for a small-sized display panel.

[0057] like Figure 3 and Figure 4 As shown, the first signal connection block 3 is disposed on a side of the drive layer 1 away from the pixel unit 2. The signal transmitted by the first signal connection block 3 includes a scan control signal. The first signal connection block 3 is used to implement zoning control of the conductive area 11 of the display block 101. In this embodiment, each of the conductive areas 11 is provided with a pixel unit 2, so each of the first signal connection blocks 3 is turned on (filled with hatching).

[0058] like Figure 3 and Figure 4As shown, the second signal connection block 4 is disposed on a side of the driving layer 1 away from the pixel unit 2. The signal transmitted by the second signal connection block 4 includes a common signal.

[0059] Example 2

[0060] like Figure 5 As shown, this embodiment provides a display panel 100. The display panel 100 includes a plurality of display blocks 101 arranged in an array. In this embodiment, the display panel 100 includes 8 display blocks 101 arranged in 2 rows and 4 columns. In other embodiments, the display panel 100 may also include 12 display blocks 101 arranged in 3 rows and 4 columns, or 15 display blocks 101 arranged in 5 rows and 3 columns, which are not limited in this embodiment.

[0061] In this embodiment, independent display blocks 101 are packaged and then a plurality of display blocks 101 are arranged in an array to form a display panel 100 , which is conducive to achieving integration and miniaturization of the package of the display panel 100 .

[0062] like Figure 6 and Figure 7 As shown, each of the display blocks 101 includes: a driving layer 1 , at least one pixel unit 2 , a first signal connection block 3 and a second signal connection block 4 .

[0063] like Figure 6 As shown, the driving layer 1 has a plurality of conductive areas 11 arranged in an array. Specifically, each display block 101 includes the conductive areas 11 arranged in m rows and n columns, where m ≥ 1 and n ≥ 1. In this embodiment, m = n = 4, i.e., each display block 101 includes 16 conductive areas 11 arranged in 4 rows and 4 columns. In other embodiments, m may not be equal to n.

[0064] like Figure 6 As shown, each conductive area 11 is provided with a conductive block group 111. In this embodiment, each conductive block group 111 includes a first conductive block pair 1111 for electrically connecting to a red LED, a second conductive block pair 1112 for electrically connecting to a green LED, and a third conductive block pair 1113 for electrically connecting to a blue LED.

[0065] like Figure 6 and Figure 7 As shown, the pixel unit 2 is disposed in the conductive region 11 of the driving layer 1 and is electrically connected to the conductive block group 111. In this embodiment, each pixel unit 2 includes a red LED 21, a green LED 22, and a blue LED 23.

[0066] like Figure 6As shown, at most one pixel unit 2 is provided in each conductive area 11 , and the projection of each pixel unit 2 on the driving layer 1 falls within the projection of its corresponding conductive area 11 on the driving layer 1 .

[0067] like Figure 6 As shown, the length of the first side of each conductive area 11 parallel to the first direction X is P1, and the length of the second side of each conductive area 11 parallel to the second direction Y is P2.

[0068] like Figure 6 As shown, the first pixel pitch between two adjacent pixel units 2 arranged along the first direction X is L1, L1=j*P1, j≥1; the second pixel pitch between two adjacent pixel units 2 arranged along the second direction Y is L2, L2=k*P2, k≥1.

[0069] like Figure 6 As shown, in this embodiment, one conductive block group 111 is provided between two adjacent pixel units 2 arranged along the first direction X within the same display block 101, with L1 = 2P1; and one conductive block group 111 is provided between two adjacent pixel units 2 arranged along the second direction Y within the same display block 101, with L2 = 2P2. This can meet user needs for small and medium-sized display panels.

[0070] Specifically, in this embodiment, each of the display blocks 101 includes four conductive pixel units 2, which are respectively located in the conductive regions 11 of the first row and first column, the first row and third column, the third row and first column, and the third row and third column. In other embodiments, the conductive pixel units 2 may also be respectively located in the conductive regions 11 of the first row and second column, the first row and fourth column, the third row and second column, and the third row and fourth column; the conductive pixel units 2 may also be respectively located in the conductive regions 11 of the second row and first column, the second row and third column, the fourth row and first column, and the fourth row and third column; the conductive pixel units 2 may also be respectively located in the conductive regions 11 of the second row and second column, the second row and fourth column, the fourth row and second column, and the fourth row and fourth column.

[0071] like Figure 7 and Figure 8 As shown, the first signal connection block 3 is disposed on a side of the drive layer 1 away from the pixel unit 2. The signal transmitted by the first signal connection block 3 includes a scan control signal. The first signal connection block 3 is used to implement zoning control of the conductive area 11 of the display block 101. In this embodiment, each conductive area 11 is provided with four pixel units 2, so each first signal connection block 3 is partially turned on (partially filled with hatching).

[0072] like Figure 7 and Figure 8As shown, the second signal connection block 4 is disposed on a side of the driving layer 1 away from the pixel unit 2. The signal transmitted by the second signal connection block 4 includes a common signal.

[0073] Example 3

[0074] like Figure 9 As shown, this embodiment provides a display panel 100. The display panel 100 includes a plurality of display blocks 101 arranged in an array. In this embodiment, the display panel 100 includes 8 display blocks 101 arranged in 2 rows and 4 columns. In other embodiments, the display panel 100 may also include 12 display blocks 101 arranged in 3 rows and 4 columns, or 15 display blocks 101 arranged in 5 rows and 3 columns, which are not limited in this embodiment.

[0075] In this embodiment, independent display blocks 101 are packaged and then a plurality of display blocks 101 are arranged in an array to form a display panel 100 , which is conducive to achieving integration and miniaturization of the package of the display panel 100 .

[0076] like Figure 10 and Figure 11 As shown, each of the display blocks 101 includes: a driving layer 1 , at least one pixel unit 2 , a first signal connection block 3 and a second signal connection block 4 .

[0077] like Figure 10 As shown, the driving layer 1 has a plurality of conductive areas 11 arranged in an array. Specifically, each display block 101 includes the conductive areas 11 arranged in m rows and n columns, where m ≥ 1 and n ≥ 1. In this embodiment, m = n = 4, i.e., each display block 101 includes 16 conductive areas 11 arranged in 4 rows and 4 columns. In other embodiments, m may not be equal to n.

[0078] like Figure 10 As shown, each conductive area 11 is provided with a conductive block group 111. In this embodiment, each conductive block group 111 includes a first conductive block pair 1111 for electrically connecting to a red LED, a second conductive block pair 1112 for electrically connecting to a green LED, and a third conductive block pair 1113 for electrically connecting to a blue LED.

[0079] like Figure 10 and Figure 11 As shown, the pixel unit 2 is disposed in the conductive area 11 of the driving layer 1 and is electrically connected to the conductive block group 111. In this embodiment, each pixel unit 2 includes a red LED 21, a green LED 22 and a blue LED 23.

[0080] like Figure 10As shown, at most one pixel unit 2 is provided in each conductive area 11 , and the projection of each pixel unit 2 on the driving layer 1 falls within the projection of its corresponding conductive area 11 on the driving layer 1 .

[0081] like Figure 10 As shown, the length of the first side of each conductive area 11 parallel to the first direction X is P1, and the length of the second side of each conductive area 11 parallel to the second direction Y is P2.

[0082] like Figure 10 As shown, the first pixel pitch between two adjacent pixel units 2 arranged along the first direction X is L1, L1=j*P1, j≥1; the second pixel pitch between two adjacent pixel units 2 arranged along the second direction Y is L2, L2=k*P2, k≥1.

[0083] like Figure 10 As shown, in this embodiment, two conductive block groups 111 are provided between two adjacent pixel units 2 arranged along the first direction X within the same display block 101, with L1 = 3P1; and two conductive block groups 111 are provided between two adjacent pixel units 2 arranged along the second direction Y within the same display block 101, with L2 = 3P2. This can meet user needs for large and medium-sized display panels.

[0084] Specifically, in this embodiment, each of the display blocks 101 includes four conductive pixel units 2 , which are respectively located in the conductive areas 11 at the four corners of the display block 101 .

[0085] like Figure 11 and Figure 12 As shown, the first signal connection block 3 is disposed on a side of the drive layer 1 away from the pixel unit 2. The signal transmitted by the first signal connection block 3 includes a scan control signal. The first signal connection block 3 is used to implement zoning control of the conductive area 11 of the display block 101. In this embodiment, each conductive area 11 is provided with four pixel units 2, so each first signal connection block 3 is partially turned on (partially filled with hatching).

[0086] like Figure 11 and Figure 12 As shown, the second signal connection block 4 is disposed on a side of the driving layer 1 away from the pixel unit 2. The signal transmitted by the second signal connection block 4 includes a common signal.

[0087] Example 4

[0088] like Figure 13As shown, this embodiment provides a display panel 100. The display panel 100 includes a plurality of display blocks 101 arranged in an array. In this embodiment, the display panel 100 includes 8 display blocks 101 arranged in 2 rows and 4 columns. In other embodiments, the display panel 100 may also include 12 display blocks 101 arranged in 3 rows and 4 columns, or 15 display blocks 101 arranged in 5 rows and 3 columns, which are not limited in this embodiment.

[0089] In this embodiment, independent display blocks 101 are packaged and then a plurality of display blocks 101 are arranged in an array to form a display panel 100 , which is conducive to achieving integration and miniaturization of the package of the display panel 100 .

[0090] like Figure 14 and Figure 15 As shown, each of the display blocks 101 includes: a driving layer 1 , at least one pixel unit 2 , a first signal connection block 3 and a second signal connection block 4 .

[0091] like Figure 14 As shown, the driving layer 1 has a plurality of conductive areas 11 arranged in an array. Specifically, each display block 101 includes the conductive areas 11 arranged in m rows and n columns, where m ≥ 1 and n ≥ 1. In this embodiment, m = n = 4, i.e., each display block 101 includes 16 conductive areas 11 arranged in 4 rows and 4 columns. In other embodiments, m may not be equal to n.

[0092] like Figure 14 As shown, each conductive area 11 is provided with a conductive block group 111. In this embodiment, each conductive block group 111 includes a first conductive block pair 1111 for electrically connecting to a red LED, a second conductive block pair 1112 for electrically connecting to a green LED, and a third conductive block pair 1113 for electrically connecting to a blue LED.

[0093] like Figure 14 and Figure 15 As shown, the pixel unit 2 is disposed in the conductive area 11 of the driving layer 1 and is electrically connected to the conductive block group 111. In this embodiment, each pixel unit 2 includes a red LED 21, a green LED 22 and a blue LED 23.

[0094] like Figure 14 As shown, at most one pixel unit 2 is provided in each conductive area 11 , and the projection of each pixel unit 2 on the driving layer 1 falls within the projection of its corresponding conductive area 11 on the driving layer 1 .

[0095] like Figure 14As shown, the length of the first side of each conductive area 11 parallel to the first direction X is P1, and the length of the second side of each conductive area 11 parallel to the second direction Y is P2.

[0096] like Figure 13 and Figure 14 As shown, the first pixel pitch between two adjacent pixel units 2 arranged along the first direction X is L1, L1=j*P1, j≥1; the second pixel pitch between two adjacent pixel units 2 arranged along the second direction Y is L2, L2=k*P2, k≥1.

[0097] like Figure 13 and Figure 14 As shown, in this embodiment, each display block 101 includes one pixel unit 2. Three conductive block groups 111 are located between two adjacent pixel units 2 arranged along the first direction X, with L1 = 4P1; and three conductive block groups 111 are located between two adjacent pixel units 2 arranged along the second direction Y, with L2 = 4P2. This can meet user requirements for large-size display panels.

[0098] like Figure 15 and Figure 16 As shown, the first signal connection block 3 is disposed on a side of the drive layer 1 away from the pixel unit 2. The signal transmitted by the first signal connection block 3 includes a scan control signal. The first signal connection block 3 is used to implement zoning control of the conductive area 11 of the display block 101. In this embodiment, each conductive area 11 is provided with four pixel units 2, so each first signal connection block 3 is partially turned on (partially filled with hatching).

[0099] like Figure 15 and Figure 16 As shown, the second signal connection block 4 is disposed on a side of the driving layer 1 away from the pixel unit 2. The signal transmitted by the second signal connection block 4 includes a common signal.

[0100] Furthermore, the above is a detailed introduction to a display panel provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: The display blocks are arranged in a plurality of arrays, wherein the display blocks are independently formed by encapsulation; Each of the display blocks comprises: A driving layer having a plurality of conductive areas arranged in an array, each of the conductive areas having a conductive block group; and At least one pixel unit is disposed in the conductive area of ​​the driving layer and is electrically connected to the conductive block group; a first signal connection block, disposed on a side of the driving layer away from the pixel unit, wherein each first signal connection block is partially conductive, and the signal transmitted by the first signal connection block includes a scanning control signal, and the first signal connection block is used to realize partition control of the conductive area of ​​the display block; At most one pixel unit is provided in each of the conductive areas, and the projection of each pixel unit on the driving layer falls within the projection of its corresponding conductive area on the driving layer; The length of the first side of each conductive area parallel to the first direction is P1, and the length of the second side of each conductive area parallel to the second direction is P2; A first pixel pitch between two adjacent pixel units arranged along the first direction is L1, where L1=j×P1, j≥2; the first pixel pitch is a pitch between two adjacent pixel units arranged along the first direction on the same side in the first direction; A second pixel pitch between two adjacent pixel units arranged along the second direction is L2, where L2=k×P2, k≥2; the second pixel pitch is a pitch between two adjacent pixel units arranged along the second direction on the same side in the second direction; There is at least one conductive block group between two adjacent pixel units arranged along the first direction in the same display block; There is at least one conductive block group between two adjacent pixel units arranged along the second direction in the same display block.

2. The display panel according to claim 1, wherein: There is one conductive block group between two adjacent pixel units arranged along the first direction in the same display block, and L1=2P1.

3. The display panel according to claim 2, wherein: There is one conductive block group between two adjacent pixel units arranged along the second direction in the same display block, and L2=2P2.

4. The display panel according to claim 1, wherein: There are two conductive block groups between two adjacent pixel units arranged along the first direction in the same display block, and L1=3P1.

5. The display panel according to claim 4, wherein: There are two conductive block groups between two adjacent pixel units arranged along the second direction in the same display block, and L2=3P2.

6. The display panel according to claim 1, wherein: Each of the display blocks includes one pixel unit, and three conductive block groups are arranged between two adjacent pixel units arranged along the first direction, where L1=4P1.

7. The display panel according to claim 6, wherein: There are three conductive block groups between two adjacent pixel units arranged along the second direction, L2=4P2.

8. The display panel according to claim 1, wherein: Each of the display blocks further includes a second signal connection block disposed on a side of the driving layer away from the pixel unit.

9. The display panel according to claim 8, wherein: The signal transmitted by the second signal connection block includes a common signal.

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