Magnetic memory structure and memory

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a magnetic memory structure and a memory, which comprises: a plurality of stacked magnetic storage units, and the magnetic storage unit at least comprises: a first transistor, the first transistor comprises a gate, the gate is used for connecting a control line, and one terminal of a source or a drain of the first transistor is used for connecting a first signal line; a magnetic tunnel junction, a bottom of the magnetic tunnel junction is used for connecting the other terminal of the source or the drain in the first transistor, and a top of the magnetic tunnel junction is used for connecting a second signal line, wherein the magnetic tunnel junction extends along the stacking direction of the magnetic storage unit; and the magnetic tunnel junctions in the plurality of stacked magnetic storage units are connected to the same second signal line, so that the integration density of the magnetic memory structure is improved.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and in particular to a magnetic memory structure and memory. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is a novel type of solid-state non-volatile memory based on the characteristics of magnetic tunnel junctions (MTJs), offering high-speed read and write capabilities. MRAM stores data using magnetic field polarization rather than electric charge. An MTJ consists of a free layer, a tunneling layer, and a fixed layer. The magnetic field polarization direction of the free layer can change, while the magnetic field direction of the fixed layer remains constant. When the magnetic field directions of the free and fixed layers are the same, the MTJ exhibits low resistance; conversely, it exhibits high resistance. By detecting the resistance of the MTJ, the stored data ("0" or "1") can be determined.

[0003] However, in existing magnetic random access memories (MRAMs), limitations in the arrangement of memory cells and the connection between magnetic tunnel junctions and transistors restrict further improvements in overall performance, thus limiting their widespread application. Therefore, improving the structure of magnetic RAMs to achieve high-density MRAM and enhance overall performance is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This disclosure provides a magnetic memory structure and memory to improve the integration density of the magnetic memory structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a magnetic memory structure, including: a plurality of stacked magnetic memory cells, each magnetic memory cell including at least: a first transistor, the gate of the first transistor being used to connect to a control line, and one terminal of the source or drain of the first transistor being used to connect to a first signal line; a magnetic tunnel junction, the bottom of the magnetic tunnel junction being used to connect to another terminal of the source or drain of the first transistor, and the top of the magnetic tunnel junction being used to connect to a second signal line, wherein the magnetic tunnel junction extends along the stacking direction of the magnetic memory cells; the magnetic tunnel junctions in the plurality of stacked magnetic memory cells are connected to the same second signal line.

[0006] In some embodiments, the control line extends along a first direction, the first transistor includes a channel region connected to the gate of the first transistor, and the source and drain of the first transistor are disposed on opposite sides of the channel region of the first transistor along a second direction, wherein the first direction intersects the second direction.

[0007] In some embodiments, the gate of the first transistor is provided to enclose the channel region.

[0008] In some embodiments, the channel region surrounds the gate of the first transistor.

[0009] In some embodiments, in the direction perpendicular to the axis of the magnetic tunnel junction, the projections of the gates of the first transistors in the stacked magnetic memory cells completely overlap, and the lines connecting the magnetic tunnel junctions and the first transistor connection points in magnetic memory cells located in different layers to the projections of the gates of the first transistors are in the same direction but have different lengths.

[0010] In some embodiments, in the direction perpendicular to the axis of the magnetic tunnel junction, the projected portions of the gates of the first transistors in the stacked magnetic memory cells may or may not overlap, and the lines connecting the magnetic tunnel junctions and the first transistor connection points in magnetic memory cells located in different layers to the projections of the gates of the first transistors are in the same direction and have the same length.

[0011] In some embodiments, in the direction perpendicular to the axis of the magnetic tunnel junction, the projections of the gates of the first transistors in the stacked magnetic memory cells completely overlap, and the projections of the magnetic tunnel junctions and the first transistor connection points in magnetic memory cells located in different layers onto the corresponding projections of the gates of the first transistors are in the same direction and have the same length.

[0012] In some embodiments, the magnetic tunnel junctions in a plurality of stacked magnetic storage cells are disposed at different heights.

[0013] In some embodiments, the magnetic tunnel junctions in a plurality of stacked magnetic storage cells are disposed at the same height.

[0014] In some embodiments, the magnetic storage cell further includes: a second transistor disposed side-by-side with the first transistor in a first direction, wherein the gate of the first transistor and the gate of the second transistor are connected to the same control line, and one terminal of the source or drain of the second transistor is connected to the same first signal line as the first transistor; the other terminal of the source or drain of the second transistor is connected to the other terminal of the source or drain of the first transistor via a transmission line, and the transmission line is electrically connected to the bottom of the magnetic tunnel junction.

[0015] In some embodiments, the first signal lines connected to the first transistors in the stacked magnetic storage cells are all connected.

[0016] In some embodiments, magnetic storage cells are arranged along a first direction, control lines and first signal lines extend along the first direction, and first transistors in different magnetic storage cells arranged in the same layer in the first direction are connected to the same control line and the same first signal line, and magnetic tunnel junctions in different magnetic storage cells arranged in the same layer are connected to different second signal lines.

[0017] In some embodiments, magnetic storage cells are arranged along a second direction, a second signal line extends along a second direction, and magnetic tunnel junctions in different magnetic storage cells arranged in the same layer along the second direction are connected to the same second signal line.

[0018] In some embodiments, in the second direction, two adjacent magnetic storage cells arranged on the same layer are symmetrically arranged, and the symmetrically arranged magnetic storage cells are connected to the same first signal line.

[0019] According to some embodiments of this disclosure, another aspect of this disclosure also provides a memory, which includes any of the magnetic memory structures provided in the above embodiments.

[0020] The technical solution provided by the embodiments of this disclosure has at least the following advantages: the memory cell includes a first transistor and a magnetic tunnel junction, wherein the gate of the first transistor is connected to a control line to realize the switching on and off of the first transistor through the control line; one terminal of the source or drain of the first transistor is used to connect to a first signal line, the other terminal of the source or drain of the first transistor is used to connect to the bottom of the magnetic tunnel junction, and the top of the magnetic tunnel junction is used to connect to a second signal line, so that writing or reading of the magnetic tunnel junction can be realized through the first signal line and the second signal line; by stacking the magnetic memory cells, the space utilization of the magnetic memory cells can be improved, thereby increasing the integration density of the magnetic memory structure.

[0021] In addition, the magnetic storage cell may also include a second transistor, which is arranged with the first transistor in a first direction. The first transistor and the second transistor share a control line and a first signal line, so that the first transistor and the second transistor can jointly drive the magnetic tunnel junction to write or read, avoiding insufficient driving capability of a single transistor and improving the driving capability of the magnetic storage cell. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figures 1 to 3 A schematic diagram of a stacked structure of multiple magnetic storage cells provided in one embodiment of this disclosure;

[0024] Figure 4This is a schematic diagram of the arrangement structure of magnetic tunnel junctions in a stacked magnetic memory cell according to an embodiment of the present disclosure;

[0025] Figure 5 A schematic diagram of a stacked structure of another magnetic storage cell provided in an embodiment of this disclosure;

[0026] Figure 6 This is a schematic diagram of a structure in which stacked magnetic storage cells are arranged in a first direction, according to an embodiment of the present disclosure.

[0027] Figure 7 This is a schematic diagram of a structure in which stacked magnetic storage cells are arranged in a first direction and a second direction, according to an embodiment of the present disclosure.

[0028] Figure 8 This is a schematic diagram of another stacked magnetic storage cell structure arranged in a first direction and a second direction, according to an embodiment of the present disclosure. Detailed Implementation

[0029] As can be seen from the background technology, how to realize the structure of high-density MRAM has become an urgent problem to be solved.

[0030] Analysis reveals that each magnetic memory cell includes at least one transistor and one magnetic tunnel junction. Individual magnetic memory cells have a relatively large area, and each cell requires connection to at least three control terminals: the control line (word line) to which the transistor's gate is connected, responsible for turning the connected transistor on or off; one end of the transistor's source or drain connected to the first signal line (source line); and the other end of the transistor's drain or source connected to one terminal of the magnetic tunnel junction, with the other terminal of the magnetic tunnel junction connected to the second signal line (bit line). Therefore, improving the integration density of MRAM has become one of the urgent technical problems to be solved.

[0031] One embodiment of this disclosure provides a magnetic memory structure to improve the integration density of the magnetic memory structure.

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] Figures 1 to 3 This is a schematic diagram of a stacked structure of multiple magnetic storage cells provided in one embodiment of the present disclosure. Figure 4 This is a schematic diagram of the arrangement structure of magnetic tunnel junctions in a stacked magnetic memory cell according to an embodiment of the present disclosure. Figure 5This is a schematic diagram of a stacked structure of another magnetic storage cell provided in one embodiment of the present disclosure. Figure 6 This is a schematic diagram of a structure in which stacked magnetic storage cells are arranged in a first direction, according to an embodiment of the present disclosure. Figure 7 This is a schematic diagram of a structure in which stacked magnetic storage cells are arranged in a first direction and a second direction, according to an embodiment of the present disclosure. Figure 8 This is a schematic diagram of another structure of stacked magnetic storage cells arranged in a first direction and a second direction according to an embodiment of the present disclosure. The magnetic memory structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0034] refer to Figure 1 The magnetic memory structure includes: a plurality of stacked magnetic memory cells 10, each magnetic memory cell 10 including at least: a first transistor 100, the gate of the first transistor 100 being connected to a control line 103, and one terminal of the source or drain of the first transistor being connected to a first signal line 101; a magnetic tunnel junction 200, the bottom of the magnetic tunnel junction being connected to another terminal of the source or drain of the first transistor 100, and the top of the magnetic tunnel junction 200 being connected to a second signal line 102, wherein the magnetic tunnel junction 200 extends along the stacking direction of the magnetic memory cells 10; the magnetic tunnel junctions 200 in the plurality of stacked magnetic memory cells 10 are connected to the same second signal line 102.

[0035] The magnetic storage cell includes a first transistor 100 and a magnetic tunnel junction 200. The gate of the first transistor 100 is connected to a control line 103, so that the first transistor 100 can be turned on or off through the control line 103. One terminal of the source or drain of the first transistor 100 is used to connect to a first signal line 101, and the other terminal of the source or drain of the first transistor 100 is used to connect to the bottom of the magnetic tunnel junction 200. The top of the magnetic tunnel junction 200 is used to connect to a second signal line 102. Thus, writing or reading from the magnetic tunnel junction 200 can be achieved through the first signal line 101 and the second signal line 102. By stacking the magnetic storage cells 10, the space utilization of the magnetic storage cells 10 can be improved, thereby increasing the integration density of the magnetic memory structure.

[0036] It should be noted that, in this embodiment, the source of the first transistor 100 is connected to the first signal line 101, and the drain of the first transistor 100 is connected to the bottom of the magnetic tunnel junction 200. The specific connection methods of the "source" and "drain" defined above do not constitute a limitation on the embodiments of this application. In other embodiments, the connection methods of "drain" replacing "source" and "source" replacing "drain" can be used.

[0037] For the first transistor 100, the first transistor 100 includes a channel region for connecting the gate of the first transistor 100, the control line 103 extends along a first direction X, and the source and drain of the first transistor 100 are disposed on opposite sides of the channel region of the first transistor 100 along a second direction Y, wherein the first direction X intersects the second direction Y.

[0038] It should be noted that in this embodiment, the channel region of the first transistor surrounds the gate of the first transistor; in other embodiments, the gate of the first transistor may surround the channel region. By surrounding the gate of the first transistor with the channel region or the gate of the first transistor surrounding the channel region, a first transistor with a fully surrounding gate structure can be formed. Increasing the area of ​​the channel region can improve the first transistor's ability to control current, thereby improving the performance of the semiconductor structure. At the same time, the fully surrounding gate structure can improve the space utilization of the semiconductor structure, thereby further increasing the integration density of the semiconductor structure.

[0039] In some embodiments, the first transistor can also be a planar transistor or a Fin Field-Effect Transistor (FinFET). The main difference between FinFET and planar transistor is that the channel region of FinFET is composed of high and thin fins protruding from an insulating substrate. The source and drain are located at the two ends of the channel region, respectively, and the three gates are close to the sidewalls and top of the channel region for auxiliary current control. This fin structure increases the area of ​​the gate surrounding the channel region and strengthens the gate's control over the channel region. This can effectively alleviate the short-channel effect that occurs in planar transistors, greatly improve circuit control and reduce leakage current, and also significantly shorten the gate length of the transistor. Therefore, FinFET can effectively reduce the scattering effect of impurity ions and improve the carrier mobility in the channel region without the need for a highly doped channel.

[0040] For the magnetic tunnel junction 200, the magnetic tunnel junction 200 can rotate the magnetic field direction based on the spin-movement torque or spin-orbit torque. The magnetic tunnel junction 200 includes a free layer 201, a tunneling layer 202 and a fixed layer 203 stacked in sequence. The magnetic field polarization direction of the free layer 201 can be changed, while the magnetic field direction of the fixed layer 203 remains unchanged. When the magnetic field directions of the free layer 201 and the fixed layer 203 are the same, the magnetic tunnel junction 200 exhibits low resistance; otherwise, the magnetic tunnel junction 200 exhibits high resistance. By detecting the resistance of the magnetic tunnel junction 200, it is possible to determine whether the stored data is "0" or "1".

[0041] In some embodiments, the materials of the free layer 201 and the fixed layer 203 include any one of cobalt iron boron, cobalt, or nickel iron; the material of the tunneling layer 202 includes magnesium oxide.

[0042] In some embodiments, in the direction perpendicular to the axis of the magnetic tunnel junction, the projections of the gates of the first transistors in the stacked magnetic memory cells completely overlap. The lines connecting the magnetic tunnel junctions and the first transistor connection points in magnetic memory cells located in different layers to the projections of the first transistor gates have the same direction but different lengths. Specifically, refer to... Figure 1 The magnetic storage cells 10 are stacked vertically. The projection of the magnetic tunnel junction 200 and the first transistor 100 connection point in the magnetic storage cells 10 located in different layers onto the gate projection of the first transistor 100 has the same direction but the length of the connection gradually increases, thereby forming a stepped stacked structure. This allows the magnetic tunnel junctions 200 in the stacked magnetic storage cells 10 to be arranged side by side in the second direction Y, forming a more regular magnetic memory structure, which facilitates the fabrication of the magnetic memory structure.

[0043] In other embodiments, in the direction perpendicular to the axis of the magnetic tunnel junction, the projected portions of the gates of the first transistors in the stacked magnetic memory cells may overlap or not overlap, and the lines connecting the magnetic tunnel junctions and the first transistor connection points in magnetic memory cells located in different layers to the projections of the first transistor gates have the same direction and the same length. Specifically, refer to... Figure 2 The magnetic storage cells 10 are stacked in a staggered manner in the second direction. The first transistors 100 located in different layers have the same structure. The magnetic tunnel junctions 200 in the stacked magnetic storage cells 10 can be arranged side by side in the second direction Y to make the structure of the first transistors 100 in different magnetic storage cells 10 uniform, so as to prevent the performance of the magnetic memory structure from being affected due to the different structure of the first transistors 100, thereby avoiding the impact on the performance of the magnetic memory structure.

[0044] In some other embodiments, in the direction perpendicular to the axis of the magnetic tunnel junction, the projections of the gates of the first transistors in the stacked magnetic memory cells completely overlap, and the lines connecting the projections of the magnetic tunnel junctions and the first transistor connection points in magnetic memory cells located in different layers to the corresponding projections of the gates of the first transistors have the same direction and the same length. Specifically, refer to Figure 3 The magnetic storage cells 10 are stacked in the vertical direction. The source or drain of the first transistor 100 connected to the magnetic tunnel junction 200 has an extension 111 in the first direction X. The bottom of the magnetic tunnel junction 200 is connected to the extension 111, so that the magnetic tunnel junctions 200 can be arranged side by side in the first direction X. This can reduce the arrangement space of the magnetic storage cells 10 in the second direction Y, which is beneficial to reduce the spatial volume of the stacked magnetic storage cells 10 in the second direction Y and improve the integration density of the magnetic memory structure.

[0045] In the stacking configuration of the magnetic storage cells 10 provided in the embodiments of this disclosure, the magnetic tunnel junctions 200 in the multiple stacked magnetic storage cells 10 are disposed at the same height; in other embodiments, the magnetic tunnel junctions in the multiple stacked magnetic storage cells may be disposed at different heights. For example, refer to... Figure 4 Since the magnetic tunnel junction 200 needs a connecting line 112 to connect to the source or drain of the corresponding first transistor 100, by setting the magnetic tunnel junctions 200 in different magnetic memory cells 10 at different heights, the connecting line 112 connecting the magnetic tunnel junction 200 to the source or drain of the corresponding first transistor 100 has the same length. This avoids the different resistance caused by the different lengths of the connecting line 112 from affecting the writing or reading process of the magnetic tunnel junction 200, thereby improving the performance of the magnetic memory structure.

[0046] It should be noted that the magnetic storage cell stacking method provided in the embodiments of this disclosure is only a partial structural diagram of the magnetic storage cell stacking and does not constitute a limitation on the number of magnetic storage cells stacked. The specific number of magnetic storage cells stacked can be set according to actual needs.

[0047] In some embodiments, the magnetic storage cell 10 may further include: a second transistor 120, arranged side by side with the first transistor 100 in a first direction X, wherein the gate of the first transistor 100 and the gate of the second transistor 120 are connected to the same control line 103, and one terminal of the source or drain of the second transistor 120 and one terminal of the source or drain of the first transistor 100 are connected to the same first signal line 101; the other terminal of the source or drain of the second transistor 120 and the other terminal of the source or drain of the first transistor 100 are connected through a transmission line 121, and the transmission line 121 is electrically connected to the bottom of the magnetic tunnel junction 200.

[0048] By arranging the second transistor 120 and the first transistor 100 in the first direction X, and with the first transistor 100 and the second transistor 120 sharing a control line 103 and a first signal line 101, the on / off state of the first transistor 100 and the second transistor 120 can be controlled simultaneously using a single control line 103. One terminal of the source or drain of the first transistor 100 is connected to one terminal of the source or drain of the second transistor 120 via the same first signal line 101, and the other terminal of the source or drain of the first transistor 100 is connected to the other terminal of the source or drain of the second transistor 120 via the same transmission line 121. The transmission line 121 is connected to the magnetic tunnel junction 200, allowing the first transistor 100 and the second transistor 120 to be connected in parallel. The first transistor 100 and the second transistor 120 can jointly drive the writing or reading of the magnetic tunnel junction 200, avoiding the insufficient driving capability of a single transistor and improving the driving capability of the magnetic memory cell.

[0049] Understandably, if the driving capability of two transistors is insufficient, more transistors can be added in parallel, such as three, five, or eight transistors arranged side by side in the first direction. These parallel transistors share the control line, the first signal line, and the transmission line. The multiple parallel transistors work together to drive the writing or reading of the magnetic tunnel junction, thereby improving the driving capability of the magnetic memory cell.

[0050] It should be noted that, in this embodiment, the source of the first transistor 100 and the source of the second transistor 120 are used to connect to the first signal line 101, and the drain of the first transistor 100 and the drain of the second transistor 120 are connected to the transmission line 121. The specific connection methods of the "source" and "drain" defined above do not constitute a limitation on the embodiments of this application. In other embodiments, the connection method of "drain" replacing "source" and "source" replacing "drain" can be used.

[0051] For the second transistor 120, the channel region of the second transistor 120 is used to connect the gate of the second transistor 120, the control line 103 extends along the first direction X, and the source and drain of the second transistor 120 are disposed on opposite sides of the channel region of the second transistor 120 along the second direction Y.

[0052] It should be noted that in this embodiment, the channel region of the second transistor surrounds the gate of the second transistor; in other embodiments, the gate of the second transistor may surround the channel region. By surrounding the gate of the second transistor with the channel region or the gate of the second transistor surrounding the channel region, a second transistor with a fully surrounding gate structure can be formed. Increasing the area of ​​the channel region can improve the current control capability of the second transistor, thereby improving the performance of the semiconductor structure. At the same time, the fully surrounding gate structure can improve the space utilization of the semiconductor structure, thereby further increasing the integration density of the semiconductor structure.

[0053] In some embodiments, the second transistor can also be a planar transistor or a Fin Field-Effect Transistor (FinFET). The main difference between FinFET and planar transistor is that the channel region of FinFET is composed of high and thin fins protruding from an insulating substrate. The source and drain are located at the two ends of the channel region, respectively, and the three gates are close to the sidewalls and top of the channel region for auxiliary current control. This fin structure increases the area of ​​the gate surrounding the channel region and strengthens the control of the gate over the channel region. This can effectively alleviate the short-channel effect that occurs in planar transistors, greatly improve circuit control and reduce leakage current, and can also significantly shorten the gate length of the transistor. Therefore, FinFET can effectively reduce the scattering effect of impurity ions and improve the carrier mobility in the channel region without the need for a highly doped channel.

[0054] It should be noted that in this embodiment, the structure of the first transistor is the same as that of the second transistor; in other embodiments, the structure of the first transistor may be different from that of the second transistor.

[0055] In some embodiments, the first signal lines connected to the first transistors in the stacked magnetic memory cells of different layers are all connected. That is, the first transistors in the stacked magnetic memory cells of different layers are all connected to the same first signal line. During the writing process of the magnetic tunnel junction, by applying a conduction voltage to the control line corresponding to the target magnetic tunnel junction, the first transistors in a column of stacked magnetic memory cells corresponding to the target magnetic tunnel junction can be turned on, further selecting the first signal line. The magnetic tunnel junctions in the column of stacked magnetic memory cells corresponding to the target magnetic tunnel junction are all in a state ready to be written. The magnetic memory cell where the target magnetic tunnel junction is located can be located through the corresponding second signal line. Then, based on the magnitude and direction of the current in the first and second signal lines, the writing of the target magnetic tunnel junction is achieved; the reading process of the magnetic tunnel junction... During the process, by applying a conduction voltage to the control line corresponding to the target magnetic tunnel junction, the first transistor in a column of stacked magnetic memory cells corresponding to the target magnetic tunnel junction is turned on, further selecting the first signal line. All magnetic tunnel junctions in the column of stacked magnetic memory cells corresponding to the target magnetic tunnel junction are in a read-read state. The corresponding second signal line can then be used to locate the magnetic memory cell containing the target magnetic tunnel junction. Based on the current in the first and second signal lines, the resistance of the target magnetic tunnel junction is determined, thus identifying the data stored in the target magnetic tunnel junction. If the magnetic tunnel junction exhibits a high resistance state, the stored data is "1"; if it exhibits a low resistance state, the stored data is "0". By connecting all the first signal lines of the stacked magnetic memory cells, the number of control terminals of the numerous first signal lines in the magnetic memory array structure can be reduced, while simultaneously improving the control capability of the magnetic memory array structure and simplifying the manufacturing process.

[0056] refer to Figure 6In some embodiments, the magnetic storage cells 10 can be arranged along a first direction X, with control lines 103 and first signal lines 101 extending along the first direction X. First transistors 100 in different magnetic storage cells 10 arranged on the same layer in the first direction X are connected to the same control line 103 and the same first signal line 101. Magnetic tunnel junctions 200 in different magnetic storage cells 10 arranged on the same layer are connected to different second signal lines 102. By arranging the magnetic storage cells 10 in the first direction X, the spatial density of the magnetic storage cells 10 can be increased, thereby improving the integration density of magnetic storage cells per unit space. Furthermore, since the first transistors 100 stacked on the same layer in the first direction X share the same control line 103, the number of control terminals on the control line 103 can be reduced, improving the control capability of the magnetic memory structure.

[0057] Further, refer to Figure 7 In some embodiments, the magnetic storage cells 10 can be further arranged along the second direction Y, and the second signal line 102 extends along the second direction Y. Magnetic tunnel junctions 200 in different magnetic storage cells 10 arranged in the same layer along the second direction Y are connected to the same second signal line 102. By stacking the magnetic storage cells 10 and arranging them in the first direction X and the second direction Y, the stacking density of the magnetic storage cells 10 can be increased per unit space, thereby improving the integration density of the magnetic memory. Furthermore, the first transistors 100 arranged in the same layer of the magnetic storage cells 10 arranged in the first direction X share a control line 103 and a first signal line 101. The connection of magnetic tunnel junctions 200 in magnetic storage cells 10 arranged in different layers along the second direction Y to the same second signal line 102 reduces the number of control terminals for the control line 103, the first signal line 101, and the second signal line 102, thus improving the control capability of the magnetic memory.

[0058] Furthermore, refer to Figure 8 In some embodiments, two adjacent magnetic storage cells 10 arranged on the same layer in the second direction Y can be symmetrically arranged, and the symmetrically arranged magnetic storage cells 10 are connected to the same first signal line 101. By having two symmetrically arranged magnetic storage cells 10 in the second direction Y share the first signal line 101, the number of control terminals of the first signal line 101 can be further reduced, the control capability of the magnetic memory can be improved, and the fabrication process of the first signal line 101 in the magnetic memory structure can be reduced, thereby improving the fabrication efficiency of the semiconductor structure.

[0059] It is understood that, based on the structure of the magnetic storage cell that may include 2, 3 or 5 transistors, the magnetic storage cell that includes multiple transistors may also be arranged in the manner described above, along the first and second directions, in order to improve the integration density of the magnetic memory structure.

[0060] It is important to note that Figures 6 to 8 The schematic diagram of the magnetic storage cell arrangement is only a partial illustration, intended solely for illustrating the arrangement of the magnetic storage cells, and does not constitute a limitation on the number of magnetic storage cells arranged. Based on the features disclosed in the magnetic memory structure provided in the above embodiments, they can be arbitrarily combined without conflict to obtain new magnetic memory structure embodiments.

[0061] The magnetic memory structure provided in this disclosure includes a first transistor and a magnetic tunnel junction in the memory cell. The gate of the first transistor is connected to a control line to turn the first transistor on or off. One terminal of the source or drain of the first transistor is connected to a first signal line, and the other terminal of the source or drain of the first transistor is connected to the bottom of the magnetic tunnel junction. The top of the magnetic tunnel junction is connected to a second signal line, thereby enabling writing or reading from the magnetic tunnel junction through the first and second signal lines. By stacking the magnetic memory cells, the space utilization of the magnetic memory cells can be improved, thereby increasing the integration density of the magnetic memory structure.

[0062] In another aspect, this disclosure also provides a memory, which includes any of the magnetic memory structures provided in the above embodiments, to improve the integration density of the magnetic memory structure.

[0063] Specifically, memory can be a storage cell or device based on a semiconductor device or component. For example, a memory device can be volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), etc.

[0064] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A magnetic memory structure, characterized in that, include: Multiple stacked magnetic storage cells, wherein the magnetic storage cells include at least: The first transistor has a gate for connecting to a control line and a terminal of the source or drain of the first transistor for connecting to a first signal line. A magnetic tunnel junction, wherein the bottom of the magnetic tunnel junction is used to connect to another terminal of the source or drain of the first transistor, and the top of the magnetic tunnel junction is used to connect to a second signal line, wherein the magnetic tunnel junction extends along the stacking direction of the magnetic memory cells; The magnetic tunnel junctions located on different layers in the multiple stacked magnetic storage cells are connected to the same second signal line.

2. The magnetic memory structure as described in claim 1, characterized in that, The control line extends along a first direction, the first transistor includes a channel region connected to the gate of the first transistor, and the source and drain of the first transistor are disposed on opposite sides of the channel region of the first transistor along a second direction, wherein the first direction intersects the second direction.

3. The magnetic memory structure as described in claim 2, characterized in that, The gate of the first transistor is disposed to surround the channel region.

4. The magnetic memory structure as described in claim 2, characterized in that, The channel region is configured to enclose the gate of the first transistor.

5. The magnetic memory structure as described in claim 1, characterized in that, In the direction perpendicular to the axis of the magnetic tunnel junction, the projections of the gates of the first transistors in the stacked magnetic memory cells completely coincide. The lines connecting the magnetic tunnel junctions and the first transistor connection points in the magnetic memory cells located in different layers are in the same direction but have different lengths.

6. The magnetic memory structure as described in claim 1, characterized in that, In the direction perpendicular to the axis of the magnetic tunnel junction, the projected portions of the gates of the first transistors in the stacked magnetic memory cells may or may not overlap. In the magnetic memory cells located in different layers, the line connecting the magnetic tunnel junction and the first transistor connection point to the first transistor gate projection has the same direction and the same length.

7. The magnetic memory structure as described in claim 1, characterized in that, In the direction perpendicular to the axis of the magnetic tunnel junction, the projections of the gates of the first transistors in the stacked magnetic memory cells completely overlap. The lines connecting the magnetic tunnel junctions and the first transistor connection points in the magnetic memory cells located in different layers to the projections of the gates of the first transistors are in the same direction and have the same length.

8. The magnetic memory structure according to any one of claims 1 to 7, characterized in that, The magnetic tunnel junctions in the multiple stacked magnetic storage cells are disposed at different heights.

9. The magnetic memory structure according to any one of claims 1 to 7, characterized in that, The magnetic tunnel junctions in the multiple stacked magnetic storage cells are disposed at the same height.

10. The magnetic memory structure as described in claim 2, characterized in that, The magnetic storage unit further includes: The second transistor is arranged side by side with the first transistor in the first direction, wherein the gate of the first transistor and the gate of the second transistor are connected to the same control line, and one terminal of the source or drain of the second transistor is connected to the same first signal line as the first transistor. The other terminal of the source or drain of the second transistor is connected to the other terminal of the source or drain of the first transistor via a transmission line, and the transmission line is electrically connected to the bottom of the magnetic tunnel junction.

11. The magnetic memory structure as described in claim 1, characterized in that, The first signal lines connected to the first transistors in the stacked magnetic storage cells are all interconnected.

12. The magnetic memory structure as described in claim 2, characterized in that, The magnetic storage cells are arranged along the first direction, the control line and the first signal line extend along the first direction, and the first transistors in different magnetic storage cells arranged in the same layer in the first direction are connected to the same control line and the same first signal line, and the magnetic tunnel junctions in different magnetic storage cells arranged in the same layer are connected to different second signal lines.

13. The magnetic memory structure as described in claim 12, characterized in that, The magnetic storage cells are arranged along the second direction, the second signal line extends along the second direction, and the magnetic tunnel junctions in different magnetic storage cells arranged in the same layer along the second direction are connected to the same second signal line.

14. The magnetic memory structure as described in claim 13, characterized in that, In the second direction, two adjacent magnetic storage cells arranged on the same layer are symmetrically arranged, and the symmetrically arranged magnetic storage cells are connected to the same first signal line.

15. A memory comprising the magnetic memory structure according to any one of claims 1 to 14.

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