Display substrate, manufacturing method thereof, and display device

Abstract

A display substrate, a manufacturing method thereof, and a display device, wherein the display substrate includes: a base substrate and a driving circuit and a first power line arranged on the base substrate, the driving circuit including at least: a first capacitor, a second capacitor, and a third capacitor; the first capacitor and the third capacitor are arranged along a first direction, the second capacitor and the third capacitor are respectively located on either side of the first capacitor, the second capacitor is located on a side of the first capacitor close to the display area, and one electrode plate of the third capacitor is electrically connected to the first power line; the first power line extends along the first direction, and the orthographic projection of the first capacitor on the base substrate at least partially overlaps with the orthographic projection of the first power line on the base substrate.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) displays offer advantages such as ultrathinness, wide viewing angles, active illumination, high brightness, continuously adjustable color, low cost, fast response, low power consumption, a wide operating temperature range, and flexible display capabilities. They are becoming a highly promising next-generation display technology. The driver circuit is a crucial auxiliary circuit in OLEDs.

[0003] With the continuous advancement of display technology, a large screen-to-body ratio (i.e., the ratio of the actual display area to the total display area) has become a sought-after aesthetic characteristic of display devices. This is especially true for wearable displays (such as smartwatches), where extreme narrow bezels and even full-screen displays are becoming a key development trend, driven by portability and viewing angle considerations. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate, comprising: a display area and a non-display area, including: a base substrate, and a driving circuit and a first power line disposed on the base substrate and located in the non-display area, wherein the driving circuit comprises at least: a first capacitor, a second capacitor, and a third capacitor; the first capacitor and the third capacitor are arranged along a first direction, the second capacitor and the third capacitor are respectively located on either side of the first capacitor, the second capacitor is located on a side of the first capacitor closer to the display area, and one plate of the third capacitor is electrically connected to the first power line;

[0006] The first power line extends along a first direction, and an orthographic projection of the first capacitor on the base substrate at least partially overlaps with an orthographic projection of the first power line on the base substrate.

[0007] In some possible implementations, an orthographic projection of the third capacitor on the substrate at least partially overlaps with an orthographic projection of the first power line on the substrate.

[0008] In some possible implementations, the display substrate further includes: a second power line, an initial signal line, a first clock signal line, and a second clock signal line, which are disposed on the base substrate and located in the non-display area;

[0009] The second power line is located on a side of the driving circuit close to the display area and extends along the first direction. The initial signal line is located on a side of the first power line away from the display area and extends along the first direction. The first clock signal line is located between the first power line and the initial signal line and extends along the first direction. The second clock signal line is located between the first clock signal line and the initial signal line and extends along the first direction.

[0010] The width of the second power line is less than or equal to the width of the first power line, and / or the width of the initial signal line is less than the width of the first power line, and / or the width of the first clock signal line is less than the width of the first power line and greater than the width of the initial signal line, and / or the width of the second clock signal line is less than the width of the first power line and greater than the width of the initial signal line.

[0011] In some possible implementations, the driving circuit includes: a plurality of shift registers arranged along a first direction, each shift register including: first to tenth transistors, first to third capacitors, a signal input terminal, a signal output terminal, a first clock signal terminal, a second clock signal terminal, a first power supply terminal, and a second power supply terminal;

[0012] The gate electrode of the first transistor is electrically connected to the first clock signal terminal, the source electrode of the first transistor is electrically connected to the signal input terminal, and the drain electrode of the first transistor is electrically connected to the first node;

[0013] A gate electrode of the second transistor is electrically connected to the first node, a source electrode of the second transistor is electrically connected to the first clock signal terminal, and a second electrode of the second transistor is electrically connected to the second node;

[0014] The gate electrode of the third transistor is electrically connected to the first clock signal terminal, the source electrode of the third transistor is electrically connected to the second power supply terminal, and the second electrode of the third transistor is electrically connected to the second node;

[0015] The gate electrode of the fourth transistor is electrically connected to the second clock signal terminal, the source electrode of the fourth transistor is electrically connected to the first node, and the drain electrode of the fourth transistor is electrically connected to the source electrode of the fifth transistor;

[0016] The gate electrode of the fifth transistor is electrically connected to the second node, and the drain electrode of the fifth transistor is electrically connected to the first power supply terminal;

[0017] The gate electrode of the sixth transistor is electrically connected to the second node, the source electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the drain electrode of the sixth transistor is electrically connected to the third node;

[0018] The gate electrode of the seventh transistor is electrically connected to the second clock signal terminal, the source electrode of the seventh transistor is electrically connected to the third node, and the drain electrode of the seventh transistor is electrically connected to the fourth node;

[0019] The gate electrode of the eighth transistor is electrically connected to the first node, the source electrode of the eighth transistor is electrically connected to the first power supply terminal, and the drain electrode of the eighth transistor is electrically connected to the fourth node;

[0020] The gate electrode of the ninth transistor is electrically connected to the fourth node, the source electrode of the ninth transistor is electrically connected to the signal output terminal, and the drain electrode of the ninth transistor is electrically connected to the first power supply terminal;

[0021] The gate electrode of the tenth transistor is electrically connected to the first node, the source electrode of the tenth transistor is electrically connected to the second power supply terminal, and the drain electrode of the tenth transistor is electrically connected to the signal output terminal;

[0022] The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the third node;

[0023] The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the second clock signal terminal;

[0024] The first plate of the third capacitor is electrically connected to the fourth node, and the second plate of the third capacitor is electrically connected to the first power supply terminal.

[0025] In some possible implementations, the first plate of the first capacitor is located on a side of the second plate of the first capacitor close to the base substrate, and an orthographic projection of the first plate of the first capacitor on the base substrate covers an orthographic projection of the second plate of the first capacitor on the base substrate;

[0026] The first electrode plate of the second capacitor is located on a side of the second electrode plate of the second capacitor close to the base substrate, and the orthographic projection of the first electrode plate of the second capacitor on the base substrate covers the orthographic projection of the second electrode plate of the second capacitor on the base substrate;

[0027] The first electrode plate of the third capacitor is located on a side of the second electrode plate of the third capacitor close to the base substrate, and the orthographic projection of the first electrode plate of the third capacitor on the base substrate covers the orthographic projection of the second electrode plate of the third capacitor on the base substrate;

[0028] The area of the overlapping portion between the first plate of the first capacitor and the first power line is positively correlated with the area of the first plate of the first capacitor, and the area of the overlapping portion between the first plate of the third capacitor and the first power line is positively correlated with the area of the first plate of the third capacitor;

[0029] An area of an overlapping portion between the first plate of the first capacitor and the first power line is smaller than an area of an overlapping portion between the first plate of the third capacitor and the first power line.

[0030] In some possible implementations, multiple shift registers in the driving circuit are cascaded, the signal input end of the first-stage shift register is electrically connected to the initial signal line, the signal output end of the i-1-stage shift register is electrically connected to the signal input end of the i-stage shift register, the first power supply ends of all shift registers are electrically connected to the first power supply line, the second power supply ends of the shift registers are electrically connected to the second power supply line, the first clock signal end of the odd-stage shift register is electrically connected to the first clock signal line, the second clock signal end of the odd-stage shift register is electrically connected to the second clock signal line, the first clock signal end of the even-stage shift register is electrically connected to the second clock signal line, and the second clock signal end of the even-stage shift register is electrically connected to the first clock signal line, wherein i is a positive integer greater than or equal to 2.

[0031] In some possible implementations, the display substrate further includes: sub-pixels arranged in an array and located in the display area and disposed on the base substrate;

[0032] The signal output end of the i-th stage shift register is electrically connected to the sub-pixels in the 2i-1th row and the sub-pixels in the 2i-th row.

[0033] In some possible implementations, each shift register includes: connecting electrodes and output signal lines arranged in different layers;

[0034] The output signal line is electrically connected to the signal output terminal of the shift register at this stage, and the orthographic projection of the connecting electrode on the base substrate at least partially overlaps with the orthographic projection of the output signal line on the base substrate;

[0035] The connecting electrodes are electrically connected to the signal output end of the shift register at the current stage and the signal input end of the shift register at the next stage respectively.

[0036] In some possible implementations, the display substrate includes: a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, and a third metal layer sequentially stacked on the base substrate;

[0037] The semiconductor layer includes: an active layer of multiple transistors; the first metal layer includes: gate electrodes of multiple transistors, a first plate of a first capacitor, a first plate of a second capacitor, and a first plate of a third capacitor; the second metal layer includes: a second plate of the first capacitor, a second plate of the second capacitor, a second plate of the third capacitor, and an output signal line; the third metal layer includes: source electrodes of multiple transistors, drain electrodes of multiple transistors, a first power line, a second power line, a first clock signal line, a second clock signal line, an initial signal line, and a connection electrode;

[0038] The resistance of the third metal layer is smaller than the resistance of the first metal layer, and smaller than the resistance of the second metal layer.

[0039] In some possible implementations, in each shift register, the active layers of all transistors include: a channel region and a source connection portion and a drain connection portion located on both sides of the channel region, the source electrode of the transistor is electrically connected to the source connection portion, and the drain electrode of the transistor is electrically connected to the drain connection portion;

[0040] The drain connection portion of the active layer of the fourth transistor is reused as a drain electrode, the source connection portion of the active layer of the fifth transistor is reused as a source electrode, and the drain connection portion of the active layer of the fourth transistor is electrically connected to the source connection portion of the active layer of the fifth transistor.

[0041] In some possible implementations, in each shift register, the gate electrode of the second transistor, the gate electrode of the tenth transistor, the gate electrode of the eighth transistor, and the first plate of the second capacitor are an integrally formed structure; the gate electrode of the fifth transistor, the gate electrode of the sixth transistor, and the first plate of the first capacitor are an integrally formed structure; and the gate electrode of the ninth transistor and the first plate of the third capacitor are an integrally formed structure.

[0042] The drain electrode of the first transistor and the source electrode of the fourth transistor are an integrated structure, the drain electrode of the second transistor and the drain electrode of the third transistor are an integrated structure, the source electrode of the third transistor, the source electrode of the tenth transistor and the second power line are an integrated structure, the drain electrode of the sixth transistor and the source electrode of the seventh transistor are an integrated structure, the drain electrode of the seventh transistor and the drain electrode of the eighth transistor are an integrated structure, the source electrode of the eighth transistor, the drain electrode of the ninth transistor, the drain electrode of the fifth transistor and the first power line are an integrated structure.

[0043] In some possible implementations, the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are located on a side of the first capacitor away from the third capacitor, and on a side of the second capacitor close to the first power line; the sixth transistor is located on a side of the first capacitor close to the second power line, and on a side of the second capacitor close to the third capacitor; the seventh transistor and the eighth transistor are located between the first capacitor and the third capacitor; and the ninth transistor and the tenth transistor are located on a side of the second capacitor close to the second power line.

[0044] In some possible implementations, in each shift register, active layers of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the ninth transistor, and the tenth transistor extend along a first direction, an active layer of the eighth transistor extends along a second direction, and a source electrode and a drain electrode of the sixth transistor are arranged along the first direction;

[0045] The first direction and the second direction intersect.

[0046] In some possible implementations, a distance between the first power line and an edge of the first capacitor close to the second power line is smaller than a distance between the first power line and a source electrode of the sixth transistor.

[0047] In some possible implementations, the output signal line in each shift register includes: a first connection portion, a second connection portion, a third connection portion, and a fourth connection portion that are integrally formed;

[0048] An orthographic projection of the first connecting portion on the substrate at least partially overlaps with an orthographic projection of the source electrode of the ninth transistor on the substrate, and at least partially overlaps with an orthographic projection of the drain electrode of the tenth transistor on the substrate, and the first connecting portion extends along a first direction;

[0049] The second connection portion, the third connection portion, and the fourth connection portion extend along the second direction, the second connection portion and the third connection portion are located on a side of the first connection portion away from the first power line, and the fourth connection portion is located on a side of the first connection portion close to the first power line;

[0050] The second connection portion is electrically connected to the sub-pixel in the 2i-1th row, the third connection portion is electrically connected to the sub-pixel in the 2ith row; the fourth connection portion is electrically connected to the signal input terminal of the next stage shift register;

[0051] The orthographic projection of the connecting electrode on the base substrate at least partially overlaps with the orthographic projection of the fourth connecting portion on the base substrate, and the fourth connecting portion is electrically connected to the signal input terminal of the next stage shift register through the connecting electrode.

[0052] In some possible implementations, for each shift register, the display substrate further includes: first to tenth via holes penetrating the first insulating layer, the second insulating layer, and the third insulating layer;

[0053] The first via hole exposes the active layer of the first transistor, the second via hole exposes the active layer of the second transistor, the third via hole exposes the active layer of the third transistor, the fourth via hole exposes the active layer of the fourth transistor, the fifth via hole exposes the active layer of the fifth transistor, the sixth via hole exposes the active layer of the sixth transistor, the seventh via hole exposes the active layer of the seventh transistor, the eighth via hole exposes the active layer of the eighth transistor, the ninth via hole exposes the active layer of the ninth transistor, and the tenth via hole exposes the active layer of the tenth transistor;

[0054] The source electrode and the drain electrode of the first transistor are electrically connected to the active layer of the first transistor through the first via, the source electrode and the drain electrode of the second transistor are electrically connected to the active layer of the second transistor through the second via, the source electrode and the drain electrode of the third transistor are electrically connected to the active layer of the third transistor through the third via, the source electrode and the drain electrode of the fourth transistor are electrically connected to the active layer of the fourth transistor through the fourth via, the source electrode and the drain electrode of the fifth transistor are electrically connected to the active layer of the fifth transistor through the fifth via, the source electrode and the drain electrode of the sixth transistor are electrically connected to the active layer of the sixth transistor through the sixth via, the source electrode and the drain electrode of the seventh transistor are electrically connected to the active layer of the seventh transistor through the seventh via, the source electrode and the drain electrode of the eighth transistor are electrically connected to the active layer of the eighth transistor through the eighth via, the source electrode and the drain electrode of the ninth transistor are electrically connected to the active layer of the ninth transistor through the ninth via, and the source electrode and the drain electrode of the tenth transistor are electrically connected to the active layer of the tenth transistor through the tenth via.

[0055] In some possible implementations, the display substrate further includes: eleventh to sixteenth via holes penetrating the second insulating layer and the third insulating layer;

[0056] The eleventh via hole exposes the gate electrode of the first transistor, the twelfth via hole exposes the gate electrode of the second transistor, the thirteenth via hole exposes the gate electrode of the fourth transistor, the fourteenth via hole exposes the gate electrode of the fifth transistor, and the sixteenth via hole exposes the first plate of the third capacitor;

[0057] The source electrode of the second transistor is electrically connected to the gate electrode of the first transistor through the eleventh via, the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor through the twelfth via, the source electrode of the sixth transistor is electrically connected to the gate electrode of the fourth transistor through the thirteenth via, the drain electrode of the third transistor is electrically connected to the gate electrode of the fifth transistor through the fourteenth via, and the drain electrode of the seventh transistor is electrically connected to the first plate of the third capacitor through the sixteenth via.

[0058] In some possible implementations, the display substrate further includes: seventeenth to twenty-first via holes disposed on the third insulating layer;

[0059] The seventeenth via hole exposes the second plate of the first capacitor, the eighteenth via hole exposes the second plate of the second capacitor, the nineteenth via hole exposes the second plate of the third capacitor, the twentieth via hole exposes the first connection portion of the signal output terminal, and the twenty-first via hole exposes the fourth connection portion of the signal output terminal;

[0060] The drain electrode of the sixth transistor is electrically connected to the second plate of the first capacitor through a seventeenth via hole, the source electrode of the sixth transistor is electrically connected to the second plate of the second capacitor through an eighteenth via hole, the drain electrode of the ninth transistor is electrically connected to the second plate of the third capacitor through a nineteenth via hole, the source electrode of the ninth transistor and the drain electrode of the tenth transistor are electrically connected to the signal output terminal through a twentieth via hole, and the connecting electrode is electrically connected to the signal output terminal through a twenty-first via hole.

[0061] There are multiple seventeenth via holes, and the multiple seventeenth via holes are arranged along the first direction;

[0062] There are multiple eighteenth via holes, and the multiple eighteenth via holes are arranged along the first direction;

[0063] There are multiple nineteenth via holes, and the multiple nineteenth via holes are arranged along the second direction;

[0064] There is a plurality of the twentieth via holes, and the plurality of twentieth via holes are arranged along the first direction.

[0065] In a second aspect, the present disclosure further provides a display device comprising the above-mentioned display substrate.

[0066] In a third aspect, the present disclosure further provides a method for manufacturing a display substrate, configured to manufacture the above-mentioned display substrate, the method comprising:

[0067] providing a substrate;

[0068] A driving circuit and a first power line are formed on a base substrate in a non-display area; the driving circuit includes: a first capacitor, a second capacitor, and a third capacitor; the first capacitor and the third capacitor are arranged along a first direction, the second capacitor and the third capacitor are respectively located on either side of the first capacitor, the second capacitor is located on a side of the first capacitor closer to the display area, and one plate of the third capacitor is electrically connected to the first power line;

[0069] The first power line extends along a first direction, and an orthographic projection of the first capacitor on the base substrate at least partially overlaps with an orthographic projection of the first power line on the base substrate.

[0070] In some possible implementations, the driving circuit includes: a plurality of shift registers, each shift register includes: a plurality of transistors and first to third capacitors, and forming the driving circuit and the first power line in the non-display area on the substrate includes:

[0071] A semiconductor layer is formed on a substrate, wherein the semiconductor layer includes: an active layer of a plurality of transistors;

[0072] A first insulating layer and a first metal layer are sequentially formed on the semiconductor layer, wherein the first metal layer includes: gate electrodes of a plurality of transistors, a first plate of a first capacitor, a first plate of a second capacitor, and a first plate of a third capacitor;

[0073] forming a second insulating layer and a second metal layer in sequence on the first metal layer, wherein the second metal layer includes: a second plate of the first capacitor, a second plate of the second capacitor, a second plate of the third capacitor, and an output signal line;

[0074] A third insulating layer and a third metal layer are sequentially formed on the second metal layer, wherein the third metal layer includes: source electrodes of multiple transistors, drain electrodes of multiple transistors, a first power line, a second power line, a first clock signal line, a second clock signal line, an initial signal line and a connecting electrode.

[0075] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0077] Figure 1 A schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0078] Figure 2 A top view of a driving circuit provided in an embodiment of the present disclosure;

[0079] Figure 3 A schematic diagram of the cross-sectional structure of a display substrate;

[0080] Figure 4 A schematic structural diagram of a driving circuit provided by an exemplary embodiment;

[0081] Figure 5 An equivalent circuit diagram of a shift register provided for an exemplary embodiment;

[0082] Figure 6 An operating timing diagram of a shift register provided for an exemplary embodiment;

[0083] Figure 7 A timing diagram of a driving circuit provided for an exemplary embodiment;

[0084] Figure 8 A schematic structural diagram of a semiconductor layer provided for an exemplary embodiment;

[0085] Figure 9 A schematic structural diagram of a first metal layer provided as an exemplary embodiment;

[0086] Figure 10 A schematic structural diagram of a second metal layer provided as an exemplary embodiment;

[0087] Figure 11 A schematic structural diagram of a third metal layer provided as an exemplary embodiment;

[0088] Figure 12 This is a schematic diagram showing a substrate after a semiconductor layer pattern is formed in the present disclosure;

[0089] Figure 13 This is a schematic diagram showing a substrate after a first metal layer pattern is formed in the present disclosure;

[0090] Figure 14 This is a schematic diagram showing a substrate after a second metal layer pattern is formed in the present disclosure;

[0091] Figure 15 This is a schematic diagram showing a substrate after a third insulating layer pattern is formed in the present disclosure;

[0092] Figure 16 This is a schematic diagram showing a substrate in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0093] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0094] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values shown in the drawings.

[0095] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0096] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0097] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0098] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0099] Those skilled in the art will understand that the transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. The thin film transistor may be an oxide semiconductor thin film transistor, a low-temperature polycrystalline silicon thin film transistor, an amorphous silicon thin film transistor, or a microcrystalline silicon thin film transistor. The thin film transistor may specifically be a bottom-gate thin film transistor or a top-gate thin film transistor, as long as the switching function can be achieved. Since the source and drain of the transistor used here are symmetrical, their source and drain can be interchanged.

[0100] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0101] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0102] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0103] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0104] Figure 1 A schematic structural diagram of a display substrate provided in an embodiment of the present disclosure is shown. Figure 2 FIG. 1 is a top view of a driving circuit provided in an embodiment of the present disclosure. Figure 1 and Figure 2As shown, the display substrate provided by the embodiment of the present disclosure may include: a display area and a non-display area located around the display area. The display substrate may include: a base substrate and a driving circuit 10 and a first power line VGH provided on the base substrate and located in the non-display area. The driving circuit may include at least: a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first capacitor C1 and the third capacitor C3 are arranged along a first direction, the second capacitor C2 and the third capacitor C3 are respectively located on both sides of the first capacitor C1, the second capacitor C2 is located on the side of the first capacitor C1 close to the display area, and one plate of the third capacitor C3 is electrically connected to the first power line VGH.

[0105] The first power line VGH extends along a first direction. The orthographic projection of the first capacitor C1 on the base substrate at least partially overlaps with the orthographic projection of the first power line VGH on the base substrate.

[0106] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0107] In an exemplary embodiment, the first power line VGH may be located on a side of the second capacitor C2 away from the display area.

[0108] In an exemplary embodiment, the first power line VGH may continuously provide a high-level DC signal.

[0109] In one exemplary embodiment, the width of the first power line VGH may be approximately 6 micrometers to 12 micrometers.

[0110] In an exemplary embodiment, the number of the first capacitor C1 , the second capacitor C2 , and the third capacitor C3 is multiple, which is determined according to actual requirements of the display substrate and is not limited in this disclosure.

[0111] In an exemplary embodiment, the display area can be provided with a plurality of regularly arranged sub-pixels PA, a plurality of first signal lines extending along the second direction (for example, including scan lines G, control signal lines and light-emitting control lines E), and a plurality of second signal lines extending along the first direction (for example, including data lines DL).

[0112] In an exemplary embodiment, at least one first signal line may extend along the second direction, and multiple first signal lines may be arranged sequentially along the first direction. At least one second signal line may extend along the first direction, and multiple second signal lines may be arranged sequentially along the second direction.

[0113] In an exemplary embodiment, at least one sub-pixel PA among the plurality of sub-pixels may include: a light emitting element and a pixel driving circuit for driving the light emitting element to emit light. The pixel driving circuit may adopt a 3T1C, 5T1C or 7T1C design.

[0114] In an exemplary embodiment, the intersection of the first direction and the second direction means that the angle between the first direction and the second direction is approximately 70 degrees to 90 degrees. The first direction and the second direction may be located in the same plane. For example, the first direction may be a row direction parallel to the direction in which the scan lines extend; and the second direction may be a column direction parallel to the direction in which the data lines extend.

[0115] In some exemplary embodiments, Figure 1 As shown, m rows of scan lines G1 to Gm are arranged along the first direction, m rows of light-emitting signal lines E1 to Em are arranged along the first direction, and n columns of data lines DL1 to DLn are arranged along the second direction. The scan lines and data lines are insulated from each other, and the light-emitting signal lines and data lines are insulated from each other. Where m and n are both integers greater than 0. Subpixels PA can be distributed at the intersections of m rows of scan lines and n columns of data lines. Multiple subpixels PA are arranged in a matrix pattern.

[0116] In an exemplary embodiment, the sub-pixel may be any one of a red (R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel, and a white sub-pixel, which is not limited in the present disclosure. When the display panel includes a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, the three sub-pixels may be arranged horizontally in parallel, vertically in parallel, or in a herringbone pattern. When the display panel includes a red (R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel, and a white sub-pixel, the four sub-pixels may be arranged horizontally in parallel, vertically in parallel, or in an array, which is not limited in the present disclosure.

[0117] Figure 3 This is a schematic diagram of the cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels on the display substrate. In a plane perpendicular to the display substrate, the display substrate may include a driver circuit layer 102 disposed on a base 101, a light-emitting device 103 disposed on the side of the driver circuit layer 102 facing away from the base substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting device 103 facing away from the base substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, but this disclosure does not limit this.

[0118] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Figure 3Each sub-pixel in the diagram only shows one transistor 101 and one storage capacitor 101A as an example. The light-emitting device 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of corresponding color under the drive of the anode 301 and the cathode 304. The encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting device 103.

[0119] In an exemplary embodiment, the organic light-emitting layer 303 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0120] In an exemplary embodiment, the light emitting structure may be an organic light emitting diode (OLED), which includes a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode).

[0121] In an exemplary embodiment, the driving circuit may be a scanning driving circuit and / or a light-emitting driving circuit, which is not limited in the present disclosure.

[0122] In some exemplary embodiments, Figure 1As shown, the non-display area may also be provided with a timing controller 20 and a data driving circuit (not shown in the figure). Among them, the driving circuit 20 may be arranged on the left or right side of the display area, and the timing controller and the data driving circuit may be arranged on the upper or lower side of the display area. Among them, the data driving circuit may provide data signals to multiple columns of sub-pixels through multiple data lines DL. The scanning driving circuit may provide scanning signals to multiple rows of sub-pixels through multiple scanning lines G. In addition to the scanning signal, the scanning driving circuit may also generate at least one control signal synchronized with the scanning signal on a row basis, and provide it to multiple rows of sub-pixels in the display area. The light-emitting driving circuit may provide light-emitting control signals to multiple rows of sub-pixels through multiple light-emitting control lines E.

[0123] In an exemplary embodiment, the timing controller can provide grayscale values and control signals suitable for the specifications of the data driving circuit to the data driving circuit, can provide clock signals, scanning start signals, etc. suitable for the specifications of the scanning driving circuit to the scanning driving circuit, and can provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driving circuit to the light-emitting driving circuit.

[0124] In one exemplary embodiment, the data driving circuit may generate a data voltage to be supplied to the data line using a grayscale value and a control signal received from the timing controller.

[0125] In an exemplary embodiment, the scan driving circuit may generate a scan signal to be provided to the scan line by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan driving circuit may sequentially provide the scan signal to the scan line. For example, the scan driving circuit may be composed of a plurality of cascaded shift registers, and each shift register may sequentially generate the scan signal under the control of a clock signal.

[0126] In one exemplary embodiment, the light driving circuit may generate a light signal to be provided to the light signal line by receiving a clock signal from a timing controller, transmitting a stop signal, etc. For example, the light driving circuit may sequentially provide the light signal to the light signal line. For example, the light driving circuit may be composed of a plurality of cascaded shift registers, and each shift register may sequentially generate the light signal under the control of a clock signal.

[0127] In an exemplary embodiment, compared to a display substrate in which the first capacitor C1 and the third capacitor C3 do not overlap with the first power line VGH, the display substrate provided by the present disclosure has a length of the first capacitor C1 that is longer along the first direction and a length that is narrower along the second direction, and a length of the third capacitor C3 that is longer along the first direction and a length that is narrower along the second direction.

[0128] The display substrate provided by the embodiment of the present disclosure includes: a base substrate and a driving circuit and a first power line arranged on the base substrate and located in a non-display area, the driving circuit including at least: a first capacitor, a second capacitor, and a third capacitor; the first capacitor and the third capacitor are arranged along a first direction, the second capacitor and the third capacitor are respectively located on either side of the first capacitor, the second capacitor is located on a side of the first capacitor close to the display area, and one electrode plate of the third capacitor is electrically connected to the first power line; the first power line is located on a side of the second capacitor away from the display area and extends along the first direction, the orthographic projection of the first capacitor on the base substrate at least partially overlaps with the orthographic projection of the first power line on the base substrate, and the orthographic projection of the third capacitor on the base substrate at least partially overlaps with the orthographic projection of the first power line on the base substrate. The embodiment of the present disclosure reduces the area occupied by the driving circuit and the width of the non-display area in the display substrate by at least partially overlapping the orthographic projection of the first capacitor on the base substrate and the orthographic projection of the first power line on the base substrate, thereby achieving a narrow frame of the display product.

[0129] like Figure 2 As shown, in an exemplary embodiment, the orthographic projection of the third capacitor C3 on the base substrate at least partially overlaps with the orthographic projection of the first power line VGH on the base substrate. This at least partially overlaps the orthographic projection of the third capacitor on the base substrate with the orthographic projection of the first power line on the base substrate, thereby reducing the area occupied by the drive circuit and the width of the non-display area of the display substrate, thereby achieving a narrow bezel for the display product.

[0130] like Figure 2 As shown, in an exemplary embodiment, the display substrate may further include: a second power line VGL, an initial signal line ESTV, a first clock signal line ECK, and a second clock signal line ECB, which are disposed on the base substrate and located in the non-display area.

[0131] In one exemplary embodiment, the second power line VGL is located on a side of the drive circuit 10 close to the display area and extends along a first direction. The initial signal line ESTV is located on a side of the first power line VGH away from the display area and extends along the first direction. The first clock signal line ECK is located between the first power line VGH and the initial signal line ESTV and extends along the first direction. The second clock signal line ECB is located between the first clock signal line ECK and the initial signal line ESTV and extends along the first direction.

[0132] In an exemplary embodiment, the second power line VGL can continuously provide a low-level DC signal. The initial signal line ESTV can provide a pulse signal. The first clock signal line ECK can provide a periodic pulse signal, and the second clock signal line ECB can provide a periodic pulse signal. The first clock signal line ECK and the second clock signal line ECB can not be active level signals at the same time.

[0133] In an exemplary embodiment, the width of the second power line VGL may be less than or equal to the width of the first power line VGH, and / or the width of the initial signal line ESTV may be less than the width of the first power line VGH, and / or the width of the first clock signal line ECK may be less than the width of the first power line VGH and may be greater than the width of the initial signal line ESTV, and / or the width of the second clock signal line ECB may be less than the width of the first power line VGH and may be greater than the width of the initial signal line ESTV.

[0134] In this embodiment, the width of the second power line VGL is smaller than or equal to the width of the first power line VGH, so as to reduce the width of the non-display area of the display substrate and achieve a narrow frame.

[0135] In one exemplary embodiment, the width of the second power line VGL may be approximately 6 micrometers to 12 micrometers.

[0136] In this embodiment, the width of the initial signal line ESTV is smaller than the width of the first power line VGH, so that the width of the non-display area of the display substrate can be reduced to achieve a narrow frame.

[0137] In one exemplary embodiment, the width of the initial signal line ESTV may be approximately 5 micrometers to 10 micrometers.

[0138] In this embodiment, the width of the first clock signal line ECK is smaller than the width of the first power line VGH, so that the width of the non-display area of the display substrate can be reduced to achieve a narrow frame.

[0139] In an exemplary embodiment, the width of the first clock signal line ECK may be approximately 6 micrometers to 20 micrometers.

[0140] In this embodiment, the width of the second clock signal line ECB is smaller than the width of the first power line VGH, so that the width of the non-display area of the display substrate can be reduced to achieve a narrow frame.

[0141] In an exemplary embodiment, the width of the second clock signal line ECB may be approximately 6 micrometers to 20 micrometers.

[0142] Figure 4 A schematic structural diagram of a driving circuit provided by an exemplary embodiment is shown. Figure 5 An equivalent circuit diagram of a shift register provided for an exemplary embodiment. Figure 4 The following description is made by taking the light-emitting driving circuit as an example. Figure 4 and Figure 5As shown, the driving circuit includes: a plurality of shift registers EOA(1) to EOA(k) arranged along a first direction, k=m / 2. Each shift register EOA includes: a first transistor T1 to a tenth transistor T10, a first capacitor C1 to a third capacitor C3, a signal input terminal EIN, a signal output terminal EOUT, a first clock signal terminal CK1, a second clock signal terminal CK2, a first power supply terminal VL1, and a second power supply terminal VL2.

[0143] The gate electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the source electrode of the first transistor T1 is electrically connected to the signal input terminal EIN, and the drain electrode of the first transistor T1 is electrically connected to the first node N1. The gate electrode of the second transistor T2 is electrically connected to the first node N1, the source electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the second node N2. The gate electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the source electrode of the third transistor T3 is electrically connected to the second power supply terminal VL2, and the second electrode of the third transistor T3 is electrically connected to the second node N2. The gate electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CK2, the source electrode of the fourth transistor T4 is electrically connected to the first node N1, and the drain electrode of the fourth transistor T4 is electrically connected to the source electrode of the fifth transistor. The gate electrode of the fifth transistor T5 is electrically connected to the second node N2, and the drain electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VL1. The gate electrode of the sixth transistor T6 is electrically connected to the second node N2, the source electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CK2, and the drain electrode of the sixth transistor T6 is electrically connected to the third node N3. The gate electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, the source electrode of the seventh transistor T7 is electrically connected to the third node N3, and the drain electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The gate electrode of the eighth transistor T8 is electrically connected to the first node N1, the source electrode of the eighth transistor T8 is electrically connected to the first power supply terminal VL1, and the drain electrode of the eighth transistor T8 is electrically connected to the fourth node N4. The gate electrode of the ninth transistor T9 is electrically connected to the fourth node N4, the source electrode of the ninth transistor T9 is electrically connected to the signal output terminal EOUT, and the drain electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VL1. The gate electrode of the tenth transistor T10 is electrically connected to the first node N1, the source electrode of the tenth transistor T10 is electrically connected to the second power supply terminal VL2, and the drain electrode of the tenth transistor T10 is electrically connected to the signal output terminal EOUT. A first plate C11 of the first capacitor C1 is electrically connected to the second node N2, and a second plate C12 of the first capacitor C1 is electrically connected to the third node N3. A first plate C21 of the second capacitor C2 is electrically connected to the first node N1, and a second plate C22 of the second capacitor C2 is electrically connected to the second clock signal terminal CK2. A first plate C31 of the third capacitor C3 is electrically connected to the fourth node N4, and a second plate C32 of the third capacitor C3 is electrically connected to the first power supply terminal VL1.

[0144] In an exemplary embodiment, the first clock signal terminal CK1 and the second clock signal terminal CK2 are respectively switched continuously between high and low levels.

[0145] In an exemplary embodiment, the first power supply terminal VL1 continuously outputs a high-level signal, and the second power supply terminal VL2 continuously outputs a low-level signal.

[0146] In an exemplary embodiment, the first capacitor C1 is configured to maintain the potential of the second node N2, the second capacitor C2 is configured to maintain the potential of the first node N1, and the third capacitor C3 is configured to maintain the potential of the fourth node N4.

[0147] In an exemplary embodiment, the first transistor T1 to the tenth transistor T10 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (Low Temperature Poly-Silicon, referred to as LTPS), and the active layer of the oxide thin film transistor adopts oxide (Oxide). Low-temperature polysilicon thin film transistors have advantages such as high mobility and fast charging, and oxide thin film transistors have advantages such as low leakage current. In an exemplary embodiment, low-temperature polysilicon thin film transistors and oxide thin film transistors can be integrated on a display substrate to form a low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, referred to as LTPO) display substrate, which can take advantage of the advantages of both, achieve high resolution (Pixel Per Inch, referred to as PPI), low-frequency driving, reduce power consumption, and improve display quality.

[0148] In one exemplary embodiment, the first transistor T1 to the tenth transistor T10 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In one exemplary embodiment, the first transistor T1 to the tenth transistor T10 may include a P-type transistor and an N-type transistor.

[0149] When a low level is applied to the gate electrode of a P-type transistor, the P-type transistor is turned on. When a high level is applied to the gate electrode of the P-type transistor, the P-type transistor is turned off. Accordingly, a clock signal is a signal that periodically switches between two different levels, and these two levels are usually used to turn the transistor on and off, respectively. Therefore, the higher of the two is usually called a high level, and the lower is called a low level.

[0150] In one exemplary embodiment, the first transistor T1 may be a P-type transistor. When the signal at the first clock signal terminal CK1 is at a low level, the first transistor T1 is in an on-state, and when the signal at the first clock signal terminal CK1 is at a high level, the first transistor T1 is in an off-state. The second transistor T2 may be a P-type transistor. When the signal at the first node N1 is at a low level, the second transistor T2 is in an on-state, and when the signal at the first node N1 is at a high level, the second transistor T2 is in an off-state. The third transistor T3 may be a P-type transistor. When the signal at the first clock signal terminal CK1 is at a low level, the third transistor T3 is in an on-state, and when the signal at the first clock signal terminal CK1 is at a high level, the third transistor T3 is in an off-state. The fourth transistor T4 may be a P-type transistor. When the signal at the second clock signal terminal CK2 is at a low level, the fourth transistor T4 is in an on-state, and when the signal at the second clock signal terminal CK2 is at a high level, the fourth transistor T4 is in an off-state. The fifth transistor T5 may be a P-type transistor. When the signal at the second node N2 is at a low level, the fifth transistor T5 is in a conducting state, and when the signal at the second node N2 is at a high level, the fifth transistor T5 is in a cut-off state. The sixth transistor T6 may be a P-type transistor. When the signal at the second node N2 is at a low level, the sixth transistor T6 is in a conducting state, and when the signal at the second node N2 is at a high level, the sixth transistor T6 is in a cut-off state. The seventh transistor T7 may be a P-type transistor. When the signal at the second clock signal terminal CK2 is at a low level, the seventh transistor T7 is in a conducting state, and when the signal at the second clock signal terminal CK2 is at a high level, the seventh transistor T7 is in a cut-off state. The eighth transistor T8 may be a P-type transistor. When the signal at the first node N1 is at a low level, the eighth transistor T8 is in a conducting state, and when the signal at the first node N1 is at a high level, the eighth transistor T8 is in a cut-off state. The ninth transistor T9 may be a P-type transistor. When the signal at the fourth node N4 is at a low level, the ninth transistor T9 is in a conducting state. When the signal at the fourth node N4 is at a high level, the ninth transistor T9 is in a cut-off state. The tenth transistor T10 may be a P-type transistor. When the signal at the first node N1 is at a low level, the tenth transistor T10 is in a conducting state. When the signal at the first node N1 is at a high level, the tenth transistor T10 is in a cut-off state.

[0151] In an exemplary embodiment, the first plate C11 of the first capacitor C1 is located on a side of the second plate C12 of the first capacitor C1 close to the base substrate, and the orthographic projection of the first plate C11 of the first capacitor C1 on the base substrate covers the orthographic projection of the second plate C12 of the first capacitor C1 on the base substrate.

[0152] In an exemplary embodiment, the area of the first capacitor C1 may be approximately 200 square micrometers to 300 square micrometers.

[0153] In an exemplary embodiment, the first plate C21 of the second capacitor C2 is located on a side of the second plate C22 of the second capacitor C2 close to the base substrate, and the orthographic projection of the first plate C21 of the second capacitor C2 on the base substrate covers the orthographic projection of the second plate C22 of the second capacitor C2 on the base substrate.

[0154] In an exemplary embodiment, the area of the second capacitor C2 may be approximately 300 square micrometers to 500 square micrometers.

[0155] In an exemplary embodiment, the first plate C31 of the third capacitor C3 is located on a side of the second plate C32 of the third capacitor C3 close to the substrate, and the orthographic projection of the first plate C31 of the third capacitor C3 on the substrate covers the orthographic projection of the second plate C32 of the third capacitor C3 on the substrate.

[0156] In an exemplary embodiment, the area of the third capacitor C3 may be approximately 300 square micrometers to 500 square micrometers.

[0157] In an exemplary embodiment, Figure 2 As shown, the area of the overlapping portion between the orthographic projection of the first plate of the first capacitor C1 on the substrate and the orthographic projection of the first power line VGH on the substrate is positively correlated with the area of the first plate of the first capacitor, that is, the larger the area of the first capacitor is, the larger the area of the overlapping region between the orthographic projection of the first capacitor C1 on the substrate and the orthographic projection of the first power line VGH on the substrate is.

[0158] In an exemplary embodiment, Figure 2 As shown, the area of the overlapping portion between the orthographic projection of the first plate of the third capacitor C3 on the substrate and the orthographic projection of the first power line VGH on the substrate is positively correlated with the area of the first plate of the first capacitor, that is, the larger the area of the first capacitor is, the larger the area of the overlapping region between the orthographic projection of the third capacitor C3 on the substrate and the orthographic projection of the first power line VGH on the substrate is.

[0159] In an exemplary embodiment, the width of the overlapping portion between the first plate of the third capacitor C3 and the first power line VGH may be equal to the width of the first power line VGH.

[0160] In an exemplary embodiment, an area of an overlapping portion between the first plate of the first capacitor and the first power line may be smaller than an area of an overlapping portion between the first plate of the third capacitor and the first power line.

[0161] The following describes a shift register provided by an exemplary embodiment through the working process of the shift register.

[0162] Taking the shift register provided by an exemplary embodiment in which the transistors T1 to T10 are all P-type transistors as an example, Figure 6 The working timing diagram of the shift register provided by an exemplary embodiment is shown in FIG. Figure 5 and Figure 6 As shown, a shift register involved in an exemplary embodiment includes: 10 switching transistors (T1 to T10), 3 capacitor units (C1 to C3), 3 signal input terminals (CK1, CK2 and EIN), 1 signal output terminal (EOUT), and 2 power supply terminals (V1 and V2).

[0163] An exemplary embodiment provides a shift register whose operation process may include: a first stage P1 to an eighth stage P8.

[0164] In the first phase P1, the signal at the signal input terminal EIN is a high-level signal, the signal at the first clock signal terminal CK1 is a low-level signal, the first transistor T1 and the third transistor T3 are turned on, and the signal at the signal input terminal EIN is written to the first node N1. At this time, the first node N1 is at a high level. The signal at the second power supply terminal VL2 is written to the second node N2. At this time, the second node N2 is at a low level. Since the first node N1 is at a high level, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off. The signal at the second clock signal terminal CK2 is a high-level signal, and the fourth transistor T4 and the seventh transistor T7 are turned off. Since the second node N2 is at a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, and the signal at the second clock signal terminal CK2 is written to the third node N3. Since the voltage across the capacitor does not change suddenly, the fourth node N4 maintains the high level of the previous frame, the ninth transistor T9 is turned off, and the output signal of the signal output terminal EOUT maintains the low level of the previous frame.

[0165] In the second phase P2, the signal of the signal input terminal EIN and the signal of the first clock signal terminal CK1 are high-level signals, the first transistor T1 and the third transistor T3 are turned off, the first node N1 maintains a high level, the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned off, the second node N2 maintains a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, and since the signal of the second clock signal terminal CK2 is a low-level signal, the fourth transistor T4 and the seventh transistor T7 are turned on, the signal of the second clock signal terminal CK2 is written into the third node N3, the third node N3 changes from a high level to a low level, the signal of the third node N3 is written into the fourth node N4, the fourth node N4 is a low level, the ninth transistor T9 is turned on, and the signal output terminal EOUT outputs a high-level signal of the first power supply terminal VL1.

[0166] In the third stage P3, the signal of the signal input terminal EIN is a high-level signal, the signal of the first clock signal terminal CK1 is a low-level signal, the first transistor T1 and the third transistor T3 are turned on, the first node N1 is at a high level, the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned off, the second node N2 maintains a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, the signal of the second clock signal terminal CK2 is written into the third node N3, and since the signal of the second clock signal terminal CK2 is a high-level signal, the third node N3 changes from the low level in the previous stage to a high level, the fourth transistor T4 and the seventh transistor T7 are turned off, the fourth node N4 maintains a low level, the ninth transistor T9 is turned on, and the signal output terminal EOUT outputs a high-level signal of the first power supply terminal VL1.

[0167] In the fourth stage P4, the signal of the signal input terminal EIN is a low-level signal, the signal of the first clock signal terminal CK1 is a high-level signal, the first transistor T1 and the third transistor T3 are turned off, the first node N1 maintains a high level, the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned off, the second node N2 maintains a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, the signal of the second clock signal terminal CK2 is written into the third node N3, and since the signal of the second clock signal terminal CK2 is a low-level signal, the third node N3 changes from the high level of the previous stage to the low level, the fourth transistor T4 and the seventh transistor T7 are turned on, the signal of the third node N3 is written into the fourth node N4, the fourth node N4 maintains a low level, the ninth transistor T9 is turned on, and the signal output terminal EOUT outputs a high-level signal of the first power supply terminal VL1.

[0168] In the fifth stage P5, the signal at the signal input terminal EIN and the signal at the first clock signal terminal CK1 are low-level signals, the first transistor T1 and the third transistor T3 are turned on, the first node N1 changes from a high level to a low level, the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned on, the second node N2 remains at a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, the signal at the second clock signal terminal CK2 is written into the third node N3, and since the signal at the second clock signal terminal CK2 is a high-level signal, the third node N3 changes from a low level in the previous stage to a high level, the fourth transistor T4 and the seventh transistor T7 are turned off, and since the eighth transistor T8 is turned on, the high-level signal at the first power supply terminal VL1 is written into the fourth node N4, and the fourth node N4 becomes a high level, the ninth transistor T9 is turned off, and since the tenth transistor T10 is turned on, the low-level signal at the second power supply terminal VL2 is written into the signal output terminal EOUT, and the signal output terminal EOUT outputs a low-level signal.

[0169] In the sixth stage P6, the signal of the signal input terminal EIN is a low-level signal, the signal of the first clock signal terminal CK1 is a high-level signal, the first transistor T1 and the third transistor T3 are turned off, the first node N1 maintains a low level, the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned on, the signal of the first clock signal terminal CK1 is written to the second node N2, the second node N2 changes from a low level to a high level, the fifth transistor T5 and the sixth transistor T6 are turned off, the third node N3 maintains a high level, since the signal of the second clock signal terminal CK2 is a low-level signal, the fourth transistor T4 and the seventh transistor T7 are turned on, the signal of the third node N3 is written to the fourth node N4, the fourth node N4 maintains a high level, the ninth transistor T9 is turned off, and since the tenth transistor T10 is turned on, the low-level signal of the second power supply terminal VL2 is written to the signal output terminal EOUT, and the signal output terminal EOUT outputs a low-level signal.

[0170] In the seventh stage P7, the signal of the signal input terminal EIN is a low-level signal, the signal of the first clock signal terminal CK1 is a low-level signal, the first transistor T1 and the third transistor T3 are turned on, the first node N1 maintains a low level, the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned on, the signal of the first clock signal terminal CK1 is written to the second node N2, the second node N2 is a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, the signal of the second clock signal terminal CK2 is written to the third node N3, since the signal of the second clock signal terminal CK2 is a high-level signal, the fourth transistor T4 and the seventh transistor T7 are turned off, the fourth node N4 maintains a high level, the ninth transistor T9 is turned off, and since the tenth transistor T10 is turned on, the low-level signal of the second power supply terminal VL2 is written to the signal output terminal EOUT, and the signal output terminal EOUT outputs a low-level signal.

[0171] In the eighth stage P8, the signal of the signal input terminal EIN is a low-level signal, the signal of the first clock signal terminal CK1 is a high-level signal, the first transistor T1 and the third transistor T3 are turned off, the first node N1 maintains a low level, the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned on, the signal of the first clock signal terminal CK1 is written to the second node N2, the second node N2 changes from a low level to a high level, the fifth transistor T5 and the sixth transistor T6 are turned off, the third node N3 maintains a high level, since the signal of the second clock signal terminal CK2 is a low-level signal, the fourth transistor T4 and the seventh transistor T7 are turned on, the signal of the third node N3 is written to the fourth node N4, the fourth node N4 maintains a high level, the ninth transistor T9 is turned off, and since the tenth transistor T10 is turned on, the low-level signal of the second power supply terminal VL2 is written to the signal output terminal EOUT, and the signal output terminal EOUT outputs a low-level signal.

[0172] After the first stage P7, the seventh stage P7 and the eighth stage P8 are repeated, the eighth transistor T8 is continuously turned on, the ninth transistor T9 is turned off, the first transistor T1 periodically charges the second capacitor C2, the first node N1 maintains a low level, the tenth transistor T10 is continuously turned on, and the signal output terminal EOUT outputs a low-level signal until a pulse from the signal input terminal EIN of the next frame enters.

[0173] In an exemplary embodiment, Figure 7 A timing diagram of a driving circuit provided by an exemplary embodiment. Figure 7 In the figure, EOUTi is the signal output terminal of the i-th stage shift register EOA(i), and EINi is the signal input terminal of the i-th stage shift register EOA(i). Figure 4 and Figure 7 As shown, the signal input terminal of the first-stage shift register EOA (1) is electrically connected to the initial signal line ESTV, the signal output terminal of the i-1-th stage shift register is electrically connected to the signal input terminal of the i-th stage shift register, the first power supply terminal VL1 of all the shift registers is electrically connected to the first power supply line VGH, the second power supply terminal VL2 of all the shift registers is electrically connected to the second power supply line VGL, the first clock signal terminal CK1 of the odd-numbered stage shift register is electrically connected to the first clock signal line ECK, the second clock signal terminal CK2 of the odd-numbered stage shift register is electrically connected to the second clock signal line ECB, the first clock signal terminal CK1 of the even-numbered stage shift register is electrically connected to the second clock signal line ECB, and the second clock signal terminal CK2 of the even-numbered stage shift register is electrically connected to the first clock signal line ECK, wherein i is a positive integer greater than or equal to 2.

[0174] In an exemplary embodiment, the signal output end of the i-th stage shift register is electrically connected to the sub-pixels in the 2i-1th row and the sub-pixels in the 2i-th row. The signal output end of the i-th stage shift register is electrically connected to the sub-pixels in the 2i-1th row through the 2i-1th row light-emitting signal line, and is electrically connected to the sub-pixels in the 2i-th row through the 2i-th row light-emitting signal line.

[0175] In an exemplary embodiment, Figure 2 As shown, each shift register includes a connecting electrode 40. The orthographic projection of the connecting electrode 40 on the substrate at least partially overlaps with the orthographic projection of the signal output terminal EOUT on the substrate. The connecting electrode is electrically connected to the signal output terminal of the current stage shift register and the signal input terminal of the next stage shift register.

[0176] In an exemplary embodiment, Figure 2As shown, the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 and the fifth transistor T5 are located on a side of the first capacitor C1 away from the third capacitor C3 , and on a side of the second capacitor C2 close to the first power line VGH.

[0177] In an exemplary embodiment, Figure 2 As shown, the sixth transistor T6 is located on the side of the first capacitor C1 close to the second power line VGL, and on the side of the second capacitor C2 close to the third capacitor C3. The sixth transistor T6 is located on the side of the first capacitor C1 close to the second power line VGL, and on the side of the second capacitor C2 close to the third capacitor C3. This can reduce the space occupied by the sixth transistor in the first direction, thereby achieving a narrow bezel for the display product.

[0178] In an exemplary embodiment, Figure 2 As shown, the seventh transistor T7 and the eighth transistor T8 are located between the first capacitor C1 and the third capacitor C3.

[0179] In an exemplary embodiment, Figure 2 As shown, the ninth transistor T9 and the tenth transistor T10 are located on a side of the second capacitor C2 close to the second power line VGL.

[0180] Figure 8 A schematic structural diagram of a semiconductor layer provided by an exemplary embodiment is shown. Figure 9 A schematic structural diagram of a first metal layer is provided for an exemplary embodiment. Figure 10 A schematic structural diagram of a second metal layer provided by an exemplary embodiment is shown. Figure 11 FIG. 1 is a schematic structural diagram of a third metal layer provided by an exemplary embodiment. Figures 8 to 11 As shown, an exemplary embodiment provides a display substrate comprising: a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer sequentially stacked on the base substrate.

[0181] In an exemplary embodiment, Figure 8 As shown, the semiconductor layer includes: active layers of multiple transistors. The active layers of the multiple transistors include: an active layer 11 of a first transistor T1, an active layer 21 of a second transistor T2, an active layer 31 of a third transistor T3, an active layer 41 of a fourth transistor T4, an active layer 51 of a fifth transistor T5, an active layer 61 of a sixth transistor T6, an active layer 71 of a seventh transistor T7, an active layer 81 of an eighth transistor T8, an active layer 91 of a ninth transistor T9, and an active layer 110 of a tenth transistor T10.

[0182] In an exemplary embodiment, Figure 8As shown, the active layer 11 of the first transistor T1, the active layer 21 of the second transistor T2, the active layer 31 of the third transistor T3, the active layer 41 of the fourth transistor T4, the active layer 51 of the fifth transistor T5, the active layer 61 of the sixth transistor T6, the active layer 71 of the seventh transistor T7, the active layer 91 of the ninth transistor T9, and the active layer 110 of the tenth transistor T10 all extend along a first direction. The active layer 81 of the eighth transistor T8 extends along a second direction. The first direction and the second direction intersect.

[0183] In an exemplary embodiment, Figure 8 As shown, in each shift register, the active layers of all transistors include: a channel region and source and drain connections located on both sides of the channel region. The source electrode of the transistor is electrically connected to the source connection, and the drain electrode of the transistor is electrically connected to the drain connection. Among them, the drain connection of the active layer of the fourth transistor is reused as the drain electrode, and the source connection of the active layer of the fifth transistor is reused as the source electrode. The drain connection of the active layer of the fourth transistor is electrically connected to the source connection of the active layer of the fifth transistor.

[0184] In some exemplary embodiments, the channel region may not be doped with impurities and may have semiconductor properties. The source and drain connections may be on either side of the channel region and may be doped with impurities and thus have conductivity. The impurities may vary depending on the type of transistor (e.g., N-type or P-type).

[0185] In an exemplary embodiment, Figure 9 As shown, the first metal layer includes: gate electrodes of multiple transistors, a first plate C11 of a first capacitor C1, a first plate C21 of a second capacitor C2, and a first plate C31 of a third capacitor C3. The gate electrodes of the multiple transistors include: a gate electrode 12 of a first transistor T1, a gate electrode 22 of a second transistor T2, a gate electrode 32 of a third transistor T3, a gate electrode 42 of a fourth transistor T4, a gate electrode 52 of a fifth transistor T5, a gate electrode 62 of a sixth transistor T6, a gate electrode 72 of a seventh transistor T7, a gate electrode 82 of an eighth transistor T8, a gate electrode 92 of a ninth transistor T9, and a gate electrode 120 of a tenth transistor T10.

[0186] In an exemplary embodiment, when the first clock signal terminal in the shift register is electrically connected to the first clock signal line and the second clock signal terminal is electrically connected to the second clock signal line, the orthographic projection of the gate electrode 12 of the first transistor T1 on the substrate at least partially overlaps with the orthographic projection of the first clock signal line on the substrate. The orthographic projection of the gate electrode 42 of the fourth transistor T4 on the substrate at least partially overlaps with the orthographic projection of the second clock signal line on the substrate, and the orthographic projection of the gate electrode 72 of the seventh transistor T7 on the substrate at least partially overlaps with the orthographic projection of the second clock signal line on the substrate. Alternatively, when the first clock signal terminal in the shift register is electrically connected to the second clock signal line and the second clock signal terminal is electrically connected to the first clock signal line, the orthographic projection of the gate electrode 12 of the first transistor T1 on the substrate at least partially overlaps with the orthographic projection of the second clock signal line on the substrate. The orthographic projection of the gate electrode 42 of the fourth transistor T4 on the substrate at least partially overlaps with the orthographic projection of the first clock signal line on the substrate. The orthographic projection of the gate electrode 72 of the seventh transistor T7 on the substrate at least partially overlaps with the orthographic projection of the first clock signal line on the substrate. Figure 2 The description is made by taking an example in which the first clock signal terminal in the shift register is electrically connected to the first clock signal line, and the second clock signal terminal is electrically connected to the second clock signal line.

[0187] In an exemplary embodiment, in each shift register, the gate electrode 22 of the second transistor T2, the gate electrode 120 of the tenth transistor T10, the gate electrode 82 of the eighth transistor T8 and the first plate C21 of the second capacitor C2 are an integrally formed structure.

[0188] In an exemplary embodiment, in each shift register, the gate electrode 52 of the fifth transistor T5 , the gate electrode 62 of the sixth transistor T6 , and the first electrode plate C11 of the first capacitor C1 are integrally formed.

[0189] In an exemplary embodiment, in each shift register, the gate electrode 92 of the ninth transistor T9 and the first electrode plate C31 of the third capacitor C3 are an integrally formed structure.

[0190] In an exemplary embodiment, Figure 9 As shown, the shape of the first plate C11 of the first capacitor can be square.

[0191] In an exemplary embodiment, Figure 9As shown, the shape of the first plate C21 of the second capacitor can be two squares superimposed, the first square and the second square are arranged along the first direction, the width of the second square is greater than the width of the first square, the length in the second direction is less than the length in the first direction, and the left edge of the second square is located on the side of the left edge in the first direction close to the gate electrode of the second transistor.

[0192] In an exemplary embodiment, Figure 9 As shown, the shape of the first electrode plate C31 of the third capacitor can be a square with a corner missing at the lower right corner.

[0193] In an exemplary embodiment, Figure 10 As shown, the second metal layer includes: a second plate C12 of the first capacitor C1, a second plate C22 of the second capacitor C2, a second plate C32 of the third capacitor C3 and an output signal line EL.

[0194] In an exemplary embodiment, Figure 9 As shown, the gate electrode 22 of the second transistor is in a “U”-shaped structure.

[0195] In an exemplary embodiment, the gate electrode 92 of the ninth transistor has a comb-like structure and includes a plurality of first branch segments 92A extending across the active layer 91 of the ninth transistor and a first connecting segment 92B connecting the plurality of first branch segments 92A.

[0196] In an exemplary embodiment, the gate electrode 120 of the tenth transistor has a comb-like structure and includes a plurality of second branch segments 120A spanning the active layer 110 of the tenth transistor and a second connecting segment 120B connecting the plurality of first branch segments 120A.

[0197] like Figure 10 As shown, the output signal line EL in each shift register may include: an integrally formed first connection portion OUT1, a second connection portion OUT2, a third connection portion OUT3, and a fourth connection portion OUT4. The orthographic projection of the first connection portion OUT1 on the substrate at least partially overlaps with the orthographic projection of the source electrode of the ninth transistor on the substrate, and at least partially overlaps with the orthographic projection of the drain electrode of the tenth transistor on the substrate. The first connection portion OUT1 extends along a first direction. The second connection portion OUT2, the third connection portion OUT3, and the fourth connection portion OUT4 extend along a second direction. The second and third connection portions OUT2 and OUT3 are located on a side of the first connection portion OUT1 away from the first power line VGH, and the fourth connection portion OUT4 is located on a side of the first connection portion OUT1 closer to the first power line VGH.

[0198] In an exemplary embodiment, the first connection portion OUT1 , the second connection portion OUT2 , and the third connection portion OUT3 may be linear structures, and the fourth connection portion OUT4 may be a zigzag structure.

[0199] In an exemplary embodiment, the second connection portion OUT2 is electrically connected to the sub-pixels in the 2i-1th row, the third connection portion OUT3 is electrically connected to the sub-pixels in the 2ith row, and the fourth connection portion OUT4 is electrically connected to the signal input terminal of the next stage shift register.

[0200] In an exemplary embodiment, the orthographic projection of the connecting electrode on the base substrate at least partially overlaps with the orthographic projection of the fourth connecting portion on the base substrate, and the fourth connecting portion is electrically connected to the signal input terminal of the next stage shift register through the connecting electrode.

[0201] In an exemplary embodiment, Figure 10 As shown, the second plate C12 of the first capacitor may be in a square shape, and a side of the second plate C12 of the first capacitor close to the output signal line EL may be in a stepped shape.

[0202] In an exemplary embodiment, Figure 10 As shown, the shape of the second plate C22 of the second capacitor may be an L-shape with the lower right corner missing, and a protrusion is provided on the edge of the second plate C22 of the second capacitor away from the output signal line EL.

[0203] In an exemplary embodiment, Figure 10 As shown, the shape of the second plate C32 of the third capacitor may be a square with a missing lower right corner, and the edge of the second plate C32 of the third capacitor close to the second capacitor may be stepped.

[0204] In an exemplary embodiment, Figure 11As shown, the third metal layer includes: source electrodes of multiple transistors, drain electrodes of multiple transistors, a signal input terminal EIN, a first clock signal terminal CK1, a second clock signal terminal CK2, a first power line VGH, a second power line VGL, a first clock signal line ECK, a second clock signal line ECB, an initial signal line ESTV, and a connection electrode 40. The source electrodes of the multiple transistors include: a source electrode 13 of the first transistor T1, a source electrode 23 of the second transistor T2, a source electrode 33 of the third transistor T3, a source electrode 43 of the fourth transistor T4, a source electrode 63 of the sixth transistor T6, a source electrode 73 of the seventh transistor T7, a source electrode 83 of the eighth transistor T8, a source electrode 93 of the ninth transistor T9, and a source electrode 130 of the tenth transistor T10. The drain electrodes of the plurality of transistors include: a drain electrode 14 of a first transistor T1, a drain electrode 24 of a second transistor T2, a drain electrode 34 of a third transistor T3, a drain electrode 54 of a fifth transistor T5, a drain electrode 64 of a sixth transistor T6, a drain electrode 74 of a seventh transistor T7, a drain electrode 84 of an eighth transistor T8, a drain electrode 94 of a ninth transistor T9, and a drain electrode 140 of a tenth transistor T10.

[0205] In an exemplary embodiment, the drain electrode 14 of the first transistor T1 and the source electrode 43 of the fourth transistor T4 may be an integrally formed structure.

[0206] In an exemplary embodiment, the drain electrode 34 of the second transistor T2 and the drain electrode 34 of the third transistor T3 may be an integrally formed structure.

[0207] In an exemplary embodiment, the source electrode 33 of the third transistor T3 , the source electrode 130 of the tenth transistor T10 , and the second power line VGL may be an integrally formed structure.

[0208] In an exemplary embodiment, the drain electrode 64 of the sixth transistor T6 and the source electrode 73 of the seventh transistor T7 may be an integrally formed structure.

[0209] In an exemplary embodiment, the drain electrode 74 of the seventh transistor T7 and the drain electrode 84 of the eighth transistor T8 may be an integrally formed structure.

[0210] In an exemplary embodiment, the source electrode 83 of the eighth transistor T8 , the drain electrode 94 of the ninth transistor T9 , the drain electrode 54 of the fifth transistor T5 , and the first power line VGH are integrally formed.

[0211] In an exemplary embodiment, the semiconductor layer may be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0212] In one exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer. The first insulating layer is referred to as a first gate insulating layer, the second insulating layer is referred to as a second gate insulating layer, and the third insulating layer is referred to as an interlayer insulating layer.

[0213] In an exemplary embodiment, the first metal layer, the second metal layer and the third metal layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0214] In one exemplary embodiment, the resistance of the third metal layer may be lower than the resistance of the first metal layer.

[0215] In one exemplary embodiment, the resistance of the third metal layer may be lower than the resistance of the second metal layer.

[0216] In an exemplary embodiment, the materials of the first metal layer and the second metal layer may include molybdenum.

[0217] In an exemplary embodiment, the third metal layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0218] In an exemplary embodiment, Figure 2 、 Figure 8 and Figure 11 As shown, in each shift register, the active layer 61 of the sixth transistor T6 extends along the first direction, and the source electrode 63 and the drain electrode 64 of the sixth transistor T6 are arranged along the first direction. The active layer 61 of the sixth transistor T6 extends along the first direction, and the source electrode 63 and the drain electrode 64 of the sixth transistor T6 are arranged along the first direction, so that the sixth transistors T6 are placed in a column direction, which can reduce the width of the driving circuit and achieve a narrow frame of the display product.

[0219] In an exemplary embodiment, Figure 2As shown, a distance L1 between the first power line VGH and an edge of the first capacitor C1 near the second power line VGL can be smaller than a distance L2 between the first power line VGH and the source electrode of the sixth transistor T6. When the distance between the first power line VGH and an edge of the first capacitor C1 near the second power line VGL is smaller than the distance between the first power line VGH and the source electrode of the sixth transistor T6, the width of the driving circuit can be reduced, thereby achieving a narrow bezel for the display product.

[0220] In an exemplary embodiment, for each shift register, the display substrate may further include: first to tenth via holes penetrating the first insulating layer, the second insulating layer, and the third insulating layer.

[0221] In an exemplary embodiment, the first via exposes the active layer of the first transistor, the second via exposes the active layer of the second transistor, the third via exposes the active layer of the third transistor, the fourth via exposes the active layer of the fourth transistor, the fifth via exposes the active layer of the fifth transistor, the sixth via exposes the active layer of the sixth transistor, the seventh via exposes the active layer of the seventh transistor, the eighth via exposes the active layer of the eighth transistor, the ninth via exposes the active layer of the ninth transistor, and the tenth via exposes the active layer of the tenth transistor. Among them, the source electrode and the drain electrode of the first transistor are electrically connected to the active layer of the first transistor through the first via, the source electrode and the drain electrode of the second transistor are electrically connected to the active layer of the second transistor through the second via, the source electrode and the drain electrode of the third transistor are electrically connected to the active layer of the third transistor through the third via, the source electrode and the drain electrode of the fourth transistor are electrically connected to the active layer of the fourth transistor through the fourth via, the source electrode and the drain electrode of the fifth transistor are electrically connected to the active layer of the fifth transistor through the fifth via, the source electrode and the drain electrode of the sixth transistor are electrically connected to the active layer of the sixth transistor through the sixth via, the source electrode and the drain electrode of the seventh transistor are electrically connected to the active layer of the seventh transistor through the seventh via, the source electrode and the drain electrode of the eighth transistor are electrically connected to the active layer of the eighth transistor through the eighth via, the source electrode and the drain electrode of the ninth transistor are electrically connected to the active layer of the ninth transistor through the ninth via, and the source electrode and the drain electrode of the tenth transistor are electrically connected to the active layer of the tenth transistor through the tenth via.

[0222] In an exemplary embodiment, for each shift register, the display substrate may further include: eleventh to sixteenth via holes penetrating the second insulating layer and the third insulating layer.

[0223] In an exemplary embodiment, the eleventh via exposes the gate electrode of the first transistor, the twelfth via exposes the gate electrode of the second transistor, the thirteenth via exposes the gate electrode of the fourth transistor, the fourteenth via exposes the gate electrode of the fifth transistor, the fifteenth via exposes the gate electrode of the seventh transistor, and the sixteenth via exposes the first plate of the third capacitor. The source electrode of the second transistor is electrically connected to the gate electrode of the first transistor through the eleventh via, the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor through the twelfth via, the source electrode of the sixth transistor is electrically connected to the gate electrode of the fourth transistor through the thirteenth via, the drain electrode of the third transistor is electrically connected to the gate electrode of the fifth transistor through the fourteenth via, and the drain electrode of the seventh transistor is electrically connected to the first plate of the third capacitor through the sixteenth via.

[0224] In an exemplary embodiment, there are two eleventh via holes, one eleventh via hole exposes an end of the gate electrode of the first transistor away from the display area, and the other eleventh via hole exposes an end of the gate electrode of the first transistor close to the display area.

[0225] In an exemplary embodiment, there are two thirteenth via holes, one thirteenth via hole exposes an end of the gate electrode of the fourth transistor away from the display area, and the other eleventh via hole exposes an end of the gate electrode of the fourth transistor close to the display area.

[0226] In an exemplary embodiment, the fifteenth via hole exposes an end of the gate electrode of the seventh transistor away from the display area.

[0227] In an exemplary embodiment, for each shift register, the display substrate may further include: seventeenth to twenty-first via holes disposed on the third insulating layer.

[0228] In an exemplary embodiment, the seventeenth via exposes the second plate of the first capacitor, the eighteenth via exposes the second plate of the second capacitor, the nineteenth via exposes the second plate of the third capacitor, the twentieth via exposes the first connection portion of the signal output terminal, and the twenty-first via exposes the fourth connection portion of the signal output terminal. The drain electrode of the sixth transistor is electrically connected to the second plate of the first capacitor via the seventeenth via, the source electrode of the sixth transistor is electrically connected to the second plate of the second capacitor via the eighteenth via, the drain electrode of the ninth transistor is electrically connected to the second plate of the third capacitor via the nineteenth via, the source electrode of the ninth transistor and the drain electrode of the tenth transistor are electrically connected to the signal output terminal via the twentieth via, and the connection electrode is electrically connected to the signal output terminal via the twenty-first via.

[0229] In an exemplary embodiment, there may be a plurality of seventeenth via holes, and the plurality of seventeenth via holes may be arranged along the first direction. For example, there may be two seventeenth via holes.

[0230] In an exemplary embodiment, the number of the eighteenth via holes may be multiple, and the multiple eighteenth via holes are arranged along the first direction. Exemplarily, the number of the seventeenth via holes may be two.

[0231] In an exemplary embodiment, there may be multiple nineteenth vias, and the multiple nineteenth vias may be arranged along the second direction. For example, the number of the nineteenth vias may be four. Arranging the multiple nineteenth vias along the second direction can reduce the width of the driving circuit and achieve a narrow frame.

[0232] In an exemplary embodiment, the number of the twentieth via holes may be plural. For example, the number of the nineteenth via holes may be twelve. The plurality of twentieth via holes are arranged along the first direction.

[0233] The structure of the display substrate is explained below by taking the example of the preparation process of the display substrate as an example. The "patterning process" mentioned in the present disclosure includes deposition of a film layer, coating of a photoresist, mask exposure, development, etching and stripping of the photoresist. Deposition can be carried out by any one or more of sputtering, evaporation and chemical vapor deposition, coating can be carried out by any one or more of spray coating and spin coating, and etching can be carried out by any one or more of dry etching and wet etching. A "thin film" refers to a layer of thin film made by a deposition or coating process on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process.

[0234] Figures 12 to 16 FIG1 is a schematic diagram of a process for preparing a display substrate provided by an exemplary embodiment. Figures 12 to 16 As shown, a manufacturing process of a display substrate provided by an exemplary embodiment may include:

[0235] (1) forming a semiconductor layer pattern on a substrate, including: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern. Figure 12 As shown, the semiconductor layer includes: an active layer 11 of a first transistor T1, an active layer 21 of a second transistor T2, an active layer 31 of a third transistor T3, an active layer 41 of a fourth transistor T4, an active layer 51 of a fifth transistor T5, an active layer 61 of a sixth transistor T6, an active layer 71 of a seventh transistor T7, an active layer 81 of an eighth transistor T8, an active layer 91 of a ninth transistor T9, and an active layer 110 of a tenth transistor T10, as shown in FIG. Figure 12As shown, Figure 12 This is a schematic diagram showing a substrate after a semiconductor layer pattern is formed in the present disclosure.

[0236] The active layer 11 of the first transistor T1, the active layer 21 of the second transistor T2, the active layer 31 of the third transistor T3, the active layer 41 of the fourth transistor T4, the active layer 51 of the fifth transistor T5, the active layer 61 of the sixth transistor T6, and the active layer 71 of the seventh transistor T7 extend along the first direction. The active layer 81 of the eighth transistor T8 extends along the second direction. The active layer 91 of the ninth transistor T9 and the active layer 110 of the tenth transistor T10 extend along the first direction and are integrally formed into a long, strip-shaped structure.

[0237] (2) forming a first metal layer pattern, comprising: depositing a first insulating film and a first metal film in sequence on a substrate on which the aforementioned pattern is formed, patterning the first insulating film and the first metal film through a patterning process to form a first insulating layer pattern and a first metal layer pattern located on the first insulating layer, wherein the first metal layer comprises: a first electrode C11 of a first capacitor C1, a first electrode C21 of a second capacitor C2, a first electrode C31 of a third capacitor C3, a gate electrode 12 of a first transistor T1, a gate electrode 22 of a second transistor T2, a gate electrode 32 of a third transistor T3, a gate electrode 42 of a fourth transistor T4, a gate electrode 52 of a fifth transistor T5, a gate electrode 62 of a sixth transistor T6, a gate electrode 72 of a seventh transistor T7, a gate electrode 82 of an eighth transistor T8, a gate electrode 92 of a ninth transistor T9, and a gate electrode 120 of a tenth transistor T10, as shown in FIG. Figure 13 As shown, Figure 13 This is a schematic diagram showing a substrate after a first metal layer pattern is formed in the present disclosure.

[0238] Each gate electrode is respectively arranged across the active layer of the corresponding transistor, that is, the extension direction of each gate electrode is perpendicular to the extension direction of the active layer of the corresponding transistor.

[0239] In an exemplary embodiment, the gate electrode 22 of the second transistor T2, the gate electrode 120 of the tenth transistor T10, the gate electrode 82 of the eighth transistor T8, and the first plate C21 of the second capacitor C2 are integrally formed. The gate electrode 52 of the fifth transistor T5, the gate electrode 62 of the sixth transistor T6, and the first plate C11 of the first capacitor C1 are integrally formed. The gate electrode 92 of the ninth transistor T9 and the first plate C31 of the third capacitor C3 are integrally formed.

[0240] In an exemplary embodiment, this process also includes a conductorization process. After forming the first metal layer pattern, the conductorization process utilizes the semiconductor layer in the areas blocked by the gate electrode 12 of the first transistor T1, the gate electrode 22 of the second transistor T2, the gate electrode 32 of the third transistor T3, the gate electrode 42 of the fourth transistor T4, the gate electrode 52 of the fifth transistor T5, the gate electrode 62 of the sixth transistor T6, the gate electrode 72 of the seventh transistor T7, the gate electrode 82 of the eighth transistor T8, the gate electrode 92 of the ninth transistor T9, and the gate electrode 120 of the tenth transistor T10 (i.e., the areas where the semiconductor layer overlaps with each gate electrode) as the channel regions of the transistors, and the semiconductor layer in the areas not blocked by the first metal layer is processed into a conductorization layer to form a conductorized source-drain connection portion.

[0241] (3) Forming a second metal layer pattern, including: depositing a second insulating film and a second metal film in sequence on the substrate formed with the aforementioned pattern, patterning the second insulating film and the second metal film through a patterning process to form a second insulating layer pattern and a second metal layer pattern located on the second insulating layer. The second metal layer includes: a second plate C12 of the first capacitor C1, a second plate C22 of the second capacitor C2, a second plate C32 of the third capacitor C3, and an output signal line EL, as shown in FIG. Figure 14 As shown, Figure 14 This is a schematic diagram showing a substrate after a second metal layer pattern is formed in the present disclosure.

[0242] (4) forming a third insulating layer pattern, comprising: depositing a third insulating film on the substrate having the aforementioned pattern, patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the aforementioned structure, wherein the third insulating layer is provided with a plurality of via hole patterns, the plurality of via hole patterns comprising: first via holes V1 to tenth via holes V10 penetrating the first insulating layer, the second insulating layer, and the third insulating layer, eleventh via holes V11 to sixteenth via holes V16 penetrating the second insulating layer and the third insulating layer, and seventeenth via holes V17 to twenty-first via holes V21 provided on the third insulating layer, as shown in FIG. Figure 15 As shown, Figure 15 This is a schematic diagram showing a substrate after a third insulating layer pattern is formed in the present disclosure.

[0243] In an exemplary embodiment, the first via V1 exposes the active layer 11 of the first transistor, the second via V2 exposes the active layer 21 of the second transistor, the third via V3 exposes the active layer 31 of the third transistor, the fourth via V4 exposes the active layer 41 of the fourth transistor, the fifth via V5 exposes the active layer 51 of the fifth transistor, the sixth via V6 exposes the active layer 61 of the sixth transistor, the seventh via exposes the active layer 71 of the seventh transistor, the eighth via V8 exposes the active layer 81 of the eighth transistor, the ninth via exposes the active layer 91 of the ninth transistor, and the tenth via V10 exposes the active layer 110 of the tenth transistor. The eleventh via hole V11 exposes the gate electrode 12 of the first transistor, the twelfth via hole V12 exposes the gate electrode 22 of the second transistor, the thirteenth via hole V13 exposes the gate electrode 42 of the fourth transistor, the fourteenth via hole V14 exposes the gate electrode 52 of the fifth transistor, the fifteenth via hole V15 exposes the gate electrode 72 of the seventh transistor, the sixteenth via hole V16 exposes the first plate C31 of the third capacitor, the seventeenth via hole V17 exposes the second plate C12 of the first capacitor, the eighteenth via hole V18 exposes the second plate C22 of the second capacitor, the nineteenth via hole V19 exposes the second plate C32 of the third capacitor, the twentieth via hole V20 exposes the first connection portion of the output signal line EL, and the twenty-first via hole V21 exposes the fourth connection portion of the output signal line EL.

[0244] (4) forming a third metal layer pattern, including: depositing a third metal film on the substrate on which the aforementioned pattern is formed, and patterning the third metal film through a patterning process to form a third metal layer pattern. The third metal layer includes: a first power line VGH, a second power line VGL, a first clock signal line ECK, a second clock signal line ECB, an initial signal line ESTV, a connection electrode 40, a source electrode 13 of the first transistor T1, a source electrode 23 of the second transistor T2, a source electrode 33 of the third transistor T3, a source electrode 43 of the fourth transistor T4, a source electrode 63 of the sixth transistor T6, a source electrode 73 of the seventh transistor T7, a source electrode 83 of the eighth transistor T8, a source electrode 93 of the ninth transistor T9, a source electrode 130 of the tenth transistor T10, a drain electrode 14 of the first transistor T1, a drain electrode 24 of the second transistor T2, a drain electrode 34 of the third transistor T3, a drain electrode 54 of the fifth transistor T5, a drain electrode 64 of the sixth transistor T6, a drain electrode 74 of the seventh transistor T7, a drain electrode 84 of the eighth transistor T8, a drain electrode 94 of the ninth transistor T9, and a drain electrode 140 of the tenth transistor T10, as shown in FIG. Figure 16 , Figure 16 This is a schematic diagram showing a substrate in an exemplary embodiment of the present disclosure.

[0245] In one exemplary embodiment, the drain electrode 14 of the first transistor T1 and the source electrode 43 of the fourth transistor T4 are integrally formed. The drain electrode 34 of the second transistor T2 and the drain electrode 34 of the third transistor T3 are integrally formed. The source electrode 33 of the third transistor T3, the source electrode 130 of the tenth transistor T10, and the second power line VGL are integrally formed. The drain electrode 64 of the sixth transistor T6 and the source electrode 73 of the seventh transistor T7 are integrally formed. The drain electrode 74 of the seventh transistor T7 and the drain electrode 84 of the eighth transistor T8 are integrally formed. The source electrode 83 of the eighth transistor T8, the drain electrode 94 of the ninth transistor T9, the drain electrode 54 of the fifth transistor T5, and the first power line VGH are integrally formed.

[0246] In one exemplary embodiment, the source electrode 13 and the drain electrode 14 of the first transistor are electrically connected to the active layer 11 of the first transistor through a first via V1. The source electrode 23 and the drain electrode 24 of the second transistor are electrically connected to the active layer 21 of the second transistor through a second via V2. The source electrode 33 and the drain electrode 34 of the third transistor are electrically connected to the active layer 31 of the third transistor through a third via V3. The source electrode 43 and the drain electrode 44 of the fourth transistor are electrically connected to the active layer 41 of the fourth transistor through a fourth via V4. The source electrode 53 and the drain electrode 54 of the fifth transistor are electrically connected to the active layer of the fifth transistor through a fifth via V5. The source electrode 63 and the drain electrode 64 of the sixth transistor are electrically connected to the active layer 61 of the sixth transistor through a sixth via V6. The source electrode 73 and the drain electrode 74 of the seventh transistor are electrically connected to the active layer 71 of the seventh transistor through a seventh via V7. The source electrode 83 and drain electrode 84 of the eighth transistor are electrically connected to the active layer 81 of the eighth transistor through an eighth via V8. The source electrode 93 and drain electrode 94 of the ninth transistor are electrically connected to the active layer of the ninth transistor through a ninth via V9. The source electrode 130 and drain electrode 140 of the tenth transistor are electrically connected to the active layer 110 of the tenth transistor through a tenth via V10. The first clock signal line ECK is electrically connected to the gate electrode 12 of the first transistor through an eleventh via V11. The source electrode 23 of the second transistor is electrically connected to the gate electrode 12 of the first transistor through the eleventh via V11. The drain electrode 14 of the first transistor is electrically connected to the gate electrode 22 of the second transistor through a twelfth via V12. The second clock signal line ECB is electrically connected to the gate electrode 42 of the fourth transistor through a thirteenth via V13. The source electrode 63 of the sixth transistor is electrically connected to the gate electrode 42 of the fourth transistor through a thirteenth via V13. The drain electrode 34 of the third transistor is electrically connected to the gate electrode 52 of the fifth transistor through a fourteenth via V14. The second clock signal line ECB is electrically connected to the gate electrode 72 of the seventh transistor through a fifteenth via V15. The drain electrode 74 of the seventh transistor is electrically connected to the first plate C31 of the third capacitor through a sixteenth via V16. The drain electrode 64 of the sixth transistor is electrically connected to the second plate C12 of the first capacitor through a seventeenth via V17. The source electrode 63 of the sixth transistor is electrically connected to the second plate C22 of the second capacitor through an eighteenth via V18. The drain electrode 94 of the ninth transistor is electrically connected to the second plate C32 of the third capacitor through a nineteenth via V19. The source electrode 93 of the ninth transistor and the drain electrode 140 of the tenth transistor are electrically connected to the first connection portion of the signal output terminal through a twentieth via V20. The connection electrode 40 is electrically connected to the fourth connection portion of the signal output terminal through a twenty-first via V21. Figure 16 The description is made by taking an example in which the first clock signal terminal of the shift register is electrically connected to the first clock signal line, and the second clock signal terminal of the shift register is electrically connected to the second clock signal line.

[0247] The cascade relationship of multiple shift registers in the driver circuit may vary for different display products. Regardless of the cascade relationship of the multiple shift registers, and regardless of how many rows of subpixels each shift register drives, as long as a large-area device such as this is modified, and the additional space created by this modification, the simple translation or stretching of small devices is within the scope of protection of this disclosure.

[0248] An embodiment of the present disclosure further provides a display device, which may include: a display substrate.

[0249] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0250] In an exemplary embodiment, the display device may be a liquid crystal display (LCD) or an organic light emitting diode (OLED) display device. The display device may be any product or component with a display function, such as an LCD panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system.

[0251] The present disclosure also provides a method for manufacturing a display substrate, which is configured to manufacture a display substrate. The method for manufacturing a display substrate provided by the present disclosure includes:

[0252] Step S1: providing a base substrate.

[0253] In an exemplary embodiment, the base substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0254] Step S2: forming a driving circuit and a first power line in the non-display area on the base substrate.

[0255] In one exemplary embodiment, the driving circuit includes: a first capacitor, a second capacitor, and a third capacitor; the first capacitor and the third capacitor are arranged along a first direction, the second capacitor and the third capacitor are located on either side of the first capacitor, the second capacitor is located on a side of the first capacitor closer to the display area, and one plate of the third capacitor is electrically connected to a first power line. The first power line extends along the first direction, and an orthographic projection of the first capacitor on the substrate at least partially overlaps with an orthographic projection of the first power line on the substrate.

[0256] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0257] In an exemplary embodiment, the driving circuit includes: a plurality of shift registers, each shift register includes: a plurality of transistors and first to third capacitors, and step S2 may include:

[0258] Step S21: forming a semiconductor layer on a substrate, wherein the semiconductor layer includes: an active layer of a plurality of transistors.

[0259] In an exemplary embodiment, the semiconductor layer may be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0260] Step S22: forming a first insulating layer and a first metal layer in sequence on the semiconductor layer, wherein the first metal layer includes: gate electrodes of multiple transistors, a first plate of a first capacitor, a first plate of a second capacitor, and a first plate of a third capacitor.

[0261] In an exemplary embodiment, the first metal layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the material of the first metal layer can include molybdenum.

[0262] Step S23: forming a second insulating layer and a second metal layer in sequence on the first metal layer, wherein the second metal layer includes: a second plate of the first capacitor, a second plate of the second capacitor, a second plate of the third capacitor, and a signal output terminal.

[0263] In an exemplary embodiment, the second metal layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplary materials for the second metal layer can include molybdenum.

[0264] Step S24: forming a third insulating layer and a third metal layer in sequence on the second metal layer, wherein the third metal layer includes: source electrodes of multiple transistors, drain electrodes of multiple transistors, a first power line, a second power line, a first clock signal line, a second clock signal line, an initial signal line, and a connection electrode.

[0265] In an exemplary embodiment, the third metal layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the third metal layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0266] In one exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer. The first insulating layer is referred to as a first gate insulating layer, the second insulating layer is referred to as a second gate insulating layer, and the third insulating layer is referred to as an interlayer insulating layer.

[0267] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0268] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0269] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, characterized in that: include: a display area and a non-display area, the display area being provided with a plurality of regularly arranged sub-pixels, the display substrate comprising: a base substrate, and a driving circuit and a first power line disposed on the base substrate and located in the non-display area, the driving circuit comprising at least: a first capacitor, a second capacitor, and a third capacitor; the first capacitor and the third capacitor being arranged along a first direction, the second capacitor and the third capacitor being respectively located on either side of the first capacitor, the second capacitor being located on a side of the first capacitor close to the display area, and one plate of the third capacitor being electrically connected to the first power line; The first power line extends along a first direction, and an orthographic projection of the first capacitor on the substrate at least partially overlaps with an orthographic projection of the first power line on the substrate; The driving circuit includes: a plurality of shift registers arranged along a first direction, each shift register includes: a first capacitor to a third capacitor, a first node and a second clock signal terminal, the first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the second clock signal terminal.

2. The display substrate according to claim 1, wherein: The orthographic projection of the third capacitor on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate.

3. The display substrate according to claim 1 or 2, wherein: The display substrate further includes: a second power supply line, an initial signal line, a first clock signal line, and a second clock signal line, which are arranged on the base substrate and located in the non-display area; The second power line is located on a side of the driving circuit close to the display area and extends along the first direction. The initial signal line is located on a side of the first power line away from the display area and extends along the first direction. The first clock signal line is located between the first power line and the initial signal line and extends along the first direction. The second clock signal line is located between the first clock signal line and the initial signal line and extends along the first direction. The width of the second power line is less than or equal to the width of the first power line, and / or the width of the initial signal line is less than the width of the first power line, and / or the width of the first clock signal line is less than the width of the first power line and greater than the width of the initial signal line, and / or the width of the second clock signal line is less than the width of the first power line and greater than the width of the initial signal line.

4. The display substrate according to claim 3, wherein: Each shift register further includes: a first transistor to a tenth transistor, a signal input terminal, a signal output terminal, a first clock signal terminal, a first power supply terminal and a second power supply terminal; The gate electrode of the first transistor is electrically connected to the first clock signal terminal, the source electrode of the first transistor is electrically connected to the signal input terminal, and the drain electrode of the first transistor is electrically connected to the first node; A gate electrode of the second transistor is electrically connected to the first node, a source electrode of the second transistor is electrically connected to the first clock signal terminal, and a second electrode of the second transistor is electrically connected to the second node; The gate electrode of the third transistor is electrically connected to the first clock signal terminal, the source electrode of the third transistor is electrically connected to the second power supply terminal, and the second electrode of the third transistor is electrically connected to the second node; The gate electrode of the fourth transistor is electrically connected to the second clock signal terminal, the source electrode of the fourth transistor is electrically connected to the first node, and the drain electrode of the fourth transistor is electrically connected to the source electrode of the fifth transistor; The gate electrode of the fifth transistor is electrically connected to the second node, and the drain electrode of the fifth transistor is electrically connected to the first power supply terminal; The gate electrode of the sixth transistor is electrically connected to the second node, the source electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the drain electrode of the sixth transistor is electrically connected to the third node; The gate electrode of the seventh transistor is electrically connected to the second clock signal terminal, the source electrode of the seventh transistor is electrically connected to the third node, and the drain electrode of the seventh transistor is electrically connected to the fourth node; The gate electrode of the eighth transistor is electrically connected to the first node, the source electrode of the eighth transistor is electrically connected to the first power supply terminal, and the drain electrode of the eighth transistor is electrically connected to the fourth node; The gate electrode of the ninth transistor is electrically connected to the fourth node, the source electrode of the ninth transistor is electrically connected to the signal output terminal, and the drain electrode of the ninth transistor is electrically connected to the first power supply terminal; The gate electrode of the tenth transistor is electrically connected to the first node, the source electrode of the tenth transistor is electrically connected to the second power supply terminal, and the drain electrode of the tenth transistor is electrically connected to the signal output terminal; The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the third node; The first plate of the third capacitor is electrically connected to the fourth node, and the second plate of the third capacitor is electrically connected to the first power supply terminal.

5. The display substrate according to claim 4, wherein: The first electrode plate of the first capacitor is located on a side of the second electrode plate of the first capacitor close to the base substrate, and the orthographic projection of the first electrode plate of the first capacitor on the base substrate covers the orthographic projection of the second electrode plate of the first capacitor on the base substrate; The first electrode plate of the second capacitor is located on a side of the second electrode plate of the second capacitor close to the base substrate, and the orthographic projection of the first electrode plate of the second capacitor on the base substrate covers the orthographic projection of the second electrode plate of the second capacitor on the base substrate; The first electrode plate of the third capacitor is located on a side of the second electrode plate of the third capacitor close to the base substrate, and the orthographic projection of the first electrode plate of the third capacitor on the base substrate covers the orthographic projection of the second electrode plate of the third capacitor on the base substrate; The area of an overlapping portion between the orthographic projection of the first plate of the first capacitor on the substrate and the orthographic projection of the first power line on the substrate is positively correlated with the area of the first plate of the first capacitor, and the area of an overlapping portion between the orthographic projection of the first plate of the third capacitor on the substrate and the orthographic projection of the first power line on the substrate is positively correlated with the area of the first plate of the third capacitor. An area of an overlapping portion between the first plate of the first capacitor and the first power line is smaller than an area of an overlapping portion between the first plate of the third capacitor and the first power line.

6. The display substrate according to claim 4, wherein: The multiple shift registers in the driving circuit are cascaded, the signal input end of the first-stage shift register is electrically connected to the initial signal line, the signal output end of the i-1-stage shift register is electrically connected to the signal input end of the i-stage shift register, the first power supply ends of all the shift registers are electrically connected to the first power supply line, the second power supply ends of the shift registers are electrically connected to the second power supply line, the first clock signal end of the odd-stage shift register is electrically connected to the first clock signal line, the second clock signal end of the odd-stage shift register is electrically connected to the second clock signal line, the first clock signal end of the even-stage shift register is electrically connected to the second clock signal line, and the second clock signal end of the even-stage shift register is electrically connected to the first clock signal line, wherein i is a positive integer greater than or equal to 2.

7. The display substrate according to claim 6, wherein: The display substrate further includes: sub-pixels arranged in an array on the base substrate and located in the display area; The signal output end of the i-th stage shift register is electrically connected to the sub-pixels in the 2i-1th row and the sub-pixels in the 2i-th row.

8. The display substrate according to any one of claims 4 to 7, wherein: Each shift register includes: connecting electrodes and output signal lines arranged in different layers; The output signal line is electrically connected to the signal output terminal of the shift register at this stage, and the orthographic projection of the connecting electrode on the base substrate at least partially overlaps with the orthographic projection of the output signal line on the base substrate; The connecting electrodes are electrically connected to the signal output end of the shift register at the current stage and the signal input end of the shift register at the next stage respectively.

9. The display substrate according to claim 8, wherein: The display substrate comprises: a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a third metal layer sequentially stacked on the base substrate; The semiconductor layer includes: an active layer of multiple transistors; the first metal layer includes: gate electrodes of multiple transistors, a first plate of a first capacitor, a first plate of a second capacitor, and a first plate of a third capacitor; the second metal layer includes: a second plate of the first capacitor, a second plate of the second capacitor, a second plate of the third capacitor, and an output signal line; the third metal layer includes: source electrodes of multiple transistors, drain electrodes of multiple transistors, a first power line, a second power line, a first clock signal line, a second clock signal line, an initial signal line, and a connection electrode; The resistance of the third metal layer is smaller than the resistance of the first metal layer, and smaller than the resistance of the second metal layer.

10. The display substrate according to claim 9, wherein: In each shift register, the active layers of all transistors include: a channel region and a source connection portion and a drain connection portion located on both sides of the channel region, the source electrode of the transistor is electrically connected to the source connection portion, and the drain electrode of the transistor is electrically connected to the drain connection portion; The drain connection portion of the active layer of the fourth transistor is reused as a drain electrode, the source connection portion of the active layer of the fifth transistor is reused as a source electrode, and the drain connection portion of the active layer of the fourth transistor is electrically connected to the source connection portion of the active layer of the fifth transistor.

11. The display substrate according to claim 9 or 10, characterized in that: In each shift register, the gate electrode of the second transistor, the gate electrode of the tenth transistor, the gate electrode of the eighth transistor, and the first plate of the second capacitor are an integrally formed structure, the gate electrode of the fifth transistor, the gate electrode of the sixth transistor, and the first plate of the first capacitor are an integrally formed structure, and the gate electrode of the ninth transistor and the first plate of the third capacitor are an integrally formed structure; The drain electrode of the first transistor and the source electrode of the fourth transistor are an integrated structure, the drain electrode of the second transistor and the drain electrode of the third transistor are an integrated structure, the source electrode of the third transistor, the source electrode of the tenth transistor and the second power line are an integrated structure, the drain electrode of the sixth transistor and the source electrode of the seventh transistor are an integrated structure, the drain electrode of the seventh transistor and the drain electrode of the eighth transistor are an integrated structure, the source electrode of the eighth transistor, the drain electrode of the ninth transistor, the drain electrode of the fifth transistor and the first power line are an integrated structure.

12. The display substrate according to claim 9 or 10, characterized in that: The first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are located on a side of the first capacitor away from the third capacitor, and on a side of the second capacitor close to the first power line; the sixth transistor is located on a side of the first capacitor close to the second power line, and on a side of the second capacitor close to the third capacitor; the seventh transistor and the eighth transistor are located between the first capacitor and the third capacitor; and the ninth transistor and the tenth transistor are located on a side of the second capacitor close to the second power line.

13. The display substrate according to claim 9 or 10, characterized in that: In each shift register, active layers of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the ninth transistor, and the tenth transistor extend along a first direction, an active layer of the eighth transistor extends along a second direction, and a source electrode and a drain electrode of the sixth transistor are arranged along the first direction; The first direction and the second direction intersect.

14. The display substrate according to claim 8, wherein A distance between the first power line and an edge of the first capacitor close to the second power line is smaller than a distance between the first power line and a source electrode of the sixth transistor.

15. The display substrate according to claim 8, wherein The output signal line in each shift register includes: a first connecting portion, a second connecting portion, a third connecting portion and a fourth connecting portion formed integrally; An orthographic projection of the first connecting portion on the substrate at least partially overlaps with an orthographic projection of the source electrode of the ninth transistor on the substrate, and at least partially overlaps with an orthographic projection of the drain electrode of the tenth transistor on the substrate, and the first connecting portion extends along a first direction; The second connection portion, the third connection portion, and the fourth connection portion extend along the second direction, the second connection portion and the third connection portion are located on a side of the first connection portion away from the first power line, and the fourth connection portion is located on a side of the first connection portion close to the first power line; The second connection portion is electrically connected to the sub-pixel in the 2i-1th row, the third connection portion is electrically connected to the sub-pixel in the 2ith row; the fourth connection portion is electrically connected to the signal input terminal of the next stage shift register; The orthographic projection of the connecting electrode on the base substrate at least partially overlaps with the orthographic projection of the fourth connecting portion on the base substrate, and the fourth connecting portion is electrically connected to the signal input terminal of the next stage shift register through the connecting electrode.

16. The display substrate according to claim 9 or 10, characterized in that: For each shift register, the display substrate further includes: first to tenth via holes penetrating the first insulating layer, the second insulating layer, and the third insulating layer; The first via hole exposes the active layer of the first transistor, the second via hole exposes the active layer of the second transistor, the third via hole exposes the active layer of the third transistor, the fourth via hole exposes the active layer of the fourth transistor, the fifth via hole exposes the active layer of the fifth transistor, the sixth via hole exposes the active layer of the sixth transistor, the seventh via hole exposes the active layer of the seventh transistor, the eighth via hole exposes the active layer of the eighth transistor, the ninth via hole exposes the active layer of the ninth transistor, and the tenth via hole exposes the active layer of the tenth transistor; The source electrode and the drain electrode of the first transistor are electrically connected to the active layer of the first transistor through the first via, the source electrode and the drain electrode of the second transistor are electrically connected to the active layer of the second transistor through the second via, the source electrode and the drain electrode of the third transistor are electrically connected to the active layer of the third transistor through the third via, the source electrode and the drain electrode of the fourth transistor are electrically connected to the active layer of the fourth transistor through the fourth via, the source electrode and the drain electrode of the fifth transistor are electrically connected to the active layer of the fifth transistor through the fifth via, the source electrode and the drain electrode of the sixth transistor are electrically connected to the active layer of the sixth transistor through the sixth via, the source electrode and the drain electrode of the seventh transistor are electrically connected to the active layer of the seventh transistor through the seventh via, the source electrode and the drain electrode of the eighth transistor are electrically connected to the active layer of the eighth transistor through the eighth via, the source electrode and the drain electrode of the ninth transistor are electrically connected to the active layer of the ninth transistor through the ninth via, and the source electrode and the drain electrode of the tenth transistor are electrically connected to the active layer of the tenth transistor through the tenth via.

17. The display substrate according to claim 9 or 10, characterized in that: The display substrate further includes: eleventh to sixteenth via holes penetrating the second insulating layer and the third insulating layer; The eleventh via hole exposes the gate electrode of the first transistor, the twelfth via hole exposes the gate electrode of the second transistor, the thirteenth via hole exposes the gate electrode of the fourth transistor, the fourteenth via hole exposes the gate electrode of the fifth transistor, the fifteenth via hole exposes the gate electrode of the seventh transistor, and the sixteenth via hole exposes the first plate of the third capacitor; The source electrode of the second transistor and a clock signal line are electrically connected to the gate electrode of the first transistor through the eleventh via, the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor through the twelfth via, the source electrode of the sixth transistor and another clock signal line are electrically connected to the gate electrode of the fourth transistor through the thirteenth via, the drain electrode of the third transistor is electrically connected to the gate electrode of the fifth transistor through the fourteenth via, and the drain electrode of the seventh transistor and another clock signal line are electrically connected to the first plate of the third capacitor through the sixteenth via.

18. The display substrate according to claim 9 or 10, characterized in that: The display substrate further includes: seventeenth to twenty-first via holes provided on the third insulating layer; The seventeenth via hole exposes the second plate of the first capacitor, the eighteenth via hole exposes the second plate of the second capacitor, the nineteenth via hole exposes the second plate of the third capacitor, the twentieth via hole exposes the first connection portion of the output signal line, and the twenty-first via hole exposes the fourth connection portion of the output signal line; the drain electrode of the sixth transistor is electrically connected to the second plate of the first capacitor through a seventeenth via, the source electrode of the sixth transistor is electrically connected to the second plate of the second capacitor through an eighteenth via, the drain electrode of the ninth transistor is electrically connected to the second plate of the third capacitor through a nineteenth via, the source electrode of the ninth transistor and the drain electrode of the tenth transistor are electrically connected to the output signal line through a twentieth via, and the connecting electrode is electrically connected to the output signal line through a twenty-first via; There are multiple seventeenth via holes, and the multiple seventeenth via holes are arranged along the first direction; There are multiple eighteenth via holes, and the multiple eighteenth via holes are arranged along the first direction; There are multiple nineteenth via holes, and the multiple nineteenth via holes are arranged along the second direction; There is a plurality of the twentieth via holes, and the plurality of twentieth via holes are arranged along the first direction.

19. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 18.

20. A method for manufacturing a display substrate, characterized in that: The method is configured to manufacture the display substrate according to any one of claims 1 to 18, the method comprising: providing a substrate; A driving circuit and a first power line are formed on a base substrate in a non-display area; the driving circuit includes: a first capacitor, a second capacitor, and a third capacitor; the first capacitor and the third capacitor are arranged along a first direction, the second capacitor and the third capacitor are respectively located on either side of the first capacitor, the second capacitor is located on a side of the first capacitor closer to the display area, and one plate of the third capacitor is electrically connected to the first power line; The first power line extends along a first direction, and an orthographic projection of the first capacitor on the base substrate at least partially overlaps with an orthographic projection of the first power line on the base substrate.

21. The method according to claim 20, characterized in that The driving circuit includes: a plurality of shift registers, each shift register includes: a plurality of transistors and first to third capacitors, and the driving circuit and the first power line formed in the non-display area on the substrate include: A semiconductor layer is formed on a substrate, wherein the semiconductor layer includes: an active layer of a plurality of transistors; A first insulating layer and a first metal layer are sequentially formed on the semiconductor layer, wherein the first metal layer includes: gate electrodes of a plurality of transistors, a first plate of a first capacitor, a first plate of a second capacitor, and a first plate of a third capacitor; forming a second insulating layer and a second metal layer in sequence on the first metal layer, wherein the second metal layer includes: a second plate of the first capacitor, a second plate of the second capacitor, a second plate of the third capacitor, and an output signal line; A third insulating layer and a third metal layer are sequentially formed on the second metal layer, wherein the third metal layer includes: source electrodes of multiple transistors, drain electrodes of multiple transistors, a first power line, a second power line, a first clock signal line, a second clock signal line, an initial signal line and a connecting electrode.

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