Display substrate, display panel, and display device

Abstract

The present application discloses a display substrate, a display panel, and a display device. The display substrate has a display area and a non-display area that at least partially surrounds the display area, wherein the non-display area includes a binding area. The display substrate includes: a substrate; a plurality of data lines located on the substrate and in the display area; a plurality of first connection lines located on the substrate and in the display area, wherein the first connection lines transmit signals from the binding area to the data lines; at least some of the first connection lines include a first portion and a second portion, wherein the second portion is connected between the first portion and the data line, and the orthographic projection of the first portion on the substrate at least partially overlaps with the orthographic projection of the second portion on the substrate. According to embodiments of the present application, display uniformity is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] With the continuous updating of display panel technology, display panels are gradually developing towards being lighter, thinner, with a higher screen-to-body ratio and ultra-narrow bezels.

[0003] A display panel typically includes a display area and a non-display area surrounding the display area. The non-display area is used to route signal lines. For example, the non-display area can be used to route fan-out wiring. In related art, some fan-out wiring can be placed in the display area to reduce the width of the non-display area, thereby achieving a narrower bezel. However, this related art still suffers from poor display quality. Summary of the Invention

[0004] The embodiments of the present application provide a display substrate, a display panel, and a display device, which are beneficial for improving display uniformity.

[0005] In a first aspect, an embodiment of the present application provides a display substrate having a display area and a non-display area at least partially surrounding the display area, the non-display area including a binding area; the display substrate includes: a substrate; a plurality of data lines located on the substrate and in the display area; a plurality of first connection lines located on the substrate and in the display area, the first connection lines transmitting signals from the binding area to the data lines; at least some of the first connection lines include a first part and a second part, the second part is connected between the first part and the data line, and the orthographic projection of the first part on the substrate at least partially overlaps with the orthographic projection of the second part on the substrate.

[0006] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a display panel, comprising a display substrate as in any one of the embodiments of the first aspect.

[0007] Based on the same inventive concept, in a third aspect, an embodiment of the present application provides a display device, comprising a display panel as in any one of the embodiments of the second aspect.

[0008] According to the display substrate, display panel and display device provided by the embodiments of the present application, since the first part and the second part at least partially overlap, a folded trace design is adopted for the first connecting trace including the first part and the second part. In this way, the total length of the first connecting trace can be extended within a limited plane space, so that the resistance of the first connecting trace can be adjusted by extending the total length of at least part of the first connecting trace, which is beneficial to making the resistance of each first connecting trace tend to be consistent, thereby helping to reduce the difference in resistance load (R Loading) of each first connecting trace, and thus improving display uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0010] Figure 1 A schematic structural diagram of a display substrate provided in an embodiment of the present application is shown;

[0011] Figure 2 Show Figure 1 Enlarged schematic diagram of the middle region Q1;

[0012] Figure 3 Show Figure 2 A schematic cross-sectional view in the A-A' direction;

[0013] Figure 4 A schematic diagram showing a film layer structure of a display substrate provided in an embodiment of the present application is shown;

[0014] Figure 5 A schematic structural diagram of a display substrate provided in an embodiment of the present application is shown;

[0015] Figure 6 Show Figure 5 Enlarged schematic diagram of the middle region Q2;

[0016] Figure 7 A schematic structural diagram of a display panel provided according to an embodiment of the present application is shown;

[0017] Figure 8 A schematic structural diagram of a display device provided according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0018] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0019] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0020] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the component is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0021] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0022] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0023] In the embodiment of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure. The first node, the second node and the third node are not actual circuit units.

[0024] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0025] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0026] In related art, some fan-out traces can be placed in the display area, and these traces can connect to some data lines. The inventors discovered that due to the different distribution of data lines, the lengths of the fan-out traces connected to each data line in the display area vary. This results in different impedances for each fan-out trace, hindering display uniformity.

[0027] To solve the above problems, embodiments of the present application provide a display substrate, a display panel, and a display device. Embodiments of the display substrate, the display panel, and the display device will be described below with reference to the accompanying drawings.

[0028] First, the display substrate provided in the embodiment of the present application is introduced.

[0029] Figure 1 A schematic structural diagram of a display substrate provided in an embodiment of the present application is shown. Figure 2 Show Figure 1 Enlarged schematic diagram of the middle region Q. Figure 3 Show Figure 2 A schematic cross-sectional view of the A-A' direction. Figure 1 As shown, the display substrate 100 may include a display area AA and a non-display area NA. The non-display area NA at least partially surrounds the display area AA. Figure 1 It is illustrated that the non-display area NA completely surrounds the display area AA.

[0030] The edges of the display area AA may form a right angle, for example, the display area AA may be rectangular, or the edges of the display area AA may form a curved corner.

[0031] The non-display area NA may include a binding area BA. The binding area BA may include binding terminals (not shown), to which the flexible circuit board can be bound and connected, and the driver chip can be bound to the flexible circuit board. The flexible circuit board can be bent to the back side of the display substrate 100, and the driver chip can be located on the back side of the display substrate 100 to achieve a narrow bezel. The binding terminals in the binding area BA can transmit drive signals, for example, the binding terminals can be used to transmit data signals to the display area.

[0032] Continue to refer Figure 1 , the display substrate 100 may include a substrate 10 , a plurality of data lines 21 and a plurality of first connection lines 31 .

[0033] The substrate 10 may be a flexible substrate or a rigid substrate and may include a display area AA and a non-display area NA.

[0034] A plurality of data lines 21 are located on the substrate 10 and disposed in the display area AA. The plurality of data lines 21 may be arranged in a first direction X and may extend along a second direction Y. The first direction X may be a row direction, and the second direction Y may be a column direction.

[0035] The display substrate 100 may further include a plurality of scan lines (not shown) and a plurality of pixel circuits (not shown). The extending direction of the scan lines intersects with the data lines 21. The plurality of pixel circuits may be arranged in an array.

[0036] A plurality of first connection lines 31 are located on the substrate 10 and in the display area AA. The total number of data lines 21 may be greater than the total number of first connection lines 31. Some data lines 21 are connected to the first connection lines 31. The first connection lines 31 transmit signals from the bonding area BA to the data lines 21 to which they are connected.

[0037] As an example, the display substrate 100 may further include second connection lines 32 located in the non-display area NA. Specifically, the second connection lines 32 may be located in the non-display area NA between the bonding area BA and the display area NA. Another portion of the data lines 21 may be connected to the second connection lines 32. The second connection lines 32 transmit signals from the bonding area BA to the data lines 21 to which they are connected.

[0038] To better distinguish the data lines connected to the first connection lines 31 and the second connection lines 32, the data lines connected to the first connection lines 31 are referred to herein as first-category data lines 211, and the data lines connected to the second connection lines 32 are referred to herein as second-category data lines 212. In the first direction X, the plurality of first-category data lines 211 can be arranged on both sides, and the plurality of second-category data lines 212 can be arranged between the first-category data lines 211.

[0039] The first connection line 31 and the second connection line 32 are connected to the binding terminals in the binding area BA. The first connection line 31 and the second connection line 32 can also be called fanout lines. The difference between the two is that the first connection line 31 is set in the display area AA, and the second connection line 32 is set in the non-display area AA.

[0040] Exemplarily, in order to connect the first connection line 31 with the binding terminal in the binding area BA, a third connection line 33 may be provided in the non-display area NA. The third connection line 33 is connected between the first connection line 31 and the binding terminal in the binding area BA.

[0041] like Figure 2 and Figure 3As shown, among the plurality of first connection traces 31, at least some of the first connection traces 31 may include a first portion 311 and a second portion 312 connected to each other, and the second portion 312 may be connected between the first portion 311 and the first type data line 211. Figure 2 As shown, the orthographic projection of the first portion 311 on the substrate 10 and the orthographic projection of the second portion 312 on the substrate 10 may at least partially overlap.

[0042] In order to more clearly show the overlapping first part 311 and second part 312, the second part 312 is represented by a gray thick solid line and the first part 311 is represented by a black slightly thin solid line in the drawings of this application. This is not used to limit the line width of the first part 311 and the second part 312.

[0043] As an example, one end of the second portion 312 is connected to the first portion 311 , and the other end is connected to the first-type data line 211 .

[0044] It is understood that the first portion 311 and the second portion 312 are located in different film layers and can be connected via a via. Figure 3 As shown in the figure, the second portion 312 and the data line 21 are also located in different film layers. The second portion 312 and the data line 21 can be connected via a via.

[0045] For example, the first portion 311 may include multiple interconnected line segments extending in different directions. The second portion 312 may include a line segment extending in one direction. It is understood that since the first portion 311 and the second portion 312 at least partially overlap, the first portion 311 and the second portion 312 include line segments extending in the same direction, and the orthographic projections of the line segments extending in the same direction on the substrate 10 may at least partially overlap. The line segments extending in the same direction and partially overlapping in the first portion 311 and the second portion 312 have a certain length, and the lengths of the two line segments may be different.

[0046] As an example, the extension direction of the second portion 312 can be the same as the extension direction of the data line 21. The extension direction of at least some segments of the first portion 311 is the same as the extension direction of the second portion 312, and the segments of the first portion 311 that extend in the same direction as the second portion 312 overlap with the second portion 312.

[0047] For the first connecting line 31 including the first portion 311 and the second portion 312 , it can be understood that a folded line design is adopted, so that the total length of the first connecting line 31 can be extended within a limited plane space.

[0048] As an example, Figure 2Taking the first first connecting trace 31 on the left and the fifth first connecting trace 31 on the left as examples, if the first first connecting trace 31 on the left only includes the first portion 311, its length will be shorter than the length of the fifth first connecting trace 31 on the left. When the first first connecting trace 31 on the left includes the first portion 311 and the second portion 312, that is, the first first connecting trace 31 on the left adopts a folded trace design, the total length of the first first connecting trace 31 on the left can be extended, so that the lengths of the first first connecting trace 31 on the left and the fifth first connecting trace 31 on the left are close to each other.

[0049] like Figure 1 and Figure 2 As shown, the first connecting traces 31 may include first-type connecting traces 31a and second-type connecting traces 31b. The first-type connecting traces 31a may be designed as folded traces, while the second-type connecting traces 31b may not be designed as folded traces. In other words, the first-type connecting traces 31a may include first and second portions 311 and 312 that at least partially overlap and connect to each other, while the second-type connecting traces 31b may not include any overlapping segments.

[0050] certainly, Figure 1 and Figure 2 This is just an example, and all the first connecting lines 31 may adopt a folded line design.

[0051] According to the display substrate provided in the embodiment of the present application, since the first part 311 and the second part 312 at least partially overlap, the first connecting trace 31 including the first part 311 and the second part 312 adopts a folded trace design method, so that the total length of the first connecting trace 31 can be extended within a limited plane space, so that the resistance of the first connecting trace 31 can be adjusted by extending the total length of at least part of the first connecting trace 31, which is beneficial to making the resistance of each first connecting trace 31 tend to be consistent, thereby helping to reduce the difference in resistance load (R Loading) of each first connecting trace 31, and thus improving display uniformity.

[0052] For example, Figure 1 As shown, the plurality of first connection lines 31 may not cross each other.

[0053] In some optional embodiments, the lengths of the plurality of first connection lines 31 may be similar. For example, the lengths of the plurality of first connection lines 31 may be the same, thereby further reducing the difference in R Loading of the first connection lines 31 .

[0054] In some optional embodiments, the second portion 312 and the data line 21 may both extend along the second direction Y. Figure 3As shown, the orthographic projection of the second portion 312 on the substrate 10 at least partially overlaps with the orthographic projection of the data line 21 to which it is connected on the substrate 10. It is understandable that the second portion 312 and the data line 21 to which it is connected transmit the same signal. The overlapping arrangement of the two, that is, preventing the second portion 312 from overlapping with other signal lines, can prevent coupling between the second portion 312 and other signal lines, thereby improving signal stability.

[0055] The length of the second portion 312 can be much smaller than the length of the data line 21. When the line width of the second portion 312 is the same as the line width of the data line 21, the orthographic projection of the data line 21 connected to the second portion 312 on the substrate 10 can cover the orthographic projection of the second portion 312 on the substrate 10.

[0056] Illustratively, the orthographic projection of the second portion 312 on the substrate 10 at least partially overlaps with the orthographic projection of the data line 211 connected to it on the substrate 10, the orthographic projection of the second portion 312 on the substrate 10 also at least partially overlaps with the orthographic projection of the first portion 311 connected to it on the substrate 10, and the orthographic projection of the first portion 311 on the substrate 10 also at least partially overlaps with the orthographic projection of the data line 21 connected to it on the substrate 10.

[0057] When the line widths of the first part 311, the second part 312 and the data line 21 are the same, the orthographic projection of the data line 21 on the substrate 10 can cover the orthographic projection of the second part 312 connected to the data line 21 on the substrate 10, and the orthographic projection of the data line 21 on the substrate 10 can cover at least part of the orthographic projection of the first part 311 connected to the data line 21 on the substrate 10.

[0058] In some optional embodiments, please continue to refer to Figure 3 The second portion 312 can be located on the side of the data line 21 facing away from the substrate 10, and the first portion 311 can be located on the side of the second portion 312 facing away from the substrate 10. That is, in the thickness direction of the display substrate, the film layer where the second portion 312 is located is located between the film layer where the data line 21 is located and the film layer where the first portion 311 is located, and the second portion 312 is connected to the data line 21 and the first portion 311 respectively through vias. Because the second portion 312 is connected between the first portion 311 and the data line 21, by positioning the film layer where the second portion 312 is located between the film layer where the data line 21 is located and the film layer where the first portion 311 is located, the depth of the connecting vias between the second portion 312 and the data line 21 and the first portion 311 can be avoided from being too deep, thereby reducing the difficulty of process manufacturing and preventing the vias from occupying a large area.

[0059] like Figure 1As shown, taking the first direction X as the row direction as an example, the second portion 312 of each first connection line 31 and the connection vias of each first-type data line 211 may not be in the same row. The inventors further discovered that, for example, for each first-type data line 211 connected to the pixel circuits in the first row, even if the lengths of each first connection line 31 are set to be close to the same by folding the routing, that is, the resistances of each first connection line 31 are set to be close to the same, the path lengths of each data signal required by each first-type data line 211 to connect to the pixel circuits in the first row are different on the data line 21. Therefore, there are still differences in the voltage drops corresponding to the connection of each first-type data line 211 to the pixel circuits in the first row.

[0060] In some optional embodiments, the metal resistivity of the film layer containing the data line 21 can be lower than the metal resistivity of the film layer containing the second portion 312, and the metal resistivity of the film layer containing the data line 21 can be lower than the metal resistivity of the film layer containing the first portion 311. In other words, the metal resistivity of the film layer containing the data line 21 is lower. Thus, when the widths of the data line 21, the first portion 311, and the second portion 312 are the same, the resistance per unit length of the data line 21 is lower than the resistance per unit length of the first portion 311 and lower than the resistance per unit length of the second portion 312. The lower resistance of the data line 21 can reduce the voltage drop differences caused by the different path lengths of various data signals along the data line 21, thereby further improving display uniformity.

[0061] For example, the data line 21 may be made of a metal material with a relatively low resistivity, and the first portion 311 and the second portion 312 may be made of a metal material with a resistivity greater than that of the data line 21 .

[0062] As an example, the resistivity of the metal in the film layer where the first portion 311 is located can be equal to the resistivity of the metal in the film layer where the second portion 312 is located. The first portion 311 and the second portion 312 can be made of the same metal material. Of course, the resistivity of the metal in the film layer where the first portion 311 is located can also be set to be different from the resistivity of the metal in the film layer where the second portion 312 is located, depending on actual conditions.

[0063] As an example, the resistance per unit length of the second portion 312 is equal to the resistance per unit length of the first portion 311. If the metal resistivity of the film layers containing the first portion 311 and the second portion 312 is equal, the line widths of the two portions can be equal. Alternatively, if the metal resistivity of the film layers containing the first portion 311 and the second portion 312 is different, the line widths of the two portions can be adjusted to ensure that the resistance per unit length of the second portion 312 is equal to the resistance per unit length of the first portion 311.

[0064] Figure 4 A schematic diagram of a film layer structure of a display substrate provided in an embodiment of the present application is shown. Figure 4 It is only used to introduce the film structure of the display substrate in the thickness direction, and does not specifically refer to the cross-sectional structure of a specific position of the display substrate. In some optional embodiments, such as Figure 4 As shown, the display substrate also includes a first metal layer M1, a capacitor metal layer MC, a gate metal layer MD, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4 stacked in a direction away from the substrate 10. An insulating layer may be provided between any adjacent metal layers. The display substrate may include at least two types of transistors. For example, the display substrate may include a low-temperature polysilicon transistor and an oxide transistor. The film layer structure of the display substrate may also include a first semiconductor layer b1 and a second semiconductor layer b2. The first semiconductor layer b1 is located between the first metal layer M1 and the substrate 10, and an insulating layer is provided between the first semiconductor layer b1 and the first metal layer M1. The second semiconductor layer b2 may be located between the capacitor metal layer MC and the gate metal layer MD, and an insulating layer is provided between the second semiconductor layer b2 and the capacitor metal layer MC and between the second semiconductor layer b2 and the second metal layer M2.

[0065] As an example, the data line 21 may be located in the second metal layer M2 , the second portion 312 may be located in the third metal layer M3 , and at least a portion of the first portion 311 may be located in the fourth metal layer M4 .

[0066] As an example, the resistivity of the metal of the second metal layer M2 may be lower than that of the metal of the third metal layer M3 , and the resistivity of the metal of the second metal layer M2 may be lower than that of the metal of the fourth metal layer M4 .

[0067] As an example, the resistivity of the metal of the third metal layer M3 may be equal to the resistivity of the metal of the fourth metal layer M4 .

[0068] In some further optional embodiments, in order to avoid different path lengths for each data signal on the data line 21 , the connecting vias of each first connecting line 31 and each first-type data line 211 may be arranged in the same row.

[0069] Figure 5 A schematic structural diagram of a display substrate provided in an embodiment of the present application is shown. Figure 6 Show Figure 5 The enlarged schematic diagram of the middle region Q2 is exemplary. Figure 5 and Figure 6As shown, taking the connecting vias between each first connecting line 31 and each first-type data line 211 as the first vias h1 as an example, each first via h1 can be located in the same row, so that the path lengths of each data signal passing through the data line 21 are the same, thereby avoiding the voltage drop difference caused by the different path lengths of each data signal passing through the data line 21, and further improving the display uniformity.

[0070] Figure 5 、 Figure 6 In the example, the first connecting lines 31 are all designed in a folded routing manner. For example, the connecting via holes of the first portion 311 and the second portion 312 are second via holes h2, and a plurality of second via holes h2 can be staggered. Figure 5 、 Figure 6 , it is shown by way of example that, in the second direction Y, the first via h1 corresponding to the same first connection line 311 is located on the side of the second via h2 away from the binding area BA, which is not intended to limit the present application. For example, in the second direction Y, the first via h1 corresponding to the first connection line 311 may be located on the side of the second via h2 close to the binding area BA. Alternatively, in the second direction Y, the first via h1 corresponding to some of the first connection lines 311 may be located on the side of the second via h2 away from the binding area BA, and the first via h1 corresponding to some of the first connection lines 311 may be located on the side of the second via h2 close to the binding area BA.

[0071] Please continue to refer to Figure 5 or Figure 6 For the first connecting trace 31 using a folded trace design, its first portion 311 may include at least a first segment 3111, a second segment 3112, and a third segment 3113. The second segment 3112 is connected between the first segment 3111 and the third segment 3113. The first segment 3111 is connected to the bonding area BA, and the third segment 3113 is connected to the second portion 312. The orthographic projection of the third segment 3113 on the substrate 10 at least partially overlaps with the orthographic projection of the second portion 312 on the substrate 10.

[0072] The third segment 3113 can extend in the same direction as the second portion 312. For example, the third segment 3113, the second portion 312, and the data line 21 all extend in the same direction. The figures herein illustrate that the length of the third segment 3113 is shorter than the length of the second portion 312, but this is not intended to limit the present application.

[0073] The third section 3113 may extend in the same direction as the first section 3111, and the second section 3112 may extend in a direction that intersects the direction of the third section 3113. In the second direction Y, the third section 3113 may be located on a side of the second section 3112 that is closer to the binding area BA. Alternatively, the third section 3113 may be located on a side of the second section 3112 that is farther from the binding area BA in the second direction Y, depending on actual needs.

[0074] Please refer to Figure 2 For the first connecting trace 31b that does not adopt a folded trace design, it may include at least a fourth segment 3114 and a fifth segment 3115 that are connected to each other. The fourth segment 3114 is connected to the binding area via the third connecting line 33, and the fifth segment 3115 is connected to the data line 21. The fourth segment 3114 may extend in the same direction as the first segment 3111, and the fifth segment 3115 may extend in the same direction as the second segment 3112.

[0075] like Figure 6 As shown, the display substrate further includes a first signal line 41 and a second signal line 42, and the first signal line 41 and the second signal line 42 transmit constant voltage signals. For example, the first signal line 41 may include a power signal line (PVDD line), and the second signal line 42 may include an initialization signal line (Vref line).

[0076] The first signal line 41 can extend in the same direction as the first segment 3111, and the second signal line 42 can extend in the same direction as the second segment 3112. The orthographic projection of the first segment 3111 on the substrate 10 can at least partially overlap with the orthographic projection of the first signal line 41 on the substrate 10, and the orthographic projection of the second segment 3112 on the substrate 10 can at least partially overlap with the orthographic projection of the second signal line 42 on the substrate 10. Because the first signal line 41 and the second signal line 42 transmit fixed signals, the overlapping arrangement of the first segment 3111 and the first signal line 41, and the overlapping arrangement of the second segment 3112 and the second signal line 42, can reduce coupling between the first segment 3111, the second segment 3112, and other signal lines, thereby improving the stability of the signals transmitted by the first segment 3111 and the second segment 3112.

[0077] Based on the same inventive concept, the present application also provides a display panel. Figure 7 FIG. 1 shows a schematic diagram of a structure of a display panel provided according to an embodiment of the present application. Figure 7 As shown, the display panel 1000 provided in the embodiment of the present application may include the display substrate 100 described in any of the above embodiments. Exemplarily, the display panel 1000 may include a light-emitting layer 200 located on one side of the display substrate 100. The light-emitting layer 200 may include a plurality of light-emitting elements distributed in an array.

[0078] Figure 7 The display panel shown may be an organic light-emitting diode (OLED) display panel.

[0079] Those skilled in the art should understand that in other implementations of the present application, the display panel may also be a micro light emitting diode (Micro LED) display panel, a quantum dot display panel, etc.

[0080] The display panel provided in the embodiment of the present application has the beneficial effects of the display substrate provided in the embodiment of the present application. For details, please refer to the specific description of the display substrate in the above embodiments, and this embodiment will not be repeated here.

[0081] This application also provides a display device, including the display panel provided by this application. Figure 8 , Figure 8 This is a structural diagram of a display device provided in an embodiment of the present application. Figure 8 The provided display device 2000 includes the display panel 1000 provided by any of the above embodiments of the present application. Figure 8 The embodiment only uses a mobile phone as an example to illustrate the display device 2000. It is understandable that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, an in-vehicle display device, or other display device with a display function, and the present application does not impose specific limitations on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0082] While the embodiments described above are not exhaustive, they do not limit the present application to the specific embodiments described. Clearly, numerous modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to better utilize the present application and its modifications. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display substrate, characterized in that: having a display area and a non-display area at least partially surrounding the display area, the non-display area including a binding area; The display substrate comprises: substrate; a plurality of data lines, located on the substrate and in the display area; a plurality of first connection lines, located on the substrate and in the display area, the first connection lines transmitting signals from the binding area to the data lines; At least some of the first connecting lines include a first portion and a second portion, the second portion is connected between the first portion and the data line, and an orthographic projection of the first portion on the substrate at least partially overlaps with an orthographic projection of the second portion on the substrate; The first end of the second part is connected to the first part, the second end of the second part is connected to the data line, and in the extending direction of the data line, the second end of the second part is located on the side of the first end of the second part away from the binding area.

2. The display substrate according to claim 1, wherein: The orthographic projection of the second portion on the substrate at least partially overlaps with the orthographic projection of the data line connected thereto on the substrate.

3. The display substrate according to claim 2, wherein: The second portion is located on a side of the data line facing away from the substrate, and the first portion is located on a side of the second portion facing away from the substrate.

4. The display substrate according to claim 3, wherein: The display substrate also includes a first metal layer, a capacitor metal layer, a gate metal layer, a second metal layer, a third metal layer and a fourth metal layer stacked in a direction away from the substrate, the data line is located in the second metal layer, the second part is located in the third metal layer, and at least part of the line segment of the first part is located in the fourth metal layer.

5. The display substrate according to claim 3, wherein: The resistivity of the metal in the film layer where the data line is located is smaller than the resistivity of the metal in the film layer where the second portion is located, and the resistivity of the metal in the film layer where the data line is located is smaller than the resistivity of the metal in the film layer where the first portion is located.

6. The display substrate according to any one of claims 1 to 4, characterized in that: The resistance per unit length of the second portion is equal to the resistance per unit length of the first portion.

7. The display substrate according to any one of claims 1 to 4, characterized in that: The lengths of the plurality of first connecting lines tend to be consistent.

8. The display substrate according to claim 1, wherein: The plurality of data lines extend in a column direction and are arranged in a row direction. The plurality of first connection lines are connected to the plurality of data lines in a one-to-one correspondence through a plurality of via holes, and the plurality of via holes are located in a same row.

9. The display substrate according to claim 1, wherein: The first portion comprises at least a first section, a second section and a third section, the second section is connected between the first section and the third section, the first section is connected to the binding area, and the third section is connected to the second portion; The orthographic projection of the third segment on the substrate at least partially overlaps with the orthographic projection of the second portion on the substrate; The display substrate further includes a first signal line and a second signal line, wherein the first signal line and the second signal line transmit constant voltage signals, the first signal line extends in the same direction as the first segment, and the second signal line extends in the same direction as the second segment; The orthographic projection of the first segment on the substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate, and the orthographic projection of the second segment on the substrate at least partially overlaps with the orthographic projection of the second signal line on the substrate.

10. A display panel, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 9.

11. A display device, characterized in that: The device comprises the display panel according to claim 10.

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