Diode device with programmable on-current and method for preparing array thereof

Abstract

The present invention discloses a diode device with programmable on-current, comprising a metal structure, a resistive switching structure and a semiconductor structure. The present invention has an ultra-high self-rectification ratio and stable unipolar resistive switching characteristics. The state density function of the semiconductor must contain at least one peak, which is located near the band gap and can form a Schottky barrier at its interface, so that the device exhibits diode characteristics, thereby effectively suppressing bypass leakage current interference in the array. The resistive switching structure has a unidirectional resistive switching capability and can perform erase and write operations in the current conduction direction. On the one hand, it avoids the problem of being unable to perform erase and write operations through reverse voltage, and on the other hand, it avoids applying reverse voltage to the barrier, thereby improving the reliability of the self-rectification effect. Based on the above structure, the present invention proposes two methods for directly preparing arrays on semiconductors and a preparation method for 3D array integration, without the need for an external gate tube. The present invention has the advantages of high integration, strong anti-interference capability, and high CMOS compatibility.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors and integrated circuits, and specifically relates to a diode device with programmable on-current based on a semiconductor structure that can be applied to large-scale memory arrays. The introduction of semiconductors makes it highly compatible with CMOS processes, and its simple structure also facilitates three-dimensional integration. Background Art

[0002] Resistive random access memory (RRAM) typically has a metal-resistive layer-metal sandwich structure, storing information by varying the resistance of the resistive material between two metal electrodes. Compared to traditional embedded flash memory technology, this type of memory offers superior storage capabilities, including low operating voltage, high on / off ratio, low power consumption, excellent durability and retention characteristics, and offers significant scaling advantages.

[0003] There is a serious read interference problem when integrating RRAM, so it is necessary to add a gate tube to suppress the interference of bypass leakage current. Common array structures include 1D1R and 1T1R, which are composed of diodes or transistors and resistive switching units. Although such a structure can effectively solve the crosstalk problem between devices, it increases the device area and thus weakens the integration. On the other hand, considering the compatibility with CMOS process, the commonly used RRAM bottom electrode technology generally uses inert metal Pt, which is difficult to etch and has poor adhesion, making the process compatible with CMOS more complicated. The present invention proposes solutions to the above three problems of read interference, integration and CMOS compatibility. Summary of the Invention

[0004] The present invention aims to address the interference of bypass current in RRAM arrays, the reduction of integration, and the lack of CMOS process compatibility. A diode device with programmable on-current based on a semiconductor structure is proposed. The diode device utilizes Schottky contact between the semiconductor structure and the oxygen vacancy conductive channel in the resistive switching structure to suppress the bypass current. The diode device is fully compatible with CMOS processes and is easy to integrate in three dimensions.

[0005] The present invention is achieved through the following technical solutions:

[0006] The present invention provides a diode device with programmable on-current, comprising a metal structure, a resistive switching structure and a semiconductor structure; the resistance of the resistive switching structure can be adjusted to achieve programmable on-current; the semiconductor structure is composed of a semiconductor, the state density function of the semiconductor contains at least one peak, so that the state density near the peak energy level is much greater than the state density of the semiconductor structure at energy levels other than the peak; the metal structure, the resistive switching structure and the semiconductor structure are directly connected in sequence.

[0007] Furthermore, the metal structure is composed of one or more metals, including but not limited to TiN, Ni, W, Ti, Al, Pd, Pt, Au, and Ru;

[0008] Furthermore, the resistive switching structure is a unipolar resistive switching oxide layer composed of one or more oxides, including but not limited to TiO2, NiO, Ni2O3, Y2O3, HfO2, WO3, ZrO2, and Ta2O5.

[0009] Furthermore, by adjusting the voltage and current limiting value applied to the metal structure, the resistive switching structure can be converted from a low resistance state to a high resistance state in the current conducting direction, and can also be converted from a high resistance state to a low resistance state.

[0010] Furthermore, for the unoperated device, by applying a higher positive voltage, a metallic conductive filament (CF) is formed in the resistive switching structure, and the device becomes a low-resistance state (LRS). This process is called forming; for the device in the LRS, by applying a smaller positive voltage, the CF is disconnected at the interface between the resistive switching structure and the metal structure, and the device returns to the high-resistance state (HRS). This process is called Reset; for the device in the HRS, by applying a larger positive voltage, the disconnected part of the CF is reconnected, and the device returns to the low-resistance state (LRS). This process is called Set.

[0011] Furthermore, the semiconductor material of the semiconductor structure includes but is not limited to Ge, SiGe, GaAs, GaN, SiC, and Ga2O3, and the state density function contains at least one peak located near the band gap.

[0012] Furthermore, the metallic oxygen vacancy conductive filaments CF locally present in the resistive switching structure can be directly connected to the semiconductor structure to form a Schottky contact, and the device behaves as a self-rectifying resistive random access memory (RRAM), which has the advantages of high CMOS compatibility and high array integration.

[0013] Furthermore, when the semiconductor material of the semiconductor structure adopts a semiconductor that can pin the Fermi level of the metal directly connected to it to near the valence band of the semiconductor without being affected by the work function of the metal itself (such as Ge material), the size of the Schottky barrier at the semiconductor surface mainly depends on the properties of the semiconductor itself, which makes the range of options for oxide types in the resistive switching structure and metal types in the metal structure wider.

[0014] Furthermore, due to the presence of the Schottky barrier, the reverse current is extremely small regardless of whether the resistive switching structure is in HRS or LRS, and the rectification ratio for the same positive and negative voltages can be as high as 10. 5The above can effectively suppress the bypass current and is suitable for large-scale array integration.

[0015] Furthermore, the reverse leakage current density of the Schottky barrier is generally a constant, and its reverse leakage current is related to the device area and the density of CF. The low-resistance current of the resistive switching structure mainly comes from the conduction of CF and is insensitive to changes in the device area. Therefore, the rectification ratio can be controlled by adjusting the device area and the density of CF.

[0016] Furthermore, the unipolar resistive oxide layer enables the device to perform Set and Reset operations during current conduction. This avoids the problem of reverse voltage operation due to reverse current suppression, and also prevents the degradation of the Schottky junction caused by the application of reverse voltage, thereby improving the reliability of the Schottky junction.

[0017] The present invention also provides two methods for preparing arrays of the above-mentioned diode devices with programmable on-current on a semiconductor substrate, and the specific steps are as follows.

[0018] Preparation plan 1:

[0019] S1: forming spaced n-type semiconductor strips as bit lines on a p-type semiconductor substrate by ion implantation or spin coating, growing an isolation layer, and etching the isolation layer to form spaced trenches, wherein the trenches are within the bit lines;

[0020] S2: growing a resistive switching structure on the structure obtained in S1;

[0021] S3: growing a metal structure on the structure obtained in S2, and etching the metal structure to form spaced word lines;

[0022] S4: On the structure obtained in S3, metal is grown at the same end of each bit line to form an extraction electrode of the bit line.

[0023] Preparation scheme 2:

[0024] S1: growing an n-type semiconductor on the insulating layer and etching the n-type semiconductor to form strip-shaped regions arranged at intervals as bit lines;

[0025] S2: growing a resistive switching structure on the structure obtained in S1;

[0026] S3: growing a metal structure on the structure obtained in S2, and etching the metal structure to form spaced word lines;

[0027] S4: On the structure obtained in S3, metal is grown at the same end of each bit line to form an extraction electrode of the bit line.

[0028] The present invention also provides a method for preparing a 3D integrated array of the above-mentioned diode device with programmable on-current. Taking Ge as an example, the specific steps are as follows:

[0029] S1: Grow a Ge stress buffer layer (Ge SRB) on a semiconductor silicon substrate, and then cyclically grow SiGe, heavily doped Ge (doping concentration greater than 10 18 cm -3 ), the top layer is SiGe; heavily doped Ge is used as the bit line; the number of cycles is greater than or equal to 2; the following is an example of a 3-cycle process: a stress buffer layer of Ge is grown on a semiconductor silicon substrate, and then SiGe / Ge / SiGe / Ge / SiGe / Ge / SiGe is grown in sequence;

[0030] S2: Selectively etch SiGe on the structure obtained in S1 and fill it with an isolation layer, which can be made of SiO2;

[0031] S3: Selectively etch heavily doped Ge on the structure obtained in S2 and fill it with lightly doped Ge (doping concentration less than 10 18 cm -3 );

[0032] S4: growing a resistive switching structure and a protective layer on the structure obtained in S3. The protective layer may be made of SiN.

[0033] S5: Selectively etching the protective layer in the device area on the structure obtained in S4, and growing a metal structure to form a word line; growing metal at the same end of each bit line to form an extraction electrode of the bit line.

[0034] Furthermore, the bit line region to which the extraction electrode of the bit line is directly connected is a heavily doped semiconductor, so that the tunneling current is dominant, thereby ensuring ohmic contact. In this case, the extraction electrode can be a common metal;

[0035] Alternatively, the extraction electrode of the bit line is a metal that can form an ohmic contact with the semiconductor structure (including but not limited to metals with a low number of free electrons such as bismuth). In this case, the bit line region directly connected to the extraction electrode is not required to be a heavily doped semiconductor.

[0036] Furthermore, the device structure described in the present invention can be implemented based on the semiconductor Ge. Ge is considered to be one of the most promising transistor substrate materials at present because its electron and hole mobility is much higher than that of Si. Currently, CMOS applications based on Ge are highly valued in the industry, and achieving excellent memory performance on Ge has great application prospects.

[0037] The beneficial effects of the present invention are as follows: First, the present invention achieves an ultra-high self-rectification ratio, enabling application in large-scale array integration; Second, the present invention eliminates the need for external diodes, utilizing the inherent rectification properties of semiconductors, resulting in a simple structure and ease of three-dimensional integration; Third, the present invention has a relatively low on-current and an operating voltage below 5V, significantly reducing power consumption; Fourth, the present invention can be fabricated directly on semiconductors, is fully compatible with advanced CMOS processes, and is suitable for the rapidly developing semiconductor integrated circuits. In summary, the present invention has the advantages of a simple fabrication process, low fabrication cost, high integration, low operating voltage, low power consumption, strong anti-interference capability, three-dimensional integration, and high CMOS compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Schematic diagram of the structure of the diode device with programmable on-current in the HRS and LRS of the present invention;

[0039] Figure 2 A current-voltage characteristic diagram of a diode device with programmable on-current according to the present invention;

[0040] Figure 3 The figure is a flow chart of the germanium (Ge)-based array preparation process in the present invention;

[0041] Figure 4 The figure is a flow chart for preparing an array based on germanium on insulating layer (GOI) in the present invention;

[0042] Figure 5 The operation mode of the array in the present invention;

[0043] Figure 6 is the read disturbance test result of the array in the present invention;

[0044] Figure 7 The erase interference test results of the array in the present invention are as follows;

[0045] Figure 8 The self-rectification reliability test results of the array in the present invention;

[0046] Figure 9 The figure shows the flow chart and three-dimensional structure diagram of the 3D array preparation based on germanium (Ge) in the present invention. DETAILED DESCRIPTION

[0047] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments. It is intended to provide a basic understanding of the present invention and is not intended to confirm the key or decisive elements of the present invention or the scope to be protected. It is easy to understand that without changing the essential spirit of the present invention, various replacements, changes and modifications are possible by those skilled in the art without departing from the spirit and scope of the present invention and the appended claims. Therefore, the following specific embodiments and the accompanying drawings are only exemplary illustrations of the technical solution of the present invention and should not be regarded as the entirety of the present invention or as a definition or limitation of the technical solution of the present invention.

[0048] Figure 1 The figure is a schematic diagram of the structure of the diode device with programmable on-current in the HRS and LRS of the present invention. The diode device with programmable on-current provided by the present invention includes a metal structure, a resistive switching structure and a semiconductor structure. The resistance of the resistive switching structure can be adjusted to achieve programmable on-current. The semiconductor structure is composed of a semiconductor, and the state density function of the semiconductor contains at least one peak, so that the state density near the peak energy level is much greater than the state density of the semiconductor structure at energy levels other than the peak; the metal structure, the resistive switching structure and the semiconductor structure are directly connected in sequence. The CF in the resistive switching structure forms a Schottky junction with the semiconductor structure.

[0049] Figure 2 This is a current-voltage characteristic diagram of the programmable on-current diode device of the present invention. Specifically, when a small positive voltage is applied to the metal structure and current is not limited, the resistive switching structure in the LRS state disconnects the CF at the interface between the resistive switching structure and the metal structure, transforming the resistive switching structure into the HRS state. When a large positive voltage is applied to the resistive switching structure in the HRS state and current is limited, the CF reconnects, transforming the resistive switching structure into the LRS state. Due to the potential barrier between the semiconductor structure and the CF, the reverse current of the device in both the HRS and LRS states is extremely low.

[0050] The self-rectification ratio is defined as the ratio of the forward current to the reverse current when a read voltage of the same magnitude and opposite polarity is applied to the device in LRS. In this embodiment, when the read voltage is 0.8V, the self-rectification ratio is greater than 10 5 , significantly suppressing the bypass current. As previously mentioned, if the device area is further reduced, the self-rectification ratio can be further improved. The device area and self-rectification ratio are not limited by this embodiment.

[0051] Furthermore, the metal structure is composed of one or more metals, including but not limited to TiN, Ni, W, Ti, Al, Pd, Pt, Au, and Ru. The resistive switching structure is a unipolar resistive switching oxide layer composed of one or more oxides, including but not limited to TiO2, NiO, Ni2O3, Y2O3, HfO2, WO3, ZrO2, and Ta2O5. The semiconductor material of the semiconductor structure includes but is not limited to Ge, SiGe, GaAs, GaN, SiC, and Ga2O3, and the state density function contains at least one peak located near the band gap.

[0052] Figure 3 The figure is a flow chart for preparing the germanium (Ge)-based array in the present invention.

[0053] The following describes in detail the various components and specific steps of this embodiment:

[0054] 101——Substrate 102——Strip region (bit line) 201——Isolation layer

[0055] 202——Resistive switching structure 301——Metal structure (word line) 302——Bit line lead electrode

[0056] S1: pre-treatment and cleaning of 101;

[0057] S2: forming spaced strip regions 102 on the structure cleaned in S1 by ion implantation;

[0058] S3: growing 201 on the structure obtained in S2, which acts as an isolation device, reduces parasitic capacitance and provides contact with the metal layer, and etching 201 to form strip-shaped grooves arranged at intervals;

[0059] S4: growing 202 on the structure obtained in S3;

[0060] S5: growing 301 on the structure obtained in S4, and etching to form strip-shaped word lines arranged at intervals.

[0061] S6: forming a heavily doped region at the same end of each strip 102 in the structure obtained in S5 and growing 302 in the region to form an ohmic contact with 102 .

[0062] In step S1, the 101 in this embodiment is p-type Ge.

[0063] In step S2, the 102 in this embodiment is n-type Ge.

[0064] In step S3, the 201 in this embodiment is 300 nanometers of SiO2.

[0065] In step S4, the 202 in this embodiment is a 5-nanometer unipolar oxide. After the device is formed, a stable conductive CF channel exists therein and forms a Schottky contact with 102.

[0066] In step S5, the 301 in this embodiment is a 100-nanometer metal.

[0067] In step S6 , the 302 in this embodiment is a 100-nanometer metal that can form an ohmic contact with the heavily doped region in 102 .

[0068] Figure 4 The figure is a flow chart for preparing the array based on germanium on insulating layer (GOI) in the present invention.

[0069] The following describes in detail the various components and specific steps of this embodiment:

[0070] 401——Substrate 402——Strip region (bit line) 501——Resistive switching structure

[0071] 601——Metal structure (word line) 602——Bit line lead electrode

[0072] S1: forming strip-shaped regions 402 arranged at intervals on 401 by etching.

[0073] S2: Grow 501 on the structure obtained in S1.

[0074] S3: growing 601 on the structure obtained in S2, and etching to form strip-shaped word lines arranged at intervals.

[0075] S4: A heavily doped region is formed at the same end of each strip 402 in the structure obtained in S5 and 602 is grown in the region to form an ohmic contact with 402 .

[0076] In step S1, in this embodiment, the 401 is an insulating layer (Si / SiO2), and the 402 is n-type Ge.

[0077] In step S2, the 501 in this embodiment is a 5-nanometer unipolar oxide. After the device is formed, a stable conductive CF channel exists in the unipolar oxide and forms a Schottky contact with 402.

[0078] In step S3, the 601 in this embodiment is a 100-nanometer metal.

[0079] In step S5 , the 602 in this embodiment is a 100-nanometer metal that can form an ohmic contact with the heavily doped region in 402 .

[0080] The preparation methods of the metal structure, resistive switching structure and semiconductor structure include but are not limited to thermal evaporation, sputtering, atomic layer deposition, chemical vapor deposition, electron beam evaporation, molecular beam epitaxy and pulsed laser deposition.

[0081] Figure 5 This is the operation mode of the array in the present invention.

[0082] Read operation: Select the word line corresponding to the device unit and apply the read voltage V read , select the bit line corresponding to the device unit and apply 0V. Connect other ports to 0V or leave them floating.

[0083] Erase and write operation: Select the word line corresponding to the device unit and apply the operating voltage V write , select the bit line corresponding to the device unit and apply 0V. Other word lines are connected to 0V or left floating, and other bit lines are connected to V write .

[0084] Figure 6 This is the read disturbance test result of the array in the present invention.

[0085] The device has strong anti-read disturb capability, which can effectively avoid interference with other devices in the array when reading the status of the device unit.

[0086] Figure 7 This is the erase / write interference test result of the array in the present invention.

[0087] The erase and write operations utilize a V operating voltage scheme, where reverse voltage is applied only to the reversely selected device cells in the array. When the reverse voltage reaches 4V, the reversely selected device cells maintain good anti-interference capabilities, ensuring that the array can be erased and written.

[0088] Figure 8 The following are the self-rectification reliability test results of the array in the present invention.

[0089] Erase and write operations utilize a V operating voltage scheme. When reverse-selected, devices in the array are subject to reverse voltage, potentially degrading the Schottky junction. The devices maintain a stable self-rectification ratio even at reverse voltages up to 4V, ensuring reliable rectification during the erase and write process.

[0090] Figure 9 The figure shows the flow chart and three-dimensional structure diagram of the 3D array preparation based on germanium (Ge) in the present invention.

[0091] The following describes in detail the various components and specific steps of this embodiment:

[0092] 801——Substrate 802——Ge stress buffer layer 803——SiGe

[0093] 804 - Heavily doped Ge (bit line) 901 - Isolation layer 902 - Semiconductor structure

[0094] 903——Resistive switching structure 904——Resistive switching structure protection layer 905——Metal structure (word line)

[0095] S1: Grow 802 on 801, and then grow 803 / 804 / 803 / 804 / 803 / 804 / 803 in sequence.

[0096] S2: Selectively etch 803 on the structure obtained in S1 and fill 901.

[0097] S3: Selectively etch 804 on the structure obtained in S2 and fill 902.

[0098] S4: Grow 903 and 904 on the structure obtained in S3.

[0099] S5: The device region on the structure obtained in S4 is selectively etched 904 and grown 905 to form word lines.

[0100] In step S1 , in this embodiment, 801 is a Si substrate, and 802 is a Ge stress buffer layer (Ge SRB).

[0101] In step S2, 901 in this embodiment is silicon dioxide.

[0102] In step S3, the 902 in this embodiment is n-type Ge.

[0103] In step S4, the 903 in this embodiment is a 5 nm unipolar oxide. After device formation, a stable conductive CF channel exists in it and forms a Schottky contact with 902. The 904 is a SiN protective layer that can protect 903 outside the device area.

[0104] In step S5, the 905 in this embodiment is a 100-nanometer metal.

[0105] The preparation methods of the metal structure, resistive switching structure and semiconductor structure include but are not limited to thermal evaporation, sputtering, atomic layer deposition, chemical vapor deposition, electron beam evaporation, molecular beam epitaxy and pulsed laser deposition.

[0106] The above description is only a preferred embodiment of the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present invention without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a 3D memory array composed of diode devices, characterized in that: The diode device includes a metal structure, a resistive switching structure and a semiconductor structure; the resistance of the resistive switching structure can be adjusted to achieve programmable conduction current; The semiconductor structure is composed of a semiconductor, and the state density function of the semiconductor includes at least one peak, so that the state density near the peak energy level is much greater than the state density of the energy level of the semiconductor structure other than the peak; The metal structure, the resistive switching structure, and the semiconductor structure are directly connected in sequence; the semiconductor structure is made of Ge, and the method includes the following steps: S1: Grow a Ge stress buffer layer on a semiconductor silicon substrate, then cyclically grow SiGe and heavily doped Ge, with the top layer being SiGe; the heavily doped Ge serves as the bit line; the number of cycles is greater than or equal to 2; S2: Selectively etching SiGe on the structure obtained in S1 and filling the isolation layer; S3: Selectively etch heavily doped Ge on the structure obtained in S2 and fill it with lightly doped Ge; S4: growing a resistive switching structure and a protective layer on the structure obtained in S3; S5: Selectively etching the protective layer in the device area on the structure obtained in S4, and growing a metal structure to form a word line; growing metal at the same end of each bit line to form an extraction electrode of the bit line.

2. The preparation method according to claim 1, characterized in that The bit line region to which the extraction electrode of the bit line is directly connected is a heavily doped semiconductor, so that tunneling current dominates, thereby ensuring ohmic contact. In this case, the extraction electrode is a common metal; Alternatively, the extraction electrode of the bit line is a metal that can form an ohmic contact with the semiconductor structure. In this case, the bit line region directly connected to the extraction electrode is not required to be a heavily doped semiconductor.

3. The preparation method according to claim 1, characterized in that The metal structure is composed of one or more metals, including TiN, Ni, W, Ti, Al, Pd, Pt, Au, and Ru; the resistive switching structure is a unipolar resistive switching oxide layer, composed of one or more oxides, including TiO2, NiO, Ni2O3, Y2O3, HfO2, WO3, ZrO2, and Ta2O5.

4. The preparation method according to claim 1, characterized in that By adjusting the voltage and current limiting value applied to the metal structure, the resistive switching structure can be converted from a low resistance state to a high resistance state in the current conducting direction, and can also be converted from a high resistance state to a low resistance state.

5. The preparation method according to claim 1, characterized in that The semiconductor material of the semiconductor structure includes Ge, SiGe, GaAs, GaN, SiC, and Ga2O3, and the state density function includes at least one peak located near the forbidden band.

6. The preparation method according to claim 1, characterized in that The metallic oxygen vacancy conductive filaments locally existing in the resistive switching structure can be directly connected to the semiconductor structure to form a Schottky contact, and the device behaves as a self-rectifying resistive switching memory.

7. The preparation method according to claim 1, characterized in that When the semiconductor material of the semiconductor structure is a semiconductor that can pin the Fermi level of the metal directly connected to it to near the semiconductor valence band without being affected by the work function of the metal itself, the size of the Schottky barrier at the semiconductor surface mainly depends on the properties of the semiconductor itself.

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