Integration of FinFETs and Schottky diodes on substrate

Abstract

This application relates to integrating a FinFET and a Schottky barrier diode on a substrate. A first fin structure and a second fin structure are formed on the substrate. The first fin structure includes a channel portion extending to two pressure source portions on two opposite sides of the channel portion, and the second fin structure includes a junction portion. The source and drain structures of the FinFET are respectively formed on the two pressure source portions of the first fin structure. A source metal material, a drain metal material, and a first metal material are formed to be electrically coupled to the source structure, the drain structure, and the junction portion of the second fin structure, respectively, thereby providing a Schottky junction between the junction portion of the second fin structure and the first metal material.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 994,781, filed March 25, 2020, entitled "Integration of FinFETs and Schottky Diodes on a Substrate," and U.S. Provisional Application No. 63 / 003,234, filed March 31, 2020, entitled "Integration of FinFETs and Schottky Diodes on a Substrate," each of which is incorporated herein by reference in its entirety. Background Technology

[0003] Over the past few decades, the continuous growth in the size and density of integrated circuits (ICs) has driven various sectors of the high-tech industry. These high-tech industries include semiconductors, electronics, computers and communications, as well as their associated software sectors used to build system platforms and derived applications. To date, this growth in IC size and density has been primarily achieved through the use of new lithography techniques with shorter wavelengths of light and / or through chemical and physical manufacturing processes with desired production yields, reproducibility, and quality control.

[0004] IC development has progressed through multiple technology nodes. Each technology node corresponds to a specific semiconductor manufacturing process, design rules, circuit generation, and architecture. Each technology node is achieved by reducing the size of the IC, improving the performance of metal-oxide-semiconductor field-effect transistors (MOSFETs), and increasing the layers and density of metal interconnects. Consequently, each new technology node is more complex than the previous one, requiring more expensive microfabrication technologies, facilities, and resources. At each new technology node, the tools, time, and manpower required to implement very large-scale integrated circuits (VLSI) also become more complex and expensive. Before the 20nm technology node, MOSFETs were integrated on substrates with planar structures, and three-dimensional (3D) structures began to be used to add height to the channel width beyond this technology node. An example of a 3D MOSFET structure is the fin structure used to construct the transistor channel. However, the deployment of technology nodes has focused on MOSFETs, with little or no involvement of other active semiconductor devices. Compared to current practices, it would be beneficial to integrate different types of semiconductor devices into integrated circuits. Summary of the Invention

[0005] This application relates to the monolithic integration of FinFETs and Schottky barrier diodes on a substrate in a manner equivalent to semiconductor microfabrication processes. Specifically, this application describes a monolithic IC manufacturing method for P-type and N-type low-threshold Schottky barrier diodes (LtSBDs). These LtSBDs, along with P-type and N-type MOSFETs provided for use in existing or upcoming FinFET technology nodes in large-scale industrial production, thereby implementing a Schottky-based complementary metal-oxide-semiconductor (SCMOS) IC. The microfabrication of the P-type and N-type LtSBDs utilizes additional and specific modules of existing semiconductor microfabrication processes. This additional module is added to a set of modules already in the front-end manufacturing process (FEOL) and mid-end manufacturing process (MOL), for example, fabricated on a P-type bulk silicon substrate. In some embodiments, this additional module includes at least (1) a photolithography process for etching through a dielectric layer to expose a fin structure specifically for fabricating the LtSBD and (2) surface cleaning and preparation on the exposed fin structure. The integration of LtSBD optionally involves an additional critical photomask for this lithography process (e.g., in some cases, the additional critical photomask is fabricated using the tightest tolerance achievable in the corresponding technology node).

[0006] In one aspect of this application, a method is provided for forming an integrated semiconductor device comprising a fin field-effect transistor (FinFET) and a Schottky barrier diode (SBD) on a substrate. The method includes forming a first fin structure and a second fin structure. The first fin structure includes a channel portion extending to two pressure source portions on two opposing sides of the channel portion, and the second fin structure includes a junction portion. The method further includes forming a source structure and a drain structure of the FinFET on the two pressure source portions of the first fin structure, respectively. The method further includes forming a source metal material, a drain metal material, and a first metal material electrically coupled to the source structure, the drain structure, and the junction portion of the second fin structure, respectively, thereby providing a Schottky junction between the junction portion of the second fin structure and the first metal material.

[0007] In some embodiments, the junction portion extends into the electrode portion of the second fin structure, and a junction path is disposed on the electrode portion of the second fin structure. A second metal material is electrically coupled to the junction path of the second fin structure. Therefore, in the Schottky barrier diode, the junction portion of the second fin structure is electrically coupled to the second metal material via the junction path and the electrode portion of the second fin structure.

[0008] In some embodiments, a plurality of trenches are defined and include a source trench, a drain trench, and a first trench for respectively receiving the junction portions of the source structure, the drain structure, and the second fin structure. The source, drain, and a first metallic material respectively fill the source trench, the drain trench, and the first trench.

[0009] From another perspective, a method for forming an integrated semiconductor device by forming a first fin structure and a second fin structure is implemented. The method includes depositing a pressure source layer covering the substrate, the first fin structure, and the second fin structure, and defining a source structure and a drain structure on the pressure source layer. The source structure and the drain structure are respectively disposed on the two pressure source portions of the first fin structure. The method further includes forming a source metal material, a drain metal material, and a first metal material electrically coupled to the junction portions of the source structure, the drain structure, and the second fin structure, respectively. A FinFET is formed on the substrate and includes the channel portion of the first fin structure, the source structure, and the drain structure, and a Schottky barrier diode is formed on the substrate and includes a Schottky junction between the junction portion of the second fin structure and the first metal material.

[0010] In another aspect, an integrated semiconductor device includes a substrate, a FinFET, and a Schottky barrier diode. The FinFET is formed on the substrate and has a first fin structure, a gate dielectric, a gate, a source structure, and a drain structure. The first fin structure includes a channel portion extending to two pressure source portions on two opposite sides of the channel portion. The source structure is electrically coupled to a source metal material, and the drain structure is electrically coupled to a drain metal material. The Schottky barrier diode is formed on the substrate and has a second fin structure and a first metal material. The second fin structure includes a junction portion, and the junction portion forms a Schottky junction with the first metal material. The first fin structure and the second fin structure are made of the same type of material, optionally with different doping types and concentrations. The same type of conductive material is used to provide the first metal material, the source metal material, and the drain metal material.

[0011] In another aspect, an integrated semiconductor device includes a substrate, a first fin structure and a second fin structure, a source structure and a drain structure, and a conductive material. The first fin structure includes a channel portion extending to two pressure source portions on two opposite sides of the channel portion, and the second fin structure includes a junction portion. The source structure and the drain structure are respectively disposed on the two pressure source portions of the first fin structure. The conductive material further includes a source metal material, a drain metal material, and a first metal material electrically coupled to the junction portions of the source structure, the drain structure, and the second fin structure, respectively. A FinFET is formed on the substrate and includes the channel portion of the first fin structure, the source structure, and the drain structure. A Schottky barrier diode is formed on the substrate and includes a Schottky junction between the junction portion of the second fin structure and the first metal material. Attached Figure Description

[0012] To better understand the various described embodiments, reference should be made to the following detailed description in conjunction with the accompanying drawings, wherein the same element symbols refer to the corresponding parts in all figures.

[0013] Figure 1 Perspective views of the devices and interconnect structures formed during the FEOL and MOL phases of the microfabrication process for forming FinFETs on a substrate, according to some embodiments.

[0014] Figure 2 An enlarged perspective view of a single FinFET according to some embodiments is shown.

[0015] Figure 3 This is a perspective view of a cutout of a FinFET-based integrated circuit containing a Schottky barrier diode, according to some implementation schemes.

[0016] Figure 4A This is a perspective view of a three-dimensional N-type FinFET structure formed on a P-type substrate according to some implementation schemes, and Figure 4B , 4C Figures 4D and 4D are cross-sectional views of the N-type FinFET structure at lines AA', BB', and CC', respectively.

[0017] Figure 5A This is a perspective view of a three-dimensional N-type SBD structure formed on a P-type substrate according to some implementation schemes, and Figure 5B , 5C 5D and 5D are cross-sectional views of the N-type SBD structure at lines AA', BB' and CC', respectively.

[0018] Figure 6AThis is a perspective view of another three-dimensional N-type FinFET structure formed on a P-type substrate and using a silicide-based metallic material, according to some implementation schemes. Figure 6B , 6C Figures 6 and 6D are cross-sectional views of this N-type FinFET structure at lines AA', BB', and CC', respectively.

[0019] Figure 7A This is a perspective view of another three-dimensional N-type SBD structure formed on a P-type substrate and using a silicide-based metallic material, according to some implementation schemes. Figure 7B , 7C 7D and 7D are cross-sectional views of this N-type SBD structure at lines AA', BB' and CC', respectively.

[0020] Figure 8A This is a perspective view of a P-type FinFET structure formed on a P-type substrate according to some implementation schemes, and Figure 8B , 8C Figures 8 and 8D are cross-sectional views of the P-type FinFET structure at lines AA', BB', and CC', respectively.

[0021] Figure 9A This is a perspective view of a P-type SBD structure formed on a P-type substrate according to some implementation schemes, and Figure 9B , 9C 9D and 9D are cross-sectional views of the P-type SBD structure at lines AA', BB' and CC', respectively.

[0022] Figure 10A This is a perspective view of an N-type FinFET structure formed on a silicon-on-insulator (SOI) substrate according to some embodiments, and Figure 10B , 10C 10D and 10D are cross-sectional views of the N-type FinFET structure at lines AA', BB' and CC' according to some implementation schemes.

[0023] Figure 11A This is a perspective view of an N-type SBD structure formed on an SOI substrate according to some implementation schemes, and Figure 11B , 11C 11D and 11D are cross-sectional views of the N-type SBD structure at lines AA', BB' and CC' according to some implementation schemes.

[0024] Figures 12A to 12C These are three cross-sectional views of the SBD structure based on some implementation schemes.

[0025] Figure 13 It is a process for the self-aligned quadruple patterning (SAQP) process applied to the formation of fin structures, spacers and interconnects in FinFET and SBD structures, according to some implementation schemes.

[0026] Figure 14 This is a flowchart of a method for forming an integrated semiconductor device on a substrate according to some implementation schemes.

[0027] The same component symbol refers to the corresponding part in all several views of the drawing. Detailed Implementation

[0028] This application relates to a Schottky-based complementary metal-oxide-semiconductor (SCMOS) technology that integrates P-type and / or N-type Schottky barrier diodes (SBDs) during SCMOS microfabrication. The Schottky barrier diode includes a metal plate disposed on a semiconductor fin structure, optionally surrounding the top or walls of the semiconductor fin structure. The fin structure used in the Schottky barrier diode is doped with a predetermined doping concentration of P-type or N-type impurity atoms. Examples of P-type impurity atoms include boron (B), and examples of N-type impurity atoms include phosphorus (P) or arsenic (As). The metal plate and fin structure thereby create rectifier contacts (i.e., Schottky junctions). The metal plate refers to the barrier metal. The electronic operation and physical model of the rectifier contacts are determined by the electrical properties of the barrier metal.

[0029] Schottky barrier diodes exhibit conductivity characteristics determined by the material composition of the barrier metal and the semiconductor fin structure, and more specifically, by the impurity characteristics of the fin structure at the Schottky junction of the diode and the physical properties of the metal-to-semiconductor interface. Examples of the electronic properties of this metal-to-semiconductor interface include (but are not limited to) the barrier height associated with the turn-on / turn-off voltage of the Schottky barrier diode. In some embodiments, the combination of the barrier metal and the semiconductor fin structure results in a relatively low barrier height and turn-on / turn-off voltage for the Schottky barrier diode compared to the threshold voltage of a MOSFET integrated in SCMOS technology. Therefore, Schottky barrier diodes with lower turn-on / turn-off voltages are also referred to as low-threshold Schottky barrier diodes (LtSBDs).

[0030] Examples of barrier metals include (but are not limited to) nickel silicide (e.g., NiSi) or cobalt silicide (e.g., CoSi2). Other materials may optionally be used as barrier metals when the surface is lightly doped with metallic materials, oxygen, and / or hydrogen impurity atoms, or when the surface is coated with a thin layer of metallic material (e.g., nickel, nickel silicide, cobalt, cobalt silicide, and the like). Impurity doping techniques involve implanting ionized atomic ions into a target and in-situ physical / chemical deposition of a thin layer of material containing impurity atoms. In some cases, thermal annealing (i.e., controlled heating cycles at elevated temperatures) is performed after ion implantation or in-situ deposition to drive impurity atoms to a certain depth in the target and activate a localized crystal structure. Through these methods, specific electronic properties of semiconductor devices can be achieved individually and in dedicated groups, and the entire IC can be tested and qualified as a reliable product with desired performance across a range of operating conditions and application environments.

[0031] In various embodiments of this application, the integration of a Schottky barrier diode in a CMOS microfabrication process is achieved by introducing at least one new photomask and its associated set of photosensitive steps. This new photomask is used to identify the location of the fin structure of the Schottky barrier diode. The Schottky barrier diode also corresponds to one or more specific processing operations on its fin structure, and requires modification of the existing photomask applied in the CMOS microfabrication process. For example, the photomask is modified to maintain a polygon of a dielectric at the location of the Schottky barrier diode to expose or protect the fin structure and its surrounding environment from the effects of the corresponding material processing operations. Optionally, the existing photomask is modified by inserting logic formulas into computer-aided design (CAD) software tools to control the photomask fabrication machine to print the circuit and device layout onto the photomask.

[0032] In some implementations, FinFETs and Schottky barrier diodes are integrated within the FinFET 14nm technology node. The substrate for integrating the FinFETs and Schottky barrier diodes is optionally a portion of a single-crystal silicon wafer or a silicon-on-insulator (SOI) wafer. The single-crystal silicon wafer is optionally doped with boron (B) or phosphorus (P) to provide a P-type or N-type silicon substrate, respectively. On the SOI wafer, fin structures are formed by selectively etching a single-crystal silicon layer deposited on an insulator of the SOI wafer. Alternatively, in some implementations, the fin structures are formed by a selective epitaxial process comprising forming trenches on a hard mask layer and filling the trenches with a semiconductor material used to form the fin structures. Similar selective epitaxial processes are applied to form silicon-germanium (SiGe) P+ source / drain structures and silicon carbide (SiC) N+ source / drain structures. The insulator is optionally a silicon dioxide (SiO2) layer or a sapphire (Al2O3) layer formed on top of the silicon substrate. In some implementations, the substrate is part of a sapphire wafer or any other electrical insulator.

[0033] Figure 1 This diagram shows perspective views of devices and interconnect structures formed during the FEOL and MOL phases of a microfabrication process 100 for forming FinFETs on a substrate, according to some embodiments. Each of the FEOL and MOL phases of the microfabrication process 100 includes a corresponding sequence of semiconductor processing operations. Each semiconductor processing operation relates to a corresponding manufacturing apparatus. In some embodiments, subsets of the processing operations are grouped into modules based on photolithography operations.

[0034] In some implementations, the FEOL is the first part of a microfabrication process 100, in which individual devices (transistors, capacitors, resistors, Schottky barrier diodes) are patterned on a substrate. The FEOL covers semiconductor processing operations (e.g., ion implantation, thin film deposition, and patterning) prior to the deposition of metal interconnect layers. The FEOL comprises multiple patterning modules. These patterning modules can be refined and reused to reduce the feature size printed by photolithography equipment and the technology selected for the patterning modules. Reference Figure 1 Multiple fin structures 102 are defined on a substrate 104 with shallow trench isolation. A sacrificial gate 106 is formed on the fin structure 102. A dielectric spacer 108 is formed around the fin structure 102 to separate the fin structure 102 from the corresponding source and drain structures 110. The source and drain structures are implanted with high-dose impurities. The sacrificial gate 106 is replaced with a gate 112 and a gate dielectric (e.g., HfO2 or other high-k dielectric). Trenches are formed on the substrate and filled with a metallic material 114 (e.g., NiSi, NiSi2) to connect the source and drain structures 110.

[0035] Alternatively, in some embodiments, the FEOL covers a first set of semiconductor processing operations up to the formation of the source and drain structures 110 and gate 112 of the MOSFET, and the MOL includes a second set of semiconductor processing operations that establish contacts from the lowest metal interconnect layer to the source and drain structures 110 of the MOSFET. The MOL (also referred to as MOL) includes patterning and etching trenches and filling the trenches with a nickel silicide-based material 114 to contact the source and drain structures 110. When the lowest metal interconnect layer (also referred to as the M1 layer) is deposited during the back-to-back fabrication process (BEOL) of the microfabrication process 100, the source and drain structures 110 are electrically coupled to the lowest metal interconnect layer via the nickel silicide-filled trenches 114.

[0036] In some embodiments, the microfabrication process 100 uses deep ultraviolet (DUV) light provided by a light source having a wavelength of 193 nm to perform DUV immersion lithography (DUVIL). In some embodiments, the microfabrication process 100 uses extreme ultraviolet (EUV) light provided by a light source having a wavelength of 13.5 nm to perform EUV lithography.

[0037] The microfabrication process 100 includes a series of ion implantation operations that create various P-type and N-type structures in MOSFETs, thereby generating different turn-on / turn-off voltages, threshold voltages, conduction strengths, leakage currents, maximum operating voltages, and other electronic characteristics. These various P-type and N-type structures are necessary for efficient very large-scale silicon integrated (VLSI) circuits using P-type and N-type MOSFETs, as well as for custom VLSI circuits for different applications and environments.

[0038] Figure 2 This image shows an enlarged perspective view of a single FinFET 200 according to some embodiments. The outline and boundaries of the ion implantation profile are not included. The FinFET 200 corresponds to a shallow trench isolation region 204 on a semiconductor substrate 202, and a fin structure 206 is formed within the shallow trench isolation region 204. The shallow trench isolation region 204 is made of a dielectric (e.g., silicon oxide, nitride, oxynitride), and the fin structure 206 comprises a P-type or N-type semiconductor material (e.g., silicon). In some embodiments, the substrate 202 is recessed on the shown trench isolation region 204 and filled with a dielectric, and the fin structure 206 extends from the body of the substrate 202 and is optionally doped with P-type or N-type impurities. Alternatively, in some embodiments, a layer of dielectric is deposited on top of the substrate 202, and the trench is opened and filled with the fin structure 206 extending to the body of the substrate 202. The fin structure 206 is optionally doped via ion implantation or in-situ deposition.

[0039] The fin structure 206 extends beyond the top surface of the trench isolation region 204 to provide the channel portion 206A of the FinFET 200. The channel portion 206A of the fin structure 206 optionally extends to two pressure source portions on two opposing sides of the channel portion. The source structure 208 and drain structure 210 of the FinFET 200 are formed on the two pressure source portions of the fin structure 206, respectively. If the FinFET 200 is a P-type transistor device, then the source and drain structures 208 and 210 are made of silicon germanium (SiGe) epitaxially grown on the FinFET 200. If the FinFET 200 is an N-type transistor device, then the source and drain structures 208 and 210 are made of silicon carbide (SiC) epitaxially grown on the FinFET 200. Reference Figure 2 The pressure source portion may be partially or completely recessed into the channel portion 206A, and therefore, the source and drain structures 208 and 210 are solid structures that contact the remaining pressure source portion or the channel portion 206A. Alternatively, in some embodiments, the pressure source portion is not recessed, and the source and drain structures 208 and 210 partially surround the pressure source portion of the fin structure 206.

[0040] Low threshold Schottky barrier diodes based on Figure 2Similar device structures as shown are integrated on the same substrate 202. The channel portion 206A of the fin structure 206 is used to form the semiconductor side of a Schottky metal-semiconductor junction. In other words, the channel portion 206A of the FinFET is reconfigured as the junction portion of a Schottky barrier diode. At least one of the source and drain structures 208 and 210 is reconfigured as a junction path configured to provide a conductive path to the semiconductor side of the Schottky barrier diode (i.e., the channel portion 206A).

[0041] The FinFET and Schottky barrier diodes are defined by different semiconductor operations on the channel portion 206A of the fin structure 206. When the portion 206A of the fin structure 206 is covered by the gate dielectric and the gate, the fin structure 206 is configured to provide a channel for a FinFET 200 having source and drain structures 208 and 210 disposed on two opposite sides of the channel. Conversely, when the portion 206A of the fin structure 206 is protected from being covered by the gate dielectric and the gate, the portion 206A of the fin structure 206 can be electrically coupled to the same conductive material for receiving the source and drain structures 208 and 210. A Schottky metal-semiconductor junction is formed between the conductive material and the portion 206A of the fin structure 206, thereby providing a Schottky barrier diode based on the fin structure 206. Further details of the integration of the FinFET and Schottky barrier diodes will be described below with respect to Figures 4 through 12.

[0042] Figure 3This is a cutaway perspective view of a FinFET-based integrated circuit 300 including a Schottky barrier diode according to some embodiments. The FinFET-based IC 300 is formed on a bulk silicon single-crystal substrate 302. The substrate 302 includes a plurality of N-type wells, a plurality of P-type wells, an isolation insulator 304, and a fin structure 306 insulated by the isolation insulator 304. See item 1. The fin structure 306 rises above the isolation insulator 304. In the FinFET, each corresponding fin structure 306 includes a channel portion covered by a gate dielectric and a gate sequence. Examples of gate dielectrics include high-k dielectrics (e.g., hafnium oxide). In an example, silicon nitride and hafnium oxide insulators 308 optionally surround the metal gate of the FinFET in the FinFET-based IC 300. See item 3. Silicon germanium (SiGe) is epitaxially grown and patterned to define the source and drain structures 310A of a P-type FinFET, and silicon carbide (SiC) is epitaxially grown and patterned to define the source and drain structures 310B of an N-type FinFET, respectively. See item 4. Conversely, in a Schottky barrier diode, each corresponding fin structure 306 includes a junction portion not covered by the gate dielectric and the gate. The junction path is formed of silicon germanium (SiGe) or silicon carbide (SiC) to connect the junction portion of each Schottky barrier diode, while SiGe and SiC are deposited and patterned to form the source and drain structures 310 of the FinFET.

[0043] A dielectric layer 312 (e.g., silicon oxide) is applied to cover the fins and the source and drain structures of each FinFET and the fin structure and junction path of each Schottky barrier diode. See item 2. Multiple trenches are drilled in the dielectric layer 312 and filled with a conductive material 314 to connect the source and drain structures 310 of the FinFET and the fin structure and junction path of the Schottky barrier diode of the FinFET-based IC 300. An example of the conductive material 314 is nickel silicide. Nickel silicide comprises several intermetallic compounds of nickel and silicon, such as Ni3Si, Ni... 31 Si 12Ni2Si, Ni3Si2, NiSi, and NiSi2. In examples, nickel disilicide is thus used as the metal side of each Schottky barrier diode and acts as the anode or cathode when it forms a Schottky junction with an N-type or P-type fin structure, respectively. In some cases, for example after forming multiple trenches, a photomask is added to expose the fin structure of the Schottky barrier diode of IC 300 to the conductive material 314. See item 6. In some embodiments, selective epitaxy of SiGe and SiC (e.g., for source and drain structures 310) is partially blocked on the junction portion of the fin structure of each Schottky barrier diode, which is reserved for depositing conductive material 314 (e.g., NiSi2) to form the anode or cathode contacts of the Schottky barrier diode via self-aligned patterning. See item 7. Furthermore, in some embodiments, the Schottky barrier diode is P-type, and a triple-well implantation is used to isolate the anode made of the P-type fin structure and the P-type substrate 302. See item 8. Therefore, existing operations in the CMOS microfabrication process are reconfigured to fabricate and integrate Schottky barrier diodes on the same substrate 302 as the FinFET-based IC 300.

[0044] The FinFET-based IC 300 further includes a plurality of metal plugs 316 formed on top of trenches filled with conductive material 314. The plurality of metal plugs 316 are electrically coupled to the source and drain structures 310 of the FinFET and the metal and semiconductor sides of the Schottky barrier diode. The plurality of metal plugs 316 are then interconnected with each other via a plurality of interconnect layers 318. In an example, the metal plugs 316 and the interconnect layers 318 are made of copper and tantalum nitride. See item 5.

[0045] Figure 4A This is a perspective view of a three-dimensional N-type FinFET structure 400 formed on a P-type substrate 405 according to some implementation schemes, and Figure 4B , 4C Figures 4 and 4D are cross-sectional views of the N-type FinFET structure 400 at lines AA', BB', and CC', respectively. Figure 5A This is a perspective view of a three-dimensional N-type SBD structure 500 formed on a P-type substrate 405 according to some embodiments, and Figure 5B , 5C Figures 5D and 5D are cross-sectional views of the N-type SBD structure 500 at lines AA', BB', and CC', respectively. The N-type FinFET structure 400 and the N-type SBD 500 are optionally formed on different regions of the P-type substrate 405, and in... Figures 4A to 4DComparison with 5A to 5D. FinFET structure 400 has a first fin structure 402, a gate dielectric 404, a gate 406, a source structure 408, and a drain structure 410. The first fin structure 402 includes a channel portion 402A extending to two pressure source portions 402B on two opposite sides of the channel portion 402A. The source structure 408 is electrically coupled to a source metal material 412, and the drain structure 410 is electrically coupled to a drain metal material 414. SBD structure 500 has a second fin structure 502 and a first metal material 504. The second fin structure 502 includes a junction portion 502A, and the junction portion forms a Schottky junction with the first metal material 504. The same type of conductive material is used to provide the first, source, and drain metal materials 504, 412, and 414. Reference Figure 5B and 5D The first metal material 504 includes a first metal layer 504A and a second metal layer 504B. The second metal layer 504B contacts the junction portion 502A of the second fin structure 502 and includes one of cobalt silicide and nickel silicide. The thickness of the first metal layer 504A is greater than the thickness of the second metal layer 504B. Optionally, the first metal layer 504A is made of tungsten or a tungsten alloy. Similarly, each of the source and drain metal materials 412 and 414 includes a corresponding first metal layer and a corresponding second metal layer.

[0046] Junction portion 502A extends into electrode portion 502B in second fin structure 502, and junction passage 506 is formed on electrode portion 502B of second fin structure 502, for example, defined on a pressure source layer bonded to source and drain structures 408 and 410. In an example, assuming FinFET 400 and SBD 500 are N-type, then source structure 408, drain structure 410, and junction passage 506 are doped with arsenic or phosphorus. In some embodiments, source structure 408, drain structure 410, and junction passage 506 are pressure source structures epitaxially grown on second fin structure 502, and optionally made of silicon carbide (SiC). Furthermore, in some embodiments, electrode portion 502B of second fin structure 502 is at least partially recessed (516) and electrically coupled to junction passage 506. If the electrode portion 502B of the second fin structure 502 is completely recessed, then the junction path 506 is electrically coupled to the remaining portion of the second fin structure 502. Similarly, in some embodiments, a subset of the pressure source portion of the first fin structure 402 may be partially or completely recessed, while allowing the source or drain structure to remain electrically coupled to the first fin structure 402.

[0047] The second metal material 508 is electrically coupled to the junction path 506 and forms an ohmic contact with the junction path 506. Optionally, like the first metal material, source metal material, and drain metal material, the second metal material 508 includes a first metal layer 508A and a second metal layer 508B that forms an ohmic contact with the junction path 506. Therefore, in the N-type SBD 500, the junction portion 502A of the second fin structure 502 (N-type) is electrically coupled to the second metal material 508 via the junction path 506 (N-type) and the electrode portion 502B of the second fin structure 502 (N-type).

[0048] In some embodiments, the first, second, source, and drain metal materials 504, 508, 408, and 410 are defined by a first trench, a second trench, a source trench, and a drain trench formed on a substrate 405. These trenches are etched through a dielectric layer to access the junction portion 502A, the junction path 506, the source structure 408, and the drain structure 410. The metal materials 504, 508, 408, and 410 fill the first, second, source, and drain trenches to provide conductive paths to the junction portion 502A, the junction path 506, the source structure 408, and the drain structure 410, respectively.

[0049] In some embodiments, a plurality of metal plugs are formed on a plurality of trenches and metal materials. The plurality of metal plugs includes a first plug 510 electrically coupled to a first metal material 504 filling a first trench, and a second plug 512 electrically coupled to a junction portion 502A of a second fin structure 502 via a second metal material 508 filling a second trench, a junction path 506, and an electrode portion 502B of a second fin structure 502. In this manner, the first and second plugs 510 and 512 form anodes and cathodes configured to electrically connect to the metal and semiconductor sides of the Schottky junction of the SBD 500, respectively. Conversely, the plurality of metal plugs includes a source plug 416 and a drain plug 418 formed on and electrically coupled to the source and drain structures 408 and 410 of the FinFET 400, respectively.

[0050] In some embodiments, the second fin structure 502 further includes a spacer portion 502C connecting the junction portion 502A to the electrode portion 502B, and the junction passage 506 at least partially surrounds the electrode portion 502B and does not contact any surface of the spacer portion 502C. A diode spacer 514 is deposited on the spacer portion 502C and optionally partially surrounds the spacer portion 502C. The diode spacer 514 is configured to separate the junction passage 506 from the first metal material 504. Conversely, a transistor spacer 422 is formed adjacent to the gate dielectric 404 and the gate 406 to separate the gate 406 from the source and drain structures. The diode spacer 514 is thicker than the transistor spacer 422, i.e., it has a width (w) greater than the width of the transistor spacer 422.

[0051] It should be noted that the first and second fin structures 402 and 502 can be etched from or deposited onto the top surface of the bulk silicon substrate 405. The first fin structure 402 of the N-type FinFET 400 is P-type, and the second fin structure 502 of the P-type FinFET 500 is N-type. In some embodiments, the FinFET 400 is formed in a P-type well isolated from the bulk of the substrate 405 via a heavily doped N-type region 420A. The FinFET 400 is also isolated from other semiconductor devices on the substrate 405 via one or more doped N-type regions 420B or dielectric material 420C. The SBD 500 is formed in an N-type well on the substrate 405. Alternatively, in some embodiments, the substrate 405 comprises a silicon-on-insulator (SOI) substrate. The first and second fin structures 402 and 502 are isolated from the semiconductor bulk of the SOI substrate via an insulating layer of the SOI substrate.

[0052] In some embodiments, gate dielectric 404 and gate 406 cover a subset or all three exposed sides of the channel portion of the first fin structure 402 of the FinFET 400. In some embodiments, the FinFET 400 has a threshold voltage, and the SBD 500 has a turn-on voltage. The threshold voltage of the FinFET 400 is greater than the turn-on voltage of the SBD 500. In some embodiments, structures associated with the source of the FinFET 400 (e.g., pressure source portion 402B, source structure 408, source metal material 412, and metal plug 416) are shared with structures associated with the source or drain of another N-type FinFET 400, or with structures associated with the cathode of another N-type SBD 500 (e.g., electrode portion 502B, junction path 506, second metal material 508, and metal plug 512). In some implementations, structures associated with the drain of FinFET 400 (e.g., pressure source portion 402B, drain structure 410, drain metal material 414, and metal plug 418) are shared with structures associated with the source or drain of another N-type FinFET 400, or with structures associated with the cathode of another N-type SBD 500 (e.g., electrode portion 502B, junction path 506, second metal material 508, and metal plug 512). Similarly, structures associated with the cathode of another N-type SBD 500 are shared with structures associated with the source or drain of another N-type FinFET 400.

[0053] Figure 6A This is a perspective view of another three-dimensional N-type FinFET structure 600 formed on a P-type substrate 405 and using a silicide-based metal material 602, according to some embodiments. Figure 6B , 6C6D and 6D are cross-sectional views of this N-type FinFET structure 600 at lines AA', BB' and CC', respectively. Figure 7A This is a perspective view of another three-dimensional N-type SBD structure 700 formed on a P-type substrate 405 and using a silicide-based metallic material 702, according to some embodiments. Figure 7B , 7C Figures 7D and 7D are cross-sectional views of the N-type SBD structure 700 at lines AA', BB', and CC', respectively. The N-type FinFET structure 600 and the N-type SBD structure 700 are optionally formed on different regions of the P-type substrate 405, and in... Figures 6A to 6D Comparison with 7A to 7D. The N-type FinFET 600 and N-type SBD 700 are the same as the N-type FinFET 400 and N-type SBD 500, respectively, except that the conductive materials used to connect the source structure 408, drain structure 410, junction portion 502A and junction path 506 are different.

[0054] In some embodiments, the source metal material 412, drain metal material 414, and first metal material 504 are either cobalt silicide or nickel silicide, and a Schottky junction is formed directly between the junction portion 502A of the second fin structure 502 and either cobalt silicide or nickel silicide of the first metal material 504. Examples of cobalt silicide include CoSi2, CoSi, Co2Si, and Co3Si. Furthermore, in some cases, the second metal material 508 is also either cobalt silicide or nickel silicide, forming an ohmic contact with the junction path 506 and providing the path to the junction portion 502A of the second fin structure 502. In some embodiments, metal plugs 510 and 512 are formed on the first and second metal materials 504 and 508, respectively, and serve as portions corresponding to the anode and cathode of the SBD 700.

[0055] In some embodiments, prior to forming the metal materials 412, 414, 504, and 508, a plurality of trenches are formed on the dielectric layer 450, including source trenches, drain trenches, and first trenches for respectively receiving junction portions 502A of the source structure 408, drain structure 410, and second fin structure 502. The source, drain, and first metal materials 412, 414, and 504 are formed by filling the source trench, drain trench, and first trench with source, drain, and first metal materials 412, 414, and 504 having the same processing module, respectively. In some embodiments, a second trench is opened on the dielectric layer 450 having the source trench, drain trench, and first trench, and is filled with a second metal material 508 having the source, drain, and first metal materials 412, 414, and 504.

[0056] In some implementation schemes, refer to Figure 5C and 7CA first metal material 504 surrounds a second fin structure 502. In other words, the first metal material 504 surrounds the top surface 502AA and two side surfaces 502AB of the junction portion 502A of the second fin structure 502. Optionally, the first metal material 504 is in direct contact with a subset or all of the top surface 502AA and two side surfaces 502AB of the junction portion 502A of the second fin structure 502, forming a Schottky junction of the SBD 500. Furthermore, in some embodiments, reference is made to… Figure 5B Junction path 506 is formed not only on one side of the Schottky junction, but also on the other side (i.e., on both sides of the Schottky junction). Therefore, junction portion 502A is electrically coupled to both junction paths 506 to reduce the parasitic resistance of the cathode coupled to the SBD 500 or 700.

[0057] Figure 8A This is a perspective view of a P-type FinFET structure 800 formed on a P-type substrate 405 according to some embodiments, and Figure 8B , 8C Figures 8 and 8D are cross-sectional views of the P-type FinFET structure at lines AA', BB', and CC', respectively. Figure 9A This is a perspective view of a P-type SBD structure 900 formed on a P-type substrate according to some embodiments, and Figure 9B , 9C Figures 9 and 9D are cross-sectional views of the P-type SBD structure at lines AA', BB', and CC', respectively. The P-type FinFET structure 800 and the P-type SBD structure 900 are optionally formed on different regions of the P-type substrate 405, and... Figures 8A to 8D And compared with 9A to 9D. In some embodiments, the N-type FinFET structure 600 and the N-type SBD structure 700 are formed on the same P-type substrate 405 having the P-type FinFET structure 800 and the P-type SBD structure 900.

[0058] FinFET structure 800 has a first fin structure 402, a gate dielectric 404, a gate 406, a source structure 408, and a drain structure 410. The first fin structure 402 includes a channel portion 402A extending to two pressure source portions 402B on two opposing sides of the channel portion 402A. The source structure 408 is electrically coupled to a source metal material 412, and the drain structure 410 is electrically coupled to a drain metal material 414. SBD structure 900 has a second fin structure 502 and a first metal material 504. The second fin structure 502 includes a junction portion 502A, and the junction portion forms a Schottky junction with the first metal material 504. The junction portion 502A extends to an electrode portion 502B in the second fin structure 502, and a junction passage 506 is formed on the electrode portion 502B of the second fin structure 502, for example, defined on a pressure source layer bonded to the source and drain structures 408 and 410. In some implementations, the P-type FinFET 800 has a threshold voltage, and the P-type SBD 900 has a turn-on voltage. The threshold voltage of the FinFET 800 is greater than the turn-on voltage of the SBD 900.

[0059] In this example, assuming the FinFET 800 and SBD 900 are P-type, then the source structure 408, drain structure 410, and junction path 506 are doped with boron. In some embodiments, the source structure 408, drain structure 410, and junction path 506 are pressure source structures epitaxially grown on the second fin structure 502, and optionally made of silicon-germanium (SiGe). In some embodiments, Figure 8C and 9C Each of the P-type source structure 408, drain structure 410, and junction path 506 has a different characteristic from the P-type source structure 408, drain structure 410, and junction path 506. Figure 4C and 5C The geometry of each of the N-type source structure 408, drain structure 410, and junction path 506.

[0060] The second metallic material 508 is electrically coupled to the junction path 506 and forms an ohmic contact with the junction path 506. In the P-type SBD 500, the junction portion 502A of the second fin structure 502 (P-type) is electrically coupled to the second metallic material 508 via the junction path 506 (P-type) and the electrode portion 502B of the second fin structure 502 (P-type). Figures 8A to 8D In some embodiments not shown in 9A to 9D, each of the source metal material 412, drain metal material 414, first metal material 504, and second metal material 508 includes a first metal layer and a second metal layer. The second metal layer contacts corresponding portions of the source structure 408, drain structure 410, junction portion 502A, and junction path 506. The second metal layer may include one of cobalt silicide and nickel silicide. Alternatively, in Figures 8A to 8DIn some embodiments shown in 9A to 9D, the source metal material 412, the drain metal material 414, the first metal material 504 and the second metal material 508 are one of cobalt silicide and nickel silicide, and a Schottky junction is formed between the junction portion 502A and one of cobalt silicide and nickel silicide.

[0061] Furthermore, in some embodiments, multiple metal plugs are formed on multiple trenches and metal materials. The multiple metal plugs include a first plug 510 electrically coupled to a first metal material 504 filling a first trench, and a second plug 512 electrically coupled to a junction portion 502A of the second fin structure 502 via a second metal material 508 filling a second trench, a junction path 506, and an electrode portion 502B of the second fin structure 502. In these ways, the first and second plugs 510 and 512 form cathode and anode portions configured to electrically contact the metal and semiconductor sides of the Schottky junction of the SBD 900, respectively.

[0062] The first fin structure 402 of the P-type FinFET 800 is N-type, and the second fin structure 502 of the P-type SBD 900 is N-type. In some embodiments, the P-type SBD 900 is formed in a P-type well isolated from the bulk of the substrate 405 via a heavily doped N-type region 920A. The SBD 900 is also isolated from other semiconductor devices on the substrate 405 via one or more doped N-type regions 920B. The P-type FinFET 800 is formed in an N-type well on the substrate 405. Alternatively, in some embodiments, the substrate 405 comprises a silicon-on-insulator (SOI) substrate. The first and second fin structures 402 and 502 of the P-type FinFET 800 and SBD 900 are isolated from the semiconductor bulk of the SOI substrate via an insulating layer of the SOI substrate.

[0063] In some embodiments, structures associated with the source of a FinFET 800 (e.g., pressure source portion 402B, source structure 408, source metal material 412, and metal plug 416) are shared with structures associated with the source or drain of another P-type FinFET 800, or with structures associated with the cathode of another P-type SBD 900 (e.g., electrode portion 502B, junction path 506, second metal material 508, and metal plug 512). In some embodiments, structures associated with the drain of a FinFET 800 (e.g., pressure source portion 402B, drain structure 410, drain metal material 414, and metal plug 418) are shared with structures associated with the source or drain of another P-type FinFET 800, or with structures associated with the cathode of another P-type SBD 900 (e.g., electrode portion 502B, junction path 506, second metal material 508, and metal plug 512). Similarly, the structure associated with the cathode of another P-type SBD 900 is shared with the structure associated with the source or drain of another P-type FinFET 800.

[0064] The FinFET and SBD structures in Figures 4 to 9 are formed on a p-type substrate 405. Alternatively, the FinFET and SBD structures are formed on an N-type substrate. The p-type FinFET and N-type SBD structures have N-type fin structures that are isolated from the bulk of the N-type substrate via heavily doped p-type regions and / or from other semiconductor devices on the substrate via one or more doped p-type regions or dielectric material. The N-type FinFET and P-type SBD structures have P-type fin structures optionally formed in p-type wells on the N-type substrate. As explained above, referring to Figures 4 to 9, the FinFET and SBD structures are formed on an N-type substrate in a similar manner to those formed on a p-type substrate. For simplicity, details are not repeated here.

[0065] Figure 10A This is a perspective view of an N-type FinFET structure 1000 formed on a silicon-on-insulator (SOI) substrate 1002 according to some embodiments, and Figure 10B , 10C 10D and 10D are cross-sectional views of the N-type FinFET structure 1000 at lines AA', BB' and CC' according to some implementation schemes. Figure 11A This is a perspective view of an N-type SBD structure 1100 formed on an SOI substrate 1002 according to some embodiments, and Figure 11B , 11CFigures 1000 and 11D are cross-sectional views of the N-type SBD structure 1100 at lines AA', BB', and CC' according to some embodiments. The N-type FinFET structure 1000 and the N-type SBD structure 1100 are optionally formed on different regions of the SOI substrate 1002, and in... Figures 10A to 10D And compare 11A to 11D.

[0066] The first and second fin structures 402 and 502 are isolated from the semiconductor body of the SOI substrate 1102 via an insulating layer 1104. Optionally, the first and second fin structures 402 and 502 are patterned from a semiconductor layer located on top of the insulating layer 1104 of the SOI substrate 1102. Optionally, the first and second fin structures 402 and 502 are deposited on the top surface of the SOI substrate 1102. The first fin structure 402 of the N-type FinFET 1000 is P-type, and the second fin structure 502 of the N-type SBD 1100 is N-type. In some embodiments, the FinFET 1000 or SBD 1100 is isolated from other semiconductor devices on the substrate 1102 via one or more doped regions 420B or dielectric material 420C. The FinFET 1000 and SBD 1100 are separated from the body of the SOI substrate 1102 by the insulating layer 1104. Figures 10A to 10D In some embodiments not shown in 11A to 11D, the fin structure of the P-type FinFET is N-type, and the fin structure of the P-type SBD is P-type. The P-type FinFET or SBD is isolated from other semiconductor devices on its substrate via one or more doped regions or dielectric materials (not shown).

[0067] Figures 12A to 12CThese are three cross-sectional views of an SBD structure 1200 according to some implementation schemes. Integrating P-type and N-type SBDs into the CMOS microfabrication process is implemented by modifying multiple process modules optionally selected by photolithography. First, these process modules exist as part of the FEOL and MOL in the CMOS microfabrication process, or are added to differentiate, improve, simplify, optimize efficiency, reduce cost, or combine thereof for corresponding technology nodes and the production of integrated circuits. Second, in some implementations, ion implantation is applied to define the fin structure of the SBD (i.e., the body of each P-type SBD anode and N-type SBD cathode), diode conduction on / off voltage, series resistance, capacitance, insulating regions from other segments of the fin structure (e.g., regions 420B or 420C), and insulating regions from the N-type or P-type silicon substrate or substrate material (e.g., region 420A). Third, surface cleaning and preparation of the allocated fin segments are performed to prepare the junction portion 502A of a second fin structure 502 for forming the Schottky junction of the SBD. Fourth, dielectric spacers 422 and 514 are deposited using fine-width patterning (e.g., self-aligned quadruple patterning (SAQP) or any other method). Fifth, single-element or composite metal layers are deposited using an electron work function. The electron work function is optimized to establish a reliable Schottky junction in the CMOS microfabrication process. Metal materials that can be used as the semiconductor side of the Schottky junction include (but are not limited to) nickel, nickel silicide, cobalt, cobalt silicide, or other barrier materials that can be used to connect the source and drain structures 408 and 410 and the junction path 506.

[0068] refer to Figure 12A When the gate dielectric 404 and gate 406 are formed on the first fin structure 402, a photomask is added to protect the junction portion 502A of the second fin structure 502 from being covered by the gate dielectric 404 and gate 406. In some embodiments, the second fin structure 502 is disconnected from other fin structures to provide isolation for the SBD 1200, and therefore, the anode and cathode of the SBD structure 1200 are not merged with the source structure 408 or drain structure 410 of other P-type or N-type FinFETs. In an example, the junction portion 502A and electrode portion 502B of the second fin structure 502 do not extend to the two pressure source portions of the first fin structure 402 of another P-type or N-type FinFET. Alternatively, localized P-type or N-type ion implantation is applied to electrically isolate the second fin structure 502 from other semiconductor devices.

[0069] Spacer portions 502C forming diode spacers 514 and second fin structures 502 isolate the anode and cathode of the SBD structure 1200. Metal materials 504 and 508, metal plugs 510 and 512, and the SBD structure 1200 and its adjacent structures are embedded in and separated from a dielectric layer 450, which is optionally a combination of shallow trench isolation (STI) insulator and interlayer dielectric (ILD). The dielectric layer 450 has a substantially low dielectric constant, for example, not greater than the dielectric constant of silicon dioxide (approximately 3.9).

[0070] An ohmic contact is formed along a take-off path starting from the metal plug 512, passing through the second metal material 508, the junction passage 506, and the electrode portion 502B of the second fin structure 502, and reaching the junction portion 502A of the second fin structure 502. A Schottky junction or contact is formed by the first metal material 504 on the three surfaces of the junction portion 502A of the second fin structure 502.

[0071] refer to Figure 12B , which corresponds to Figure 12A The B-B' section in the junction (e.g., by selective epitaxial growth) forms a junction passage 506 to contact the second fin structure 502. Optionally, the second metal material 508 formed on the junction passage 506 includes a first metal layer 508A (e.g., a silicide cap coating the junction passage 506) and a second metal layer 508B filling the second trench. (See reference...) Figure 12C , which corresponds to Figure 12A In the C-C' section, a first metal material 504 is formed on the junction portion 502A of the second fin structure 502. Optionally, the first metal material 504 formed on the junction portion 502A includes a first metal layer 504A (e.g., a silicide cap coating the junction portion 502A) and a second metal layer 504B filling the first trench.

[0072] Figure 13 This is a flow of a self-aligned quadruple patterning (SAQP) process 1300 applied to the formation of fin structures, spacers, and interconnects in FinFET and SBD structures, according to some implementation schemes. The SAQP process includes one or more of the following: mandrel patterning, first spacer deposition, first spacer etching, core removal, amorphous silicon (a-Si) etching, second spacer deposition, second spacer etching, silicon nitride etching, titanium nitride etching, low-k dielectric trench etching, and trench metal filling and chemical mechanical planarization (CMP).

[0073] Figure 14This is a flowchart of a method 1400 for forming an integrated semiconductor device on a substrate according to some embodiments. Method 1400 includes forming a (1402) FinFET and a Schottky barrier diode on a substrate 405. Optionally, substrate 405 comprises a large semiconductor substrate or a silicon-on-insulator (SOI) substrate. Optionally, substrate 405 comprises a dielectric substrate (e.g., a sapphire substrate). In some embodiments, the FinFET has a threshold voltage and the Schottky barrier diode has a turn-on voltage, wherein the magnitude of the threshold voltage is greater than the magnitude of the turn-on voltage.

[0074] A first fin structure 402 and a second fin structure 502 are formed (1404) on a substrate 405. The first fin structure 402 includes a channel portion 402A extending to two pressure source portions 402B on two opposing sides of the channel portion 402A, and the second fin structure 502 includes a junction portion 502A. In some embodiments, the substrate 405 includes a bulk silicon substrate, and the first and second fin structures 402 and 502 are etched from the bulk silicon substrate. Furthermore, in some embodiments, the bulk silicon substrate has a bulk doping concentration, and the junction portion 502A of the second fin structure has a Schottky semiconductor doping concentration different from the bulk doping concentration. In an example, the bulk silicon substrate is P-type, and the Schottky barrier diode is P-type. A first heavily doped N-type region 420A is formed under the second fin structure 502, and one or more second heavily doped N-type regions 420B are formed adjacent to the second fin structure 402 to isolate the Schottky barrier diode from one or more other semiconductor devices on the substrate 405.

[0075] A source structure 408 and a drain structure 410 of a FinFET (1406) are formed on the two pressure source portions 402B of the first fin structure 402, respectively. A gate dielectric 404 and a gate 406 are formed to cover two or more surfaces of the channel portion 402A of the first fin structure. In some embodiments, a sacrificial gate is formed to facilitate the formation of a transistor spacer 422, and is subsequently replaced by the gate dielectric 404 and the gate 406.

[0076] A source metal material 412, a drain metal material 414, and a first metal material 504 are formed (1408) and electrically coupled to the junction portion 502A of the source structure 408, the drain structure 410, and the second fin structure 502, respectively, thereby providing a Schottky junction between the junction portion 502A of the second fin structure 502 and the first metal material 504. In some embodiments, the junction portion extends to the electrode portion in the second fin structure, and a junction path 506 is disposed (1410) on the electrode portion 502B of the second fin structure 502. Optionally, the junction path 506 partially surrounds the electrode portion 502B. A second metal material 508 is formed (1412) and electrically coupled to the junction path 506. In a Schottky barrier diode, the junction portion 502A of the second fin structure is electrically coupled to the second metal material 508 via the junction path 506 and the electrode portion 502B of the second fin structure.

[0077] Furthermore, in some embodiments, the second fin structure 502 further includes a spacer portion 502C connecting the junction portion 502A to the electrode portion 502B, and the junction passage 506 at least partially surrounds the electrode portion 502B and does not contact any surface of the spacer portion 502C. A gate dielectric 404 and a gate 406 are formed to cover two or more surfaces of the channel portion 402A of the first fin structure. A transistor spacer 422 separates the gate 406 from the source structure 408. A diode spacer 514 separates the first metal material 504 from the junction passage 506 or the second metal material 508. The diode spacer 514 is thicker than the transistor spacer 422.

[0078] In some embodiments, FinFET 600 and SBD 700 are N-type. First fin structure 402 is P-type, and second fin structure 502 is N-type. Source structure 408, drain structure 410, and junction path 506 are made of epitaxial silicon carbide. In some embodiments, source structure 408, drain structure 410, and junction path 506 may be doped with arsenic or phosphorus. Conversely, in some embodiments, FinFET 800 and SBD 900 are P-type. First fin structure 402 is N-type, and second fin structure 502 is P-type. Source structure 408, drain structure 410, and junction path 506 are made of epitaxial silicon germanium. In some embodiments, source structure 408, drain structure 410, and junction path 506 may be doped with boron.

[0079] In some embodiments, subsets of the two pressure source portions 402B of the first fin structure 402 and the electrode portion 502B of the second fin structure 502 are at least partially recessed and electrically coupled to the corresponding portions of the source structure 408, the drain structure 410, and the junction path 506.

[0080] In some embodiments, a plurality of trenches are formed, including source trenches, drain trenches, and first trenches for respectively receiving the junction path 506 of the source structure 408, drain structure 410, and second fin structure. The source trenches, drain trenches, and first trenches are filled with source metal material 412, drain metal material 414, and first metal material 504, respectively. In some embodiments, the plurality of trenches include second trenches filled with second metal material 508 for electrically coupling to the junction portion of the second fin structure via the junction path 506 and electrode portion 502B.

[0081] Furthermore, in some embodiments, a plurality of metal plugs are formed on a plurality of trenches. The plurality of metal plugs includes a first plug 510 electrically coupled to a first metal material 412 filling a first trench, and a second plug 512 electrically coupled to a junction portion 502A of a second fin structure via a second metal material 508 filling a second trench, a junction path 506, and an electrode portion 502B of a second fin structure. Conversely, in some embodiments, the plurality of metal plugs includes a source plug 416 and a drain plug 418, respectively electrically coupled to the source and drain structures 408 and 410 of the FinFET.

[0082] In some embodiments, reference Figures 9A to 9D The Schottky barrier diode includes a P-type Schottky barrier diode. The junction portion 502A of the second fin structure is P-type, and the second metal plug 512, the second metal material 508 filling the second trench, the junction path 506, and the electrode portion 502A of the second fin structure form the anode of the Schottky barrier diode. The first metal material 504 and the first metal plug 510 form the cathode of the Schottky barrier diode. Conversely, refer to... Figures 5A to 5D 7A to 7D and 11A to 11D, the Schottky barrier diodes include N-type Schottky barrier diodes. The junction portion 502A of the second fin structure is N-type, and the second metal plug 512, the second metal material 508 filling the second trench, the junction path 506, and the electrode portion 502A of the second fin structure form the cathode of the Schottky barrier diode. The first metal material 504 and the first metal plug 510 form the anode of the Schottky barrier diode.

[0083] In some embodiments, the source metal material 412, drain metal material 414, and first metal material 504 are one of cobalt silicide and nickel silicide, and a Schottky junction is formed between the junction portion 502A of the second fin structure and one of the cobalt silicide and nickel silicide. Alternatively, in some embodiments, each of the source metal material 412, drain metal material 414, and first metal material 504 includes a first metal layer and a second metal layer, the second metal layer contacting a corresponding one of the source structure 408, drain structure 410, and junction portion 502A of the second fin structure. The second metal layer includes one of cobalt silicide and nickel silicide.

[0084] In some implementations, the first fin structure 402 and the second fin structure 502 are formed using the same photomask and processing modules. The first fin structure and the second fin structure can be doped differently using different doping processes. One or more pressure source layers are deposited over the substrate and the first and second fin structures 402 and 502. The source structure 408 and drain structure 410 of the N-type FinFET and the junction path 506 of the N-type SBD are patterned from the same pressure source layer. The source structure 408 and drain structure 410 of the P-type FinFET and the junction path 506 of the P-type SBD are patterned from the same pressure source layer. Multiple trenches are opened on the dielectric layer 450 via the same etching operation. The source metal material, drain metal material, first metal material, and drain metal material have the same type of metal material used to fill the trenches via the same physical or mechanical deposition operation. Similarly, metal plugs 416, 418, 510, and 512 are patterned from the same metal layer.

[0085] Although Schottky barrier diodes are largely compatible with CMOS microfabrication processes, additional photomasks are added and existing photomasks are modified to integrate the Schottky barrier diode. For example, the second fin structure 502 of the Schottky barrier diode is not covered by the gate dielectric 404 and gate 406. One or more photomasks are added to protect the second fin structure 502 from the deposited gate dielectric 404 and gate 406, or the gate dielectric 404 and gate 406 are removed from the second fin structure 502. Further details of the modified CMOS microfabrication process are explained in Table 1 below:

[0086] Table 1: Example Process Integration for Manufacturing Schottky Barrier Diodes

[0087]

[0088]

[0089] Other CMOS microfabrication processes can be similarly modified to integrate Schottky barrier diodes into CMOS integrated circuits.

[0090] In summary, P-type and N-type Schottky barrier diodes are formed of a barrier metal plate, preferably (but not limited to) cobalt silicide or nickel silicide, which contacts one or both walls of the silicon fin segment (e.g., the junction portion 502A of the second fin structure 502 in Figures 5, 7, 9, and 11), and may also contact the top of the silicon fin segment. The silicon fins are preferably defined and constructed using the same microfabrication methods and steps as those used to provide fin structures for FinFETs. Table 2 lists the structures of these diodes and the possible ways to connect their anode (A) and cathode (K) terminals to other circuit components on the silicon substrate:

[0091] Table 2: Components of the LtSBD Structure

[0092]

[0093]

[0094] It should be understood that the specific order of operations described in each of the above figures is for illustrative purposes only and is not intended to indicate that the described order is the only possible order of operations. Those skilled in the art will recognize various ways in which an integrated semiconductor device with FinFETs and Schottky barrier diodes can be formed on the same substrate as described herein. Furthermore, it should be noted that details described with respect to one of the above processes also apply in a similar manner to any of the others. For the sake of brevity, similar details are not repeated.

[0095] It should also be understood that although the terms "first," "second," etc., are used herein (in some instances) to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish elements from one another. For example, without departing from the scope of the various described embodiments, a first type of audio feature may be referred to as a second type of audio feature, and similarly, a second type of audio feature may be referred to as a first type of audio feature. The first type of audio feature and the second type of audio feature are audio feature types, but they are not the same type of audio feature.

[0096] The terminology used in the descriptions of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the descriptions of the various embodiments and in the appended claims, the singular forms “a” and “described” are intended to also include the plural forms, unless the context clearly indicates otherwise. It should be understood that the term “and / or” as used herein refers to and covers any and all possible combinations of one or more associated items. It should be understood that the terms “comprising” and / or “including” as used in this specification specifically mean the presence of the stated feature, integer, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0097] As used herein, the term “if…” may optionally be interpreted as meaning “when…” or “after…” or “in response to determination” or “in response to detection” or “according to determination…”, depending on the context. Similarly, the phrase “if determination…” or “if [a condition or event] is detected” may optionally be interpreted as meaning “after determination…” or “in response to determination…” or “after detection [the condition or event]” or “in response to detection [the condition or event]” or “according to determination of the detected [condition or event]”, depending on the context.

[0098] Although various diagrams illustrate several logical levels in a specific order, levels independent of this order can be reordered and other levels can be combined or decomposed. While some reorderings or other groupings are specifically mentioned, those skilled in the art will understand that other reorderings or groupings exist, and therefore the orderings and groupings presented herein are not an exhaustive list of alternatives. Furthermore, it should be recognized that stages can be implemented in hardware, firmware, software, or any combination thereof.

[0099] For illustrative purposes, the above description has been given reference to specific embodiments. However, the illustrative discussion above is not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Many modifications and variations can be made in light of the teachings above. The embodiments have been chosen to best explain the principles under the claims and their practical application, thereby enabling others skilled in the art to best use the embodiments and various modifications according to the particular purpose contemplated.

Claims

1. A method for forming an integrated semiconductor device, comprising: A fin field-effect transistor and a Schottky barrier diode are formed on a substrate, comprising: A first fin structure and a second fin structure are formed, wherein the first fin structure includes a channel portion extending to two pressure source portions on two opposing sides of the channel portion, and the second fin structure includes a knot portion; The source and drain structures of the fin field-effect transistor are formed on the two pressure source portions of the first fin structure, respectively. A source metal material, a drain metal material, and a first metal material are formed and electrically coupled to the junction portions of the source structure, the drain structure, and the second fin structure, respectively, thereby providing a Schottky junction between the junction portion of the second fin structure and the first metal material. Defining a junction pathway, wherein the junction portion extends into the electrode portion of the second fin structure, and the junction pathway is disposed on the electrode portion of the second fin structure; and A second metallic material is formed to electrically couple to the junction pathway; In the Schottky barrier diode, the junction portion of the second fin structure is electrically coupled to the second metal material via the junction path of the second fin structure and the electrode portion.

2. The method of claim 1, wherein the second fin structure further comprises a spacer portion connecting the junction portion to the electrode portion, and the junction passage at least partially surrounds the electrode portion and does not contact any surface of the spacer portion.

3. The method according to claim 1, comprising: A gate dielectric and a gate are formed covering two or more surfaces of the channel portion of the first fin structure; Forming a transistor spacer that separates the gate from the source structure; and A diode spacer is formed that separates the first metal material from the junction path and the second metal material; The diode spacer is thicker than the transistor spacer.

4. The method according to claim 1, wherein: The fin field-effect transistor is N-type and the Schottky barrier diode is N-type; The source structure, the drain structure, and the junction path are made of epitaxial silicon carbide.

5. The method according to claim 1, wherein: The fin field-effect transistor is P-type and the Schottky barrier diode is P-type; The source structure, the drain structure, and the junction path are made of epitaxial silicon germanium.

6. The method according to claim 1, wherein the fin field-effect transistor is N-type and the Schottky barrier diode is N-type, and the source structure, the drain structure and the junction path are doped with arsenic or phosphorus.

7. The method of claim 1, wherein a subset of the two pressure source portions of the first fin structure is at least partially recessed and electrically coupled to the source structure and the drain structure, and the electrode portion of the second fin structure is at least partially recessed and electrically coupled to the junction path.

8. The method according to any one of the preceding claims, further comprising: Define a plurality of trenches including a source trench, a drain trench, and a first trench for respectively receiving the junction portion of the source structure, the drain structure, and the second fin structure; The formation of the source metal material, the drain metal material and the first metal material includes filling the source trench, the drain trench and the first trench with the source metal material, the drain metal material and the first metal material.

9. The method of claim 8, wherein the plurality of trenches includes a second trench filled with a second metallic material for electrically coupling to the junction portion of the second fin structure via the junction pathway and electrode portion of the second fin structure.

10. The method of claim 9, further comprising: Multiple metal plugs are formed on the multiple grooves; The plurality of metal plugs includes a first plug electrically coupled to the first metal material filling the first trench and a second plug electrically coupled to the junction portion of the second fin structure via the second metal material filling the second trench, the junction passage, and the electrode portion of the second fin structure.

11. The method of claim 10, wherein the plurality of metal plugs comprises source plugs and drain plugs respectively electrically coupled to the source structure and the drain structure of the fin field-effect transistor.

12. The method according to claim 10, wherein: The Schottky barrier diode includes a P-type Schottky barrier diode; and The junction portion of the second fin structure is P-type, and the second plug, the second metal material filling the second trench, the junction path, and the electrode portion of the second fin structure form the anode of the Schottky barrier diode.

13. The method of claim 10, wherein: The Schottky barrier diode includes a P-type Schottky barrier diode; and The junction portion of the second fin structure is P-type, and the first plug is coupled to the first metal material filling the first trench and forms the cathode of the Schottky barrier diode.

14. The method according to any one of claims 1 to 7, wherein the source metal material, the drain metal material and the first metal material are one of cobalt silicide and nickel silicide, and the Schottky junction is formed between the junction portion of the second fin structure and one of cobalt silicide and nickel silicide.

15. The method according to any one of claims 1 to 7, wherein each of the source metal material, the drain metal material, and the first metal material comprises a first metal layer and a second metal layer, wherein the second metal layer of the source metal material contacts the source structure, the second metal layer of the drain metal material contacts the drain structure, and the second metal layer of the first metal material contacts the junction portion of the second fin structure, the second metal layer comprising one of cobalt silicide and nickel silicide.

16. The method according to any one of claims 1 to 7, wherein the substrate comprises a bulk silicon substrate, and the first fin structure and the second fin structure are etched from the bulk silicon substrate.

17. The method of claim 16, wherein the bulk silicon substrate has a bulk doping concentration, and the junction portion of the second fin structure has a Schottky semiconductor doping concentration different from the bulk doping concentration.

18. The method of claim 16, wherein the bulk silicon substrate is P-type and the Schottky barrier diode is P-type, the method further comprising: A first heavily doped N-type region is formed in the second fin structure; and One or more second heavily doped N-type regions are formed adjacent to the second fin structure to isolate the Schottky barrier diode from one or more other semiconductor devices on the substrate.

19. The method according to any one of claims 1 to 7, wherein the substrate comprises a silicon-on-insulator substrate.

20. The method according to any one of claims 1 to 7, comprising: A gate dielectric and a gate are formed covering two or more surfaces of the channel portion of the first fin structure.

21. The method according to any one of claims 1 to 7, wherein the fin field-effect transistor has a threshold voltage and the Schottky barrier diode has a turn-on voltage, and wherein the magnitude of the threshold voltage is greater than the magnitude of the turn-on voltage.

22. A method of forming an integrated semiconductor device, comprising: A first fin structure and a second fin structure are formed on a substrate. The first fin structure includes a channel portion that extends to two pressure source portions on two opposing sides of the channel portion. The second fin structure includes a junction portion. Deposit a pressure source layer covering the substrate and the first fin structure and the second fin structure; Define the source structure and drain structure on the pressure source layer, wherein the source structure and the drain structure are respectively disposed on the two pressure source portions of the first fin structure; A source metal material, a drain metal material, and a first metal material are formed and electrically coupled to the junction portion of the source structure, the drain structure, and the second fin structure, respectively. Defining a junction pathway, wherein the junction portion extends into the electrode portion of the second fin structure, and the junction pathway is disposed on the electrode portion of the second fin structure; and A second metallic material is formed to electrically couple to the junction pathway; The fin field-effect transistor is formed on the substrate and includes the channel portion of the first fin structure, the source structure, and the drain structure; and The Schottky barrier diode is formed on the substrate and includes a Schottky junction between the junction portion of the second fin structure and the first metal material, wherein in the Schottky barrier diode, the junction portion of the second fin structure is electrically coupled to the second metal material via the junction path of the second fin structure and the electrode portion.

23. An integrated semiconductor device comprising: (1) Substrate; (2) A fin field-effect transistor, formed on the substrate and having a first fin structure, a gate dielectric, a gate, a source structure, and a drain structure, wherein: The first fin structure includes a channel portion that extends to two pressure source portions on two opposing sides of the channel portion; The source structure is electrically coupled to the source metal material; and The drain structure is electrically coupled to the drain metal material; and (3) A Schottky barrier diode, formed on the substrate and having a second fin structure and a first metallic material, wherein: The second fin structure includes a knot portion; A junction path, wherein the junction portion extends into the electrode portion of the second fin structure, and the junction path is disposed on the electrode portion, wherein a second metal material is electrically coupled to the junction path, and the junction portion of the second fin structure is electrically coupled to the second metal material via the junction path and the electrode portion of the second fin structure; and The junction portion forms a Schottky junction with the first metal material; The first fin structure and the second fin structure are made of the same material having the same or different doping types and concentrations; and The same material is conductive and is used to provide the first metal material, the source metal material, and the drain metal material.

24. An integrated semiconductor device comprising: Substrate; A first fin structure and a second fin structure, the first fin structure including a channel portion extending to two pressure source portions on two opposing sides of the channel portion, and the second fin structure including a knot portion; A source structure and a drain structure, wherein the source structure and the drain structure are respectively disposed on the two pressure source portions of the first fin structure; A junction path, wherein the junction portion extends into the electrode portion of the second fin structure and the junction path is disposed on the electrode portion, wherein a second metal material is electrically coupled to the junction path, and the junction portion of the second fin structure is electrically coupled to the second metal material via the junction path of the second fin structure and the electrode portion; and A conductive material comprising a source metal material, a drain metal material, and a first metal material, which are electrically coupled to the junction portions of the source structure, the drain structure, and the second fin structure, respectively. The fin field-effect transistor is formed on the substrate and includes the channel portion of the first fin structure, the source structure, and the drain structure; and The Schottky barrier diode is formed on the substrate and includes a Schottky junction between the junction portion of the second fin structure and the first metal material.

25. The integrated semiconductor device of claim 24, further comprising: A gate dielectric and a gate that cover two or more surfaces of the channel portion of the first fin structure.

Images