Laminated structures and electronic devices

Abstract

Crystals having excellent crystallinity, layered structures, and devices and electronic devices made using these. We provide chairs, electronic equipment, and systems. [Solution] A laminated structure in which an epitaxial film made of a conductive metal oxide is formed directly on a buffer layer or via another layer, wherein the buffer layer includes a crystalline film containing an oxide of Hf and / or Zr, is used to manufacture semiconductor devices such as Schottky barrier diodes (SBDs), junction barrier Schottky diodes (JBSs), metal-semiconductor field-effect transistors (MESFETs), high electron-mobility transistors (HEMTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), electrostatic induction transistors (SITs), junction field-effect transistors (JFETs), insulated-gate bipolar transistors (IGBTs), light-emitting diodes (LEDs), or combinations thereof.

Description

Technical Field

[0001] The present invention relates to a laminated structure, an element, an electronic device, an electronic apparatus, and a system.

Background Art

[0002] Conventionally, for the purpose of preventing malfunction and destruction of an IC due to parasitic elements in the horizontal and vertical directions generated by PN separation, SOI (Silicon On Insulator) technology that separates between respective elements using a SiO2 film is known. In recent years, formation of a plurality of semiconductor elements having different breakdown voltages on a single semiconductor substrate has also been studied. In particular, application to wide bandgap semiconductors (for example, SiC, GaN, etc.) has also been studied (Patent Document 1).

[0003] Also, attempts have been made to form a device on a flexible substrate such as plastic using SOI technology. For example, as disclosed in Patent Document 2, after partially opening a window in the SOI layer using a completed SOI substrate to expose the BOX (Buried Oxide) layer, HF etching is performed, and the BOX is etched by the lateral penetration of HF to form a pillar. After pillar formation, the SOI layer is attached to PET (polyethylene terephthalate) or the like, peeled off from the substrate with the pillar portion as a boundary, and a method of transferring the SOI layer on which a device is fabricated onto PET or the like to form it on a flexible substrate exists.

[0004] However, none of the SOI technologies are yet satisfactory in terms of the crystallinity of the semiconductor film formed on the insulating film, the crystallinity of the insulating film, the insulating properties, etc., and further improvement in crystallinity and semiconductor properties has been awaited. Also, as a buffer layer, an SOI technology that brings good crystallinity not only to semiconductors but also to piezoelectric bodies and the like has been desired. Furthermore, when peeling and transferring the SOI layer, the process becomes complicated or peeling is difficult, so a new SOI technology that can be easily peeled and transferred has also been awaited.

Prior Art Documents

[0005] [Patent Document 1] Japanese Patent Publication No. 2021-5718 [Patent Document 2] Japanese Patent Publication No. 2014-179580 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] The present invention aims to provide laminated structures having excellent crystallinity, and elements, electronic devices, electronic equipment, and systems using these. [Means for solving the problem]

[0007] As a result of diligent research to achieve the above objectives, the present inventors have discovered that by forming at least an oxide film on a crystalline substrate, and then laminating a crystalline film containing crystals made of crystalline metal oxides mainly composed of metal oxides including Hf and Zr oxides, and by performing the lamination using oxygen atoms in the oxide film to form the crystalline film, crystals and laminated structures with excellent crystallinity can be easily obtained; they are particularly useful for crystal growth for the production of soft crystalline films; when conductive films, semiconductor films, and piezoelectric films are formed on the crystals, they exhibit excellent crystallinity, resulting in excellent electrode properties and various functional film properties; they are particularly suitable as buffer layers for thin film formation of functional films with a thickness of less than 1 μm; and they are also useful for peeling and transfer. Based on these findings, the inventors have discovered that such crystals and laminated structures can solve the above-mentioned conventional problems all at once. Furthermore, after obtaining the above findings, the inventors conducted further studies and completed the present invention.

[0008] In other words, the present invention relates to the following invention. [1] A laminated structure in which an epitaxial film made of a conductive metal oxide is formed directly on a buffer layer or via another layer, wherein the buffer layer includes a crystalline film containing an oxide of Hf and / or Zr. [2] The laminated structure according to [1], wherein the crystalline film contains an oxide of Hf. [3] The laminated structure according to [1] or [2], wherein the crystalline film has a cubic or hexagonal crystalline structure. [4] The laminated structure according to any one of [1] to [3], wherein the crystalline film is oriented to (111), (100), (010), or (0001). [5] The laminated structure according to any one of [1] to [4], wherein the conductive metal oxide is an oxide containing In and / or Sn. [6] The laminated structure according to any one of [1] to [5], wherein the buffer layer is laminated directly or via other layers onto a single crystal substrate having a cubic or hexagonal crystal structure. [7] The laminated structure according to [6], wherein the buffer layer is laminated on the single crystal substrate by crystal growth. [8] The laminated structure according to [6] or [7], wherein the single crystal substrate is a Si substrate. [9] The laminated structure according to any one of [1] to [8], further comprising a layer made of a piezoelectric material or a semiconductor laminated on the epitaxial film.

[10] An element comprising a laminated structure, wherein the laminated structure is a laminated structure according to any one of [1] to [9] above.

[11] The element described in

[10] , which is a piezoelectric element or a semiconductor element.

[12] An electronic device comprising a laminated structure, wherein the laminated structure is a laminated structure according to any one of [1] to [9] above.

[13] The electronic device described in

[12] above, which is a piezoelectric device or a semiconductor device.

[14] An electronic device including an electronic device, wherein the electronic device is the electronic device described in

[12] or

[13] .

[15] A system including an electronic device, wherein the electronic device is the electronic device described in

[14] .

Effect of the Invention

[0009] The laminated structure of the present invention has excellent crystallinity, and the elements, electronic devices, electronic apparatuses, and systems using the laminated structure have the effect of making the characteristics of their respective functional films good.

Brief Description of the Drawings

[0010] [Figure 1] It is a diagram schematically showing an example of a preferred embodiment of the laminated structure of the present invention. [Figure 2] It is a diagram schematically showing an SOI island formation process in peeling / transfer, which is an example of a preferred application example of the laminated structure of the present invention. [Figure 3] It is a diagram schematically showing an HF etching process in peeling / transfer, which is an example of a preferred application example of the laminated structure of the present invention. [Figure 4] It is a diagram schematically showing an attachment process to a flexible substrate in peeling / transfer, which is an example of a preferred application example of the laminated structure of the present invention. [Figure 5] It is a diagram schematically showing a peeling process in peeling / transfer, which is an example of a preferred application example of the laminated structure of the present invention. [Figure 6] It is a diagram schematically showing an example of a compound film formation process of a preferred manufacturing method of the laminated structure of the present invention. [Figure 7] It is a diagram schematically showing an example of an insulating film formation process of a preferred manufacturing method of the laminated structure of the present invention. [Figure 8] It shows a cross-sectional STEM image observed in the example. [Figure 9] It shows the XPS analysis results in the example. [Figure 10]It is a diagram schematically showing a preferred example of an insulated gate bipolar transistor (IGBT) obtained in the present invention. [Figure 11] It is a diagram schematically showing an example of a preferred manufacturing process of the insulated gate bipolar transistor (IGBT) of FIG. 10. [Figure 12] It is a diagram schematically showing a preferred example of a power supply system. [Figure 13] It is a diagram schematically showing a preferred example of a system device. [Figure 14] It is a diagram schematically showing a preferred example of a power circuit diagram of a power supply device. [Figure 15] It is a diagram schematically showing a film forming apparatus suitably used in an embodiment.

Mode for Carrying Out the Invention

[0011] The laminated structure of the present invention is a laminated structure in which an epitaxial film made of a conductive metal oxide is formed directly on a buffer layer or via another layer, and the buffer layer includes a crystalline film containing an oxide of Hf and / or Zr. The crystal of the crystalline film may be a single crystal or a polycrystal.

[0012] The conductive metal oxide is usually conductive and is a crystalline metal oxide. The crystalline metal oxide is not particularly limited as long as it contains a metal oxide as a main component. Further, the oxide is not particularly limited as long as it contains an oxide of Hf and Zr, but those containing an oxide of Hf and Zr as a main component are preferred. Here, the "main component" means that, for example, if the atomic ratio of the oxides in the crystal contains an oxide of Hf and Zr at a ratio of 0.5 or more, that is sufficient. In the present invention, it is preferable that the atomic ratio of Hf and Zr to all metal elements in the oxide is 0.7 or more, and more preferably 0.8 or more.

[0013] In the present invention, it is preferable that the oxide or the crystalline metal oxide has a cubic or hexagonal crystal structure, and more preferably is oriented to (111), (100), (010), or (0001). Furthermore, in the present invention, it is also preferable that the oxide contains 50 atomic percent or more of Hf oxide and Zr oxide relative to the crystalline metal oxide. Such a preferred range is preferable because it can not only be used as an excellent buffer layer, but can also exhibit good properties as a ferroelectric, and furthermore, its electrical properties (especially the interface between the conductive layer and the insulating layer) can be made even better.

[0014] In the present invention, it is preferable that the crystal is in the form of a film (hereinafter also referred to as "crystalline film"), and if it is in the form of a film, it is preferable that the film thickness is 1 μm or more from the viewpoint of pressure resistance, etc. Such a preferred crystal can be easily obtained by forming at least an oxide film on a crystalline substrate, and then laminating a crystalline film containing crystals made of a crystalline metal oxide mainly composed of a metal oxide, by performing the lamination using oxygen atoms in the oxide film to form the crystalline film. The means for forming the crystalline film are not particularly limited and may be known means (e.g., MBE method, ion plating method, etc.), and the crystal growth conditions can also be set as appropriate. The laminated structure obtained by the above method and the method for manufacturing the same are also included in the present invention.

[0015] Figure 1 shows a preferred example of the laminated structure, in which an oxide film 5 is laminated as a first epitaxial layer on a crystal substrate 9 using an oxide film, and a conductive film, semiconductor film, or piezoelectric film 4 is laminated as a second epitaxial layer on top of the first epitaxial layer. Furthermore, an epitaxial film 1 made of a compound piezoelectric or compound semiconductor is laminated on top of the conductive film, etc. 4. In this specification, the terms "film" and "layer" may be interchanged depending on the case or situation.

[0016] The laminated structure can be easily manufactured, for example, as shown in Figure 2, by forming an oxide film 5 on a crystalline substrate 9, and then using the oxygen in the oxide film 5 to form a crystalline film (first epitaxial layer) made of the crystalline metal oxide on the crystalline substrate 9. In the present invention, the laminated structure may have the oxide film 5 on the crystalline substrate 9, but the oxide film 5 may disappear if all the oxygen in the oxide film 5 is incorporated during the formation of the crystalline film. Preferred embodiments of the present invention will be described in more detail below, but the present invention is not limited to these specific examples.

[0017] The crystalline substrate (hereinafter also simply referred to as "substrate") is not particularly limited as long as it does not hinder the objectives of the present invention, and may be a known crystalline substrate. It may be an organic compound or an inorganic compound. In the present invention, it is preferable that the crystalline substrate contains an inorganic compound. In the present invention, it is preferable that the substrate has crystals on part or all of its surface, more preferably that it is a crystalline substrate having crystals on all or part of the main surface on the crystal growth side, and most preferably that it is a crystalline substrate having crystals on all of the main surface on the crystal growth side. The crystals are not particularly limited as long as they do not hinder the objectives of the present invention, and the crystal structure is not particularly limited, but they are preferably cubic, tetragonal, trigonal, hexagonal, orthorhombic, more preferably cubic or hexagonal, and most preferably (111), (100), or (0001) oriented. The crystalline substrate may also have an off-angle, and examples of the off-angle include an off-angle of 0.2° to 12.0°. Here, "off-angle" refers to the angle between the substrate surface and the crystal growth surface. The substrate shape is not particularly limited as long as it is plate-shaped and serves as a support for the insulating film. It may be an insulating substrate or a semiconductor substrate, but in the present invention, the substrate is preferably a Si substrate, more preferably a crystalline Si substrate, and most preferably a crystalline Si substrate oriented to (111), (100), or (0001). Examples of the substrate material include, in addition to a Si substrate, one or more metals belonging to groups 3 to 15 of the periodic table or oxides of these metals. The shape of the substrate is not particularly limited and may be substantially circular (e.g., round, elliptical, etc.) or polygonal (e.g., triangular, square, rectangular, pentagonal, hexagonal, heptagonal, octagonal, nonagonal, etc.), and various shapes can be suitably used.

[0018] Furthermore, in the present invention, it is preferable that the crystal substrate has a flat surface, but it is also preferable that the crystal substrate has an uneven shape on part or all of its surface, as this can improve the quality of crystal growth of the crystal film. The crystal substrate having the uneven shape only needs to have an uneven portion consisting of recesses or protrusions on part or all of its surface, and the uneven portion is not particularly limited as long as it consists of protrusions or recesses, and may be an uneven portion consisting of protrusions, an uneven portion consisting of recesses, or an uneven portion consisting of both protrusions and recesses. In addition, the uneven portion may be formed from regular protrusions or recesses, or from irregular protrusions or recesses. In the present invention, it is preferable that the uneven portion is formed periodically, and more preferably that it is patterned periodically and regularly. The shape of the uneven portion is not particularly limited, and examples include stripe-like, dot-like, mesh-like, or random-like, but in the present invention, dot-like or stripe-like is preferred, and dot-like is more preferred. Furthermore, if the uneven surfaces are patterned periodically and regularly, it is preferable that the pattern shape of the uneven surfaces be a polygonal shape such as a triangle, quadrilateral (e.g., square, rectangle, or trapezoid), pentagon or hexagon, circular, or elliptical. When the uneven surfaces are formed in a dot shape, it is preferable that the lattice shape of the dots be a grid shape such as a square grid, rhombic grid, triangular grid, or hexagonal grid, and more preferably a triangular grid. The cross-sectional shape of the recesses or protrusions of the uneven surfaces is not particularly limited, but examples include a U-shape, inverted U-shape, wave shape, or a polygonal shape such as a triangle, quadrilateral (e.g., square, rectangle, or trapezoid), pentagon or hexagon. The thickness of the crystal substrate is not particularly limited, but is preferably 50 to 2000 μm, and more preferably 100 to 1000 μm.

[0019] The oxide film is not particularly limited as long as it is an oxide film that can incorporate oxygen atoms into the crystal film, and usually contains an oxidizing material. The oxidizing material is not particularly limited as long as it does not hinder the objective of the present invention, and may be a known oxidizing material. Examples of the oxidizing material include oxides of metals or metalloids. In the present invention, it is preferable that the oxide film contains an oxidizing material of the crystal substrate, and examples of such an oxide film include a thermal oxide film of the crystal substrate and a native oxide film. Furthermore, in the present invention, the oxide film may be a sacrificial layer in which part or all of the film disappears or is destroyed when oxygen atoms are incorporated, and in the present invention, it is preferable that the oxide film is an oxygen-supplying sacrificial layer in which oxygen atoms are incorporated during the crystal growth of the epitaxial layer and the oxide film itself disappears. Furthermore, the oxide film may be patterned, for example, it may be patterned in the shape of stripes, dots, mesh, or random shapes. The thickness of the oxide film is not particularly limited, but is preferably greater than 1 nm and less than 100 nm.

[0020] The crystalline film (first epitaxial layer) preferably includes an epitaxial film into which oxygen atoms from the oxide film are incorporated. "An epitaxial film into which oxygen atoms from the oxide film are incorporated" means that during the crystal growth of the epitaxial film, oxygen atoms from the oxide film were absorbed by the epitaxial film. Furthermore, in the present invention, the crystalline film preferably includes a neutron absorbent. The neutron absorbent may be any known neutron absorbent, and in the present invention, by using such a neutron absorbent to incorporate oxygen from the oxide film, adhesion, crystallinity, and the properties of the functional film can be improved. Suitable examples of the neutron absorbent include, for example, hafnium (Hf).

[0021] In the present invention, it is preferable that a second epitaxial layer, made of a conductive film, a semiconductor film, or a piezoelectric film, is laminated on the crystalline film, either directly or via another layer. By laminating in this manner, the first epitaxial layer can be regularly transformed at the interface between the first epitaxial layer and the second epitaxial layer so that the lattice constant of the first epitaxial layer is substantially the same as that of the second epitaxial layer. As an example of the manner of the regular transformation, for example, a transformation in which the shape is changed to a peak-and-valley structure is a suitable example, and in the present invention, it is preferable that the angles between adjacent vertices and bases of the peak-and-valley structure are different, and it is more preferable that the angles are within the range of 30° to 45°. Here, the first epitaxial layer usually has a first crystal plane and a second crystal plane, but the transformation may cause a difference in lattice constants between the first crystal plane and the second crystal plane, so it is preferable that the difference in lattice constants between the first crystal plane and the second crystal plane be within the range of 0.1% to 20%. In the present invention, since the lattice constant of the first crystal plane can be substantially the same as that of the second epitaxial layer, it is easy to achieve a difference in lattice constants between the first epitaxial layer and the second epitaxial layer within the range of 0.1% to 20%.

[0022] In the present invention, when a conductive film is laminated on the crystalline film, and the conductive film is made of a single crystal film of a conductive metal, a large-area defect-free film can be easily obtained, and not only the function as an electrode but also the properties of the device and the like can be improved. The conductive metal is not particularly limited as long as it does not hinder the objective of the present invention, and examples include gold, silver, platinum, palladium, silver-palladium, copper, nickel, or alloys thereof, but in the present invention, it is preferable to include platinum. In the present invention, according to the above manufacturing method, preferably 100 nm 2 A defect-free single-crystal film can be obtained as an electrode over the above area, more preferably 1000 nm. 2A defect-free single-crystal film can be easily obtained over the above area. Furthermore, a single-crystal film with a thickness of preferably 100 nm or more can be easily obtained as an electrode. When the conductive film, which consists of a single-crystal film of a conductive metal, is laminated on the crystalline film, the laminated structure can be suitably used as an electrode substrate in which a crystalline conductive film is laminated on the insulating film.

[0023] The semiconductor film is not particularly limited as long as it contains a semiconductor, and may be a known semiconductor film, but in the present invention, it is preferable that it contains a cubic semiconductor. Examples of the cubic semiconductor include c-BN, c-AlN, c-GaN, c-InN, c-SiC, GaAs, AlAs, InAs, GaP, AlP, InP, or mixed crystal semiconductors thereof.

[0024] The piezoelectric film is not particularly limited as long as it is made of a piezoelectric material, and may be a film made of a known piezoelectric material, but in the present invention, it is preferable that it is a piezoelectric material having a trigonal or hexagonal crystal structure. Examples of the piezoelectric material include lead zirconate titanate (PZT), other types of ceramic materials having a so-called perovskite structure represented by the ABO3 type, such as barium titanate, lead titanate, potassium niobate, lithium niobate, lithium tantalate, sodium tungstate, zinc oxide, barium strontium titanate (BST), strontium bismuth tantalate (SBT), lead metaniobate, zinc niobate, lead scandium niobate, etc., or polyvinylidene fluoride, quartz, etc.

[0025] The thickness of each of the conductive film, the semiconductor film, and the piezoelectric film is not particularly limited, but is preferably 10 nm to 1000 μm, and more preferably 10 nm to 100 μm.

[0026] The aforementioned laminated structure can be easily obtained in a method for manufacturing a laminated structure in which an insulating film is laminated on a crystalline substrate via at least an oxide film, by performing the lamination by forming a crystalline film using oxygen atoms in the oxide film at 350°C to 700°C. Within the temperature range of ℃ to 700℃, oxygen atoms in the oxide film can be easily incorporated into the crystal film, allowing for crystal growth.

[0027] In the present invention, it is preferable to form the crystalline film using oxygen gas after using oxygen atoms in the oxide film to form the laminate.

[0028] In the lamination process described above, the means for forming the insulating film is usually preferred, and the means for forming the film may be any known means. In the present invention, it is preferable that the means for forming the film is vapor deposition or sputtering.

[0029] The laminated structure obtained as described above can be used as is, or, if desired, further processed, in accordance with conventional methods, as an element. When using the laminated structure as an element, it may be used as is, or other layers (for example, an insulating layer, a semi-insulating layer, a conductive layer, a semiconductor layer, a buffer layer, or other intermediate layers) may be formed on it before use. In the present invention, it is preferable to use the laminated structure as an SOI substrate on which a functional film (for example, a semiconductor film, a piezoelectric film, etc.) is laminated on the crystalline film.

[0030] The element is used in conventional methods, for example, in electronic devices (preferably piezoelectric devices). More specifically, for example, the element can be used as a piezoelectric element, connected to a power supply or electrical / electronic circuit, mounted on a circuit board, or packaged to constitute various electronic devices. In the present invention, it is preferable that the electronic device is a piezoelectric device, and more preferably a piezoelectric device in electronic equipment such as a gyroscope or motion sensor. Furthermore, for example, by connecting an amplifier and a rectifier circuit and packaging them, it can be used in various sensors such as magnetic sensors.

[0031] The aforementioned electronic device is suitably used in electronic devices in accordance with conventional methods. Besides the electronic devices described above, the device can be applied to a variety of other electronic devices. More specifically, suitable examples include liquid dispensing heads, liquid dispensing devices, vibration wave motors, optical instruments, vibration devices, imaging devices, piezoelectric acoustic components, and audio playback devices, audio recording devices, mobile phones, and various information terminals.

[0032] Furthermore, in the present invention, it is preferable that the element is a semiconductor element, and it is also preferable that the electronic device is a semiconductor device. The semiconductor element or semiconductor device (hereinafter collectively referred to as "semiconductor device") is not particularly limited as long as it does not hinder the objective of the present invention, and may be a known semiconductor element or semiconductor device.

[0033] The semiconductor device is not particularly limited as long as it does not hinder the objectives of the present invention, and may be a known semiconductor device. It may be a vertical device or a horizontal device, but in the present invention, it is preferable that the semiconductor device is a vertical device. Examples of the semiconductor device include diodes and transistors, and more specifically, examples of preferred semiconductor devices include Schottky barrier diodes (SBDs), junction barrier Schottky diodes (JBSs), high electron mobility transistors (HEMTs), metal-semiconductor field-effect transistors (MESFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), electrostatic induction transistors (SITs), junction field-effect transistors (JFETs), insulated gate bipolar transistors (IGBTs), light-emitting diodes (LEDs), or combinations thereof.

[0034] Hereinafter, preferred examples will be described with reference to the drawings in which the laminated structure is applied to a semiconductor device, more specifically, the buffer layer in the laminated structure is applied to an electrode or buffer layer for ohmic bonding or electron emission of the semiconductor device, and the epitaxial film in the laminated structure is applied to a semiconductor layer of the semiconductor device. However, the present invention is not limited to these examples. In the semiconductor device illustrated below, other layers (e.g., insulating layer, semi-insulating layer, conductive layer, semiconductor layer, buffer layer, or other intermediate layer) may be included as long as they do not hinder the objective of the present invention, and the crystal substrate, buffer layer, etc. may be omitted as appropriate.

[0035] (SBD) Figure 3 shows an example of a Schottky barrier diode (SBD) according to the present invention. The SBD in Figure 3 comprises an n-type semiconductor layer 101, an n-type semiconductor layer 101a, an n+-type semiconductor layer 101b, an insulating layer 104, a Schottky electrode 105a, and an ohmic electrode 105b.

[0036] The electrode material, such as a Schottky electrode, may be a known electrode material. Examples of such electrode materials include metals or alloys thereof such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag; metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, or polypyrrole; or mixtures thereof.

[0037] Electrodes can be formed by known means such as vacuum deposition or sputtering. More specifically, for example, when forming a Schottky electrode, a layer made of Mo and a layer made of Al can be stacked, and the Mo layer and the Al layer can be patterned using photolithography.

[0038] Examples of materials for the insulating layer 104 include GaO, AlGaO, InAlGaO, AlInZnGaO4, AlN, Hf2O3, SiN, SiON, Al2O3, MgO, GdO, SiO2, or Si3N4. The insulating layer 104 is provided between the n-type semiconductor layer 101 and the Schottky electrode 105a. The insulating layer can be formed by known means such as sputtering, vacuum deposition, or CVD.

[0039] When a reverse bias is applied to the SBD in Figure 3, a depletion layer (not shown) spreads within the n-type semiconductor layer 101a, resulting in a high-voltage SBD. When a forward bias is applied, electrons flow from the ohmic electrode 105b to the Schottky electrode 105a. In this way, the SBD using the semiconductor structure is excellent for high-voltage and high-current applications, has a fast switching speed, excellent voltage resistance and reliability, excellent insulation properties, and superior current controllability.

[0040] (JBS) Figure 4 shows a junction barrier Schottky diode (JBS), which is one of the preferred embodiments of the present invention. The semiconductor device in Figure 4 comprises an n-type semiconductor layer 101, an n-type semiconductor layer 101a, an n+-type semiconductor layer 101b, a p-type semiconductor layer 102, a Schottky electrode 105a, an ohmic electrode 105b, and a guard ring 106. The n-type semiconductor layer 101a includes a Schottky electrode 105a provided on the n-type semiconductor layer 101a and capable of forming a Schottky barrier between itself and the n-type semiconductor layer 101a, and a p-type semiconductor layer 102 provided between the Schottky electrode 105a and the n-type semiconductor layer 101a and capable of forming a Schottky barrier with a barrier height greater than the barrier height of the Schottky barrier of the Schottky electrode 105a between itself and the n-type semiconductor layer 101a. The p-type semiconductor layer 102 is embedded in the n-type semiconductor layer 101a. In the present invention, it is preferable that p-type semiconductor layers 102 are provided at regular intervals, and it is more preferable that p-type semiconductor layers 102 are provided between both ends of the Schottky electrode 105a and the n-type semiconductor layer 101a. With this preferred configuration, the JBS is configured to have superior thermal stability and adhesion, reduced leakage current, and superior semiconductor characteristics such as breakdown voltage.

[0041] (MESFET) Figure 5 shows an example of a metal-semiconductor field-effect transistor (MESFET) according to the present invention. The MESFET in Figure 5 comprises an n-type semiconductor layer 111a, an n+-type semiconductor layer 111b, a buffer layer 118, a crystal substrate 119, a semi-insulating layer 114, a gate electrode 115a, a source electrode 115b, and a drain electrode 115c.

[0042] The materials for the gate electrode, drain electrode, and source electrode may be known electrode materials, and examples of such electrode materials include metals or alloys thereof such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag; metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, or polypyrrol; or mixtures thereof. The gate electrode, drain electrode, and source electrode can be formed by known means such as vacuum deposition or sputtering.

[0043] The semi-insulating layer 114 only needs to be composed of a semi-insulating material, and examples of such semi-insulating materials include those containing a semi-insulating dopant or those that have not undergone doping treatment.

[0044] In the MESFET shown in Figure 5, a good depletion layer is formed beneath the gate electrode, allowing for efficient control of the current flowing from the drain electrode to the source electrode.

[0045] (HEMT) Figure 6 shows an example of a photomobility transistor (HEMT) according to the present invention. The HEMT in Figure 6 comprises a wide-bandgap n-type semiconductor layer 121a, a narrow-bandgap n-type semiconductor layer 121b, an n+-type semiconductor layer 121c, an electron transport layer 123, a semi-insulating layer 124, a gate electrode 125a, a source electrode 125b, a drain electrode 125c, a buffer layer 128, and a crystal substrate 129.

[0046] The materials for the gate electrode, drain electrode, and source electrode may each be known electrode materials, and examples of such electrode materials include metals or alloys thereof such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag; metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, or polypyrrol; or mixtures thereof. The gate electrode, drain electrode, and source electrode can be formed by known means such as vacuum deposition or sputtering.

[0047] The n-type semiconductor layer beneath the gate electrode consists of at least a layer 121a with a wide band gap and a layer 121b with a narrow band gap. The semi-insulating layer 124 only needs to be made of a semi-insulating material, and examples of such semi-insulating materials include those containing a semi-insulating dopant or those that have not undergone doping treatment. The electron transport layer 123 formed on the semi-insulating layer 124 can be made of i(intentionally undoped) GaN, for example, when GaN, a nitride semiconductor, is used as the semiconductor.

[0048] In the HEMT shown in Figure 6, a good depletion layer is formed beneath the gate electrode, allowing for efficient control of the current flowing from the drain electrode to the source electrode. Furthermore, in this invention, a recess structure can be added to achieve normally-off.

[0049] (MOSFET) Figure 7 shows an example where the semiconductor device of the present invention is a MOSFET. Figure 7 shows a preferred example of a metal-oxide-semiconductor field-effect transistor (MOSFET) comprising an n-type semiconductor layer 131a, a first n+-type semiconductor layer 131b, a second n+-type semiconductor layer 131c, a p-type semiconductor layer 132, a p+-type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135c. Note that the p+-type semiconductor layer 132a may be a p-type semiconductor layer, or it may be the same as the p-type semiconductor layer 132.

[0050] On the drain electrode 135c made of the conductive crystal film, an n+ type semiconductor layer 131b with a thickness of, for example, 100 nm to 100 μm is formed, and on the n+ type semiconductor layer 131b, an n- type semiconductor layer 131a with a thickness of, for example, 100 nm to 100 μm is formed.

[0051] Furthermore, multiple trench grooves are formed within the n-type semiconductor layer 131a and the p-type semiconductor layer 132, with a depth that reaches partway through the n-type semiconductor layer 131a. Within these trench grooves, gate electrodes 135a are embedded and formed via gate insulating films 134 with a thickness of, for example, 10 nm to 1 μm.

[0052] In the ON state of the MOSFET in Figure 7, when a voltage is applied between the source electrode 135b and the drain electrode 135c, and a positive voltage is applied to the gate electrode 135a relative to the source electrode 135b, a channel layer is formed on the side surface of the n-type semiconductor layer 131a, electrons are injected into the n-type semiconductor layer, and the MOSFET turns on. In the OFF state, by setting the voltage of the gate electrode to 0V, the channel layer does not form, the n-type semiconductor layer becomes filled with a depletion layer, and the MOSFET turns off.

[0053] In the MOSFET shown in Figure 7, an etching mask is provided in predetermined regions of the n-type semiconductor layer 131a, the p-type semiconductor 132, and the n+-type semiconductor layer 131c. Using the etching mask as a mask, anisotropic etching is performed by reactive ion etching or the like to form a trench groove with a depth that extends from the surface of the n+-type semiconductor layer 131c to partway through the n-type semiconductor layer 131a. Next, a gate insulating film 134 with a thickness of, for example, 50 nm to 1 μm is formed on the side and bottom surfaces of the trench groove using known means such as thermal oxidation, vacuum deposition, sputtering, or CVD. Then, a gate electrode material, such as polysilicon, is formed in the trench groove with a thickness less than or equal to the thickness of the n-type semiconductor layer using CVD, vacuum deposition, sputtering, or the like.

[0054] Then, a power MOSFET can be manufactured by forming a source electrode 135b on an n+ type semiconductor layer 131c using known means such as vacuum deposition, sputtering, or CVD. The electrode material of the source electrode may be any known electrode material, and examples of such electrode materials include metals or alloys thereof such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag; metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, or polypyrrol; or mixtures thereof.

[0055] The MOSFET obtained in this way has even better voltage resistance than conventional trench-type MOSFETs. Although Figure 7 shows an example of a trench-type vertical MOSFET, the present invention is not limited to this and can be applied to various MOSFET configurations. For example, the depth of the trench groove in Figure 7 may be deepened to reach the bottom surface of the n-type semiconductor layer 131a to reduce the series resistance.

[0056] (SIT) Figure 8 shows an example where the semiconductor device of the present invention is a SIT. The SIT in Figure 8 comprises an n-type semiconductor layer 141a, n+-type semiconductor layers 141b and 141c, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

[0057] On the drain electrode 145c, which is made of a conductive crystalline film, an n+ type semiconductor layer 141b with a thickness of, for example, 100 nm to 100 μm is formed, and on the n+ type semiconductor layer 141b, an n- type semiconductor layer 141a with a thickness of, for example, 100 nm to 100 μm is formed. Furthermore, an n+ type semiconductor layer 141c is formed on the n- type semiconductor layer 141a, and the source electrode 145b is formed on the n+ type semiconductor layer 141c.

[0058] Furthermore, within the n-type semiconductor layer 141a, a plurality of trench grooves are formed that penetrate the n+-type semiconductor layer 141c and reach a depth partway through the n-type semiconductor layer 141a. A gate electrode 145a is formed on the n-type semiconductor layer within the trench grooves. In the ON state of the SIT in Figure 8, when a voltage is applied between the source electrode 145b and the drain electrode 145c, and a positive voltage is applied to the gate electrode 145a relative to the source electrode 145b, a channel layer is formed in the n-type semiconductor layer 141a, electrons are injected into the n-type semiconductor layer, and the device turns on. In the OFF state, the voltage of the gate electrode is set to 0V, which prevents the formation of the channel layer, fills the n-type semiconductor layer with a depletion layer, and the device turns off.

[0059] Known methods can be used to manufacture the SIT shown in Figure 8. For example, in the same manner as the manufacturing process for the MOSFET described above, an etching mask is provided in a predetermined region of the n-type semiconductor layer 141a and the n+-type semiconductor layer 141c, and anisotropic etching is performed using the etching mask as a mask, for example by reactive ion etching, to form a trench groove that reaches from the surface of the n+-type semiconductor layer 141c to partway up the n-type semiconductor layer. Next, a gate electrode material, such as polysilicon, is formed in the trench groove to a thickness less than or equal to the thickness of the n-type semiconductor layer using CVD, vacuum deposition, sputtering, etc. Then, using known methods such as vacuum deposition, sputtering, and CVD, a source electrode 145b is formed on the n+-type semiconductor layer 141c and a drain electrode 145c is formed on the n+-type semiconductor layer 141b, respectively, thereby manufacturing the SIT shown in Figure 8.

[0060] The electrode material of the source electrode may be any known electrode material, and examples of such electrode materials include metals or alloys thereof such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag; metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, or polypyrrole; or mixtures thereof.

[0061] Figure 9 shows a preferred example of a junction field-effect transistor (JFET) comprising an n-type semiconductor layer 141a, a first n+-type semiconductor layer 141b, a second n+-type semiconductor layer 141c, a p-type semiconductor layer 142, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

[0062] Figure 10 shows a preferred example of an insulated-gate bipolar transistor (IGBT) comprising an n-type semiconductor layer 151, an n-type semiconductor layer 151a, an n+-type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b, and a collector electrode 155c.

[0063] (LED) Figure 11 shows an example where the semiconductor device of the present invention is a light-emitting diode (LED). The semiconductor light-emitting device in Figure 11 has an n-type semiconductor layer 161 on a second electrode 165b, and a light-emitting layer 163 is laminated on the n-type semiconductor layer 161. A p-type semiconductor layer 162 is laminated on the light-emitting layer 163. A translucent electrode 167 that transmits light generated by the light-emitting layer 163 is provided on the p-type semiconductor layer 162, and a first electrode 165a is laminated on the translucent electrode 167. Note that the semiconductor light-emitting device in Figure 11 may be covered with a protective layer except for the electrode portion.

[0064] Examples of materials for translucent electrodes include conductive materials such as oxides containing indium (In) or titanium (Ti). More specifically, examples include In2O3, ZnO, SnO2, Ga2O3, TiO2, CeO2, or mixed crystals of two or more of these, or doped materials thereof. Translucent electrodes can be formed by providing these materials by known means such as sputtering. Alternatively, after forming the translucent electrode, thermal annealing may be performed to make the translucent electrode transparent.

[0065] In the semiconductor light-emitting element shown in Figure 11, the first electrode 165a is the positive electrode and the second electrode 165b is the negative electrode. By passing current through these electrodes to the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161, the light-emitting layer 163 emits light.

[0066] Examples of materials for the first electrode 165a include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or alloys thereof; metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, or polypyrrole; or mixtures thereof. The method for forming the electrode is not particularly limited and can be formed according to a method appropriately selected from wet methods such as printing, spraying, and coating; physical methods such as vacuum deposition, sputtering, and ion plating; and chemical methods such as CVD and plasma CVD, taking into consideration the suitability with the material.

[0067] In addition to the matters described above, the semiconductor device of the present invention can be suitably used as a semiconductor device such as a power module, inverter, or converter by known means, and can also be suitably used in a semiconductor system such as a power supply unit as a semiconductor device. The power supply unit can be manufactured by connecting the semiconductor device to a wiring pattern, etc., by known means. Figure 12 shows an example of a power supply system. Figure 12 shows a power supply system configured using a plurality of the power supply units and a control circuit. The power supply system can be used in a system device in combination with an electronic circuit, as shown in Figure 13. An example of a power supply circuit diagram for a power supply unit is shown in Figure 14. Figure 14 shows a power supply circuit for a power supply unit consisting of a power circuit and a control circuit. An inverter (composed of MOSFETs A to D) switches the DC voltage at high frequency and converts it to AC, then a transformer performs isolation and voltage transformation, rectifies it with rectifier MOSFETs (A to B'), smooths it with DCL (smoothing coils L1, L2) and a capacitor, and outputs a DC voltage. At this time, a voltage comparator compares the output voltage with a reference voltage, and a PWM control circuit controls the inverter and rectifier MOSFETs to obtain the desired output voltage. [Examples]

[0068] (Example 1) The crystal growth side of the Si substrate (100) was treated with RIE, and after heating in the presence of oxygen to form a thermal oxide film, an insulating film made of crystalline oxide was formed on the Si substrate by a vapor deposition method without using oxygen, causing a thermal reaction between the metal of the deposition source and the oxygen in the oxide film on the Si substrate. Then, oxygen was flowed, the temperature was lowered, and the pressure was increased, and another insulating film was deposited by vapor deposition. The conditions for the vapor deposition method during this film formation were as follows. Vapor deposition source: Hf, Zr Voltage: 3.5~4.75V Pressure: 3 × 10 -2 ~6×10 -2 Pa Substrate temperature: 500~650℃ On the insulating film of the obtained laminated structure, an ITO film was further laminated according to the method described above, and a PZT film was laminated on the ITO film to obtain a laminated structure as shown in Figure 1.

[0069] (Example 2) A laminated structure was obtained in the same manner as in Example 1, except that a Si substrate was used instead of (111).

[0070] Figure 15 shows the deposition apparatus used in Example 1. The deposition apparatus in Figure 15 is equipped with at least a crucible containing metal sources 1101a to 1101b, grounds 1102a to 1102h, ICP electrodes 1103a to 1103b, cut filters 1104a to 1104b, DC power supplies 1105a to 1105b, RF power supplies 1106a to 1106b, lamps 1107a to 1107b, Ar source 1108, reactive gas source 1109, power supply 1110, substrate holder 1111, substrate 1112, cut filter 1113, ICP ring 1114, vacuum chamber 1115, and rotating shaft 1116. Note that the ICP electrodes 1103a to 1103b in Figure 15 have a substantially concave or parabolic shape that curves toward the center of the substrate 1112.

[0071] As shown in Figure 15, the substrate 1112 is secured on the substrate holder 1111. Then, the rotating shaft 1116 is rotated using the power supply 1110 and a rotating mechanism (not shown) to rotate the substrate 1112. The substrate 112 is also heated by lamps 1107a to 1107b, and the inside of the vacuum chamber 1115 is evacuated to create a vacuum or reduced pressure using a vacuum pump (not shown). After that, Ar gas is introduced into the vacuum chamber 1115 from the Ar source 1108, and the surface of the substrate 1112 is cleaned by forming argon plasma on the substrate 1112 using DC power supplies 1105a to 1105b, RF power supplies 1106a to 1106b, ICP electrodes 1103a to 1103b, cut filters 1104a to 1104b, and grounds 1102a to 1102h.

[0072] Ar gas is introduced into the vacuum chamber 1115, and a reactive gas is also introduced using the reactive gas source 1109. At this time, the lamp heaters, lamps 1107a to 1107b, are alternately turned on and off, which allows for the formation of a higher quality crystal growth film. [Industrial applicability]

[0073] The laminated structure of the present invention can be used in a wide range of fields, including semiconductors (e.g., compound semiconductor electronic devices), electronic components, electrical equipment components, optical and electrophotographic equipment, and industrial materials, but is particularly suitable for use in semiconductor devices. [Explanation of symbols]

[0074] 1. Epitaxial film (compound piezoelectric or compound semiconductor) 4. In2O3 film or ITO film 5. Oxide film 9. Crystal Substrate 101 n-type semiconductor layer 101a n-type semiconductor layer 101b n+ type semiconductor layer 102 p-type semiconductor layer 104 Insulator layer 105a Schottky electrode 105b Ohmic electrode 106 Guard Ring 111a n-type semiconductor layer 111b n+ type semiconductor layer 114 Semi-insulating layer 115a Terminal 115b Source electrode 115c drain electrode 118 Buffer Layers 119 Crystal Substrate 121a N-type semiconductor layer with a wide bandgap 121b Narrow bandgap n-type semiconductor layer 121c n+ type semiconductor layer 123 Electron transport layer 124 Semi-insulating layer 125a Grid control 125b Source electrode 125c drain electrode 128 Buffer Layers 129 Crystal Substrate 131a n-type semiconductor layer 131b First n+ type semiconductor layer 131c Second n+ type semiconductor layer 132 p-type semiconductor layer 134 Gate insulating film 135a Token 135b Source electrode 135c drain electrode 141a n-type semiconductor layer 141b First n+ type semiconductor layer 141c Second n+ type semiconductor layer 142 p-type semiconductor layer 145a Terminal 145b Source electrode 145c drain electrode 151 n-type semiconductor layer 151a n-type semiconductor layer 151b n+ type semiconductor layer 152 p-type semiconductor layer 154 Gate Insulator 155a Terminal 155b Emitter electrode 155c collector electrode 161 n-type semiconductor layer 162 p-type semiconductor layer 163 Emitting layer 165a First electrode 165b Second electrode 167 Translucent electrode 1101a~101b Metal source 1102a~102j Earth 1103a~103b ICP electrode 1104a~104b Cut Filter 1105a~105b DC power supply 1106a~106b RF power supply 1107a~107b Lamp 1108 Ar source 1109 Reactive gas source 1110 Power supply 1111 Circuit board holder 1112 circuit board 1113 Cut Filter 1114 ICP ring 1115 Vacuum chamber 1116 Rotation axis

Claims

1. A crystalline substrate which is a Si substrate, A buffer layer is laminated on the aforementioned crystalline substrate and includes a crystalline film containing an oxide of Hf and / or Zr, An epitaxial film, consisting of a conductive film, a semiconductor film, or a piezoelectric film, is laminated on the buffer layer, A laminated structure having, The aforementioned buffer layer, The first crystal plane which is the interface with the epitaxial film, The second crystal plane opposite to the first crystal plane, Includes, At the interface between the buffer layer and the epitaxial film, the lattice constant of the buffer layer is the same as the lattice constant of the epitaxial film. A laminated structure in which the difference between the lattice constant of the first crystal plane and the lattice constant of the second crystal plane is within the range of 0.1% to 20%.

2. The laminated structure according to claim 1, wherein at the interface between the buffer layer and the epitaxial film, a peak-and-valley structure is formed in which the angles between adjacent peaks and troughs are different.

3. The laminated structure according to claim 2, wherein the angles between adjacent vertices and bases are each within the range of 30° to 45°.

4. The epitaxial film is made of the conductive film, The laminated structure according to any one of claims 1 to 3, wherein the conductive film comprises gold, silver, platinum, palladium, silver-palladium, copper, nickel, or an alloy thereof.

5. The epitaxial film is made of the piezoelectric film, The laminated structure according to any one of claims 1 to 3, wherein the piezoelectric film comprises lead zirconate titanate, barium titanate, lead titanate, potassium niobate, lithium niobate, lithium tantalate, sodium tungstate, zinc oxide, barium strontium titanate, strontium bismuth tantalate, lead metaniobate, zinc niobate, lead scandium niobate, polyvinylidene fluoride, or quartz.

6. An electronic device comprising a laminated structure, wherein the laminated structure is a laminated structure according to any one of claims 1 to 3.

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