Logic acceleration circuit and logic acceleration method for high-speed capacitive SAR-type ADC

Abstract

The application discloses a logic acceleration circuit and method of high-speed capacitive SAR ADC. The logic acceleration circuit comprises a two-way selector, a latch, a comparator and an adaptive asynchronous clock generator. The two-way selector is used for selecting the output latch result and the comparator result and is connected to the switch of the control capacitor array analog-digital converter (CDAC). The latch is used for latching the comparator result and is connected to the two-way selector. The comparator is used for comparing the output value of the CDAC with a reference voltage V ref , and outputting the comparison result. The comparison result is output to the two-way selector. After the comparison is completed, a comparison completion flag signal is output to the adaptive asynchronous clock generator. The adaptive asynchronous clock generator comprises a delay module DELAY and a plurality of NAND gates and NOT gates and is used for controlling the successive approximation steps. The application accelerates the logic operation, and each bit operation can be accelerated.

Description

Technical Field

[0001] This invention relates to a logic acceleration circuit and a logic acceleration method for a high-speed capacitive SAR ADC, which is used to improve the conversion speed of the ADC so that it can work normally at a higher sampling rate. Technical Background

[0002] SAR-type ADCs are widely used in the detection of physiological signals, the quantization of biological signals, low-power wireless communication systems, and the compensation of errors in circuit systems. For example, in power management modules, if the circuit system needs to output a high-precision voltage value, it can be corrected by an ADC. Typically, this circuit system requires more than one ADC because SAR-type ADCs can achieve single-ended, differential, and multi-channel input. Therefore, a single high-speed SAR-type ADC can meet the ADC requirements of this power management system.

[0003] Successive approximation analog-to-digital converters currently generally have a resolution of less than 16 bits. The analog circuits are simple, and a large part of the circuits are digital circuits. They do not require high-performance operational amplifiers and have good compatibility with manufacturing processes.

[0004] Due to its advantages such as strong process compatibility and low power consumption per unit area, successive approximation analog-to-digital converters (ADCs) are typically chosen for complex integrated circuit system designs when performance specifications are suitable. The conversion rate of a successive approximation ADC is closely related to the manufacturing process; generally, with the same architecture, a more advanced manufacturing process results in a faster conversion rate and lower power consumption.

[0005] SAR ADCs mainly include resistive, capacitive, and hybrid resistive-capacitive architectures. Resistive architectures achieve faster speeds, but due to poorer resistor matching compared to capacitors, they are more susceptible to temperature variations, resulting in lower accuracy. Furthermore, resistive architectures exhibit static power consumption, leading to higher overall power consumption. Capacitive architectures, on the other hand, have no static power consumption, offer better matching, and in high-resolution SAR ADCs, bridging capacitors can save area and reduce the total capacitance. However, mismatched bridging capacitors can introduce significant errors.

[0006] In a typical SAR-type ADC, the operation time of the digital logic includes the comparator comparison time, the latch latching time, and the logic circuitry that controls the capacitor array level based on the comparison result stored in the latch. Conventional acceleration methods generate an asynchronous clock for the logic operation based on the comparator comparison completion signal, making the internal timing more compact. Excluding the time spent by the digital and analog sections working together, the digital logic accounts for approximately 50% of the total conversion time, highlighting the urgent need for a method to further improve the conversion rate by accelerating the digital logic operation time. Summary of the Invention

[0007] The conversion rate of the SAR type ADC in the prior art is determined by the sampling time and the conversion time, in order to make the SAR type ADC have a faster conversion rate, the purpose of the present application is to provide a logic acceleration circuit and a logic acceleration method for a high-speed capacitive SAR type ADC.

[0008] The logic acceleration circuit for the high-speed capacitive SAR type ADC comprises a 2-way selector MUX, a latch LATCH, a comparator Comparator, and an adaptive asynchronous clock generator.

[0009] The 2-way selector is used for selecting the output latch result and the comparator result and is connected to the switch of the capacitive data to analog converter CDAC.

[0010] The latch is used for latching the comparator result and is connected to the 2-way selector.

[0011] The comparator is used for comparing the output value of the CDAC with a reference voltage V ref , and outputs a comparison result, the comparison result is output to the 2-way selector, and a comparison completion flag signal is output to the adaptive asynchronous clock generator after the comparison is completed.

[0012] The adaptive asynchronous clock generator comprises a delay module DELAY and a plurality of NAND gates, NOT gates, and a buffer for outputting a driving next stage, and is used for controlling the successive approximation steps.

[0013] The 2-way selector comprises two transmission gates.

[0014] The latch comprises two transmission gates and two inverters.

[0015] The output control of the 2-way selector adopts a 2-way selector control switch, and the 2-way selector control switch is controlled by a state register signal (one bit of the state register signal is generated in the logic circuit every asynchronous clock cycle) in the logic circuit of the non-acceleration circuit and a delay module and a NAND gate.

[0016] The adaptive asynchronous clock generator comprises four NAND gates, one delay module, one inverter, and one buffer. A method for performing logic acceleration by using the logic acceleration circuit for the high-speed capacitive SAR type ADC, and the steps are as follows:

[0017] 1) After the ADC is controlled to sample by an external input sampling clock, the comparator starts to work; after the comparator completes each comparison, the 2-way selector selects the comparison result of the comparator, and the latch latches the comparison result, and the latched result is kept until the next quantization.

[0018] 2) The adaptive asynchronous clock generator generates an asynchronous clock with a period long enough for the subsequent operation according to the flag signal of the comparison completion of the comparator output;

[0019] 3) The 2-way selector first outputs the i-th bit comparison result of the comparator output, and at the same time, the latch latches the i-th bit comparison result; according to the asynchronous clock and the additional delay module control the switch of the 2-way selector, after the latch latches is completed, the output is converted from the comparison result to the latch result, and is kept until the next quantization;

[0020] 4) The i-th bit ADC output value DATA signal is output by the D flip-flop, and the CDAC is operated according to the output result of the i-th bit 2-way selector;

[0021] 5) After the latch completes the latching, the comparator is reset, and the asynchronous clock controls the comparator to perform the next comparison;

[0022] 6) Repeat steps 1) to 5) until the quantization of the analog signal is completed by successive approximation.

[0023] In the step 3), when the asynchronous clock becomes 1, the i-th bit working state register in the logic circuit of the non-accelerating circuit becomes 1, at this time, the 2-way selector selects the comparator result output, and the latch starts to constantly latch the input result, at the same time, the comparator also starts to work; the output signal of the i-th bit state register passes through a delay module, after a certain delay, the 2-way selector selects the latch latching result, and the latch keeps the latched data; after the above operation is completed, the next step is entered.

[0024] In the step 5), after the comparator reset is completed, the CDAC needs to have a stable output to start comparison, the adaptive asynchronous clock generator outputs the i-th bit of the state register, the state register output result passes through a delay module and a NAND gate to generate a temporary 0 signal, which is used as the ACC signal acceleration asynchronous clock or DELAY The signal is asynchronous with the clock.

[0025] The method controls the adaptive asynchronous clock generator to slow down the clock for high-bit input signals and to speed up the clock for low-bit input signals.

[0026] The present application has the following advantages:

[0027] In practical application, in 0.18um process, the traditional method is 100ps to 200ps slower than the logic acceleration circuit structure mentioned in the present application according to the layout back simulation of each process angle, for an N-bit resolution ADC, 100*N ps to 200*N ps conversion time can be saved for each sampling quantization period. For a high-speed SAR type ADC, the level conversion from the completion of the asynchronous logic to the logic control capacitor array can be accelerated by 20%-30% after adding the acceleration circuit. In addition, the overall conversion speed can be further improved by about 10% after cooperating with the adaptive asynchronous clock generator. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a structural schematic diagram of the logic acceleration circuit of the high-speed capacitive SAR type ADC;

[0029] Figure 1 V in is an input signal, V ref is a reference voltage, STEP COMPARATOR_DONE is the comparator comparison done signal, S selects the input of the i-th 2-way selector, LATCH_DATA DATA for the latch to latch the i-th bit comparison result For the i-th bit comparison result, ACC for the i-th clock cycle, DELAY is the i th bit clock cycle delay signal, SAR_EN is the SAR logic clock enable signal, SAR_CLK is the SAR logic clock, MUX is a 2-way selector, LATCH is a latch, Comparator is a comparator, and DELAY is a delay module.

[0030] Figure 2 is a schematic diagram of the structure of the successive approximation logic circuit acceleration in the SAR type ADC in the present application.

[0031] Figure 3 is a 2-way selector.

[0032] Figure 3 E and E_I in are the selection signals of the 2-way selector, D is the input, and Q is the output.

[0033] Figure 4 is a latch structure in a standard logic unit.

[0034] Figure 4 E and E_I in are the enable signals of the latch, D is the input, and Q is the output.

[0035] Figure 5 is a waveform diagram of the key signals in the successive approximation logic circuit.

[0036] Figure 5 SWITCH The signal is the switch on the i-th capacitor array, and other signals are Figure 1 The same as in the middle.

[0037] Figure 6 It is a logic operation waveform diagram embodying the SAR type ADC.

[0038] Figure 7 It is a capacitor array switch method suitable for high-speed capacitive SAR type ADC.

[0039] Figure 8 It is a circuit structure for generating an asynchronous clock in a high-speed SAR type ADC. DETAILED DESCRIPTION

[0040] The present application is described and explained in conjunction with the accompanying drawings and examples, but the described examples are not intended to limit the present application.

[0041] The conversion rate of high-speed SAR type ADC is greatly affected by process, voltage, temperature (PVT) under the same process and the same architecture. In order to make the high-speed SAR type ADC achieve a high conversion rate under the condition of PVT not ideal, the present application designs a logic acceleration circuit for high-speed capacitive SAR type ADC.

[0042] As shown in Figure 1 , a logic acceleration circuit for high-speed capacitive SAR type ADC, comprising a 2-way selector MUX, a latch LATCH, a comparator Comparator, and an adaptive asynchronous clock generator. The connection mode of the acceleration circuit is as shown in Figure 2 , the 2-way selector selects the comparator result or the latch result output, and selects the comparator result for output, which will output the result earlier than the latch, to achieve the purpose of acceleration.

[0043] The 2-way selector, as shown in Figure 3 , is composed of two transmission gates. It is used to select and output the latch result and the comparator result and is connected to the switch of the capacitive data to analog converter CDAC (Capacitive data to analog converter). The specific structure of the 2-way selector can be selected as shown in Figure 3 , which includes two transmission gates. The 2-way selector control switch is controlled by the state register signal (one bit of state register signal will be generated in the logic circuit every asynchronous clock cycle) in the logic circuit of the non-acceleration circuit and a delay module and NAND gate.

[0044] The latch is used to latch the comparator result and is connected to the 2-way selector. The structure of the latch in the present embodiment is as shown in Figure 4 , which includes two transmission gates and two inverters. Figure 5 the timing diagram and Figure 1 The input-output signals in the timing diagram and The signal changes significantly faster than the signal shown by the dashed line in the figure without the acceleration circuit.

[0045] Figure 6 As can be seen from the waveform diagram, the comparator clock determines the upper limit of the ADC's sampling rate during one complete cycle of ADC operation. The comparator is used to compare the CDAC's output value with the reference voltage V. ref The comparison result is output to a 2-way selector. After the comparison is complete, a comparison completion flag signal is generated and output to the adaptive asynchronous clock generator. The specific operation of the CDAC is as follows: Figure 1 The capacitor array digital-to-analog converter obtains V through a sampling switch. in V in The most significant quantized value can be obtained by comparing it with the reference voltage. Based on the comparison result, the switching mode of the capacitor array is as follows: Figure 7 As shown, for example, the upper-level board samples the input signal V. in For quantization without a sign bit, the lower-level board of the capacitor array is connected to the reference voltage. If the comparison result of the i-th bit is 1, the upper-level board of the i-th bit capacitor is connected to V. ref Connect to GND potential; if the comparison result of the i-th bit is 0, the capacitor of the (i-1)-th bit is connected from GND to V. ref Potential, the i-th capacitor is determined by V ref Connect to GND potential.

[0046] The adaptive asynchronous clock generator includes a delay module (DELAY) and several NAND and NOT gates to control the successive approximation steps. In this embodiment, its structure is as follows: Figure 8 As shown. This structure includes four NAND gates, one delay module, one NOT gate, and one buffer. Two of the NAND gates can be used in conjunction with the ACC gate. and DELAY The signal can accelerate and delay the clock. The state register outputs a result through a delay module and a NAND gate to generate a temporary 0 signal, which is used as the ACC signal acceleration asynchronous clock or DELAY The signal is asynchronous with the clock. Usually, the DELAY signal is used as high logic operation to ensure that the high capacitor can complete the level conversion, and the ACC signal is used for low operation to reduce the clock period.

[0047] The present application accelerates the logic operation of each bit that needs to be converted by several 2-way selectors, so that the clock for successive approximation inside the high-speed SAR ADC can work at a higher frequency. The design steps include:

[0048] 1) Determine the capacitor size, capacitor switch resistance size, and level conversion time of the control capacitor array for the required precision and sampling rate of the designed high-speed SAR ADC, so as to meet the requirements of the ADC precision and conversion rate;

[0049] 2) Design the added logic circuit. Add a logic acceleration circuit for controlling the level conversion of the capacitor array in the logic circuit;

[0050] 3) Design the clock for successive approximation inside the ADC to ensure that the conversion of the ADC can be completed in each period.

[0051] The specific operation of step 2) is as follows:

[0052] First, the i-th flip-flop is converted, and the ADC enters the logic operation of the i-th bit.

[0053] The comparator completes the i-th comparison, and outputs a comparison completion signal.

[0054] After the i-th comparison of the i-th bit is completed, the i-th 2-way selector selects the output result of the comparator, and at the same time, the latch stores the i-th comparison result.

[0055] The output result of the 2-way selector makes the level of the capacitor array start to convert after a series of logic operations according to the switch mode of the capacitor array.

[0056] After the latch stores the comparison result, the 2-way selector selects the latch result, and the latch stops working. After the latch stops latching, the comparator starts to reset, and after the reset is completed and the level conversion of the capacitor array is completed, the next comparison is performed. Because of the acceleration circuit, the capacitor array operates early, and the level conversion will be completed earlier. Step 1) can determine that the level conversion time is less than the period size of the asynchronous clock.

[0057] A method for logic acceleration using the logic acceleration circuit of the high-speed capacitive SAR ADC, the steps are as follows:

[0058] 1) ADC is controlled by the sampling clock inputted from outside to complete sampling, then the comparator starts to work. After the comparator completes each comparison, the 2-way selector selects the comparison result of the comparator, and the latch latches the comparison result. The latched result is kept until the next quantization. The signal of controlling CDAC can change only when the state register is opened. After each conversion is completed, the state register signal is reset, and the latch does not need to be reset. The advantage of this is that the dynamic power consumption caused by the reset of the latch can be reduced.

[0059] 2) According to the flag signal of the comparison completion outputted by the comparator, an asynchronous clock generator generates an asynchronous clock with a period long enough for subsequent operations. This asynchronous clock is generated by the circuit structure shown in Figure 8 After the comparator completes the comparison, a high level 1 is generated. This signal will not pass through any delay module, but only through 6-level logic operation to make the asynchronous clock become 0, and this 0 type makes the comparator reset. After the comparator reset is completed, the output, the comparison completion flag signal becomes 0. This 0 signal will be affected by the delay module. The function of this delay module is to ensure that the CDAC output is stable when the comparator compares next time and compares with V ref and DELAY The time it takes for the SAR_CLK signal to become 1 is accelerated or delayed depending on the settling time of the CDAC output signal during the high-to-low bit conversion.

[0060] 3) The 2-way selector first outputs the comparison result of the i-th bit from the comparator, and simultaneously latches the comparison result of the i-th bit. The switching of the 2-way selector is controlled by an asynchronous clock and an additional delay module. After the latch is complete, the output is converted from the comparison result to the latch result and remains until the next quantization. The 2-way selector selects the... Figure 3 The structure shown is fast and simple. The latch uses... Figure 4 The structure shown is also a rapid structure. In practical applications... Figure 4 The structure is still relatively slow, but it can be used... Figure 3 The two selectors shown are used for acceleration, which allows the CDAC output to start changing faster, thus shortening its settling time. The comparator is a dynamic comparator, which includes a preamplifier to amplify the signal and isolate kickback noise. Since the preamplifier has bandwidth, there is still a certain time between the CDAC output stabilizing and the start of the comparison. Accelerating the stabilization of the CDAC output signal also reduces the bandwidth pressure on the preamplifier. If bandwidth allows, increasing the clock speed can improve the ADC's conversion rate.

[0061] 4) The DATA signal, the output value of the i-th ADC, is output by a D flip-flop. The CDAC is operated based on the output result of the i-th 2-way selector. The D flip-flop used for the output result is uniformly set after conversion. Figure 1 The quantized data output is latched by the latch in the circuit. When the output signal of the 2-way selector is 1 in the status register, it can control the CDAC to change the output voltage.

[0062] 5) After the latch completes latching, the comparator is reset, and the asynchronous clock controls the comparator to perform the next comparison. It's important to note that the comparator reset must be slower than the time it takes for the 2-way selector to select the latch output. This is to prevent the comparator output from being latched after the 2-way selector is reset. It must also be slower than the time it takes for the latch to enter the hold phase. This is to prevent latching onto the comparator output after the reset.

[0063] 6) Repeat steps 1) through 5) until the quantization of the analog signal is nearly complete. An N-bit ADC needs to repeat the above operation N times. That is, the acceleration circuit can function N times.

[0064] The step 3), when the asynchronous clock becomes 1, the i bit state register in the logic circuit of the non-accelerating circuit becomes 1, at this time the 2-way selector selects the comparator result output, the latch starts to continuously latch the input result, at the same time, the comparator also starts to work; the output signal of the i bit state register passes through a delay module, after a certain delay, the 2-way selector selects the latch latching result, and the latch keeps the latched data. After the above operation is completed, the next step is entered.

[0065] The step 5), after the comparator reset is completed, a stable output of the CDAC is needed to start comparison, when the adaptive asynchronous clock generator is in the i bit output state of the state register, the state register output result passes through a delay module and a NAND gate to generate a temporary 0 signal, the signal is used as the ACC signal acceleration asynchronous clock or DELAY The signal is asynchronous clock deceleration. The method, using high several input signal clock deceleration, low several input signal acceleration clock. If not with adaptive asynchronous clock generation structure, need to comply with the highest bit change CDAC output voltage stability needs time. However, low bit change, because the low bit change is CDAC output voltage stability fast, and low bit change when compared with two voltage value difference small, preamplifier bandwidth pressure is small, so it will lead to low bit has a lot of time empty.

[0066] The logic operation circuit of the control capacitor array switch must have a register or latch to save the comparison result of the comparator. Figure 4 A latch structure, Figure 3 The structure of 2-way selector, from the logic operation level and structure, 2-way selector is obviously faster than the latch.

[0067] Determine the conversion time and reset time of the comparator to ensure that the clock of step 5) can make the comparator complete the level comparison and complete the reset. After the comparator reset is completed, the CDAC needs to have a stable output to start comparison. Because the output of CDAC is stable for a long time when operating in high bit, and for a short time when operating in low bit, it is necessary to adjust Figure 8 The delay module in the internal logic operation clock cycle and use ACC and DELAY The signal is assisted. The status register output result generates a temporary 0 signal through a delay module and a NAND gate, which is used as the ACC signal acceleration asynchronous clock or DELAY The signal is asynchronous with the clock. Usually, the DELAY signal is used as high logic operation to ensure that the high capacitor can complete the level conversion, and the ACC signal is used for low operation to reduce the clock period. Figure 6 As can be seen from the waveform diagram, in a complete cycle of the ADC operation, the comparator clock determines the upper limit of the sampling rate of the ADC.

[0068] The successive approximation logic operation needs a plurality of registers to record the working state, a latch to record the comparison result of each bit, and operation on the capacitor array according to the comparison result of each bit. An internal comparator clock (also a clock generated by the adaptive asynchronous logic clock generator to control the internal logic operation) that is asynchronous with the sampling clock is generated in the ADC. This clock is used to control the working state of the internal successive approximation logic operation and the comparator. After the sampling is completed, the register is affected by the comparator clock, STEP<0> enters the working state of 1, and the logic operation is started. When the comparator result is output, the comparator result is latched. After the latching, the comparator clock enters the reset state. At the same time, the logic circuit controls the level conversion of the capacitor array. After the conversion is completed, the next comparator cycle is started. The successive approximation comparison is performed, and finally the latched result is output. The result is the quantization value of the ADC. The quantization value of the ADC is output by a special register.

[0069] After the logic operation circuit of the application is added, the capacitor array can enter the level conversion operation faster after the comparison is completed, and the logic is accelerated.

[0070] The principle of the logic acceleration in step 3) is that the 2-way selector is much faster than the latch in converting and outputting. The 2-way selector is used to output the comparison result of the comparator and cooperate with the adaptive asynchronous clock to accelerate. The 2-way selector outputs the comparison result of the comparator and latches the comparison result of the comparator at the same time. The output result of the 2-way selector is faster than the latch. The output result of the 2-way selector controls the level conversion of the capacitor array, so that the capacitor array completes the level conversion in advance. After the level conversion is completed, the comparator cannot directly compare. If the bandwidth of the preamplifier of the comparator is not enough, the comparison error will occur. This acceleration structure reduces the pressure on the bandwidth of the amplifier. This acceleration structure is particularly obvious in improving the conversion rate of the high-speed SAR ADC in the SS process corner and high-temperature operation. Since the operation is performed on the logic operation, the performance of the SAR ADC will not be affected.

[0071] In the 0.18um process, the layout of each process corner is simulated in actual application, and it can be seen that only Figure 4 The structure is faster than Figure 2 The structure accelerated by the latch and the 2-way selector slows 100ps to 200ps, and for an N-bit resolution ADC, each sampling and quantization cycle can save 100*N ps to 200*N ps of conversion time. Comparing the completion of the level conversion to the logic control capacitor array in the asynchronous logic of the added acceleration circuit can speed up 20%-30%. Cooperating with the adaptive asynchronous clock generator mentioned in the present application can further improve the overall conversion speed by about 10%.

[0072] The embodiments in the above description can be further combined or replaced, and the embodiments are only used to describe the preferred embodiments of the present application, and do not limit the concept and scope of the present application. Without departing from the design idea of the present application, various changes and improvements made by those skilled in the art to the technical solutions of the present application all belong to the protection scope of the present application. The protection scope of the present application is given by the appended claims and any equivalents thereof. ​

Claims

1. A method for logic acceleration using a high-speed capacitive SAR-type ADC logic acceleration circuit, characterized in that, The logic acceleration circuit of the high-speed capacitive SAR ADC includes a 2-way selector (MUX), a latch (LATCH), a comparator (Comparator), and an adaptive asynchronous clock generator. A 2-way selector is used to select the output latch result and comparator result and connects to the switch that controls the capacitor array analog-to-digital converter (CDAC). A latch is used to latch the comparator result and is connected to a 2-way selector; The comparator is used to compare the output value of the CDAC with the reference voltage V. ref The comparison result is output to the 2-way selector. After the comparison is completed, a comparison completion flag signal is generated and output to the adaptive asynchronous clock generator. The adaptive asynchronous clock generator includes a delay module DELAY and several NAND and NOT gates to control the successive approximation steps; The steps for accelerating logic are as follows: 1) The ADC is controlled by the external input sampling clock. After sampling is completed, the comparator starts to work. After the comparator completes each comparison, the 2-way selector selects the comparison result of the comparator, and the latch latches the comparison result. The latched result is kept until the next quantization. 2) Based on the comparison completion flag signal output by the comparator, the adaptive asynchronous clock generator generates an asynchronous clock with a cycle length sufficient for subsequent operations; 3) The 2-way selector first outputs the comparison result of the i-th bit of the comparator output, and at the same time the latch latches the comparison result of the i-th bit; the switching of the 2-way selector is controlled according to the asynchronous clock and the additional delay module. After the latch is completed, the output is converted from the comparison result to the latch result, and it is held until the next quantization. 4) The DATA signal, the output value of the i-th ADC, is output by a D flip-flop, and the CDAC is operated according to the output result of the i-th 2-way selector; 5) After the latch completes latching, the comparator is reset, and the asynchronous clock controls the comparator to perform the next comparison; 6) Repeat steps 1) to 5) until the quantization of the analog signal is completed by successive approximation.

2. The method according to claim 1, characterized in that, The 2-way selector includes two transmission gates.

3. The method according to claim 1, characterized in that, The latch includes two transmission gates and two inverters.

4. The method according to claim 1, characterized in that, The output control of the 2-way selector adopts a 2-way selector control switch. The 2-way selector control switch is controlled by a status register signal in the logic circuit of the non-acceleration circuit (a status register signal is generated in the logic circuit in each asynchronous clock cycle) in conjunction with a delay module and a NAND gate.

5. The method according to claim 1, characterized in that, The adaptive asynchronous clock generator includes four NAND gates, one delay module, one inverter, and one buffer.

6. The method according to claim 1, characterized in that, In step 3), when the asynchronous clock becomes 1, the i-th working status register in the logic circuit of the non-accelerated circuit becomes 1. At this time, the 2-way selector selects the comparator result output, and the latch starts to continuously latch the input result. At the same time, the comparator also starts to work. The output signal of the i-th status register passes through a delay module. After a certain delay, it controls the 2-way selector to select the latch to latch the result and makes the latch hold the latched data. Proceed to the next step.

7. The method according to claim 1, characterized in that, (Step 5) After the comparator reset is complete, the CDAC needs a stable output before comparison can begin. When the adaptive asynchronous clock generator outputs the i-th bit of the status register, the status register output is processed by a delay module and a NAND gate to generate a temporary 0 signal. This signal serves as the ACC signal. Signal acceleration asynchronous clock or DELAY The signal slows down the asynchronous clock.

8. The method according to claim 7, characterized in that, The clock is slowed down by using the higher-order bits of the input signal and accelerated by using the lower-order bits of the input signal.

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