A method and apparatus for transmitting information

Abstract

This application provides a method and apparatus for transmitting information. The method includes: a first apparatus sending first indication information to a second apparatus to indicate whether there is cache sharing capability between the links of the first apparatus; the first apparatus may also send second indication information to indicate the cache status; the second apparatus can determine the link for the first apparatus to send cached data based on the first indication information, or the first and second indication information, thereby improving the flexibility of information transmission, enhancing transmission performance, and solving the problem of resource waste caused by the mismatch between resource allocation and actual needs.

Description

Technical Field

[0001] This application relates to the field of communications. In particular, it relates to a method and apparatus for transmitting information. Background Technology

[0002] With the development of communication technology, the amount of information transmitted by communication systems is constantly increasing, which places higher demands on Wireless Local Area Networks (WLANs). Multi-Link Operation (MLO), as one of the key technologies for the future, enables WLAN devices to send and receive information across multiple frequency bands, thereby utilizing greater bandwidth for data transmission and significantly improving throughput. However, existing multi-link device (MLD) information scheduling and transmission mechanisms lack flexibility, and resource reporting does not match actual needs, easily leading to significant resource waste. Therefore, how to improve the flexibility of information transmission, avoid resource waste, and enhance transmission performance is an urgent problem to be solved. Summary of the Invention

[0003] This application provides a method and apparatus for transmitting information.

[0004] Firstly, a method for transmitting information is provided, applied to a first MLD, the first MLD comprising N stations (STAs), the N STAs involving N links, where N is a positive integer, the method may include:

[0005] The first MLD sends a first indication message on the first link. The first indication message is used to indicate whether there is a cache sharing capability between the links of the first MLD. The cache sharing capability is used to determine the link corresponding to the cached data to be sent in the first MLD. The first link is one of N links.

[0006] It should be understood that N is a positive integer, which can be a positive integer greater than or equal to 1, or a positive integer greater than or equal to 2. For example, generally, an MLD includes multiple STAs, but it is not excluded that an MLD may contain only one STA through functional integration or other means.

[0007] This method indicates to the second MLD whether the links of the first MLD have cache sharing capability by sending an indication message. This solves the problem that the second MLD cannot obtain whether the links included in the first MLD have cache sharing capability. The second MLD can use the first indication message as a reference factor to determine the scheduling link, avoiding the problem that the link scheduled by the second MLD has no sharing capability with the sending link of the first MLD, which would cause the first MLD to be unable to prepare cache data.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the method may further include:

[0009] The first MLD sends a second indication message on the second link, which is one of N links. The second indication message is used to indicate the buffer status. The second link corresponds to the first STA, and the buffer data to be sent is the buffer data of the first STA.

[0010] It should be understood that the cache status can include the cache size, as well as the ownership of that cache size, such as whether it belongs to the first MLD or a certain STA.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, the second indication information includes a first field, which is used to indicate the cache size of the cache area.

[0012] If the first indication information indicates that the links of the first MLD have cache sharing capability, the first field is used to indicate the cache size of the first MLD.

[0013] If the first indication information indicates that the links of the first MLD do not have cache sharing capability, the first field is used to indicate the cache size of the first MLD.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the second indication information includes a second field, which is used to indicate the BSR of the first MLD in the buffer state, or the buffer state of the first MLD.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the method may further include:

[0016] The first MLD receives the trigger frame TF on the third link, which is determined based on the first indication information, or based on the first indication information and the second indication information;

[0017] The first MLD sends the buffered data of the first STA on the third link.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the first indication information indicates that the links of the first MLD do not have cache sharing capability, and the third link is the second link.

[0019] or,

[0020] The first indication information indicates that the links of the first MLD have cache sharing capability, and the third link is one of the links with cache sharing capability.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, the method may further include: the first MLD sending second indication information on the second link, the second link being one of N links, the second indication information being used to indicate the buffer status.

[0022] In conjunction with the first aspect, in some implementations of the first aspect, the second indication information may include a first field, which is used to indicate the cache state as either the first STA or the first MLD.

[0023] In conjunction with the first aspect, in some implementations of the first aspect, the second indication information may include a second field, which is used to indicate the cache size of the cache area.

[0024] If the first indication information indicates that the links of the first MLD have cache sharing capability, the second field is used to indicate the cache size of the MLD.

[0025] If the first indication information indicates that the links of the first MLD do not have cache sharing capability, the second field is used to indicate the cache size of the first STA.

[0026] That is, the first MLD can also send a second indication message to indicate the status of the buffer to the second MLD. This can be done by explicitly indicating to the second MLD whether the buffer status belongs to the first STA or the MLD to which that STA belongs; or implicitly indicating to the second MLD whether it has buffer sharing capability. For example, an MLD with buffer sharing capability across links indicates the total buffer status of that MLD; otherwise, it only indicates the buffer status of one of the STAs.

[0027] In conjunction with the first aspect, in some implementations of the first aspect, the method may further include:

[0028] The first MLD receives the trigger frame TF on the third link, which is determined based on the first indication information, or the first indication information and the second indication information.

[0029] The first MLD sends the buffered data of the first STA on the third link.

[0030] In conjunction with the first aspect, in some implementations of the first aspect, the first indication information indicates that the links included in the MLD do not have cache sharing capability, and the third link is the second link.

[0031] or,

[0032] The first indication information indicates that the links included in the MLD have cache sharing capability, and the third link is one of the links with cache sharing capability.

[0033] It should be understood that when the links included in MLD have cache sharing capabilities, the selection of the third link may be affected by other factors, such as the inability to select a link if it is temporarily closed.

[0034] This scheme determines the path for the first device to transmit information based on the cache sharing capability indication, or based on the cache sharing capability indication and cache status reporting information. This avoids the problem of scheduled links not being able to be shared, and further determines the link that can send the service information completely based on the cache status. It can also reasonably allocate resources, further improving the flexibility of information transmission.

[0035] In conjunction with the first aspect, in some implementations of the first aspect, the first indication information may include a third field.

[0036] When the third field takes the first value, it can be used to indicate that any two links out of N links have cache sharing capability; when the third field takes the second value, it can be used to indicate that any two links out of N links do not have cache sharing capability.

[0037] or,

[0038] When the third field takes the first value, it can be used to indicate that there is no cache sharing capability between any two links in N links. When the third field takes the second value, it can be used to indicate that there is cache sharing capability between any two links in N links.

[0039] In conjunction with the first aspect, in some implementations of the first aspect, the third field may include 1 bit.

[0040] It should be understood that the first value can be 1 and the second value can be 0; or, the first value can be 0 and the second value can be 1.

[0041] In conjunction with the first aspect, in some implementations of the first aspect, the first indication information may be located in the multi-link device capability domain (MLD Capability).

[0042] In conjunction with the first aspect, in some implementations of the first aspect, the first indication information includes a cache shared delay field, which is used to indicate the time between the first MLD receiving the TF and sending the cached data.

[0043] In conjunction with the first aspect, in some implementations of the first aspect, the value of the cache sharing delay domain can be a first preset value, which is less than a first threshold. The cache sharing delay domain can be used to indicate that any two links among N links have cache sharing capability.

[0044] or,

[0045] The value of the cache sharing delay domain can be a second preset value, which is greater than or equal to the first threshold. The cache sharing delay domain can be used to indicate that there is no cache sharing capability between any two links in N links.

[0046] It should be understood that due to the different capabilities of MLD, the cache latency of each link may also be different. The cache sharing latency field can indicate the cache sharing latency, and can also be used as a reference condition to indicate whether cache sharing can be achieved between links.

[0047] In conjunction with the first aspect, in some implementations of the first aspect, the cache shared latency domain can be located in the multi-link device capability domain (MLD Capability).

[0048] In conjunction with the first aspect, in some implementations of the first aspect, the first indication information may include a cache sharing indication field, the cache sharing indication field may include a cache sharing indication bitmap, the cache sharing indication bitmap may include m bits, the value of each bit may be used to indicate whether the links included in the first link pair have cache sharing capability, the links included in the first link pair may be the links indicated by the first link identifier and the links indicated by the second link identifier, the first link identifier may be the link identifier included in each site profile sub-element, the second link identifier may be the link identifier included in the site control information STA Control, and the cache sharing indication bitmap may be located in the site information STA Info of each site profile sub-element.

[0049] In conjunction with the first aspect, in some implementations of the first aspect, the i-th bit of the cache sharing indicator bitmap can be 1, indicating that the links included in the first link pair have cache sharing capability; the i-th bit of the cache sharing indicator bitmap can be 0, indicating that the links included in the first link pair do not have cache sharing capability.

[0050] or,

[0051] The i-th bit of the cache sharing indicator bitmap can be 1, indicating that the links included in the first link pair do not have cache sharing capability; or the i-th bit of the cache sharing indicator bitmap can be 0, indicating that the links included in the first link pair have cache sharing capability.

[0052] Where 0≤i≤n-1, the second link is identified as link i.

[0053] In conjunction with the first aspect, in some implementations of the first aspect, each site profile sub-element may also include a cache sharing indicator, which is used to indicate whether a cache sharing indicator bitmap appears in the STA Info.

[0054] In conjunction with the first aspect, in some implementations of the first aspect, the first indication information may include a cache delay indication bitmap. The cache delay indication bitmap may include k fields, and the value of each field can be used to indicate whether the links included in the second link pair have cache sharing capability. The links included in the second link pair are the links indicated by the third link identifier and the links indicated by the fourth link identifier. The third link identifier is the link identifier included in each site profile sub-element, and the fourth link identifier is the link identifier included in the site control information STA Control. The cache delay indication bitmap is located in the site information STA Info of each site profile sub-element. Where 0 ≤ j ≤ k-1.

[0055] In conjunction with the first aspect, in some implementations of the first aspect, the value of the j-th field of the cache latency indicator bitmap can be a third preset value, which is less than the second threshold. The j-th field is used to indicate that the links included in the first link pair have cache sharing capability.

[0056] or,

[0057] The value of the j-th field in the cache latency indicator bitmap can be a fourth preset value, which is greater than or equal to a second threshold. The j-th field is used to indicate that the links included in the first link pair have cache sharing capability.

[0058] Where 0≤j≤k-1, the fourth link is identified as link j.

[0059] In conjunction with the first aspect, in some implementations of the first aspect, each site profile sub-element may also include a cache delay indicator, which is used to indicate whether a cache delay indicator bitmap appears in the site information STA Info.

[0060] In conjunction with the first aspect, in some implementations of the first aspect, the first indication information may include a cache sharing capability indication bitmap, which may include N fields, each corresponding one-to-one with N links, wherein each field includes 1 bit.

[0061] Links corresponding to fields with a value of 0 have cache-sharing capabilities with other links corresponding to fields with a value of 0, while links corresponding to fields with a value of 1 do not have cache-sharing capabilities with any other link.

[0062] or,

[0063] Links with a value of 0 do not have cache sharing capability with any other link, while links with a value of 1 have cache sharing capability with other links with a value of 1.

[0064] In conjunction with the first aspect, in some implementations of the first aspect, the first indication information may include a cache sharing capability indication bitmap, which includes N fields, each of the N fields including at least two bits, and the N fields corresponding one-to-one with the N links.

[0065] Links corresponding to fields with the third value do not have cache sharing capabilities with any other link, while links corresponding to fields with values ​​other than the third value have cache sharing capabilities with links corresponding to fields with the same value.

[0066] It should be understood that the values ​​of the bits or fields mentioned above are just examples. The values ​​can be the first value or the second value. The first and second values ​​can be determined according to the number of bits and the change of the base. For example, in binary, the first and second values ​​can be 0 or 1, and in other bases, they can be the corresponding values. This application does not limit this.

[0067] Secondly, a method for transmitting information is provided, applied to a second MLD, the second MLD including N access points (APs), the N APs involving N links, where N is a positive integer, the method may include:

[0068] The second MLD receives the first indication information on the first link. The first indication information is used to indicate whether there is cache sharing capability between the links of the first MLD. The cache sharing capability is used by the second MLD to determine the link corresponding to the cached data to be received. The first link is one of N links.

[0069] It should be understood that N is a positive integer, which can be a positive integer greater than or equal to 1, or a positive integer greater than or equal to 2. For example, generally, an MLD includes multiple APs, but it is not excluded that an MLD may also include only one AP through functional integration or other means.

[0070] This method indicates to the second MLD whether the links of the first MLD have cache sharing capability by sending an indication message. This solves the problem that the second MLD cannot obtain whether the links of the first MLD have cache sharing capability. The second MLD can use the first indication message as a reference factor to determine the scheduling link, avoiding the problem that the link scheduled by the second MLD has no sharing capability with the sending link of the first STA, which would cause the first STA to be unable to prepare cached data.

[0071] In conjunction with the second aspect, in some implementations of the second aspect, the method may further include:

[0072] The second MLD receives the second indication information on the second link, which is one of N links. The second indication information is used to indicate the buffer status. The second link corresponds to the first STA, and the buffer data to be received is the buffer data of the first STA.

[0073] In conjunction with the second aspect, in some implementations of the second aspect, the second indication information includes a first field, which is used to indicate the cache size of the cache area.

[0074] If the first indication information indicates that the links of the first MLD have cache sharing capability, the first field is used to indicate the cache size of the first MLD.

[0075] If the first indication information indicates that the links of the first MLD do not have cache sharing capability, the first field is used to indicate the cache size of the first STA.

[0076] In conjunction with the second aspect, in some implementations of the second aspect, the second indication information includes a second field, which is used to indicate the cache state as either the first STA or the first MLD.

[0077] In conjunction with the second aspect, in some implementations of the second aspect, the method may further include:

[0078] The second MLD sends a trigger frame TF on the third link, which is determined based on the first indication information, or based on the first indication information and the second indication information.

[0079] The second MLD receives the buffered data from the first STA on the third link.

[0080] In conjunction with the second aspect, in some implementations of the second aspect, the first indication information indicates that the links of the first MLD do not have cache sharing capability, and the third link is the second link, or...

[0081] The first indication information indicates that the links of the first MLD have cache sharing capability, and the third link is one of the links with cache sharing capability.

[0082] It should be understood that when the links included in MLD have cache sharing capabilities, the selection of the third link may be affected by other factors, such as the inability to select a link if it is temporarily closed.

[0083] This scheme determines the path for transmitting the first MLD information based on the cache sharing capability indication, or based on the cache sharing capability indication and cache status reporting information. This avoids the problem of scheduled links not being able to be shared, and further determines the link that can send the service information completely based on the cache status. It can also reasonably allocate resources, further improving the flexibility of information transmission.

[0084] In conjunction with the second aspect, in some implementations of the second aspect, the first indication information may include a third field.

[0085] When the third field takes the first value, it can be used to indicate that any two links out of N links have cache sharing capability; when the third field takes the second value, it can be used to indicate that any two links out of N links do not have cache sharing capability.

[0086] or,

[0087] When the third field takes the first value, it can be used to indicate that there is no cache sharing capability between any two links in N links. When the third field takes the second value, it can be used to indicate that there is cache sharing capability between any two links in N links.

[0088] In conjunction with the second aspect, in some implementations of the second aspect, the third field may include 1 bit.

[0089] It should be understood that the first value can be 1 and the second value can be 0; or, the first value can be 0 and the second value can be 1.

[0090] In conjunction with the second aspect, in some implementations of the second aspect, the first indication information may be located in the Multi-Link Device Capability domain (MLD Capability).

[0091] In conjunction with the second aspect, in some implementations of the second aspect, the first indication information includes a cache shared delay field, which is used to indicate the time between the first MLD receiving the TF and sending the cached data.

[0092] In conjunction with the second aspect, in some implementations of the second aspect, the value of the cache sharing delay domain can be a first preset value, which is less than a first threshold. The cache sharing delay domain can be used to indicate that any two links among N links have cache sharing capability.

[0093] or,

[0094] The value of the cache sharing delay domain can be a second preset value, which is greater than or equal to the first threshold. The cache sharing delay domain can be used to indicate that there is no cache sharing capability between any two links in N links.

[0095] It should be understood that due to the different capabilities of MLD, the cache latency of each link may also be different. The cache sharing latency field can indicate the cache sharing latency, and can also be used as a reference condition to indicate whether cache sharing can be achieved between links.

[0096] In conjunction with the second aspect, in some implementations of the second aspect, the cache shared latency domain can be located in the multi-link device capability domain (MLD Capability).

[0097] In conjunction with the second aspect, in some implementations of the second aspect, the first indication information may include a cache sharing indication field, the cache sharing indication field may include a cache sharing indication bitmap, the cache sharing indication bitmap may include m bits, the value of each bit may be used to indicate whether the links included in the first link pair have cache sharing capability, the links included in the first link pair may be the links indicated by the first link identifier and the links indicated by the second link identifier, the first link identifier may be the link identifier included in each site profile sub-element, the second link identifier may be the link identifier included in the site control information STA Control, and the cache sharing indication bitmap may be located in the site information STA Info of each site profile sub-element.

[0098] In conjunction with the second aspect, in some implementations of the second aspect, the i-th bit of the cache sharing indicator bitmap can be 1, indicating that the links included in the first link pair have cache sharing capability; the i-th bit of the cache sharing indicator bitmap can be 0, indicating that the links included in the first link pair do not have cache sharing capability.

[0099] or,

[0100] The i-th bit of the cache sharing indicator bitmap can be 1, indicating that the links in the first link pair do not have cache sharing capability, or the i-th bit of the cache sharing indicator bitmap can be 0, indicating that the links in the first link pair have cache sharing capability.

[0101] Where 0≤i≤n-1, the second link is identified as link i.

[0102] In conjunction with the second aspect, in some implementations of the second aspect, each site profile sub-element may also include a cache sharing indicator, which is used to indicate whether a cache sharing indicator bitmap appears in the STA Info.

[0103] In conjunction with the second aspect, in some implementations of the second aspect, the first indication information may include a cache delay indication bitmap. The cache delay indication bitmap may include k fields, and the value of each field can be used to indicate whether the links included in the second link pair have cache sharing capability. The links included in the second link pair are the links indicated by the third link identifier and the links indicated by the fourth link identifier. The third link identifier is the link identifier included in each site profile sub-element, and the fourth link identifier is the link identifier included in the site control information (STA Control). The cache delay indication bitmap is located in the site information (STA Info) of each site profile sub-element. Where 0 ≤ j ≤ k-1.

[0104] In conjunction with the second aspect, in some implementations of the second aspect, the value of the j-th field of the cache latency indicator bitmap can be a third preset value, which is less than the second threshold. The j-th field is used to indicate that the links included in the first link pair have cache sharing capability.

[0105] or,

[0106] The value of the j-th field in the cache latency indicator bitmap can be a fourth preset value, which is greater than or equal to a second threshold. The j-th field is used to indicate that the links included in the first link pair have cache sharing capability.

[0107] Where 0≤j≤k-1, the fourth link is identified as link j.

[0108] In conjunction with the second aspect, in some implementations of the second aspect, each site profile sub-element may also include a cache delay indicator, which is used to indicate whether a cache delay indicator bitmap appears in the site information STA Info.

[0109] In conjunction with the second aspect, in some implementations of the second aspect, the first indication information may include a cache sharing capability indication bitmap, which may include N fields, each corresponding one-to-one with N links, wherein each field includes 1 bit.

[0110] Links corresponding to fields with a value of 0 have cache-sharing capabilities with other links corresponding to fields with a value of 0, while links corresponding to fields with a value of 1 do not have cache-sharing capabilities with any other link.

[0111] or,

[0112] Links with a value of 0 do not have cache sharing capability with any other link, while links with a value of 1 have cache sharing capability with other links with a value of 1.

[0113] In conjunction with the second aspect, in some implementations of the second aspect, the first indication information may include a cache sharing capability indication bitmap, which includes N fields, each of which includes at least two bits, and the N fields correspond one-to-one with the N links.

[0114] Links corresponding to fields with the third value do not have cache sharing capabilities with any other link, while links corresponding to fields with values ​​other than the third value have cache sharing capabilities with links corresponding to fields with the same value.

[0115] Thirdly, a communication device is provided, which may include a transceiver unit and a processing unit. The transceiver unit is used to send first indication information on a first link. The first indication information is used to indicate whether there is a cache sharing capability between the links of the first MLD. The cache sharing capability is used to determine the link corresponding to the cached data to be sent in the first MLD. The first link is one of N links.

[0116] In conjunction with the third aspect, in some implementations of the third aspect, the transceiver unit is also used to send second indication information on the second link, which is one of N links, and the second indication information is used to indicate the status of the buffer area.

[0117] In conjunction with the third aspect, in some implementations of the third aspect, the second indication information may include a first field, which is used to indicate the buffer state as either a first STA or an MLD.

[0118] In conjunction with the third aspect, in some implementations of the third aspect, the second indication information may include a second field, which is used to indicate the cache size of the cache area.

[0119] If the first indication information indicates that the links included in the first MLD have cache sharing capability, the second field is used to indicate the cache size of the MLD.

[0120] If the first indication information indicates that the links included in the first MLD do not have cache sharing capability, the second field is used to indicate the cache size of the first STA.

[0121] In conjunction with the third aspect, in some implementations of the third aspect, the transceiver unit is also used to receive a trigger frame TF on a third link, the third link being determined according to the first indication information, or the first indication information and the second indication information; and to transmit the buffered data of the first STA on the third link.

[0122] In conjunction with the third aspect, in some implementations of the third aspect, the first indication information indicates that the links included in the MLD do not have cache sharing capability, and the third link is the second link.

[0123] or,

[0124] The first indication information indicates that the links included in the MLD have cache sharing capability, and the third link is one of the links with cache sharing capability.

[0125] It should be understood that when the links included in MLD have cache sharing capabilities, the selection of the third link may be affected by other factors, such as the inability to select a link if it is temporarily closed.

[0126] In conjunction with the third aspect, in some implementations of the third aspect, the first indication information may include a third field.

[0127] When the third field takes the first value, it can be used to indicate that any two links out of N links have cache sharing capability; when the third field takes the second value, it can be used to indicate that any two links out of N links do not have cache sharing capability.

[0128] or,

[0129] When the third field takes the first value, it can be used to indicate that there is no cache sharing capability between any two links in N links. When the third field takes the second value, it can be used to indicate that there is cache sharing capability between any two links in N links.

[0130] In conjunction with the third aspect, in some implementations of the third aspect, the third field may include 1 bit.

[0131] It should be understood that the first value can be 1 and the second value can be 0; or, the first value can be 0 and the second value can be 1.

[0132] In conjunction with the third aspect, in some implementations of the third aspect, the first indication information may be located in the Multi-Link Device Capability (MLD Capability) domain.

[0133] In conjunction with the third aspect, in some implementations of the third aspect, the first indication information includes a buffer shared delay field, which is used to indicate the time between the transceiver unit receiving the TF and transmitting the buffered data.

[0134] In conjunction with the third aspect, in some implementations of the third aspect, the value of the cache sharing delay domain can be a first preset value, which is less than a first threshold. The cache sharing delay domain can be used to indicate that any two links among N links have cache sharing capability.

[0135] or,

[0136] The value of the cache sharing delay domain can be a second preset value, which is greater than or equal to the first threshold. The cache sharing delay domain can be used to indicate that there is no cache sharing capability between any two links in N links.

[0137] In conjunction with the third aspect, in some implementations of the third aspect, the cache shared latency domain can be located in the multi-link device capability domain (MLD Capability).

[0138] In conjunction with the third aspect, in some implementations of the third aspect, the first indication information may include a cache sharing indication field, the cache sharing indication field may include a cache sharing indication bitmap, the cache sharing indication bitmap may include m bits, the value of each bit may be used to indicate whether the links included in the first link pair have cache sharing capability, the links included in the first link pair may be the links indicated by the first link identifier and the links indicated by the second link identifier, the first link identifier may be the link identifier included in each site profile sub-element, the second link identifier may be the link identifier included in the site control information STA Control, and the cache sharing indication bitmap may be located in the site information STA Info of each site profile sub-element.

[0139] In conjunction with the third aspect, in some implementations of the third aspect, the i-th bit of the cache sharing indicator bitmap can be 1, indicating that the links included in the first link pair have cache sharing capability; the i-th bit of the cache sharing indicator bitmap can be 0, indicating that the links included in the first link pair do not have cache sharing capability.

[0140] or,

[0141] The i-th bit of the cache sharing indicator bitmap can be 1, indicating that the links in the first link pair do not have cache sharing capability, or the i-th bit of the cache sharing indicator bitmap can be 0, indicating that the links in the first link pair have cache sharing capability.

[0142] Where 0≤i≤n-1, the second link is identified as link i.

[0143] In conjunction with the third aspect, in some implementations of the third aspect, each site profile sub-element may also include a cache sharing indicator, which is used to indicate whether a cache sharing indicator bitmap appears in the STA Info.

[0144] In conjunction with the third aspect, in some implementations of the third aspect, the first indication information may include a cache delay indication bitmap. The cache delay indication bitmap may include k fields, and the value of each field can be used to indicate whether the links included in the second link pair have cache sharing capability. The links included in the second link pair are the links indicated by the third link identifier and the links indicated by the fourth link identifier. The third link identifier is the link identifier included in each site profile sub-element, and the fourth link identifier is the link identifier included in the site control information (STA Control). The cache delay indication bitmap is located in the site information (STA Info) of each site profile sub-element. Where 0 ≤ j ≤ k-1.

[0145] In conjunction with the third aspect, in some implementations of the third aspect, the value of the j-th field of the cache latency indicator bitmap can be a third preset value, which is less than the second threshold. The j-th field is used to indicate that the links included in the first link pair have cache sharing capability.

[0146] or,

[0147] The value of the j-th field in the cache latency indicator bitmap can be a fourth preset value, which is greater than or equal to a second threshold. The j-th field is used to indicate that the links included in the first link pair have cache sharing capability.

[0148] Where 0≤j≤k-1, the fourth link is identified as link j.

[0149] In conjunction with the third aspect, in some implementations of the third aspect, each site profile sub-element may also include a cache delay indicator, which is used to indicate whether a cache delay indicator bitmap appears in the site information STA Info.

[0150] In conjunction with the third aspect, in some implementations of the third aspect, the first indication information may include a cache sharing capability indication bitmap. This bitmap may include N fields, each corresponding to one of the N links, with each field comprising one bit.

[0151] Links corresponding to fields with a value of 0 have cache-sharing capabilities with other links corresponding to fields with a value of 0, while links corresponding to fields with a value of 1 do not have cache-sharing capabilities with any other link.

[0152] or,

[0153] Links with a value of 0 do not have cache sharing capability with any other link, while links with a value of 1 have cache sharing capability with other links with a value of 1.

[0154] In conjunction with the third aspect, in some implementations of the third aspect, the first indication information may include a cache sharing capability indication bitmap. This bitmap includes N fields, each of which contains at least two bits. Each of the N fields corresponds one-to-one with one of the N links.

[0155] Links corresponding to fields with the third value do not have cache sharing capabilities with any other link, while links corresponding to fields with values ​​other than the third value have cache sharing capabilities with links corresponding to fields with the same value.

[0156] Fourthly, a communication device is provided, which may include a transceiver unit and a processing unit, and a method for transmitting information, applied to a multi-link device (MLD). The MLD includes N access points (APs) and N links, where N is a positive integer greater than or equal to 2, and the N APs correspond one-to-one with the N links. The method may include:

[0157] The first AP receives first indication information on the first link. The first indication information is used to indicate whether there is buffer sharing capability among the links included in the MLD. The buffer sharing capability is used to determine the link through which the first STA sends buffered data. The first link is one of N links.

[0158] This method indicates to the first AP whether the links of the MLD where the first STA is located have cache sharing capability by sending an indication message. This solves the problem that the first AP cannot obtain whether the links included in the first STA have cache sharing capability. The first AP can use the first indication message as a reference factor to determine the scheduling link, avoiding the problem that the link scheduled by the first AP has no sharing capability with the sending link of the first STA, which would cause the first STA to be unable to prepare cached data.

[0159] Fourthly, a communication device is provided, which may include a transceiver unit and a processing unit.

[0160] The transceiver unit is used to receive first indication information on the first link. The first indication information is used to indicate whether there is cache sharing capability between the links of the first MLD. The cache sharing capability is used by the processing unit to determine the link corresponding to the cached data to be received. The first link is one of N links.

[0161] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the transceiver unit is also used to receive second indication information on the second link, the second link being one of N links, the second indication information being used to indicate the buffer status, the second link corresponding to the first STA, and the buffer data to be received being the buffer data of the first STA.

[0162] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the second indication information includes a first field, which is used to indicate the cache size of the cache area.

[0163] If the first indication information indicates that the links of the first MLD have cache sharing capability, the first field is used to indicate the cache size of the first MLD.

[0164] If the first indication information indicates that the links of the first MLD do not have cache sharing capability, the first field is used to indicate the cache size of the first STA.

[0165] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the second indication information includes a second field, which is used to indicate the cache state as either the first STA or the first MLD.

[0166] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the transceiver unit is also used to send a trigger frame TF on a third link, the third link being determined according to the first indication information, or according to the first indication information and the second indication information, and to receive buffered data of the first STA on the third link.

[0167] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the first indication information indicates that the links of the first MLD do not have cache sharing capability, the third link is the second link, or...

[0168] The first indication information indicates that the links of the first MLD have cache sharing capability, and the third link is one of the links with cache sharing capability.

[0169] It should be understood that when the links included in MLD have cache sharing capabilities, the selection of the third link may be affected by other factors, such as the inability to select a link if it is temporarily closed.

[0170] This scheme determines the path for transmitting the first MLD information based on the cache sharing capability indication, or based on the cache sharing capability indication and cache status reporting information. This avoids the problem of scheduled links not being able to be shared, and further determines the link that can send the service information completely based on the cache status. It can also reasonably allocate resources, further improving the flexibility of information transmission.

[0171] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the first indication information may include the third field.

[0172] When the third field takes the first value, it can be used to indicate that any two links out of N links have cache sharing capability; when the third field takes the second value, it can be used to indicate that any two links out of N links do not have cache sharing capability.

[0173] or,

[0174] When the third field takes the first value, it can be used to indicate that there is no cache sharing capability between any two links in N links. When the third field takes the second value, it can be used to indicate that there is cache sharing capability between any two links in N links.

[0175] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the third field may include 1 bit.

[0176] It should be understood that the first value can be 1 and the second value can be 0; or, the first value can be 0 and the second value can be 1.

[0177] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the first indication information may be located in the Multi-Link Device Capability (MLD Capability) domain.

[0178] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the first indication information includes a cache shared delay field, which is used to indicate the time between the first MLD receiving the TF and sending the cached data.

[0179] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the value of the cache sharing delay domain can be a first preset value, which is less than a first threshold. The cache sharing delay domain can be used to indicate that any two links among N links have cache sharing capability.

[0180] or,

[0181] The value of the cache sharing delay domain can be a second preset value, which is greater than or equal to the first threshold. The cache sharing delay domain can be used to indicate that there is no cache sharing capability between any two links in N links.

[0182] It should be understood that due to the different capabilities of MLD, the cache latency of each link may also be different. The cache sharing latency field can indicate the cache sharing latency, and can also be used as a reference condition to indicate whether cache sharing can be achieved between links.

[0183] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the cache shared latency domain can be located in the multi-link device capability domain (MLD Capability).

[0184] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the first indication information may include a cache sharing indication field, the cache sharing indication field may include a cache sharing indication bitmap, the cache sharing indication bitmap may include m bits, the value of each bit may be used to indicate whether the links included in the first link pair have cache sharing capability, the links included in the first link pair may be the links indicated by the first link identifier and the links indicated by the second link identifier, the first link identifier may be the link identifier included in each site profile sub-element, the second link identifier may be the link identifier included in the site control information STA Control, and the cache sharing indication bitmap may be located in the site information STA Info of each site profile sub-element.

[0185] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the i-th bit of the cache sharing indicator bitmap can be 1, indicating that the links included in the first link pair have cache sharing capability; the i-th bit of the cache sharing indicator bitmap can be 0, indicating that the links included in the first link pair do not have cache sharing capability.

[0186] or,

[0187] The i-th bit of the cache sharing indicator bitmap can be 1, indicating that the links in the first link pair do not have cache sharing capability, or the i-th bit of the cache sharing indicator bitmap can be 0, indicating that the links in the first link pair have cache sharing capability.

[0188] Where 0≤i≤n-1, the second link is identified as link i.

[0189] In conjunction with the fourth aspect, in some implementations of the fourth aspect, each site profile sub-element may also include a cache sharing indicator, which is used to indicate whether a cache sharing indicator bitmap appears in the STA Info.

[0190] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the first indication information may include a cache delay indication bitmap. The cache delay indication bitmap may include k fields, the value of which can be used to indicate whether the links included in the second link pair have cache sharing capability. The second link pair includes the links indicated by the third link identifier and the links indicated by the fourth link identifier. The third link identifier is the link identifier included in each site profile sub-element, and the fourth link identifier is the link identifier included in the site control information (STA Control). The cache delay indication bitmap is located in the site information (STA Info) of each site profile sub-element. Where 0 ≤ j ≤ k-1.

[0191] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the value of the j-th field of the cache latency indicator bitmap can be a third preset value, which is less than the second threshold. The j-th field is used to indicate that the links included in the first link pair have cache sharing capability.

[0192] or,

[0193] The value of the j-th field in the cache latency indicator bitmap can be a fourth preset value, which is greater than or equal to a second threshold. The j-th field is used to indicate that the links included in the first link pair have cache sharing capability.

[0194] Where 0≤j≤k-1, the fourth link is identified as link j.

[0195] In conjunction with the fourth aspect, in some implementations of the fourth aspect, each site profile sub-element may also include a cache delay indicator, which is used to indicate whether a cache delay indicator bitmap appears in the site information STA Info.

[0196] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the first indication information may include a cache sharing capability indication bitmap. This bitmap may include N fields, each corresponding to one of the N links, with each field comprising one bit.

[0197] Links corresponding to fields with a value of 0 have cache-sharing capabilities with other links corresponding to fields with a value of 0, while links corresponding to fields with a value of 1 do not have cache-sharing capabilities with any other link.

[0198] or,

[0199] Links with a value of 0 do not have cache sharing capability with any other link, while links with a value of 1 have cache sharing capability with other links with a value of 1.

[0200] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the first indication information may include a cache sharing capability indication bitmap. This bitmap includes N fields, each of which contains at least two bits. Each of the N fields corresponds one-to-one with one of the N links.

[0201] Links corresponding to fields with the third value do not have cache sharing capabilities with any other link, while links corresponding to fields with values ​​other than the third value have cache sharing capabilities with links corresponding to fields with the same value.

[0202] It should be understood that the explanation and supplementation of the first aspect and the possible implementation methods in the first aspect also apply to the second, third or fourth aspects, which will not be repeated here.

[0203] Fifthly, a communication device is provided, which can be a terminal device or a chip within a terminal device. The communication device may include a processing unit and a transceiver unit. When the communication device is a terminal device, the processing unit may be a processor, and the transceiver unit may be a transceiver; the terminal device may further include a storage unit, which may be a memory; the storage unit is used to store instructions, and the processing unit executes the instructions stored in the storage unit to cause the terminal device to perform the methods of terminal device execution in the above aspects. When the device is a chip within a terminal device, the processing unit may be a processor, and the transceiver unit may be an input / output interface, pin, or circuit, etc.; the processing unit executes the instructions stored in the storage unit to cause the terminal device to perform the methods of terminal device execution in the above aspects; the storage unit may be a storage unit within the chip (e.g., a register, cache, etc.), or a storage unit located outside the chip within the terminal device (e.g., a read-only memory, random access memory, etc.).

[0204] Optionally, the processor can be a general-purpose processor, which can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. This memory can be integrated into the processor or located outside the processor and exist independently.

[0205] When the program is executed, the processor performs the method described in the first aspect or any possible implementation thereof via the transceiver.

[0206] Sixthly, a communication device is provided, which may be a network device or a chip within a network device. The communication device may include a processing unit and a transceiver unit. When the communication device is a network device, the processing unit may be a processor, and the transceiver unit may be a transceiver; the network device may further include a storage unit, which may be a memory; the storage unit is used to store instructions, and the processing unit executes the instructions stored in the storage unit to cause the network device to perform the network device execution methods described in the above aspects. When the device is a chip within a network device, the processing unit may be a processor, and the transceiver unit may be an input / output interface, pin, or circuit, etc.; the processing unit executes the instructions stored in the storage unit to cause the network device to perform the network device execution methods described in the above aspects; the storage unit may be a storage unit within the chip (e.g., a register, cache, etc.), or a storage unit located outside the chip within the network device (e.g., a read-only memory, random access memory, etc.).

[0207] Optionally, the processor can be a general-purpose processor, which can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. This memory can be integrated into the processor or located outside the processor and exist independently.

[0208] When the program is executed, the processor performs the method described in the second aspect or any possible implementation thereof via the transceiver.

[0209] A seventh aspect provides a computer-readable storage medium including a computer program that, when run on a communication device, causes the communication device to perform the method as described in the first aspect or any implementation thereof.

[0210] Eighthly, a computer-readable storage medium is provided, including a computer program that, when executed on a communication device, causes the communication device to perform the method as described in the second aspect or any implementation thereof.

[0211] Ninth aspect, a computer program product is provided that, when the computer program product is run on a computer, causes the computer to perform the method as described in the first aspect or any implementation thereof.

[0212] In a tenth aspect, a computer program product is provided that, when the computer program product is run on a computer, causes the computer to perform the method as described in the second aspect or any implementation thereof.

[0213] It should be noted that the beneficial effects on the device side are similar to those on the method side. For details, please refer to the description of the beneficial effects on the method side, which will not be repeated here. Attached Figure Description

[0214] Figure 1 A communication system applicable to this application is shown;

[0215] Figure 2 A schematic diagram illustrating the relationship between MLD, STA, AP, and links applicable to this application is shown;

[0216] Figure 3 This illustrates a method for transmitting information;

[0217] Figure 4 A method for transmitting information applicable to this application is shown;

[0218] Figure 5 A frame structure applicable to this application is shown;

[0219] Figure 6 Another frame structure applicable to this application is shown;

[0220] Figure 7 Another frame structure applicable to this application is shown;

[0221] Figure 8 Another frame structure applicable to this application is shown;

[0222] Figure 9 Another frame structure applicable to this application is shown;

[0223] Figure 10 Another frame structure applicable to this application is shown;

[0224] Figure 11 This is a schematic block diagram of a communication device applicable to this application;

[0225] Figure 12 This is a schematic block diagram of a communication device applicable to this application. Detailed Implementation

[0226] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0227] The technical solutions of this application embodiment can be applied to various communication systems, such as: Global System of Mobile communication (GSM) system, Code Division Multiple Access (CDMA) system, Wideband Code Division Multiple Access (WCDMA) system, General Packet Radio Service (GPRS), Long Term Evolution (LTE) system, LTE Frequency Division Duplex (FDD) system, LTE Time Division Duplex (TDD) system, Universal Mobile Telecommunication System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX) communication system, future 5th Generation (5G) system, or New Radio (NR), etc.

[0228] The terminal device in this application embodiment can refer to user equipment, access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user device. The terminal device can also be a cellular phone, cordless phone, Session Initiation Protocol (SIP) phone, Wireless Local Loop (WLL) station, Personal Digital Assistant (PDA), handheld device with wireless communication capabilities, computing device or other processing device connected to a wireless modem, in-vehicle device, wearable device, terminal device in future 5G networks, or terminal device in future evolved Public Land Mobile Network (PLMN), etc., and this application embodiment does not limit this to these categories.

[0229] The network device in this application embodiment can be a device for communicating with terminal devices. The network device can be a base station (BTS) in a Global System of Mobile communication (GSM) system or Code Division Multiple Access (CDMA), a base station (NodeB, NB) in a Wideband Code Division Multiple Access (WCDMA) system, an evolved NodeB (eNB or eNodeB) in an LTE system, a radio controller in a Cloud Radio Access Network (CRAN) scenario, or a relay station, access point, vehicle-mounted device, wearable device, or a network device in a future 5G network or a network device in a future evolved PLMN network, etc. The embodiments of this application are not limited.

[0230] To facilitate understanding of the embodiments of this application, a brief introduction to the relevant concepts will be given in advance:

[0231] 1. Link

[0232] WLAN devices have the ability to send and receive information on multiple frequency bands. These multiple frequency bands include, but are not limited to, the 2.4GHz WiFi band, the 5GHz WiFi band, and the 6GHz WiFi band. Access and transmission on each of these frequency bands is called a link, or access and transmission within a frequency range of the same frequency band is called a link.

[0233] 2. Multi-link devices

[0234] Next-generation IEEE 802.11 standard station equipment that simultaneously supports multiple links is called a Multi-Link Device (MLD), and the internal entity responsible for any one link is called a Station (STA). If all STAs within an MLD are non-access point stations, such as... Figure 2 The first STA (220) to the Nth STA (230) can be further referred to as a non-access point station (non-AP STA, i.e., the first MLD in this application), such as Figure 2 The first MLD (210) in the MLD; if all STAs within a certain MLD are Access Points (APs), such as Figure 2The first AP (270) to the Nth AP (280) can be further referred to as an Access Point Multi-Link Device (AP MLD, i.e., the second MLD in this application), such as Figure 2 The second MLD (260) in the series. There are N links between the MLDs, where N is a positive integer, such as... Figure 2 Link 1 (240) to Link N (250) in the middle.

[0235] 3. Cache sharing capability

[0236] The ability of a cached data to be sent across multiple links by the AP MLD via Trigger Based PHY Protocol Data Unit (TB PPDU).

[0237] The description "AP 1@AP MLD@link 1" in the following diagrams and textual discussions indicates that AP 1 in AP MLD is operating on link 1, which can be... Figure 2 The first AP (270) in the MLD. The description form "STA 1@non-AP MLD@link 1" indicates that STA 1 in the non-AP MLD is operating on link 1, which can be... Figure 2 The first STA (220) in the network. AP 1@AP MLD@link1 and AP 2@AP MLD@link 2 belong to the same AP MLD, and can be... Figure 2 The second MLD (260) operates on link 1 and link 2 respectively. STA 1@non-AP MLD@link 1 and STA2@non-AP MLD@link 2 belong to the same non-AP MLD and can be... Figure 2 The first MLD (210) in the process operates on link 1 and link 2 respectively, and can be Figure 2 Link 1 (240) and Link N (250) in the middle.

[0238] Figure 3This is a schematic diagram of the uplink transmission process based on trigger frame (TF) scheduling. Non-access point stations (non-AP STAs) can send buffer state report frames (BSRs) to report their buffer status. After winning channel access, the access point (AP) sends a TF frame to schedule uplink data transmission for the non-AP STA. Upon receiving the TF frame, the non-AP STA performs high-efficiency (HE) uplink transmission based on the trigger-based PHY Protocol Data Unit (TB PPDU) on the corresponding Resource Unit (RU) according to the scheduling information.

[0239] In multi-link transmission, the two STAs (STA 1 and STA 2) in the non-AP MLD each have a buffer. However, the data packets in the buffer of STA 1@non-AP MLD@link 1 cannot be prepared on link 2 within the Short Inter Frame Space (SIFS) time, meaning they cannot be transmitted on link 2 after the SIFS time. This inability to prepare buffer data can mean either that the buffer data cannot be shared from the buffer of STA 1@non-AP MLD@link 1 to the buffer of STA 2@non-AP MLD@link 2 within the SIFS time, or that the buffer data of STA 1@non-AP MLD@link 1 cannot be shared with STA 2@non-AP MLD@link 2 within the SIFS time. Conversely, the data packets in the buffer of STA 2@non-AP MLD@link 2 also cannot be prepared on link 1 within the SIFS time, meaning they cannot be transmitted on link 1 after the SIFS time. If STA 1@non-AP MLD@link 1 has buffered data packets in its buffer and sends a BSR to AP 1@AP MLD@link 1, while STA 2@non-AP MLD@link 2 has no buffered data packets, and APMLD defaults to the ability for non-AP MLD to transmit on both links, then after AP 2@AP MLD@link 2 wins the channel access on link 2, it sends a TF to schedule STA 2@non-AP MLD@link 2 to send a TB PPDU on link 2. However, because the data packets in STA 1@non-AP MLD@link 1's buffer cannot be prepared on link 2 within the SIFS time, STA 2@non-AP MLD@link 2 cannot transmit data packets. Therefore, it can only transmit padding bits corresponding to the uplink duration (ULLength) in the TF frame, without transmitting uplink service information, resulting in a significant waste of resources.

[0240] Another possible scenario is that, for a period of time, STA 1@non-AP MLD@link 1 has a smaller buffer data volume, while STA 2@non-AP MLD@link 2 has a larger buffer data volume. STA 1@non-AP MLD@link 1 feeds back its buffer status to AP 1@AP MLD@link 1 via BSR on link 1, while STA 2@non-AP MLD@link 2 does not have the opportunity to feed back its buffer status to AP 2@AP MLD@link 2 during this period. AP1@AP MLD@link 1 schedules STA 1@non-AP MLD@link 1 to transmit uplink data on link 1 by sending TF frames based on the buffer status fed back by STA 1@non-AP MLD@link 1. However, AP 1@AP MLD@link 1 only obtains the buffer status on STA 1@non-AP MLD@link 1, and based on this buffer status, determines that the traffic volume of the non-AP MLD is small, thus allocating only a small amount of resources to it. In reality, the buffer cache of STA 2@non-AP MLD@link 2, which also belongs to the non-AP MLD, has a large amount of data waiting to be transmitted, but the AP MLD is unaware of this and therefore does not allocate sufficient resources to it, resulting in the non-AP MLD's service needs not being met in a timely manner. In summary, the existing buffer reporting mechanism causes a mismatch between the reported buffer status and the actual total resource requirements of the MLD.

[0241] To address the aforementioned problems, one embodiment of this application proposes as follows: Figure 4 The method shown:

[0242] 401: The first device sends a first indication message, which is used to indicate whether there is a cache sharing capability between the links of the first device, and the cache sharing capability indicates the links through which the first device can send cached data.

[0243] 402: The second device receives the first instruction information.

[0244] This method proposes that whether the links of the first device have cache sharing capability can be indicated to the second device by sending indication information. This solves the problem that the second device cannot obtain whether the links included in the first device have cache sharing capability. The second device can use the first indication information as a reference factor to determine the scheduling link, thus avoiding the problem that the first device cannot prepare cache data on the links scheduled by the second device.

[0245] It should be understood that the first device can be a non-AP MLD or an AP MLD, and the second device can be an AP MLD; this application does not limit this.

[0246] It should be understood that the MLD in this application can be a terminal device or a network device. The STA and AP in this application are both internal entities of the MLD; that is, an MLD can contain multiple STAs or multiple APs. The MLD includes N links, where N is a positive integer. Information is transmitted between the N STAs and the N APs through these N links. The correspondence between STAs and APs can be determined at the time of network access or it can be preset; this application does not limit this.

[0247] Optionally, the method may further include:

[0248] 402: The first device sends second indication information on the second link, which is one of N links, and the second indication information is used to indicate the status of the buffer area;

[0249] 403: The second device receives the second instruction information, determines the third link based on the first instruction information, or the first instruction information and the second instruction information, and sends a TF on the link;

[0250] 404: The first device receives the TF on the third link and transmits information on that link.

[0251] The second indication information can be a buffer state report (BSR).

[0252] This method determines the path for the first device to transmit information based on the cache sharing capability indication, or based on the cache sharing capability indication and cache status reporting information. In addition to avoiding the problem of scheduled links not being able to be shared, it further determines the link that can send the service information completely based on the cache status, and can also reasonably allocate resources, thereby further improving the flexibility of information transmission.

[0253] The following describes the scheme using the example of a first device being a non-AP MLD (first MLD) and a second device being an AP MLD (second MLD).

[0254] For example, the first MLD reports its cache sharing capability to the second MLD via an indication message. The second MLD receives the indication message and determines whether the links of the first MLD can share the cache based on the content of the indication message.

[0255] If the links of the first MLD can share a buffer, the second MLD can choose to send TF on any link.

[0256] It should be understood that the link through which the second MLD transmits the TF can be the link through which the second MLD has won the right to use the channel.

[0257] If the links of the first MLD cannot share a buffer, the second MLD can send a TF on the link where the first MLD sent the BSR;

[0258] The first MLD receives the TF and sends the buffered data on the link where the TF is located.

[0259] It should be understood that in the first MLD, all links may have cache sharing capability, all links may not have cache sharing capability, and some links may have cache sharing capability. When the first AP determines the link to send TF based on the first instruction information or the second instruction information, there may be other limiting factors.

[0260] For example, when the first indication information indicates that all links included in the MLD have cache sharing capabilities, but due to other factors, such as a link being shut down after the second MLD receives the indication information, the second MLD will exclude that link when determining the link to send the TF.

[0261] Understandably, after receiving the instruction information, similar situations will be taken into consideration when the second MLD determines the link to send the TF.

[0262] It should be understood that the first STA belongs to the non-AP MLD. The non-AP MLD can fill a buffer sharing information field in a frame or information element to indicate whether the MLD supports buffer sharing.

[0263] The following describes several specific methods for indicating buffer sharing capabilities, all using the MLD Capability field within the Multilink Element (ML element) in IEEE 802.11be as an example. It should be noted that the ML element is the preferred element for carrying signaling, but the buffer sharing information field may also be carried in the Extremely High Throughput Capability element or other newly created element fields. This application does not limit this.

[0264] It should be understood that the information exchanged between the first MLD and the second MLD can be transmitted through internal entities, such as STA and AP.

[0265] To facilitate understanding, the cache sharing capabilities of non-AP MLDs are categorized as follows:

[0266] Level 0: The AP does not need to perform special processing when sending Trigger Frames (TF). Non-AP MLDs can send uplink data via TB PPDU after the Trigger Frame SIFS. In other words, the links of this MLD have buffer sharing capability and do not need buffer sharing delay to prepare data.

[0267] Level 1: The AP needs to pad the sent Trigger frames for buffer delay based on the parameters reported by the non-AP MLD, so that the non-AP MLD has enough time to prepare to send uplink data using TB PPDU. In other words, the links of this MLD can share the buffer, but it takes a certain amount of time to share.

[0268] Level 2: Non-AP MLDs require a long time (e.g., more than hundreds of microseconds) to internally schedule data, making it unsuitable for AP MLDs to schedule them by adding a long padding to the Trigger frame. However, AP MLDs can first use a frame to inform the non-AP MLD to prepare buffered data on a certain link. After a certain waiting time, the AP MLD then schedules the non-AP MLD to send data via the Trigger frame. In other words, the links included in this MLD can share buffers, but the time for sharing buffers between links exceeds a certain threshold.

[0269] Level 3: Non-AP MLDs do not support cache sharing, meaning their cache is based on links or STAs. Cache data for a specific link must be uploaded through that link. In other words, cache sharing is not possible between the links included in the MLD.

[0270] It should be understood that the above classification is for ease of understanding and is an example of classifying MLD capabilities; this application does not limit it.

[0271] It should also be understood that the links included in MLD may not all have cache sharing capabilities, or they may only have some. Different indication methods may be used for different specific situations. The specific indication methods are described in detail below.

[0272] One possible implementation is to use a field to indicate whether all links included in the MLD have cache sharing capabilities.

[0273] For example, a field is introduced in the MLD Capability field of IEEE 802.11be to indicate, such as Figure 5 As shown.

[0274] It should be understood that this field may include one bit or multiple bits, and this application does not limit this.

[0275] Among them, the value of 1 in the Buffer Sharing Capability indicator field indicates that all links included in the non-AP MLD can share the buffer. After the first STA receives a Trigger frame on any link, it can use TB PPDU to send buffered data uplink.

[0276] A value of 0 in the Buffer Sharing Capability field indicates that the non-APMLD can only receive Trigger frames on the link with the first STA's data buffer and transmit buffered data uplink via TB PPDU on that link. If the BSR only allows transmission on the data buffer link, then the link sending the BSR is the data buffer link; if the BSR allows transmission on any link, then the corresponding link needs to be indicated in the BSR.

[0277] It should be understood that the values ​​0 and 1 can be interchanged. For example, a value of 0 in the Buffer Sharing Capability field indicates that buffer sharing is possible among all links in the non-AP MLD. After receiving a Trigger frame on any link, buffered data can be sent uplink using a TB PPDU. A value of 1 indicates that all links in the non-AP MLD can only receive Trigger frames on the link where the first STA sends a BSR, and buffered data can only be sent uplink on that link using a TB PPDU.

[0278] This implementation method is applicable when all links in the non-AP MLD have the same cache sharing capability and all links can share cache, or when none of the links can share cache. For example, it can be applied to Level 0 and Level 3 MLDs. In real-world applications, there are also cases where the cache sharing capabilities of each link are different.

[0279] One possible implementation, such as Figure 6 As shown, a Buffer Sharing Indication Bitmap can be added to the STAInfo field of each site profile sub-element to indicate whether a pair of links has buffer sharing capability. The i-th bit of the Buffer Sharing Indication Bitmap in a site profile sub-element is used to indicate the buffering capability between the link corresponding to that site profile sub-element and the link identified as i.

[0280] Optionally, a Buffer Sharing Indication field can be added to the STA Control field of the Per-STA Profile subelement of the Basic variant Multi-link element. This field indicates whether a Buffer Sharing Indication Bitmap appears in the STA Info field of the Per-STA Profile subelement.

[0281] Specifically, when the cache sharing indicator bit map appears, assuming its length is m bits, its bit i (0 <= i <= m-1) represents whether the link identifier link i included in STA Control and the link corresponding to the link identifier in the per-site profile sub-element can share the cache.

[0282] For example, bit 6 represents whether the cache can be shared between link 6 and the link corresponding to the sub-element of the site profile. When bit 6 is 1, it can be shared, and when bit 6 is 0, it cannot be shared; or, when bit 6 is 1, it cannot be shared, and when bit 6 is 0, it can be shared.

[0283] It should be understood that two links with symmetrical shared capabilities can be indicated in a single instruction, while two links with asymmetrical shared capabilities require instruction in different directions, doubling the signaling overhead. For example, the shared capability between link 6 and the link corresponding to each site profile sub-element needs to be indicated, and the shared capability between the link corresponding to each site profile sub-element and link 6 also needs to be indicated.

[0284] Another possible implementation, such as Figure 7 As shown, since the 11be standard supports a maximum of 16 links, a total of 16 bits can be used to indicate the buffer sharing capability of the links, with 1 bit used to indicate each link.

[0285] For example, if the bit value corresponding to the i-th link is 0, it means that link i cannot share its cached data with other links; if the bit value corresponding to the i-th link is 1, it means that link i can share its cached data with other links. In other words, a link with a bit value of 0 cannot share its cache with other links, while multiple links with a bit value of 1 can share their caches.

[0286] Another possible implementation is to use multiple bits to indicate a link, that is, to indicate it through a field that includes at least two bits.

[0287] When the value of the field corresponding to the i-th link is 0, it means that link i cannot share its cached data with other links. When the value of the bit corresponding to the i-th link is non-zero, it means that link i can share its cached data with other links that have the same value.

[0288] In other words, links corresponding to fields with a value of 0 cannot share cache with other links, while links corresponding to fields with a value of k (k>0) can share cache.

[0289] It should be understood that the values ​​of bits or fields in this application are only examples. The values ​​can be a first value or a second value. The first and second values ​​can be determined according to the number of bits and the change of the base. For example, in binary, the first and second values ​​can be 0 or 1, and in other bases, they can be the corresponding values. This application does not limit this.

[0290] Since MLD supports no more than 8 links in many scenarios, in order to save signaling overhead, when all link IDs do not exceed 7, a buffer sharing capability length field can be introduced to indicate that the length of the buffer sharing capability field is 8 or 16.

[0291] One possible implementation, such as Figure 8 As shown, the first indication information can also be used to indicate the buffer sharing delay, which can be the delay time required for a non-AP MLD to transmit buffered data uplink using a TB PPDU frame. The buffer sharing delay of this MLD can be indicated by the buffer sharing delay field.

[0292] It should be understood that the delay time can be the time other than the minimum trigger frame processing time (MinTrigProcTime) of a single link feedback, or the total delay time including the single link MinTrigProcTime. Which one to use can be specified in the standard.

[0293] MinTrigProcTime is a parameter introduced in the IEEE 802.11ax standard. It is the time that a non-AP STA reports to the AP to inform it of the time required to prepare uplink data after receiving a Trigger frame scheduled for it.

[0294] Understandably, when the delay time is the total delay duration including the single-link MinTrigProcTime, the value of the delay time must be greater than or equal to the reported MinTrigProcTime.

[0295] Generally, the length of the cache shared latency field is greater than or equal to 2 bits. The following example uses 3 bits.

[0296] Typically, a buffer shared latency value (e.g., 0) represents a latency of 0, meaning that trigger frames can be sent via the AP on any link without needing to add extra padding to the trigger frames.

[0297] Optionally, a cache sharing latency value, such as 7, can be reserved, which means that the latency exceeds a preset threshold, i.e., cross-link scheduling of cached data is not supported. In this case, AP MLD needs to use Trigger frames to schedule on the link where the first STA sends the BSR, and cannot schedule across links.

[0298] It should be understood that the correspondence between each value and the delay time can be calculated by a formula or enumerated in a table in a standard, and this application does not limit it.

[0299] This implementation method applies when the cache sharing capability of each link in the non-AP MLD is the same, meaning that the latency of non-APs within the MLD is the same. In real-world applications, there are also cases where the cache sharing latency of each link is different.

[0300] One possible implementation, such as Figure 9 As shown, a buffer delay indicator can be added to the STA Info field of the Per-STA Profile subelement. This buffer delay indicator contains several subfields, each of which can be used to indicate the buffer shared delay time between a pair of links. For example, the i-th subfield is used to indicate the buffer shared delay time between the link corresponding to this Per-STA Profile subelement and the link identified as i.

[0301] Optionally, a Buffer Delay Indication field is added to the STA Control field of each Per-STA Profile subelement of the Basic variant Multi-link element to indicate whether a Buffer Delay Indication Bitmap appears in the STA Info field of the Per-STA Profile subelement.

[0302] When the Buffer Delay Indication Bitmap appears, it contains k or k - 1 subfields. In the case of k subfields, subfield j (0 ≤ j ≤ k - 1) represents the shared delay between the link with link identifier link j in the STA control information and the link corresponding to the link identifier included in this Per-STA Profile subelement; in the case of k - 1 subfields, assuming the link identifier corresponding to this Per-STA Profile subelement is s, when j < s, subfield j (0 ≤ j ≤ k - 2) represents the shared delay between the link with link identifier link j in the STA control information and the link corresponding to the link identifier included in this Per-STA Profile subelement; when j ≥ k, subfield j (0 ≤ j ≤ k - 2) represents the shared delay between the link with link identifier link j + 1 in the STA control information and the link corresponding to the link identifier included in this Per-STA Profile subelement.

[0303] It should be understood that the above size relationship is for illustration rather than limitation.

[0304] Figure 9 The sharing ability between a pair of links is symmetric. For example, the delay of caching data shared from link 1 to link 2 is equal to the delay of caching data shared from link 2 to link 1. If the sharing ability of two links is not symmetric, then it is necessary to further indicate the sharing ability in different directions for each link pair, that is, it is necessary to indicate the delay of sharing from link 1 to link 2 and the delay of sharing from link 2 to link 1, so the signaling overhead needs to be doubled.

[0305] In the above embodiments, the buffer sharing capability of non-AP STAs is indicated to AP by adding indication information. AP can determine the link to schedule non-AP STAs to send buffered data based on the content of the indication information. This avoids the problem that non-AP STAs cannot transmit uplink service information and thus cause a large waste of resources because they have not prepared buffered data on the link scheduled by AP. They can only transmit padding bits of the corresponding duration according to the uplink duration (UL Length) in the TF frame.

[0306] Another embodiment of this application proposes a method for reporting buffer status, which can add rule constraints to the standard.

[0307] This method does not require modification of the existing IEEE 802.11ax Buffer State Report (BSR) frame structure, but it requires the following constraints:

[0308] The BSR reported by a non-AP STA with cache sharing capability is the total cache status of that non-AP MLD, that is, the total buffer status of all STAs belonging to that non-AP MLD.

[0309] The BSR reported by a non-AP STA that does not have cache sharing capability is only the cache status of that STA itself.

[0310] In another embodiment of this application, a new A-Control type is introduced, wherein 1 bit indicates whether the feedback content is link-based or MLD-based, and the remaining bits are used to indicate the specific buffer size.

[0311] It should be understood that the indication information may be provided by designing a new Control ID field to use unused bits for indication, or it may be provided by reusing a bit from an existing Control Information field.

[0312] Considering that multi-link communication is introduced in the embodiments of this application, the frame structure needs to be improved.

[0313] Another embodiment of this application, such as Figure 10As shown, a new A-Control type is introduced, using a new A-Control frame to indicate multi-link level buffer status reporting information. The A-Control field from IEEE 802.11ax is adopted. The control identifier field in the A-Control field uses an existing reserved value (e.g., 11) to indicate multi-link level buffer status reporting. The control information field consists of multiple subfields, similar to the subfield settings of existing BSRs in IEEE 802.11ax, except that the value of the scaling factor field has changed, as shown in Table 1.

[0314] Table 1. Relationship between the range of scaling factor values ​​and the meaning of scaling factor

[0315] Scale factor range Scale factor meaning (in bytes) 0 32 1 512 2 8192 3 131072

[0316] It should be understood that Table 1 is an example rather than a limitation, and may be used in part or in whole.

[0317] In another embodiment of this application, it is not necessary to introduce a new A control type; the BSR frame structure of IEEE 802.11ax is reused. The BSR frame in IEEE 802.11ax also uses the A control frame structure, with its control identifier field fixed at a value of 3.

[0318] For links with buffer sharing capabilities, the BSR reported by non-AP STAs can be the overall buffer status at the multi-link level. In this case, the Scaling Factor field value of the BSR frame has the same meaning as in Table 1.

[0319] For links without buffer sharing capabilities, the BSR reported by the non-AP STA can be the buffer status of its own STA. The meaning of the scale factor field value in the BSR frame is consistent with the existing IEEE 802.11ax.

[0320] This scheme, through the design of constraint rules and / or the introduction of a new A-Control type, instructs the AP based on the indication information. The BSR reported by the non-AP STA is either the total buffer status of the non-AP MLD or the buffer status of the non-AP STA. After receiving the indication information and buffer status, the AP can allocate resources reasonably, avoiding the problem of mismatch between the reported buffer status and the actual total resource requirements of the MLD. This is beneficial to the integrity of service transmission and improves the flexibility of service transmission.

[0321] Similar to the above concept, such as Figure 11As shown, this application embodiment also provides an apparatus 1300 for implementing the functions of the network device or terminal device in the above method. For example, the apparatus can be a software module or a chip system. In this application embodiment, the chip system can be composed of chips or may include chips and other discrete devices. The apparatus 1300 may include: a processing unit 1310 and a communication unit 1320.

[0322] In this embodiment of the application, the communication unit may also be called a transceiver unit, which may include a sending unit and / or a receiving unit, respectively used to perform the steps of sending and receiving the first MLD and / or the second MLD in the above method embodiment.

[0323] The following, combined with Figures 11 to 12 This application provides a detailed description of the communication device provided in its embodiments. It should be understood that the descriptions of the device embodiments correspond to the descriptions of the method embodiments; therefore, any content not described in detail here will be referred to the method embodiments above, and for the sake of brevity, will not be repeated here.

[0324] A communication unit can also be called a transceiver, transceiver device, or transceiver unit. A processing unit can also be called a processor, processing board, processing module, or processing device. Optionally, the device in communication unit 1320 used to implement the receiving function can be considered a receiving unit, and the device in communication unit 1320 used to implement the transmitting function can be considered a transmitting unit; that is, communication unit 1320 includes a receiving unit and a transmitting unit. A communication unit can sometimes also be called a transceiver, transceiver unit, or interface circuit. A receiving unit can sometimes be called a receiver, receiver circuit, or receiving unit. A transmitting unit can sometimes be called a transmitter, transmitter, or transmitting circuit.

[0325] Communication device 1300 performs the above embodiment Figures 3 to 10 In any of the illustrated processes, the function of the first MLD is as follows:

[0326] The processing unit is used to prepare cached data based on the information of the second MLD or to determine the resources for transmitting information according to a predefined definition.

[0327] The communication unit is used for sending and receiving information, such as sending instruction information and receiving TF signals.

[0328] Communication device 1300 performs the above embodiment Figures 3 to 10 In any of the illustrated processes, the function of the second MLD is as follows:

[0329] The processing unit is used to configure resources or determine whether the links included in the first MLD have cache sharing capabilities.

[0330] The communication unit is used to send and receive information, such as sending TF signals and receiving instruction information.

[0331] The above is just an example. Processing unit 1310 and communication unit 1320 can also perform other functions. For a more detailed description, please refer to [link / reference needed]. Figures 3 to 10 The descriptions of the method embodiments shown or other method embodiments are not repeated here.

[0332] like Figure 12 The image shown is of the apparatus 1400 provided in an embodiment of this application. Figure 12 The device shown can be Figure 11 The illustrated device represents one hardware circuit implementation. This communication device can be applied to the flowchart shown above to perform the functions of the terminal device or network device in the method embodiments described. For ease of explanation, Figure 12 Only the main components of the communication device are shown.

[0333] like Figure 12 As shown, the communication device 1400 includes a processor 1410 and an interface circuit 1420. The processor 1410 and the interface circuit 1420 are coupled to each other. It is understood that the interface circuit 1420 can be a transceiver or an input / output interface. Optionally, the communication device 1400 may also include a memory 1430 for storing instructions executed by the processor 1410, or storing input data required by the processor 1410 to execute instructions, or storing data generated after the processor 1410 executes instructions.

[0334] When the communication device 1400 is used to implement Figures 3 to 10 In the method shown, processor 1410 is used to implement the functions of the processing unit 1310, and interface circuit 1420 is used to implement the functions of the communication unit 1320.

[0335] When the aforementioned communication device is a chip applied to a terminal device, the terminal device chip implements the functions of the terminal device in the above method embodiments. The terminal device chip receives information from other modules (such as an RF module or antenna) in the terminal device, the information being sent to the terminal device by the network device; or, the terminal device chip sends information to other modules (such as an RF module or antenna) in the terminal device, the information being sent to the network device by the terminal device.

[0336] When the aforementioned communication device is a chip applied to a network device, the network device chip implements the functions of the network device in the above method embodiments. The network device chip receives information from other modules (such as radio frequency modules or antennas) in the network device, which is information sent from the terminal device to the network device; or, the network device chip sends information to other modules (such as radio frequency modules or antennas) in the network device, which is information sent from the network device to the terminal device.

[0337] It is understood that the processor in the embodiments of this application may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor may be a microprocessor or any conventional processor.

[0338] In embodiments of this application, the processor may be a random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), register, hard disk, portable hard disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0339] In another embodiment of this application, a computer program product includes a computer program that, when run on a computer, can perform the methods described in the above embodiments.

[0340] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, etc.) containing computer-usable program code.

[0341] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0342] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0343] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

[0344] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for transmitting information, applied to a first multi-link device (MLD), the first MLD comprising N stations (STAs), the N STAs involving N links, where N is a positive integer, characterized in that, include: The first MLD sends first indication information on the first link. The first indication information is used to indicate whether there is a cache sharing capability between the links of the first MLD. The cache sharing capability is used to determine the link corresponding to the cached data to be sent in the first MLD. The first link is one of the N links. The first MLD receives a trigger frame TF on a third link, which is determined according to the first indication information, and the first MLD sends the buffered data of the first STA on the third link; The third link is determined based on the first indication information and includes: The first indication information indicates that the links of the first MLD do not have cache sharing capability, and the third link is the second link; Wherein, the second link is one of the N links, the second link corresponds to the first STA, and the buffered data to be sent is the buffered data of the first STA.

2. The method according to claim 1, characterized in that, The method further includes: The first MLD sends a second indication message on the second link, the second indication message being used to indicate the buffer status.

3. The method according to claim 2, characterized in that, The second indication information includes a first field, which indicates the cache size of the cache area. If the first indication information indicates that the links of the first MLD have cache sharing capability, the first field is used to indicate the cache size of the cache area of ​​the first MLD. If the first indication information indicates that the links of the first MLD do not have cache sharing capability, the first field is used to indicate the cache size of the cache area of ​​the first STA.

4. The method according to claim 2 or 3, characterized in that, The second indication information includes a second field, which is used to indicate whether the buffer state is the buffer state of the first STA or the buffer state of the first MLD.

5. The method according to claim 2 or 3, characterized in that, The method further includes: The third link is determined based on the first indication information and the second indication information.

6. The method according to claim 5, characterized in that, The third link is determined based on the first indication information, or the third link is determined based on the first indication information and the second indication information, including: The first indication information indicates that the links of the first MLD have cache sharing capability, and the third link is one of the links with cache sharing capability.

7. The method according to any one of claims 1 to 3, characterized in that, The first indication information includes a third field. When the third field takes the first value, it indicates that any two links among the N links have cache sharing capability; when the third field takes the second value, it indicates that any two links among the N links do not have cache sharing capability. or, When the third field takes the value of the first value, it is used to indicate that there is no cache sharing capability between any two links in the N links. When the third field takes the value of the second value, it is used to indicate that there is cache sharing capability between any two links in the N links.

8. The method according to claim 7, characterized in that, The first indication information is located in the Multi-Link Device Capability (MLD Capability) domain.

9. The method according to any one of claims 1 to 3, characterized in that, The first indication information includes a cache shared delay field, which is used to indicate the time delay between the first MLD receiving the TF and sending the cached data to be sent.

10. The method according to claim 9, characterized in that, The cache sharing delay domain is set to a first preset value, which is used to indicate that there is no cache sharing capability between any two links among the N links.

11. The method according to claim 9, characterized in that, The cache shared latency domain is located in the Multi-Link Device Capability (MLD Capability) domain.

12. The method according to any one of claims 1 to 3, characterized in that, The first indication information includes a cache sharing indication field, which includes a cache sharing indication bitmap. The cache sharing indication bitmap includes m bits, and the value of the i-th bit is used to indicate whether the links included in the first link pair have cache sharing capability. The first link pair includes the link indicated by the first link identifier and the link with link identifier i (0≤i≤m-1). The first link identifier is the link identifier included in the STA Control field of the site control information in each site profile sub-element. The cache sharing indication bitmap is located in the STA Info of the site information in each site profile sub-element.

13. The method according to claim 12, characterized in that, The i-th bit of the cache sharing indicator bitmap is set to 1, indicating that the links included in the first link pair have cache sharing capability; the i-th bit of the cache sharing indicator bitmap is set to 0, indicating that the links included in the first link pair do not have cache sharing capability. or, The i-th bit of the cache sharing indicator bit map is set to 1, indicating that the links included in the first link pair do not have cache sharing capability. The i-th bit of the cache sharing indicator bit map is set to 0, indicating that the links included in the first link pair have cache sharing capability.

14. The method according to claim 12, characterized in that, The per-site profile sub-element also includes a cache sharing indicator, which is used to indicate whether the cache sharing indicator bitmap appears in the STA Info.

15. The method according to any one of claims 1 to 3, characterized in that, The first indication information includes a cache sharing capability indication bitmap, which includes N fields, each corresponding one-to-one with one of the N links, wherein each field includes 1 bit. Links corresponding to fields with a value of 0 have cache-sharing capabilities with other links corresponding to fields with a value of 0, while links corresponding to fields with a value of 1 do not have cache-sharing capabilities with any other link. or, Links with a value of 0 do not have cache sharing capability with any other link, while links with a value of 1 have cache sharing capability with other links with a value of 1.

16. The method according to any one of claims 1 to 3, characterized in that, The first indication information includes a cache sharing capability indication bitmap, which includes N fields, each of which includes at least two bits. Each of the N fields corresponds one-to-one with one of the N links. The link corresponding to the field with the third value does not have cache sharing capability with any other link, while the link corresponding to the field with a value other than the third value has cache sharing capability with the link corresponding to the field with the same value.

17. A method for transmitting information, applied to a second multi-link device (MLD), the second MLD comprising N access points (APs), the N APs involving N links, where N is a positive integer, characterized in that, include: The second MLD receives first indication information on the first link. The first indication information is used to indicate whether there is cache sharing capability between the links of the first MLD. The cache sharing capability is used by the second MLD to determine the link corresponding to the cached data to be received. The first link is one of the N links. The second MLD sends a trigger frame TF on the third link, which is determined according to the first indication information, and the second MLD receives the buffered data of the first STA on the third link; The third link is determined based on the first indication information and includes: The first indication information indicates that the links of the second MLD do not have cache sharing capability, and the third link is the second link. Wherein, the second link is one of the N links, the second link corresponds to the first STA, and the cached data to be received is the cached data of the first STA.

18. The method according to claim 17, characterized in that, The method further includes: The second MLD receives second indication information on the second link, which is used to indicate the buffer status.

19. The method according to claim 18, characterized in that, The second indication information includes a first field, which indicates the cache size of the cache area. If the first indication information indicates that the links of the second MLD have cache sharing capability, the first field is used to indicate the cache size of the cache area of ​​the first MLD. If the first indication information indicates that the links of the second MLD do not have cache sharing capability, the first field is used to indicate the cache size of the cache area of ​​the first STA.

20. The method according to claim 18 or 19, characterized in that, The second indication information includes a second field, which is used to indicate whether the buffer state is the buffer state of the first STA or the buffer state of the first MLD.

21. The method according to claim 18 or 19, characterized in that, The method further includes: The third link is determined based on the first indication information and the second indication information.

22. The method according to claim 21, characterized in that, The third link is determined based on the first indication information and the second indication information, including: The first indication information indicates that the links of the second MLD have cache sharing capability, and the third link is one of the links with cache sharing capability.

23. The method according to any one of claims 17 to 19, characterized in that, The first indication information includes a third field. When the third field takes the first value, it indicates that any two links among the N links have cache sharing capability; when the third field takes the second value, it indicates that any two links among the N links do not have cache sharing capability. or, When the third field takes the value of the first value, it is used to indicate that there is no cache sharing capability between any two links in the N links. When the third field takes the value of the second value, it is used to indicate that there is cache sharing capability between any two links in the N links.

24. The method according to claim 23, characterized in that, The first indication information is located in the Multi-Link Device Capability (MLD Capability) domain.

25. The method according to any one of claims 17 to 19, characterized in that, The first indication information includes a cache shared delay field, which is used to indicate the time delay between the first MLD receiving the TF and sending the cached data of the first STA.

26. The method according to claim 25, characterized in that, The cache sharing delay domain is set to a first preset value, which is used to indicate that there is no cache sharing capability between any two links among the N links.

27. The method according to claim 25, characterized in that, The cache shared latency domain is located in the Multi-Link Device Capability (MLD Capability) domain.

28. The method according to any one of claims 17 to 19, characterized in that, The first indication information includes a cache sharing indication field, which includes a cache sharing indication bitmap. The cache sharing indication bitmap includes m bits, and the value of the i-th bit is used to indicate whether the links included in the first link pair have cache sharing capability. The first link pair includes the link indicated by the first link identifier and the link with the link identifier i (0≤i≤m-1). The first link identifier is the link identifier included in the STA Control field of the site control information in each site profile sub-element. The cache sharing indication bitmap is located in the STAInfo of the site information of each site profile sub-element.

29. The method according to claim 28, characterized in that, The i-th bit of the cache sharing indicator bitmap is set to 1, indicating that the links included in the first link pair have cache sharing capability; the i-th bit of the cache sharing indicator bitmap is set to 0, indicating that the links included in the first link pair do not have cache sharing capability. or, The i-th bit of the cache sharing indicator bit map is set to 1, indicating that the links included in the first link pair do not have cache sharing capability. The i-th bit of the cache sharing indicator bit map is set to 0, indicating that the links included in the first link pair have cache sharing capability.

30. The method according to claim 28, characterized in that, The per-site profile sub-element also includes a cache sharing indicator, which is used to indicate whether the cache sharing indicator bitmap appears in the STA Info.

31. The method according to any one of claims 17 to 19, characterized in that, The first indication information includes a cache sharing capability indication bitmap, which includes N fields, each corresponding one-to-one with one of the N links, wherein each field includes 1 bit. Links corresponding to fields with a value of 0 have cache-sharing capabilities with other links corresponding to fields with a value of 0, while links corresponding to fields with a value of 1 do not have cache-sharing capabilities with any other link. or, Links with a value of 0 do not have cache sharing capability with any other link, while links with a value of 1 have cache sharing capability with other links with a value of 1.

32. The method according to any one of claims 17 to 19, characterized in that, The first indication information includes a cache sharing capability indication bitmap, which includes N fields, each of which includes at least two bits. Each of the N fields corresponds one-to-one with one of the N links. Links corresponding to fields with the third value do not have cache sharing capabilities with any other link, while links corresponding to fields with values ​​other than the third value have cache sharing capabilities with links corresponding to fields with the same value.

33. A communication device, characterized in that, It includes at least one processor for executing a computer program or instructions to cause the apparatus to perform the method as described in any one of claims 1 to 16 and / or 17 to 32.

34. A computer program product, characterized in that, Includes a computer program that, when run on a computer, causes the computer to perform the method as described in any one of claims 1 to 16 and / or 17 to 32.

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