Display panel, pixel circuit and display device

Abstract

A display panel (01) comprises: a substrate (201), a plurality of sub-pixels (10) arranged on the substrate (201), and a plurality of gate control lines (GL); each sub-pixel (10) comprises a pixel circuit (100); the pixel circuit (100) comprises a driving transistor (Td) and at least one first switching transistor (T1), the first switching transistor (T1) being electrically connected to a control electrode of the driving transistor (Td); and each pixel circuit (100) is electrically connected to at least two gate control lines (GL). The first switching transistor (T1) includes an active layer (T1'), the active layer (T1') includes an active layer body (t1) and at least one extension (p), the active layer body (t1) includes at least one channel region and at least one conductive region; the extension (p) is electrically connected to the conductive region of the active layer body (t1); the orthographic projection of the extension (p) on the substrate (201) at least partially overlaps with the orthographic projection of a gate control line (GL) on the substrate (201), and the overlapping portion of the two forms a voltage-stabilizing capacitor.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a pixel circuit, and a display device. Background Art

[0002] At present, OLED (Organic Light-Emitting Diode) display devices are widely used due to their self-luminescence, fast response, wide viewing angle and ability to be manufactured on flexible substrates. OLED display devices include multiple sub-pixels, each of which includes a pixel circuit and a light-emitting device. The pixel circuit drives the light-emitting device to emit light, thereby achieving display. Summary of the Invention

[0003] In one aspect, a display panel is provided, comprising: a substrate, a plurality of sub-pixels disposed on the substrate, and a plurality of gate control lines. Each sub-pixel includes a pixel circuit; the pixel circuit includes a drive transistor and at least one first switching transistor, the first switching transistor being electrically connected to the control electrode of the drive transistor. Each pixel circuit is electrically connected to at least two gate control lines. The first switching transistor includes an active layer, the active layer including an active layer body and at least one extension, the active layer body including at least one channel region and at least one conductive region. The extension is electrically connected to the conductive region of the active layer body; the orthographic projection of the extension on the substrate at least partially overlaps with the orthographic projection of a gate control line on the substrate, and the overlapping portion forms a voltage-stabilizing capacitor.

[0004] In some embodiments, the active layer of the first switching transistor includes at least one first extension; the main body of the active layer of the first switching transistor includes two channel regions and three conductive regions, the conductive regions are electrically connected to the channel regions in alternating order, and one of the conductive regions is located between the two channel regions; an orthographic projection of a gate control line on the substrate overlaps with an orthographic projection of two channel regions of the first switching transistor on the substrate; the first extension of the first switching transistor is electrically connected to the conductive region located between the two channel regions of the first switching transistor, and an orthographic projection of the first extension of the first switching transistor on the substrate at least partially overlaps with an orthographic projection of a gate control line on the substrate.

[0005] In some embodiments, the three conductive regions of the first switch transistor are a first conductive region, a second conductive region, and a third conductive region, respectively. The second conductive region is located between two channel regions of the first switch transistor. One end of the extension portion is electrically connected to the second conductive region, and the other end extends away from the second conductive region. The first extension portion is located between the first conductive region and the third conductive region, or on one side of the active layer body of the first transistor.

[0006] In some embodiments, the active layer of the first switching transistor further includes at least one second extension portion; one of the three conductive regions of the first switching transistor is electrically connected to the control electrode of the driving transistor; the second extension portion of the first switching transistor is electrically connected to one of the three conductive regions that is electrically connected to the control electrode of the driving transistor, and the orthographic projection of the second extension portion of the first switching transistor on the substrate at least partially overlaps with the orthographic projection of the gate control line on the substrate.

[0007] In some embodiments, the three conductive regions of the first switch transistor are a first conductive region, a second conductive region, and a third conductive region, respectively. The second conductive region is located between the two channel regions of the first switch transistor. The first conductive region is electrically connected to the control electrode of the driving transistor. One end of the second extension is electrically connected to the first conductive region, and the other end extends away from the first conductive region. The second extension is located between the first conductive region and the third conductive region, or on one side of the active layer of the first switch transistor.

[0008] In some embodiments, the active layer of the first switching transistor includes at least one third extension portion; the main body of the active layer of the first switching transistor includes a channel region, a fourth conductive region and a fifth conductive region, and the fourth conductive region and the fifth conductive region are respectively located on both sides of the channel region; wherein the fourth conductive region is electrically connected to the control electrode of the driving transistor; the third extension portion is connected to the fourth conductive region, and the orthographic projection of the third extension portion on the substrate at least partially overlaps with the orthographic projection of the gate control line on the substrate.

[0009] In some embodiments, the active layer of the first switch transistor further includes a fourth extension portion; the fourth extension portion is electrically connected to the fifth conductive region, and an orthographic projection of the fourth extension portion on the substrate at least partially overlaps with an orthographic projection of the gate control line on the substrate.

[0010] In some embodiments, the display panel further includes: a plurality of initialization signal lines, and each pixel circuit is electrically connected to at least one of the initialization signal lines. The gate control line electrically connected to the pixel circuit includes a first reset signal line; the at least one first switching transistor includes a first transistor; the control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to an initialization signal line, and the second electrode of the first transistor is electrically connected to the control electrode of the drive transistor. The orthographic projection of the extension of the first transistor on the substrate at least partially overlaps with the orthographic projection of the first reset signal line on the substrate.

[0011] In some embodiments, the gate control line electrically connected to the pixel circuit further includes a gate scan line; the at least one first switching transistor further includes a second transistor; the control electrode of the second transistor is electrically connected to the gate scan line, the first electrode of the second transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the second transistor is electrically connected to the control electrode of the driving transistor. An orthographic projection of an extension of the second transistor on the substrate at least partially overlaps with an orthographic projection of the gate scan line on the substrate; or an orthographic projection of the extension of the second transistor on the substrate at least partially overlaps with an orthographic projection of the first reset signal line on the substrate.

[0012] In some embodiments, the display panel further comprises: a plurality of first voltage signal lines, a plurality of light emission control lines, and a plurality of data lines. The gate control line electrically connected to the pixel circuit further comprises a second reset signal line. Each pixel circuit is also electrically connected to a first voltage signal line.

[0013] The pixel circuit also includes a storage capacitor; the storage capacitor includes a first plate and a second plate arranged opposite to each other; the first plate is arranged in the same layer as the multiple gate control lines, and the first plate is electrically connected to the control electrode of the driving transistor; the second plate is arranged on the side of the first plate away from the substrate; the second plate is electrically connected to the first voltage signal line.

[0014] Each pixel circuit is electrically connected to a light emitting control line, a data line, and the second reset signal line; the pixel circuit also includes at least one second switching transistor, each second switching transistor is electrically connected to the first electrode or the second electrode of the driving transistor.

[0015] On the other hand, a pixel circuit is provided, including: a driving subcircuit, a storage subcircuit, a first reset subcircuit, a compensation subcircuit, a first voltage stabilization subcircuit, and a second voltage stabilization subcircuit.

[0016] The driver subcircuit is configured to generate a drive current. The storage subcircuit is electrically connected to the driver subcircuit and a first voltage signal line; the storage subcircuit is configured to store a received signal and maintain the potential of a connection terminal between the storage subcircuit and the driver subcircuit. The first reset subcircuit is electrically connected to a first reset signal line, the driver subcircuit, and an initialization signal line; the reset subcircuit is configured to transmit an initialization signal received at the initialization signal line to the driver subcircuit in response to a first gate signal received at the first reset signal line. The compensation subcircuit is electrically connected to the driver subcircuit and a gate scan line; the compensation subcircuit is configured to perform threshold compensation on the driver subcircuit in response to a gate scan signal received at the gate scan line.

[0017] The first voltage stabilizing subcircuit is electrically connected to the first reset subcircuit, the first reset signal line, or the gate scan line; the first voltage stabilizing subcircuit is configured to suppress leakage of the first reset subcircuit. The second voltage stabilizing subcircuit is electrically connected to the compensation subcircuit, the first reset signal line, or the gate scan line; the first voltage stabilizing subcircuit is configured to suppress leakage of the compensation subcircuit.

[0018] In some embodiments, the driving subcircuit includes a driving transistor; the first voltage stabilization subcircuit includes at least one first voltage stabilization capacitor; the first reset subcircuit includes a first transistor, which is a dual-gate transistor; the first transistor includes a first sub-transistor and a second sub-transistor; the control electrode of the first sub-transistor is electrically connected to the first reset signal line, the first electrode of the first sub-transistor is electrically connected to the initialization signal line, and the second electrode of the first sub-transistor is electrically connected to the first electrode of the second sub-transistor; the control electrode of the second sub-transistor is electrically connected to the first reset signal line, and the second electrode of the second sub-transistor is electrically connected to the control electrode of the driving transistor; the first end of the first voltage stabilization capacitor is electrically connected to the second electrode of the first sub-transistor, and the second end of the first voltage stabilization capacitor is electrically connected to the first reset signal line.

[0019] In some embodiments, the first voltage-stabilizing sub-circuit further includes at least one second voltage-stabilizing capacitor; the first end of the second voltage-stabilizing capacitor is electrically connected to the second electrode of the second sub-transistor, and the second end of the second voltage-stabilizing capacitor is electrically connected to the first reset signal line or the gate scan line.

[0020] In some embodiments, the driver subcircuit includes a driver transistor; the first voltage stabilization subcircuit includes at least one third voltage stabilization capacitor and at least one fourth voltage stabilization capacitor. The first reset subcircuit includes a first transistor, a control electrode of the first transistor electrically connected to the first reset signal line, a first electrode of the first transistor electrically connected to the initialization signal line, and a second electrode of the first transistor electrically connected to the control electrode of the driver transistor. A first end of the third voltage stabilization capacitor is electrically connected to the second electrode of the first transistor, and a second end of the third voltage stabilization capacitor is electrically connected to the first reset signal line or the gate scan line. A first end of the fourth voltage stabilization capacitor is electrically connected to the first electrode of the first transistor, and a second end of the fourth voltage stabilization capacitor is electrically connected to the first reset signal line or the gate scan line.

[0021] In some embodiments, the driving sub-circuit includes a driving transistor; the second voltage stabilization sub-circuit includes at least one fifth voltage stabilization capacitor. The compensation sub-circuit includes a second transistor, which is a dual-gate transistor; the second transistor includes a third sub-transistor and a fourth sub-transistor; the control electrode of the third sub-transistor is electrically connected to the gate scan line, the first electrode of the third sub-transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the third sub-transistor is electrically connected to the first electrode of the fourth sub-transistor; the control electrode of the fourth sub-transistor is electrically connected to the gate scan line, and the second electrode of the fourth sub-transistor is electrically connected to the control electrode of the driving transistor. The first end of the fifth voltage stabilization capacitor is electrically connected to the second electrode of the third sub-transistor, and the second end of the fifth voltage stabilization capacitor is electrically connected to the first reset signal line or the gate scan line.

[0022] In some embodiments, the second voltage stabilization sub-circuit further includes at least one sixth voltage stabilization capacitor, wherein a first end of the sixth voltage stabilization capacitor is electrically connected to the second electrode of the fourth sub-transistor, and a second end of the sixth voltage stabilization capacitor is electrically connected to the first reset signal line or the gate scan line.

[0023] In some embodiments, the driving subcircuit includes a driving transistor; the second voltage stabilization subcircuit includes at least one seventh voltage stabilization capacitor and at least one eighth voltage stabilization capacitor. The compensation subcircuit includes a second transistor, the control electrode of the second transistor being electrically connected to the gate scan line, the first electrode of the second transistor being electrically connected to the second electrode of the driving transistor, and the second electrode of the second transistor being electrically connected to the control electrode of the driving transistor. The first end of the seventh voltage stabilization capacitor is electrically connected to the second electrode of the second transistor, and the second end of the seventh voltage stabilization capacitor is electrically connected to the first reset signal line or the gate scan line. The first end of the eighth voltage stabilization capacitor is electrically connected to the first electrode of the second transistor, and the second end of the eighth voltage stabilization capacitor is electrically connected to the first reset signal line or the gate scan line.

[0024] In some embodiments, the pixel circuit further includes: a data write subcircuit, a second reset subcircuit, a first light emission control subcircuit, and a second light emission control subcircuit. The data write subcircuit is electrically connected to the gate scan line, the data line, and the driver subcircuit; the data write subcircuit is configured to transmit a data signal received at the data line to the driver subcircuit in response to a gate scan signal received at the gate scan line. The driver subcircuit and the compensation subcircuit are further configured to transmit the data signal to the storage subcircuit.

[0025] The second reset sub-circuit is electrically connected to a second reset signal line, the initialization signal line, and the light-emitting device; the second reset sub-circuit is configured to transmit the initialization signal received at the initialization signal line to the light-emitting device in response to a gate scan signal received at the gate scan line. The first light-emission control sub-circuit is electrically connected to a light-emission control line, the first voltage signal line, and the driver sub-circuit; the first light-emission control sub-circuit is configured to transmit the first voltage signal received at the first voltage signal line to the driver sub-circuit in response to a light-emission control signal received at the light-emission control line. The second light-emission control sub-circuit is electrically connected to the light-emission control line, the driver sub-circuit, and the light-emitting device; the second light-emission control sub-circuit is configured to transmit the drive current generated by the driver sub-circuit to the light-emitting device to control the light-emitting device to emit light.

[0026] On the other hand, a display device is provided, comprising the display panel according to any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0028] Figure 1 is a structural diagram of a display device according to some embodiments;

[0029] Figure 2 is a structural diagram of a display panel according to some embodiments;

[0030] Figure 3A is a structural diagram of a pixel circuit according to some embodiments;

[0031] Figure 3B is a structural diagram of another pixel circuit according to some embodiments;

[0032] Figure 4 is a timing diagram of a pixel circuit according to some embodiments;

[0033] Figure 5 is a diagram of a film layer structure of a display panel according to some embodiments;

[0034] Figure 6 is a structural diagram of a semiconductor layer according to some embodiments;

[0035] Figure 7 is a structural diagram of another semiconductor layer according to some embodiments;

[0036] Figure 8 is a structural diagram of a first gate layer according to some embodiments;

[0037] Figure 9 is a structural diagram of a second gate layer according to some embodiments;

[0038] Figure 10 is a structural diagram of a source / drain metal layer according to some embodiments;

[0039] Figure 11 is an overall layout diagram of a pixel circuit according to some embodiments;

[0040] Figure 12 is an overall layout diagram of another pixel circuit according to some embodiments;

[0041] Figure 13 is a structural diagram of another semiconductor layer according to some embodiments;

[0042] Figure 14 is a structural diagram of a semiconductor layer and a first gate layer according to some embodiments;

[0043] Figure 15 is a structural diagram of another semiconductor layer and a first gate layer according to some embodiments;

[0044] Figure 16 is a structural diagram of another semiconductor layer and a first gate layer according to some embodiments;

[0045] Figure 17 is a structural diagram of another semiconductor layer and a first gate layer according to some embodiments;

[0046] Figure 18 is a structural diagram of another semiconductor layer and a first gate layer according to some embodiments;

[0047] Figure 19 is a structural diagram of another semiconductor layer and a first gate layer according to some embodiments;

[0048] Figure 20 is a structural diagram of another semiconductor layer and a first gate layer according to some embodiments;

[0049] Figure 21 is a structural diagram of another semiconductor layer and a first gate layer according to some embodiments;

[0050] Figure 22 is an overall layout diagram of another pixel circuit according to some embodiments;

[0051] Figure 23 is a structural diagram of another semiconductor layer according to some embodiments;

[0052] Figure 24 is a structural diagram of another semiconductor layer and a first gate layer according to some embodiments;

[0053] Figure 25 is a structural diagram of another semiconductor layer and a first gate layer according to some embodiments;

[0054] Figure 26 is an overall layout diagram of another pixel circuit according to some embodiments;

[0055] Figure 27 is a structural diagram of another pixel circuit according to some embodiments;

[0056] Figure 28A Based on Figure 27 A schematic diagram of the second transistor in the pixel circuit in an on state;

[0057] Figure 28B Based on Figure 27 A schematic diagram of the second transistor in the pixel circuit in the off state;

[0058] Figure 29 is a structural diagram of another pixel circuit according to some embodiments;

[0059] Figure 30A Based on Figure 29 A schematic diagram of the second transistor in the pixel circuit in an on state;

[0060] Figure 30B Based on Figure 29 A schematic diagram of the second transistor in the pixel circuit in the off state;

[0061] Figure 31 is a structural diagram of another pixel circuit according to some embodiments;

[0062] Figure 32 is a structural diagram of another pixel circuit according to some embodiments;

[0063] Figure 33A Based on Figure 32 A schematic diagram of the second transistor in the pixel circuit in an on state;

[0064] Figure 33B Based on Figure 32 Schematic diagram of the second transistor in the pixel circuit in the off state. DETAILED DESCRIPTION

[0065] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0066] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0067] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0068] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0069] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0070] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0071] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.

[0072] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0073] Some embodiments of the present disclosure provide a display device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a car computer, a wearable display device, etc., such as a watch. Figure 1 As shown, the display device 1000 may be a mobile phone. The embodiment of the present disclosure does not impose any particular limitation on the specific form of the above-mentioned display device.

[0074] In some examples, the display device may also be an electroluminescent display device or a photoluminescent display device. In the case where the display device is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot electroluminescent display device (QLED). In the case where the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0075] The display device 1000 includes a display panel 01. Figure 2 As shown, the display panel 01 includes a display area AA (Active Area, referred to as AA area; also called effective display area) and a peripheral area BB located on at least one side of the display area AA.

[0076] In some embodiments, a display panel includes a substrate 201, a plurality of subpixels 10 disposed on the substrate 201, a plurality of gate control lines GL, a plurality of data lines DL, a plurality of initialization signal lines VINT, and a plurality of first voltage signal lines VDD. Exemplarily, the plurality of gate control lines GL and the plurality of initialization signal lines Vint extend along a horizontal direction X, and the plurality of data lines DL and the plurality of first voltage signal lines VDD extend along a vertical direction Y. The plurality of subpixels 10, the plurality of gate control lines GL, the plurality of data lines DL, the plurality of initialization signal lines Vint, and the plurality of first voltage signal lines VDD are all disposed in a display area AA.

[0077] For ease of explanation, the above-mentioned multiple sub-pixels 10 are described in the present disclosure by arranging them in a matrix form as an example. For example, the multiple sub-pixels 10 are arranged in N rows and M columns. In this case, the sub-pixels 10 arranged in a row along the horizontal direction X are called a row of sub-pixels, and the sub-pixels 10 arranged in a row along the vertical direction Y are called a column of sub-pixels. Each sub-pixel 10 includes a light-emitting device and a pixel circuit 100 for controlling the light-emitting device to emit light. The pixel circuit 100 is provided on the substrate 201 of the display panel 01. A row of sub-pixels can be coupled to one or two gate control lines GL. For example, each pixel circuit 100 is electrically connected to at least two gate control lines GL. A row of sub-pixels can also be coupled to one or two light-emitting timing signal lines EL, and a column of sub-pixels can be coupled to one data signal line DL.

[0078] The display panel 01 may be an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, etc., and the present disclosure does not make any specific limitation on this.

[0079] The following embodiments of the present disclosure are all described by taking the display panel 01 as an organic light emitting diode display panel as an example.

[0080] Exemplarily, the pixel circuit 100 generally includes components such as a switching transistor, a driving transistor, and a storage capacitor. The storage capacitor has two opposite ends, namely a reference potential end and a signal holding end. Exemplarily, the reference potential end of the storage capacitor is electrically connected to the first voltage signal line VDD, and the signal holding end of the storage capacitor is coupled to the control electrode (gate) of the driving transistor.

[0081] During the driving process of the pixel circuit 100, in the light-emitting phase, the storage capacitor is used to maintain a voltage signal, so that the potential of its signal holding terminal is kept constant, forming a voltage between the gate and source of the driving transistor, thereby controlling the driving transistor to form a driving current, and then driving the light-emitting diode to emit light. In this process, under ideal conditions, the switching transistor electrically connected to the control electrode of the driving transistor is in the off state, and no current flows, so that the potential of the signal holding terminal can be kept stable. However, in actual circuits, the switching transistor itself has leakage current in the off state, and due to process anomalies, the leakage current of the switching transistor is more significant. As a result, the potential of the signal holding terminal of the storage capacitor cannot be kept constant for a long time, resulting in instability of the driving current formed by the driving transistor, affecting the brightness of the light-emitting device, and further affecting the display effect of the display device.

[0082] Specifically, if Figure 3A and Figure 3B As shown, some embodiments of the present disclosure provide a pixel circuit 100, which includes a storage sub-circuit 101, a driving sub-circuit 102, a first reset sub-circuit 103, a compensation sub-circuit 104, a data writing sub-circuit 105, a first light-emitting control sub-circuit 106, a second light-emitting control sub-circuit 107 and a second reset sub-circuit 108.

[0083] The driving sub-circuit 102 is configured to generate a driving current.

[0084] The storage sub-circuit 101 is electrically connected to the driving sub-circuit 102 and the first voltage signal line VDD; the storage sub-circuit 101 is configured to store the received signal and maintain the potential of the connection terminal between the storage sub-circuit 101 and the driving sub-circuit 102 .

[0085] The first reset sub-circuit 103 is electrically connected to the driving sub-circuit 102, the first reset signal line Reset1 and the initialization signal line Vint; the reset sub-circuit is configured to transmit the initialization signal received at the initialization signal line Vint to the driving sub-circuit 102 in response to the first gate signal received at the first reset signal line Reset1.

[0086] The compensation sub-circuit 104 is electrically connected to the driving sub-circuit 102 and the gate scan line Gate; the compensation sub-circuit 104 is configured to perform threshold compensation on the driving sub-circuit 102 in response to a gate scan signal received at the gate scan line Gate.

[0087] like Figure 3A and Figure 3BThe node electrically connected to the driving sub-circuit 102, the storage sub-circuit 101, the first reset sub-circuit 103, and the compensation sub-circuit 104 is hereinafter referred to as the first node N1. The first reset sub-circuit 103 can transmit an initialization signal to the first node N1 to reset the first node N1.

[0088] Exemplarily, the storage sub-circuit 101 includes a storage capacitor Cst, a first end of the storage capacitor Cst is electrically connected to the first voltage signal line VDD, and a second end of the storage capacitor Cst is electrically connected to the first node N1.

[0089] The driving sub-circuit 102 includes a driving transistor Td, and a control electrode of the driving transistor Td is electrically connected to the first node N1.

[0090] The first reset sub-circuit 103 includes a first transistor T1 , a control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1 , a first electrode of the first transistor T1 is electrically connected to the initialization signal line Vint, and a second electrode of the first transistor T1 is electrically connected to the first node N1 .

[0091] In some examples, such as Figure 3B As shown, the first transistor T1 is a dual-gate transistor, comprising a first sub-transistor T11 and a second sub-transistor T12. The control electrode of the first sub-transistor T11 is electrically connected to the first reset signal line Reset1, the first electrode of the first sub-transistor T11 is electrically connected to the initialization signal line Vint, and the second electrode of the first sub-transistor T11 is electrically connected to the first electrode of the second sub-transistor T12. The control electrode of the second sub-transistor T12 is electrically connected to the first reset signal line Reset1, and the second electrode of the second sub-transistor T12 is electrically connected to the control electrode of the drive transistor Td. It can be understood that the control electrode of the first transistor T1 is the control electrode of the first sub-transistor T11 and the second sub-transistor T12, the first electrode of the first transistor T1 is the first electrode of the first sub-transistor T11, and the second electrode of the first transistor T1 is the second electrode of the second sub-transistor T12.

[0092] The compensation sub-circuit 104 includes a second transistor T2 , a control electrode of the second transistor T2 electrically connected to the gate scan line Gate, a first electrode of the second transistor T2 electrically connected to the second electrode of the driving transistor Td, and a second electrode of the second transistor T2 electrically connected to the first node N1 .

[0093] In some examples, such as Figure 3BAs shown, the second transistor T2 is a dual-gate transistor, comprising a third sub-transistor T21 and a fourth sub-transistor T22. The control electrode of the third sub-transistor T21 is electrically connected to the gate scan line Gate, the first electrode of the third sub-transistor T21 is electrically connected to the second electrode of the drive transistor Td, and the second electrode of the third sub-transistor T21 is electrically connected to the first electrode of the fourth sub-transistor T22. The control electrode of the fourth sub-transistor T22 is electrically connected to the gate scan line Gate, and the second electrode of the fourth sub-transistor T22 is electrically connected to the control electrode of the drive transistor Td. It can be understood that the control electrode of the second transistor T2 is the control electrode of the second sub-transistor T12 and the fourth sub-transistor T22, the first electrode of the second transistor T2 is the first electrode of the third sub-transistor T21, and the second electrode of the second transistor T2 is the second electrode of the fourth sub-transistor T22.

[0094] Hereinafter, a node where the first electrode of the second transistor T2 and the second electrode of the driving transistor Td are electrically connected is referred to as a second node N2.

[0095] The data writing sub-circuit 105 is electrically connected to the gate scanning line Gate, the driving sub-circuit 102 and the data line DL. The data writing sub-circuit 105 is configured to transmit the data signal received at the data line DL to the driving sub-circuit 102 in response to the gate scanning signal received at the gate scanning line Gate.

[0096] The first light-emitting control sub-circuit 106 is electrically connected to the light-emitting control line EL, the first voltage signal line VDD and the driving sub-circuit 102. The first light-emitting control sub-circuit 106 is configured to transmit the first voltage signal received at the first voltage signal line VDD to the driving sub-circuit 102 in response to the light-emitting control signal received at the light-emitting control line EL.

[0097] Hereinafter, the node where the driving sub-circuit 102 is electrically connected to the data writing sub-circuit 105 and the first light emitting control sub-circuit 106 is referred to as a third node N3.

[0098] Exemplarily, the data writing sub-circuit 105 includes a third transistor T3, a control electrode of the third transistor T3 is electrically connected to the gate scan line Gate, a first electrode of the third transistor T3 is electrically connected to the data line DL, and a second electrode of the third transistor T3 is electrically connected to the third node N3.

[0099] The first light emitting control subcircuit 106 includes a fourth transistor T4, a control electrode of the fourth transistor T4 is electrically connected to the light emitting control line EL, a first electrode of the fourth transistor T4 is electrically connected to the first voltage signal line VDD, and a second electrode of the fourth transistor T4 is electrically connected to the third node N3.

[0100] The second reset sub-circuit 108 is electrically connected to the second reset signal line Reset2, the initialization signal line Vint and the light-emitting device 109. The second reset sub-circuit 108 is configured to, in response to a second reset signal received at the second reset signal line Reset2, transmit the initialization signal received at the initialization signal line Vint to the light-emitting device 109 to reset the light-emitting device 109.

[0101] The second light-emitting control sub-circuit 107 is electrically connected to the light-emitting control line EL, the driving sub-circuit 102 and the light-emitting device 109. The second light-emitting control sub-circuit 107 is configured to receive the driving signal output by the driving sub-circuit 102 in response to the light-emitting control signal received at the light-emitting control line EL, and transmit the driving signal to the light-emitting device 109 to control the light-emitting device 109 to emit light.

[0102] In some examples, the second reset subcircuit 108 and the second light control subcircuit 107 are both coupled to the anode of the light emitting device 109, and the cathode of the light emitting device 109 is electrically connected to the second voltage signal line VSS.

[0103] Hereinafter, the node where the light emitting device 109 is electrically connected to the second reset sub-circuit 108 and the second light emitting control sub-circuit 107 is referred to as a fourth node N4.

[0104] Exemplarily, the second reset subcircuit 108 includes a fifth transistor T5, a control electrode of the fifth transistor T5 electrically connected to the second reset signal line Reset2, a first electrode of the fifth transistor T5 electrically connected to the initialization signal line Vint, and a second electrode of the fifth transistor T5 electrically connected to the fourth node N4.

[0105] The second light emitting control subcircuit 107 includes a sixth transistor T6, a control electrode of the sixth transistor T6 is electrically connected to the light emitting control line EL, a first electrode of the sixth transistor T6 is electrically connected to the third node N3, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.

[0106] In some embodiments, the gate scan line Gate and the second reset signal line Reset2 electrically connected to the pixel circuit 100 in a sub-pixel are the same gate control line GL, that is, the gate scan signal and the second reset signal are the same signal. When the sub-pixels are arranged in an array of N rows and M columns, the first reset signal line Reset1 electrically connected to the pixel circuit 100 of a row of sub-pixels is the gate scan line Gate electrically connected to the sub-pixels in the previous row.

[0107] In some embodiments, the transistors included in each of the above sub-circuits are of the same on / off type. For example, the first transistor T1 to the sixth transistor T6 and the driving transistor Td are all P-type transistors or N-type transistors. For example, the above transistors are all low-temperature polysilicon thin film transistors (LTPTs). This disclosure is described using the example that the above transistors are all P-type transistors.

[0108] See Figure 4 The driving process of the above-mentioned pixel circuit 100 is as follows: one frame period includes a reset phase P1, an input and compensation phase P2, and a light emitting phase P3.

[0109] Among them, in the reset phase P1:

[0110] In response to the first reset signal received at the first reset signal line Reset1 , the first reset sub-circuit 103 transmits the initialization signal received at the initialization signal line Vint to the first node N1 to reset the first node N1 .

[0111] The energy storage sub-circuit and the driving sub-circuit 102 are both electrically connected to the first node N1 . In the reset phase, the energy storage sub-circuit and the driving sub-circuit 102 are reset.

[0112] For example, Figure 3A and Figure 3B As shown, in the case where each sub-circuit in the pixel circuit 100 includes a transistor or a capacitor, the reset phase P1 includes:

[0113] In the present disclosure, "each subcircuit in the pixel circuit 100 includes a transistor or a capacitor" refers to the case where the energy storage subcircuit includes a storage capacitor Cst, the driving subcircuit 102 includes a driving transistor Td, the first reset subcircuit 103 includes a first transistor T1, the compensation subcircuit 104 includes a second transistor T2, the data subcircuit includes a second transistor T2, the data write subcircuit 105 includes a third transistor T3, the first light emission control subcircuit 106 includes a fourth transistor, and the second light emission control subcircuit 107 includes a sixth transistor T6. In the following, "0" represents a low level for a signal, and "1" represents a high level for a signal.

[0114] In the reset phase P1 , the first reset signal is 0, the gate scan signal (second reset signal) is 1, and the light emitting control signal is 1.

[0115] The first transistor T1 is turned on under the control of the first reset signal to transmit the initialization signal to the first node N1. The second transistor T2 to the sixth transistor T6 and the driving transistor Td are all turned off.

[0116] In some examples, when the first transistor T1 is a dual-gate transistor and includes a first sub-transistor T11 and a second sub-transistor T12, turning on the first transistor T1 under the control of the first reset signal means that both the first sub-transistor T11 and the second sub-transistor T12 are turned on under the control of the first reset signal to transmit the initialization signal.

[0117] In the input and compensation phase P2:

[0118] The second reset sub-circuit 108 transmits the initialization signal received at the initialization signal line Vint to the fourth node N4 in response to the second reset signal received at the second reset signal line Reset2 to reset the light emitting device 109 .

[0119] The data writing sub-circuit 105 transmits the data signal received at the data line DL to the third node N3 in response to the gate scan signal received at the gate scan line Gate.

[0120] Under the influence of the voltages at the first node N1 and the third node N3 , the driving sub-circuit 102 transmits the data signal at the third node N3 to the second node N2 .

[0121] The compensation sub-circuit 104 transmits the data signal received at the second node N2 to the first node N1 in response to the gate scan signal received at the gate scan line Gate, and performs threshold compensation on the driving sub-circuit 102 .

[0122] The energy storage sub-circuit receives and stores the voltage of the first node N1.

[0123] For example, Figure 3A and Figure 3B As shown, in the case where each sub-circuit in the pixel circuit 100 includes a transistor or a capacitor, the input and compensation phase P2 includes:

[0124] In the input and compensation phase P2 , the first reset signal is 1, the gate scan signal (the second reset signal) is 0, and the light emitting control signal is 1.

[0125] The fifth transistor T5 is turned on under the control of the second reset signal, and transmits the initialization signal to the fourth node N4 to reset the anode of the light emitting device 109 .

[0126] The third transistor T3 is turned on under the control of the gate scan signal and transmits the data signal to the third node N3.

[0127] The potential of the control electrode (gate) of the driving transistor Td is the potential of the first node N1, that is, the potential of the initialization signal, and the potential of the first electrode (source) of the driving transistor Td is the potential of the third node N3, that is, the potential of the data signal V data , the gate-source voltage difference of the driving transistor Td is less than its threshold voltage V th , the driving transistor Td is turned on, and the data signal is transmitted from the third node N3 to the second node N2.

[0128] The second transistor T2 is turned on under the control of the gate scan line Gate, transmitting the data signal at the second node N2 to the first node N1, thereby writing the data signal to the storage capacitor Cst. The storage capacitor Cst maintains the potential of the first node N1. If the second transistor T2 is a dual-gate transistor and includes a third sub-transistor T21 and a fourth sub-transistor T22, turning on the second transistor T2 under the control of the gate scan line Gate means that both the third sub-transistor T21 and the fourth sub-transistor T22 are turned on under the control of the gate scan line Gate.

[0129] The potential of the first node N1 is determined by the potential of the initialization signal V int Gradually increases, when the potential of the first node N1 rises to V data +V th When , the driving transistor Td is turned off, and the input and compensation phase ends, thereby writing the voltage of the data signal and the threshold voltage into the storage capacitor Cst.

[0130] In the lighting phase P3:

[0131] The first light emission control sub-circuit 106 transmits the first voltage signal received at the first voltage signal line VDD to the third node N3 in response to the light emission control signal received at the light emission control line EL.

[0132] The driving sub-circuit 102 generates a driving current under the control of the voltages of the first node N1 and the third node N3 , and outputs the driving current to the second node N2 .

[0133] The second light-emitting control subcircuit 107 responds to the light-emitting control signal received at the light-emitting signal line and transmits the driving signal received at the second node N2 to the fourth node N4, i.e., the anode of the light-emitting device 109, so that the light-emitting device 109 emits light under the control of the driving signal.

[0134] The first transistor T1 , the fourth transistor T4 , and the sixth transistor T6 are turned off.

[0135] For example, Figure 3A and Figure 3BAs shown, in the case where each sub-circuit in the pixel circuit 100 includes a transistor or a capacitor, the light emitting phase P3 includes:

[0136] In the light emitting phase P3 , the first reset signal is 1, the gate scanning signal (second reset signal) is 1, and the light emitting control signal is 0.

[0137] The fourth transistor T4 transmits the first voltage signal to the third node N3 under the control of the light emitting control signal.

[0138] The potential of the third node N3 is the voltage of the first voltage signal, and the potential of the first node N1 is V data +V th , the driving transistor Td generates a driving current under the control of the voltages of the first node N1 and the third node N3, and the driving transistor Td operates in the saturation region. According to the saturation current formula, the driving current generated by the driving transistor Td (the current input to the light emitting device 109) is:

[0139]

[0140] Where W / L is the channel width-to-length ratio of the driving transistor Td; μ is the carrier mobility; C ox is the unit area channel capacitance of the driving transistor Td; V gs is the gate-source voltage difference of the driving transistor Td; V th is the threshold voltage of the driving transistor Td.

[0141] It can be seen that the current I input to the light emitting device 109 oled The size of the written data signal voltage V data Related to the first voltage signal, and the threshold voltage V th This avoids the problem that the difference in threshold voltage of the driving transistor Td of each pixel circuit 100 caused by the manufacturing process affects the magnitude of the driving current, thereby affecting the display effect.

[0142] During the entire light-emitting phase P3 of a frame period, during the light-emitting process of the light-emitting device 109108, the driving signal generated by the driving transistor Td in the driving sub-circuit 102 is the driving current. According to the calculation formula of the driving current, for the driving transistor Td, the difference between the driving signal formed and the gate-source voltage difference of the driving transistor Td and the threshold voltage (V gs -V th ), the stability of the potential of the control electrode of the driving transistor Td (i.e., the potential of the first node N1) can affect the stability and effective value of the driving signal formed, thereby affecting the stability and continuity of the light emitting device 109.

[0143] During the light-emitting phase P3, ideally, the first transistor T1, the second transistor T2, and the third transistor T3 are all in the off state, with no current flowing through them. Thus, the potential of the first node N1 is maintained. However, in practice, leakage current may occur in the off state of the switching transistors, and due to process anomalies, the leakage current of the switching transistors may be large, causing the potentials of the first node N1 and the third node N3 to vary during the light-emitting phase and to become unstable. Due to the differences in the first transistor T1, the second transistor T2, and the third transistor T3 in different pixel circuits 100, the potentials of the first node N1 and the third node N3 vary in different pixel circuits 100. This results in significant variations in the gate-source voltage difference of the driving transistor Td, causing fluctuations in the current generated by the driving transistor Td, making it impossible to drive the light-emitting device 109 to emit stable light. This, in turn, causes the pixel to become brighter or darker, resulting in problems such as bright and dark spots.

[0144] In the pixel circuit 100 provided in some embodiments of the present disclosure, the transistor electrically connected to the control electrode (first node N1) of the driving transistor Td is called a first switching transistor, and the transistor electrically connected to the first electrode or the second electrode of the driving transistor Td is called a second switching transistor.

[0145] The inventors of the present disclosure have discovered that, in addition to the reasons described above, leakage current in the switching transistor in the off state is also affected by the voltage difference between the source and drain of the switching transistor. The larger the source-drain voltage difference of the switching transistor, the more severe the leakage current. When the voltages of the drain and drain of the switching transistor are substantially equal, substantially no leakage current flows. Furthermore, when the potential of the first electrode of the switching transistor is greater than the potential of the second electrode, leakage current is substantially unable to flow from the second electrode of the switching transistor to the first electrode, and vice versa. Based on this, in some embodiments, the inventors of the present disclosure redesigned the pattern of the active layer of the first switching transistor (i.e., the first transistor T1 and the second transistor T2) so that a portion of the active layer of the first switching transistor overlaps with the gate control line GL to form a capacitor, thereby adding a voltage stabilization subcircuit to the pixel circuit 100. This voltage stabilization subcircuit can stabilize the voltages of the source and drain of the first switching transistor, reducing the source-drain voltage difference, thereby reducing leakage current of the first switching transistor during the light-emitting phase and stabilizing the potential of the first node N1.

[0146] The following first introduces the film layer structures included in the display panel 01.

[0147] In some embodiments, as Figure 5As shown, the display panel 01 has the following structure, which includes a substrate 201, a semiconductor layer 202, a first gate insulating layer 203, a first gate layer 204, a second gate insulating layer 205, a second gate layer 206, an interlayer insulating layer 207 and a source / drain metal layer stacked in sequence. Figures 6 to 9 The corresponding Figure 3A and Figure 3B The pixel circuit 100 shown includes a semiconductor layer 202 , a first gate layer 204 , a second gate layer 206 , and source / drain metal layers. Figure 11 and Figure 12 : is the overall layout diagram of each film layer in the pixel circuit 100 (wherein the first gate insulating layer 203, the first gate insulating layer 203 and the interlayer insulating layer 207 are transparent). Figure 6 To correspond Figure 3A The structure diagram of the semiconductor layer 202 of the pixel circuit 100 is shown in FIG. Figure 7 To correspond Figure 3B FIG. 1 is a structural diagram of the semiconductor layer 202 of the pixel circuit 100 .

[0148] In some examples, the semiconductor layer 202 is disposed on the substrate 201, the semiconductor layer 202 has a predetermined pattern, and the semiconductor layer 202 includes an active layer of each transistor in each pixel circuit 100, which is referred to herein as an active layer body. Figure 6 and Figure 7 As shown, within a sub-pixel region, the semiconductor layer 202 includes an active layer body td of a driving transistor Td, an active layer body t1 of a first transistor T1, an active layer body t2 of a second transistor T2, an active layer body t3 of a third transistor T3, an active layer body t4 of a fourth transistor T4, an active layer body t5 of a fifth transistor T5, and an active layer body t6 of a sixth transistor T6. The active layer body of each transistor may include at least one channel region and at least one conductive region, wherein the conductive region is a source region or a drain region. The active region of a transistor is the portion of the active layer body that overlaps with the corresponding gate control line GL, for example Figure 6 and Figure 7 The portion in the dotted line box is the active region of each transistor. For example, the active layers of each transistor are integrated.

[0149] For example, the semiconductor layer 202 can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source region and drain region can be regions doped with n-type impurities or p-type impurities. The semiconductor layer 202 can be prepared, for example, by depositing a semiconductor material on the surface of the substrate 201 and then performing an etching process to form the semiconductor layer 202, so that the semiconductor layer 202 has a predetermined pattern.

[0150] The first gate insulating layer 203 is arranged on the side of the semiconductor layer 202 away from the substrate 201, and the first gate layer 204 is arranged on the side of the first gate insulating layer 203 away from the substrate 201. The first gate insulating layer 203 is configured to isolate the semiconductor layer 202 and the first gate layer 204 from each other and protect the semiconductor layer 202.

[0151] In some examples, such as Figure 8 As shown, the first gate layer 204 includes multiple gate control lines GL, multiple emission control lines EL, and multiple first plates Cst1 of storage capacitors Cst. Specifically, the first gate layer 204 includes a first reset signal line Reset1, a second reset signal line Reset2, a gate scan line Gate, and the emission control line EL. Exemplarily, the portion where the signal lines in the first gate layer 204 overlap with the active layer of the transistor in the semiconductor layer 202 serves as the gate of the transistor, and the portion of the active layer of the transistor directly opposite the gate serves as the channel region.

[0152] For example, Figure 11 As shown, the main body of the active layer of the first transistor T1 overlaps with the first reset signal line Reset1 at two locations, and the gate of the first transistor T1 is the portion of the first reset signal line Reset1 that overlaps with the active layer of the first transistor T1. The active layer of the first transistor T1 includes two channel regions. It is understood that the first transistor T1 is a dual-gate transistor. Alternatively, Figure 12 As shown, the main body of the active layer of the first transistor T1 overlaps with the first reset signal line Reset1 at one point, and the gate of the first transistor T1 is the portion of the first reset signal line Reset1 that overlaps with the active layer of the first transistor T1. The active layer of the first transistor T1 includes a channel region. It can be understood that the first transistor T1 is a single-gate transistor.

[0153] For example, Figure 11 As shown, the main body of the active layer of the second transistor T2 overlaps with the gate scan line Gate at two locations, and the gate of the second transistor T2 is the portion of the gate scan line Gate that overlaps with the active layer of the second transistor T2. The active layer of the second transistor T2 includes two channel regions. It can be understood that the second transistor T2 is a dual-gate transistor. Alternatively, Figure 12 As shown, the main body of the active layer of the second transistor T2 overlaps with the gate scan line Gate, and the gate of the second transistor T2 is the portion of the gate scan line Gate that overlaps with the active layer of the second transistor T2. The active layer of the second transistor T2 includes a channel region. It can be understood that the second transistor T2 is a single-gate transistor.

[0154] The above is only an example of the active layer and gate of the first transistor T1 and the second transistor T2. The gates and channel regions of the active layers of other transistors can refer to the drawings and the above description of the first transistor T1 and the second transistor T2, which will not be repeated here.

[0155] It should be noted that Figure 6 and Figure 7 The dashed rectangular boxes in illustrative figures show portions where the active layer of each transistor in the pixel circuit 100 overlaps with the first gate layer 204 .

[0156] The second gate insulating layer 205 is arranged on the side of the first gate layer 204 away from the substrate 201, and the second gate layer 206 is arranged on the side of the second gate insulating layer 205 away from the substrate 201. The second gate insulating layer 205 is configured to isolate the first gate layer 204 and the second gate layer 206 from each other and protect the first gate layer 204.

[0157] In some examples, such as Figure 9 As shown, the second gate layer 206 includes a plurality of initialization signal lines Vint and a plurality of second plates of storage capacitors Cst. Each initialization signal line Vint is electrically connected to the conductive region of the first transistor T1 and the seventh transistor through a via. The orthographic projection of the first plate of the storage capacitor Cst on the substrate 201 and the orthographic projection of the second plate of the storage capacitor Cst on the substrate 201 have an overlapping portion, and the overlapping portion forms the storage capacitor Cst.

[0158] The interlayer insulating layer 207 is arranged on the side of the second gate layer 206 away from the substrate 201, and the source-drain electrode layer 208 is arranged on the side of the interlayer insulating layer 207 away from the substrate 201. The interlayer insulating layer 207 is configured to isolate the second gate layer 206 and the source-drain electrode layer 208 from each other and protect the second gate layer 206.

[0159] In some examples, such as Figure 10 As shown, the source-drain electrode layer 208 includes a plurality of first voltage signal lines VDD, a plurality of data lines DL, and at least one connection portion 2081. One first voltage signal line VDD is electrically connected to the second plate of a storage capacitor Cst through a via, and one data line DL is electrically connected to the conductive region of the fourth transistor T4 through a via. The connection portion 2081 is configured to electrically connect a transistor to a signal line, or to electrically connect a transistor to another transistor.

[0160] To address leakage issues associated with the first switching transistor in pixel circuit 100 during the light-emitting phase, in some embodiments, the active layer of the first switching transistor has a redesigned pattern. The following describes the pattern of the active layer of the first switching transistor. For details about the first gate insulating layer 203, first gate layer 204, second gate insulating layer 205, second gate layer 206, interlayer insulating layer 207, and source / drain metal layers included in display panel 01, refer to the above description. It should be noted that the "first switching transistor" hereinafter refers to both the first transistor T1 and the second transistor T2.

[0161] like Figure 13 As shown, in some embodiments, the first switch transistor includes an active layer, the active layer including an active layer body and at least one extension, the active layer body including at least one channel region and at least one conductive region. The extension is electrically connected to the conductive region of the active layer body. For example, see Figure 13 The first switching transistor is a first transistor T1, which includes an active layer T1', which includes an active layer body t1 and at least one extension portion p, and the active layer body includes at least one channel region and at least one conductive region. Alternatively, the first switching transistor is a second transistor T2, which includes an active layer T2', which includes an active layer body t2 and at least one extension portion p', and the active layer body includes at least one channel region and at least one conductive region, wherein the portion of the active layer body indicated by the dotted line is the channel region, and the other regions are conductive regions.

[0162] like Figure 14 As shown, the orthographic projection of each extension on substrate 201 at least partially overlaps with the orthographic projection of a gate control line GL on substrate 201, and the overlapping portion forms a voltage-stabilizing capacitor. For example, the orthographic projection of the extension p of the first transistor T1 on substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 on substrate 201, and the overlapping portion forms a voltage-stabilizing capacitor. That is, in addition to the active layer body mentioned above, the active layer of the first switching transistor also includes at least one extension electrically connected to the conductive region of the active layer body, and the positional relationship between the extension and the gate control line GL is such that the orthographic projection of the extension on substrate 201 at least partially overlaps with the orthographic projection of the gate control line GL on substrate 201.

[0163] In the display panel 01 provided in some embodiments of the present disclosure, the semiconductor layer 202 has a specially designed pattern. That is, the pattern of the active layer of the first switching transistor of each pixel circuit 100 is designed to include an active layer body and at least one extension portion. The at least one extension portion is electrically connected to the conductive area of the active layer body, and the orthographic projection of the extension portion on the substrate 201 at least partially overlaps with the orthographic projection of a gate control line GL on the substrate 201. The overlapping portion of the two forms a voltage-stabilizing capacitor, which is equivalent to connecting the first switching transistor and the voltage-stabilizing capacitor in parallel. According to the characteristics of the capacitor, the capacitor has the ability to store charge and can maintain a stable voltage across it. Therefore, by providing the voltage-stabilizing capacitor, the drain and drain voltages of the first switching transistor can be made substantially equal, thereby reducing the leakage current of the first switching transistor, improving the stability of the potential of the control electrode of the driving transistor Td generated by the driving transistor Td (i.e., the potential of the first node N1), and further improving the stability of the driving signal, thereby improving the stability and continuity of the light emission of the light-emitting device 109, and improving the poor bright and dark spots of the display screen caused by the leakage of the first switching transistor.

[0164] Moreover, the semiconductor layer 202 in the above-mentioned display panel 01 can be prepared by first depositing semiconductor material and then forming a pattern through an etching process to obtain the semiconductor layer 202. Other film layers remain unchanged and there is no need to add an additional mask. Therefore, the above-mentioned display panel 01 improves the poor bright and dark spots of the display screen caused by leakage of the first switching transistor without increasing the difficulty of the preparation process.

[0165] like Figure 27 、 Figure 29 、 Figure 31 and Figure 32 As shown, corresponding to the pattern design of the active layer of the above-mentioned first switching transistor, the pixel circuit 100 provided in some embodiments of the present disclosure includes, in addition to the aforementioned storage sub-circuit 101, driving sub-circuit 102, first reset sub-circuit 103, second reset sub-circuit 108, compensation sub-circuit 104, data writing sub-circuit 105, first light-emitting control sub-circuit 106 and second light-emitting control sub-circuit 107, a first voltage stabilizing sub-circuit 110 and a second voltage stabilizing sub-circuit 111.

[0166] The first voltage stabilization sub-circuit 110 is electrically connected to the first reset sub-circuit 103, the first reset signal line Reset1, or the gate scan line Gate; the first voltage stabilization sub-circuit 110 is configured to suppress leakage of the first reset sub-circuit 103. The second voltage stabilization sub-circuit 111 is electrically connected to the compensation sub-circuit 104, the first reset signal line Reset1, or the gate scan line Gate; the first voltage stabilization sub-circuit 110 is configured to suppress leakage of the compensation sub-circuit 104.

[0167] In the above-mentioned pixel circuit 100, by providing the first voltage stabilizing sub-circuit 110 and the second voltage stabilizing sub-circuit 111, it is possible to suppress leakage of the first reset sub-circuit 103 and the compensation sub-circuit 104 during the light-emitting stage, thereby improving the stability of the potential of the first node N1, and further improving the stability of the driving signal generated by the driving sub-circuit 102, thereby improving the stability and continuity of the light emission of the light-emitting device 109, and improving the poor bright and dark spots of the display screen caused by leakage of the first reset sub-circuit 103 and the compensation sub-circuit 104.

[0168] The following describes the structure of the active layer of the first switch transistor in the case where the first switch transistor is a dual-gate transistor or a single-gate transistor.

[0169] In some embodiments, as Figures 13 to 21 As shown, the main active layer (t1 or t2) of the first switching transistor (T1 or T2) includes two channel regions and three conductive regions. The conductive regions are electrically connected to the channel regions in alternating order, and one conductive region is located between two channel regions. The orthographic projection of a gate control line GL on substrate 201 overlaps with the orthographic projections of the two channel regions of the first switching transistor on substrate 201. In other words, the first switching transistor is a dual-gate transistor.

[0170] The active layer (T1' or T2') of the first switching transistor (T1 or T2) includes at least one first extension (p1 or p1'). The first extension (p1 or p1') of the first switching transistor (T1 or T2) is electrically connected to a conductive region located between two channel regions of the first switching transistor (T1 or T2). Furthermore, the orthographic projection of the first extension (p1 or p1') of the first switching transistor (T1 or T2) on the substrate 201 and the orthographic projection of a gate control line GL on the substrate 201 at least partially overlap to form a voltage-stabilizing capacitor (C1 or C5). The gate control line GL includes a first reset signal line Reset1 or a gate scan line Gate.

[0171] Exemplarily, the active layer of the first switching transistor includes one first extension, two first extensions, or three first extensions, and the portion where the first extension of the first switching transistor overlaps with the gate control line GL forms one, two, or three voltage-stabilizing capacitors. If the active layer of the first switching transistor includes multiple first extensions, and the portions where the multiple first extensions of the first switching transistor overlap with the gate control line GL form multiple voltage-stabilizing capacitors, the voltage stability of the ends of the multiple voltage-stabilizing capacitors electrically connected to the first switching transistor can be enhanced, thereby further enhancing the effect of improving leakage in the first switching transistor. The following embodiments of the present disclosure are described using the example of a first switching transistor having an active layer including one first extension.

[0172] like Figures 15 to 21 As shown, in some examples, the three conductive regions of the first switch transistor (T1 or T2) are a first conductive region (t13 or t23), a second conductive region (t14 or t24), and a third conductive region (t15 or t25). The second conductive region (t14 or t24) is located between the two channel regions of the first switch transistor (T1 or T2). One end of the first extension portion (p1 or p1') is electrically connected to the second conductive region (t14 or t24), and the other end extends away from the second conductive region (t14 or t24). The first extension portion (p1 or p1') is located between the first conductive region and the third conductive region, or on one side of the active layer body of the first switch transistor.

[0173] The following describes the active layer of the first switch transistor by taking the first switch transistor being the first transistor T1 or the second transistor T2 as an example.

[0174] For example, Figures 15 to 18 As shown, the first switch transistor is a first transistor T1, and the first transistor T1 is a dual-gate transistor. The active layer body t1 of the first transistor T1 is U-shaped and includes a first channel region t11, a second channel region t12, a first conductive region t13, a second conductive region t14, and a third conductive region t15. One end of a first extension p1 of the first transistor T1 is electrically connected to the second conductive region t14, and the other end extends in a direction away from the second conductive region t14. The orthographic projection of the first extension p1 of the first transistor T1 on the substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 on the substrate 201, and the overlapping portion of the two forms a first voltage-stabilizing capacitor C1. Figure 16 and Figure 17 As shown, the first extension portion of the first transistor T1 is located between the first conductive region t13 and the third conductive region t15; or Figure 15 and Figure 18 As shown, the first extension portion p1 of the first transistor T1 is located on one side of the active layer body t1 of the first transistor T1 , for example, the first extension portion p1 of the first transistor T1 is located on a side of the first conductive region t13 away from the third conductive region t15 .

[0175] It should be noted that the portion where at least one first extension p1 of the first transistor T1 overlaps with the first reset signal line Reset1 forms at least one first stabilizing capacitor C1. That is, the number of the first extension p1 of the first transistor T1 is the same as the number of the first stabilizing capacitors C1.

[0176] For example, Figures 15 to 18As shown, the first switching transistor is a second transistor T2, and the second transistor T2 is a dual-gate transistor. The active layer body t2 of the second transistor T2 is L-shaped. The active layer body t2 of the second transistor T2 includes a first channel region t21, a second channel region t22, a first conductive region t23, a second conductive region t24, and a third conductive region t25. One end of the first extension portion p1' of the second transistor T2 is electrically connected to the second conductive region t24, and the other end extends in a direction away from the second conductive region t24. The orthographic projection of the first extension portion p1' of the second transistor T2 on the substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 or the gate scan line Gate on the substrate 201, and the overlapping portion forms a fifth voltage-stabilizing capacitor C5.

[0177] like Figure 16 As shown, the first extension portion p1' of the second transistor T2 is located between the first conductive region t23 and the third conductive region t25, and the orthographic projection of the first extension portion p1' of the second transistor T2 on the substrate 201 at least partially overlaps with the orthographic projection of the gate scan line Gate on the substrate 201. Alternatively, as Figure 15 、 Figure 17 and Figure 18 As shown, the first extension portion p1' of the second transistor T2 is located on one side of the active layer body t2 of the second transistor T2, and the orthographic projection of the first extension portion p1' of the second transistor T2 on the substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 or the gate scan line Gate on the substrate 201, for example, Figure 15 and Figure 17 As shown, the first extension portion p1' of the second transistor T2 is located on a side of the second conductive region t24 away from the first conductive region t23, and the orthographic projection of the first extension portion p1' of the second transistor T2 on the substrate 201 at least partially overlaps with the orthographic projection of the gate scan line Gate on the substrate 201. Figure 18 As shown, the first extension p1 ′ of the second transistor T2 is located on a side of the second conductive region t24 away from the first conductive region t23 , and the orthographic projection of the first extension p1 ′ of the second transistor T2 on the substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 on the substrate 201 .

[0178] It should be noted that the portion where at least one first extension of the second transistor T2 overlaps with the first reset signal line Reset1 or the gate scan line Gate forms at least one fifth stabilizing capacitor C5, that is, the number of the first extensions of the second transistor T2 is the same as the number of the fifth stabilizing capacitors C5.

[0179] like Figure 27As shown, corresponding to the pattern design of the active layer of the above-mentioned first switching transistor (T1 or T2), in the pixel circuit 100 provided in some embodiments of the present disclosure, the first voltage stabilizing subcircuit 110 includes at least one first voltage stabilizing capacitor C1, and the second voltage stabilizing subcircuit 111 includes at least one fifth voltage stabilizing capacitor C5.

[0180] like Figure 27 As shown, when the first reset sub-circuit 103 includes a first transistor T1, and the first transistor T1 is a dual-gate transistor, the first transistor T1 includes a first sub-transistor T11 and a second sub-transistor T12; the control electrode of the first sub-transistor T11 is electrically connected to the first reset signal line Reset1, the first electrode of the first sub-transistor T11 is electrically connected to the initialization signal line Vint, and the second electrode of the first sub-transistor T11 is electrically connected to the first electrode of the second sub-transistor T12; the control electrode of the second sub-transistor T12 is electrically connected to the first node N1, and the second electrode of the second sub-transistor T12 is electrically connected to the control electrode of the driving transistor Td, that is, the second electrode of the second sub-transistor T12 is electrically connected to the first node N1. The first end of the first stabilizing capacitor C1 is electrically connected to the second electrode of the first sub-transistor T11, that is, the first end of the first stabilizing capacitor C1 is electrically connected to the first node N1, and the second end of the first stabilizing capacitor C1 is electrically connected to the first reset signal line Reset1.

[0181] When the compensation sub-circuit 104 includes a second transistor T2, and the second transistor T2 is a dual-gate transistor, the second transistor T2 includes a third sub-transistor T21 and a fourth sub-transistor T22. The control electrode of the third sub-transistor T21 is electrically connected to the gate scan line Gate, the first electrode of the third sub-transistor T21 is electrically connected to the second electrode of the driving transistor Td, and the second electrode of the third sub-transistor T21 is electrically connected to the first electrode of the fourth sub-transistor T22. The control electrode of the fourth sub-transistor T22 is electrically connected to the gate scan line Gate, and the second electrode of the fourth sub-transistor T22 is electrically connected to the control electrode of the driving transistor Td, that is, the second electrode of the fourth sub-transistor T22 is electrically connected to the first node N1. The first end of the fifth voltage-stabilizing capacitor C5 is electrically connected to the second electrode of the third sub-transistor T21, that is, the first end of the fifth voltage-stabilizing capacitor C5 is electrically connected to the first node N1, and the second end of the fifth voltage-stabilizing capacitor C5 is electrically connected to the first reset signal line Reset1 or the gate scan line Gate.

[0182] The following uses the operation of the second transistor T2 and the fifth voltage-stabilizing capacitor C5 as an example to describe the principle by which the fifth voltage-stabilizing capacitor C5 suppresses leakage in the second transistor T2. Since the structures of the first transistor T1 and the first voltage-stabilizing capacitor C1 are similar to those of the second transistor T2 and the fifth voltage-stabilizing capacitor C5, the principle by which the first voltage-stabilizing capacitor C1 suppresses leakage in the first transistor T1 can be found in the following description and will not be further elaborated here.

[0183] like Figure 28A and Figure 28B As shown, for the convenience of explanation, the equivalent diagram of the fifth voltage-stabilizing capacitor C5 and the second transistor T2 is simplified. The second transistor T2 includes a third sub-transistor T21 and a fourth sub-transistor T22. In the following description, the potential of the first electrode of the third sub-transistor T21 is V s , the potential of the second electrode of the third sub-transistor T21 is V d’ , the potential of the first electrode of the fourth sub-transistor T22 is V s’ , the potential of the second electrode of the fourth sub-transistor T22 is V d , the potential of the first terminal of the fifth voltage stabilizing capacitor C5 is V c5 .

[0184] In the input and compensation phase P2, the third sub-transistor T21 and the fourth sub-transistor T22 are both turned on under the control of the gate scan signal, transmitting the electrical signal I from the second node N2 to the first node N1. After the input and compensation phase P2 ends, V s Greater than V d’ , V d’ Equal to or approximately equal to V s’ , and V s’ Greater than V d , V c5 Equal to or approximately equal to V s’ , that is, due to the voltage holding effect of the capacitor, the potential V c5 In the light emitting phase P3, the third sub-transistor T21 and the fourth sub-transistor T22 are both turned off under the control of the gate scanning signal. Since the potential V c5 is maintained, so V s’ and V d’ remains roughly unchanged, V s’ Still greater than V d In this way, the current cannot flow from the second electrode to the first electrode of the fourth sub-transistor T22, which can suppress the reverse leakage of the first node N1 through the fourth sub-transistor T22. Similarly, V s Still greater than V d’ In this way, current cannot flow from the second electrode to the first electrode of the third sub-transistor T21, which can suppress the reverse leakage of the third sub-transistor T21. Therefore, by providing the fifth voltage-stabilizing capacitor C5, the leakage of the third sub-transistor T21 and the fourth sub-transistor T22 in the light-emitting phase P3 can be effectively reduced, so that the voltage of the first node N1 can be maintained.

[0185] In some embodiments, as Figures 19 to 21As shown, when the first switching transistor is a dual-gate transistor, the active layer of the first switching transistor (T1 or T2) includes at least one first extension (p1 or p1') and at least one second extension (p2 or p2'). One of the three conductive regions of the first switching transistor (T1 or T2) is electrically connected to the control electrode of the driving transistor Td; the second extension of the first switching transistor is electrically connected to one of the three conductive regions that is electrically connected to the control electrode of the driving transistor Td. The orthographic projection of the second extension (p2 or p2') of the first switching transistor on substrate 201 at least partially overlaps with the orthographic projection of a gate control line GL on substrate 201, and the overlapping portion forms a voltage-stabilizing capacitor. The gate control line GL includes a first reset signal line Reset1 or a gate scan line Gate.

[0186] Exemplarily, the active layer of the first switching transistor includes one, two, or three second extensions, and the portion where the second extension of the first switching transistor overlaps with the gate control line GL forms one, two, or three voltage-stabilizing capacitors. If the active layer of the first switching transistor includes multiple second extensions, and the portions where the multiple second extensions of the first switching transistor overlap with the gate control line GL form multiple voltage-stabilizing capacitors, the voltage stability of the ends of the multiple voltage-stabilizing capacitors electrically connected to the first switching transistor can be enhanced, thereby further enhancing the effect of improving leakage in the first switching transistor. The following embodiments of the present disclosure are described using the example of a first switching transistor having an active layer including one second extension.

[0187] like Figures 19 to 21 As shown, in some examples, the three conductive regions of the first switch transistor are a first conductive region (t13 or t23), a second conductive region (t14 or t24), and a third conductive region (t15 or t25). The second conductive region (t14 or t24) is located between the two channel regions of the first switch transistor (T1 or T2). The first conductive region (t13 or t23) is electrically connected to the control electrode of the drive transistor Td. One end of the second extension (p2 or p2') is electrically connected to the first conductive region (t13 or t23), and the other end extends away from the first conductive region (t13 or t23). The second extension is located between the first conductive region and the third conductive region, or on one side of the active layer of the first switch transistor.

[0188] The following describes the active layer of the first switch transistor by taking the first switch transistor being the first transistor T1 or the second transistor T2 as an example.

[0189] For example, Figures 19 to 21As shown, the first switching transistor is a first transistor T1, and the first transistor T1 is a dual-gate transistor. The active layer body t1 of the first transistor T1 is U-shaped and includes a first channel region t11, a second channel region t12, a first conductive region t13, a second conductive region t14, and a third conductive region t15. One end of the second extension p2 of the first transistor T1 is electrically connected to the first conductive region t13, and the other end extends in a direction away from the first conductive region t13. The orthographic projection of the second extension p2 of the first transistor T1 on the substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 or the gate scan line Gate on the substrate 201, and the overlapping portion of the two forms a second voltage-stabilizing capacitor C2.

[0190] like Figure 19 As shown, the second extension p2 of the first transistor T1 is located between the first conductive region t13 and the third conductive region t15, and the orthographic projection of the second extension p2 of the first transistor T1 on the substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 on the substrate 201. Alternatively, as Figure 20 and Figure 21 The second extension portion p2 of the first transistor T1 is located on one side of the active layer body of the first transistor T1. Figure 20 As shown, the second extension portion p2 of the first transistor T1 is located on a side of the first conductive region t13 away from the third conductive region t15 and close to the first reset signal line Reset1. The orthographic projection of the second extension portion p2 of the first transistor T1 on the substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 on the substrate 201. Exemplarily, the second extension portion p2 of the first transistor T1 is located on a side of the first conductive region t13 away from the third conductive region t15 and close to the gate scan line Gate. The orthographic projection of the second extension portion p2 of the first transistor T1 on the substrate 201 at least partially overlaps with the orthographic projection of the gate scan line Gate on the substrate 201.

[0191] It should be noted that the portion where at least one second extension portion p2 of the first transistor T1 overlaps with the first reset signal line Reset1 or the gate scan line Gate forms at least one second stabilizing capacitor C2. That is, the number of the second extension portions of the first transistor T1 is the same as the number of the second stabilizing capacitors C2.

[0192] For example, Figure 19 and Figure 20As shown, the first switching transistor is a second transistor T2, and the second transistor T2 is a dual-gate transistor. The active layer body of the second transistor T2 is L-shaped. The active layer body t2 of the second transistor T2 includes a first channel region t21, a second channel region t22, a first conductive region t23, a second conductive region t24, and a third conductive region t25. One end of a second extension p2' of the second transistor T2 is electrically connected to the second conductive region t24, and the other end extends in a direction away from the second conductive region t24. The orthographic projection of the second extension p2' of the second transistor T2 on the substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 or the gate scan line Gate on the substrate 201, and the overlapping portion of the two forms a sixth voltage-stabilizing capacitor C6.

[0193] For example, Figure 19 and Figure 20 As shown, the second extension portion p2′ of the second transistor T2 is located on one side of the active layer body t2 of the first transistor T1, and the orthographic projection of the second extension portion p2′ of the second transistor T2 on the substrate 201 at least partially overlaps with the orthographic projection of the gate scan line Gate on the substrate 201. Alternatively, the orthographic projection of the second extension portion p2′ of the second transistor T2 on the substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 on the substrate 201.

[0194] It should be noted that the portion where at least one second extension portion p2 ′ of the second transistor T2 overlaps with the first reset signal line Reset1 or the gate scan line Gate forms at least one sixth stabilizing capacitor C6 , that is, the number of the first extension portions of the second transistor T2 is the same as the number of the fifth stabilizing capacitors C5 .

[0195] like Figure 29 As shown, corresponding to the pattern design of the active layer of the above-mentioned first switching transistor, in the pixel circuit 100 provided in some embodiments of the present disclosure, the first voltage-stabilizing sub-circuit 110 includes at least one second voltage-stabilizing capacitor C2 on the basis of including at least one first voltage-stabilizing capacitor C1, and the second voltage-stabilizing sub-circuit 111 includes at least one sixth voltage-stabilizing capacitor C6 on the basis of including at least one fifth voltage-stabilizing capacitor C5.

[0196] A first end of the second voltage-stabilizing capacitor C2 is electrically connected to the second electrode of the second sub-transistor T12, and a second end of the second voltage-stabilizing capacitor C2 is electrically connected to the first reset signal line Reset1 or the gate scan line Gate. Since the second electrode of the second sub-transistor T12 is electrically connected to the first node N1, the first end of the second voltage-stabilizing capacitor C2 is electrically connected to the first node N1.

[0197] A first end of the sixth voltage-stabilizing capacitor C6 is electrically connected to the second electrode of the fourth sub-transistor T22, and a second end of the sixth voltage-stabilizing capacitor C6 is electrically connected to the first reset signal line Reset1 or the gate scan line Gate. Because the second electrode of the fourth sub-transistor T22 is electrically connected to the first node N1, the first end of the second voltage-stabilizing capacitor C2 is electrically connected to the first node N1.

[0198] like Figure 30A and Figure 30B As shown, the sixth voltage-stabilizing capacitor C6 is electrically connected to the first node N1, which is equivalent to the sixth voltage-stabilizing capacitor C6 being connected in parallel with the storage capacitor Cst. During the reset phase and the input and compensation phase P2, while the storage capacitor Cst is being charged, the sixth voltage-stabilizing capacitor C6 is also charged, i.e., the potential of the first end of the sixth voltage-stabilizing capacitor C6 is consistent with the potential of the first end of the storage capacitor Cst. When the light-emitting phase enters, even if the second transistor T2 (the third sub-transistor T21 and the fourth sub-transistor T22) has leakage, the charge stored in the sixth voltage-stabilizing capacitor C6 can provide a portion of the charge to the first node N1, thereby compensating for the voltage drop caused by the leakage of the second transistor T2. The provision of the sixth voltage-stabilizing capacitor C6 is equivalent to enhancing the charge storage capacity of the storage capacitor Cst, thereby stabilizing the potential of the first node N1 and reducing the voltage difference between the first and second electrodes of the second transistor T2, thereby reducing the leakage of the second transistor T2. The operating principle of the second voltage-stabilizing capacitor C2 can refer to the description of the operating principle of the sixth voltage-stabilizing capacitor C6 and is not repeated here.

[0199] It should be noted that the above embodiments of the present disclosure and Figures 15 to 21 Various pattern designs of the semiconductor layer 202 are provided. The present disclosure may also include other embodiments as long as the function of suppressing leakage of the first switch transistor can be achieved. Figure 22 The structure of the semiconductor layer 202, the first gate layer 204, the second gate layer 206 and the source / drain metal layer is shown in FIG. 1 , wherein the active layer of the first transistor T1 in the semiconductor layer 202 includes an active layer body and an extension portion, and the active layer of the second transistor T2 includes an active layer body and an extension portion. The patterns of the remaining film layers are relatively Figure 11 No changes have occurred, just Figures 15 to 21 The semiconductor layer 202 is shown with Figure 22 By replacing the semiconductor layer 202 in the figure, various structures can be obtained.

[0200] The following describes a case where the first switch transistor is a single-gate transistor.

[0201] like Figures 23 to 25As shown, in some embodiments, the active layer body (t1 or t2) of the first switch transistor (T1 or T2) includes a channel region (t11 or t22), a fourth conductive region (t16 or t26), and a fifth conductive region (t17 or t27), wherein the fourth conductive region (t16 or t26) and the fifth conductive region (t17 or t27) are respectively located on either side of the channel region (t11 or t22); an orthographic projection of a gate control line GL on the substrate 201 overlaps with an orthographic projection of the channel region of the first switch transistor on the substrate 201. The fourth conductive region (t16 or t26) is electrically connected to the control electrode of the drive transistor Td.

[0202] The active layer (T1' or T2') of the first switching transistor (T1 or T2) includes at least one third extension (p3 or p3'); the third extension (p3 or p3') is electrically connected to the fourth conductive region (t16 or t26), and the orthographic projection of the third extension (p3 or p3') on the substrate 201 at least partially overlaps with the orthographic projection of the gate control line GL on the substrate 201. The overlapping portion forms a voltage-stabilizing capacitor. The gate control line GL includes the first reset signal line Reset1 or the gate scan line Gate.

[0203] In some embodiments, the active layer (T1' or T2') of the first switching transistor (T1 or T2) further includes a fourth extension portion (p4 or p4'); the fourth extension portion (p4 or p4') is electrically connected to the fifth conductive region (t17 or t27), and the orthographic projection of the fourth extension portion (p4 or p4') on the substrate 201 at least partially overlaps with the orthographic projection of the gate control line GL on the substrate 201.

[0204] Exemplarily, the active layer of the first switching transistor includes one third extension / fourth extension, or two third extensions / fourth extensions, or three third extensions / fourth extensions, and the portion where the third extension of the first switching transistor overlaps with the gate control line GL forms one, two, or three voltage-stabilizing capacitors. When the active layer of the first switching transistor includes multiple third extensions / fourth extensions, and the portions where the multiple second extensions of the first switching transistor overlap with the gate control line GL form multiple voltage-stabilizing capacitors, the voltage stability of the ends of the multiple voltage-stabilizing capacitors electrically connected to the first switching transistor can be enhanced, thereby further enhancing the effect of improving leakage of the first switching transistor. The embodiments of the present disclosure are described using the example of a first switching transistor having an active layer including one third extension and one fourth extension.

[0205] The following describes the active layer of the first switch transistor by taking the first switch transistor being the first transistor T1 or the second transistor T2 as an example.

[0206] For example, Figure 24 As shown, the first switching transistor is a first transistor T1, and the first transistor T1 is a single-gate transistor. The active layer body t1 of the first transistor T1 includes a channel region t11, a fourth conductive region t16 and a fifth conductive region t17. The fourth conductive region t16 and the fifth conductive region t17 are respectively located on both sides of the channel region t11. The fourth conductive region t16 is electrically connected to the control electrode of the driving transistor Td. The third extension p3 of the first transistor T1 is electrically connected to the fourth conductive region t16 of the first transistor T1. The orthographic projection of the third extension p3 of the first transistor T1 on the substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 on the substrate 201. The overlapping portion of the two forms a third voltage-stabilizing capacitor C3.

[0207] In some examples, such as Figure 25 As shown, the first transistor T1 further includes a fourth extension portion p4, the fourth extension portion p4 of the first transistor T1 is electrically connected to the fifth conductive region t17 of the first transistor T1, and the orthographic projection of the fourth extension portion p4 of the first transistor T1 on the substrate 201 at least partially overlaps with the orthographic projection of the first reset signal line Reset1 on the substrate 201, and the overlapping portion of the two forms a fourth voltage-stabilizing capacitor C4.

[0208] For example, Figure 24 As shown, the first switching transistor is the second transistor T2, and the second transistor T2 is a single-gate transistor. The active layer body of the second transistor T2 includes a channel region t22, a fourth conductive region t26, and a fifth conductive region t27. The fourth conductive region t26 and the fifth conductive region t27 are respectively located on both sides of the channel region t22. The fourth conductive region t26 is electrically connected to the control electrode of the driving transistor Td. The third extension p3' of the second transistor T2 is connected to the fourth conductive region t26 of the second transistor T2, and the orthographic projection of the third extension t26 of the second transistor T2 on the substrate 201 at least partially overlaps with the orthographic projection of the gate scan line Gate on the substrate 201. The overlapping portion of the two forms a seventh voltage-stabilizing capacitor C7.

[0209] In some examples, such as Figure 25 As shown, the second transistor T2 further includes a fourth extension portion p4', the fourth extension portion p4' of the second transistor T2 is electrically connected to the fifth conductive region t27 of the second transistor T2, and the orthographic projection of the fourth extension portion p4' of the second transistor T2 on the substrate 201 is at least partially overlapped with the orthographic projection of the gate scan line Gate on the substrate 201, and the overlapping portion of the two forms an eighth voltage-stabilizing capacitor C8.

[0210] like Figure 31 and Figure 32As shown, corresponding to the pattern design of the active layer of the above-mentioned first switching transistor, in the pixel circuit 100 provided by some embodiments of the present disclosure, for the case where the first switching transistor is a single-gate transistor, the first voltage-stabilizing sub-circuit 110 includes at least one third voltage-stabilizing capacitor C3, and the second voltage-stabilizing sub-circuit 111 includes at least one seventh voltage-stabilizing capacitor C7, or the first voltage-stabilizing sub-circuit 110 includes at least one third voltage-stabilizing capacitor C3 and at least one fourth voltage-stabilizing capacitor C4, and the second voltage-stabilizing sub-circuit 111 includes at least one seventh voltage-stabilizing capacitor C7 and at least one eighth voltage-stabilizing capacitor C8.

[0211] The first reset sub-circuit 103 includes a first transistor T1, which is a single-gate transistor. The control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the initialization signal line Vint, and the second electrode of the first transistor T1 is electrically connected to the control electrode of the drive transistor Td. One end of a third voltage-stabilizing capacitor C3 is electrically connected to the second electrode of the first transistor T1, and the second end of the third voltage-stabilizing capacitor C3 is electrically connected to the first reset signal line Reset1 or the gate scan line Gate. One end of a fourth voltage-stabilizing capacitor C4 is electrically connected to the first electrode of the first transistor T1, and the second end of the fourth voltage-stabilizing capacitor C4 is electrically connected to the first reset signal line Reset1 or the gate scan line Gate.

[0212] When the compensation sub-circuit 104 includes a second transistor T2, and the second transistor T2 is a single-gate transistor, the control electrode of the second transistor T2 is electrically connected to the gate scan line Gate, the first electrode of the second transistor T2 is electrically connected to the second electrode of the driving transistor Td, and the second electrode of the second transistor T2 is electrically connected to the control electrode of the driving transistor Td. A first end of a seventh voltage-stabilizing capacitor C7 is electrically connected to the second electrode of the second transistor T2, and a second end of the seventh voltage-stabilizing capacitor C7 is electrically connected to the first reset signal line Reset1 or the gate scan line Gate. A first end of an eighth voltage-stabilizing capacitor C8 is electrically connected to the first electrode of the second transistor T2, and a second end of a fourth voltage-stabilizing capacitor C4 is electrically connected to the first reset signal line Reset1 or the gate scan line Gate.

[0213] The following uses the operating process of the second transistor T2 and the seventh and eighth voltage-stabilizing capacitors C7 and C8 as an example to describe the principle by which the seventh and eighth voltage-stabilizing capacitors C7 and C8 suppress leakage from the second transistor T2. Since the structures of the first transistor T1, the third and fourth voltage-stabilizing capacitors C3 and C4 are similar to those of the second transistor T2, the seventh and eighth voltage-stabilizing capacitors C7 and C8, the principle by which the third and fourth voltage-stabilizing capacitors C3 and C4 suppress leakage from the first transistor T1 can be referred to in the following description and will not be further elaborated here.

[0214] like Figure 33A and Figure 33B For the convenience of explanation, in the following description, the potential of the first electrode of the second transistor T2 is V s , the potential of the second electrode of the second sub-transistor T12 is V d , the potential of the first terminal of the seventh voltage stabilizing capacitor C7 is V c7 , the potential of the first terminal of the eighth voltage stabilizing capacitor C8 is V c8 .

[0215] In the input and compensation phase P2, the second transistor T2 is turned on under the control of the gate scan signal, and transmits the electrical signal I from the second node N2 to the first node N1. After the input and compensation phase P2 ends, V s Greater than V d , V c7 Equal to or approximately equal to V d , V c8 Equal to or approximately equal to V s , and due to the voltage holding effect of the capacitor, the potential V c7 and the potential V of the first terminal of the eighth voltage stabilizing capacitor C8 c8 In the light-emitting phase P3, the second sub-transistor T12 is turned off under the control of the gate scanning signal, and the potential V c7 and the potential V of the first terminal of the eighth voltage stabilizing capacitor C8 c8 is maintained, so V s and V d remains roughly unchanged, V s Still greater than V d In this way, current cannot flow from the second electrode to the first electrode of the second transistor T2, which can suppress reverse leakage of the first node N1 through the second transistor T2, so that the voltage of the first node N1 can be maintained.

[0216] And, as Figure 33A and Figure 33BAs shown, the seventh voltage-stabilizing capacitor C7 is electrically connected to the first node N1, which is equivalent to the seventh voltage-stabilizing capacitor C7 being connected in parallel with the storage capacitor Cst. During the reset phase and the input and compensation phase P2, while the storage capacitor Cst is being charged, the seventh voltage-stabilizing capacitor C7 is also charged, i.e., the potential of the first end of the seventh voltage-stabilizing capacitor C7 is consistent with the potential of the first end of the storage capacitor Cst. When the light-emitting phase enters, even if the second transistor T2 is leaking, the charge stored in the seventh voltage-stabilizing capacitor C7 can provide a portion of the charge to the first node N1, thereby compensating for the voltage drop caused by the leakage of the second transistor T2. The provision of the seventh voltage-stabilizing capacitor C7 is equivalent to enhancing the charge storage capacity of the storage capacitor Cst, thereby stabilizing the potential of the first node N1 and reducing the voltage difference between the first electrode and the second electrode of the second transistor T2, thereby reducing the leakage of the second transistor T2. The operating principle of the third voltage-stabilizing capacitor C3 can refer to the description of the operating principle of the seventh voltage-stabilizing capacitor C7 and is not repeated here.

[0217] It should be noted that the above embodiments of the present disclosure and Figures 23 to 25 Various pattern designs of the semiconductor layer 202 are provided. The present disclosure may also include other embodiments as long as the function of suppressing leakage of the first switch transistor can be achieved. Figure 26 The structure of the semiconductor layer 202, the first gate layer 204, the second gate layer 206 and the source / drain metal layer is shown in FIG. 1 , wherein the active layer of the first transistor T1 in the semiconductor layer 202 includes an active layer body and an extension portion, and the active layer of the second transistor T2 includes an active layer body and an extension portion. The patterns of the remaining film layers are relatively Figure 12 No changes have occurred, just Figures 23 to 25 The semiconductor layer 202 is shown with Figure 26 By replacing the semiconductor layer 202 in the figure, various overall structural diagrams can be obtained.

[0218] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, characterized in that: include: substrate; a plurality of sub-pixels disposed on the substrate; Each sub-pixel includes pixel circuitry; The pixel circuit includes a driving transistor and at least one first switching transistor, wherein the first switching transistor is electrically connected to the control electrode of the driving transistor; and A plurality of gate control lines are provided on the substrate; each pixel circuit is electrically connected to at least two gate control lines; Wherein, the first switch transistor includes an active layer, and the active layer includes an active layer body and at least one first extension portion; The active layer body of the first switch transistor includes two channel regions and three conductive regions, the conductive regions are electrically connected to the channel regions alternately in sequence, and one of the conductive regions is located between the two channel regions; An orthographic projection of a gate control line on the substrate overlaps with an orthographic projection of two channel regions of the first switch transistor on the substrate; The first extension portion of the first switching transistor is electrically connected to a conductive region located between two channel regions of the first switching transistor, and an orthographic projection of the first extension portion of the first switching transistor on the substrate at least partially overlaps with an orthographic projection of a gate control line on the substrate, and the overlapping portion of the two forms a voltage-stabilizing capacitor.

2. The display panel according to claim 1, wherein: The three conductive regions of the first switch transistor are respectively a first conductive region, a second conductive region and a third conductive region, and the second conductive region is located between the two channel regions of the first switch transistor; One end of the extension portion is electrically connected to the second conductive area, and the other end thereof extends in a direction away from the second conductive area; The first extension portion is located between the first conductive region and the third conductive region, or is located on one side of the active layer body of the first transistor.

3. The display panel according to claim 1, wherein: The active layer of the first switch transistor further includes at least one second extension; One of the three conductive regions of the first switch transistor is electrically connected to the control electrode of the drive transistor; The second extension portion of the first switching transistor is electrically connected to a conductive region of the three conductive regions that is electrically connected to the control electrode of the driving transistor, and the orthographic projection of the second extension portion of the first switching transistor on the substrate at least partially overlaps with the orthographic projection of the gate control line on the substrate.

4. The display panel according to claim 3, wherein: The three conductive regions of the first switch transistor are respectively a first conductive region, a second conductive region and a third conductive region, the second conductive region is located between the two channel regions of the first switch transistor; the first conductive region is electrically connected to the control electrode of the driving transistor; One end of the second extension portion is electrically connected to the first conductive area, and the other end thereof extends in a direction away from the first conductive area; The second extension portion is located between the first conductive region and the third conductive region, or is located on one side of the active layer body of the first switch transistor.

5. A display panel, characterized in that: include: substrate; a plurality of sub-pixels disposed on the substrate; Each sub-pixel includes pixel circuitry; The pixel circuit includes a driving transistor and at least one first switching transistor, wherein the first switching transistor is electrically connected to the control electrode of the driving transistor; and A plurality of gate control lines are provided on the substrate; each pixel circuit is electrically connected to at least two gate control lines; Wherein, the first switch transistor includes an active layer, and the active layer includes an active layer body and at least one third extension portion; The active layer body of the first switch transistor includes a channel region, a fourth conductive region, and a fifth conductive region, wherein the fourth conductive region and the fifth conductive region are respectively located on both sides of the channel region; wherein the fourth conductive region is electrically connected to the control electrode of the driving transistor; The third extension portion is connected to the fourth conductive region, and an orthographic projection of the third extension portion on the substrate at least partially overlaps with an orthographic projection of the gate control line on the substrate, and the overlapping portion thereof forms a voltage-stabilizing capacitor.

6. The display panel according to claim 5, wherein: The active layer of the first switch transistor further includes a fourth extension; The fourth extension portion is electrically connected to the fifth conductive region, and an orthographic projection of the fourth extension portion on the substrate at least partially overlaps with an orthographic projection of the gate control line on the substrate.

7. The display panel according to any one of claims 1 to 6, wherein: Also includes: a plurality of initialization signal lines, each pixel circuit being electrically connected to at least one initialization signal line; Wherein, the gate control line electrically connected to the pixel circuit includes a first reset signal line; The at least one first switching transistor includes a first transistor; a control electrode of the first transistor is electrically connected to the first reset signal line, a first electrode of the first transistor is electrically connected to an initialization signal line, and a second electrode of the first transistor is electrically connected to the control electrode of the driving transistor; An orthographic projection of the extending portion of the first transistor on the substrate at least partially overlaps with an orthographic projection of the first reset signal line on the substrate.

8. The display panel according to claim 7, wherein: The gate control line electrically connected to the pixel circuit further includes a gate scanning line; The at least one first switching transistor further includes a second transistor; a control electrode of the second transistor is electrically connected to the gate scan line, a first electrode of the second transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the second transistor is electrically connected to the control electrode of the driving transistor; An orthographic projection of the extension portion of the second transistor on the substrate at least partially overlaps with an orthographic projection of the gate scan line on the substrate; Alternatively, an orthographic projection of the extension portion of the second transistor on the substrate at least partially overlaps with an orthographic projection of the first reset signal line on the substrate.

9. The display panel according to any one of claims 1 to 6, wherein: Also includes: a plurality of first voltage signal lines, a plurality of light emitting control lines and a plurality of data lines; The gate control line electrically connected to the pixel circuit further includes a second reset signal line; Each pixel circuit is also electrically connected to a first voltage signal line; The pixel circuit further includes a storage capacitor; The storage capacitor includes a first electrode plate and a second electrode plate arranged opposite to each other; The first electrode plate is provided in the same layer as the plurality of gate control lines, and the first electrode plate is electrically connected to the control electrode of the driving transistor; The second electrode plate is arranged on a side of the first electrode plate away from the substrate; the second electrode plate is electrically connected to the first voltage signal line; Each pixel circuit is electrically connected to a light emitting control line, a data line, and the second reset signal line; The pixel circuit further includes at least one second switching transistor, and each second switching transistor is electrically connected to the first electrode or the second electrode of the driving transistor.

10. The display panel according to any one of claims 1 to 6, wherein: The pixel circuit comprises: A driving subcircuit; the driving subcircuit is configured to generate a driving current; a storage sub-circuit; the storage sub-circuit being electrically connected to the drive sub-circuit and the first voltage signal line; the storage sub-circuit being configured to store the received signal and maintain the potential of the connection terminal between the storage sub-circuit and the drive sub-circuit; a first reset sub-circuit; the first reset sub-circuit is electrically connected to a first reset signal line, the driver sub-circuit, and an initialization signal line; the reset sub-circuit is configured to transmit an initialization signal received at the initialization signal line to the driver sub-circuit in response to a first gate signal received at the first reset signal line; a compensation subcircuit; the compensation subcircuit being electrically connected to the driving subcircuit and the gate scan line; the compensation subcircuit being configured to perform threshold compensation on the driving subcircuit in response to a gate scan signal received at the gate scan line; a first voltage stabilizing subcircuit; the first voltage stabilizing subcircuit is electrically connected to the first reset subcircuit, and the first voltage stabilizing subcircuit is electrically connected to the first reset signal line or the gate scan line; the first voltage stabilizing subcircuit is configured to suppress leakage of the first reset subcircuit; and a second voltage stabilizing subcircuit; the second voltage stabilizing subcircuit is electrically connected to the compensation subcircuit, and the second voltage stabilizing subcircuit is electrically connected to the first reset signal line or the gate scan line; the first voltage stabilizing subcircuit is configured to suppress leakage of the compensation subcircuit.

11. The display panel according to claim 10, wherein: The driving subcircuit includes a driving transistor; the first voltage stabilizing subcircuit includes at least one first voltage stabilizing capacitor; The first reset sub-circuit includes a first transistor, which is a dual-gate transistor; The first transistor includes a first sub-transistor and a second sub-transistor; the control electrode of the first sub-transistor is electrically connected to the first reset signal line, the first electrode of the first sub-transistor is electrically connected to the initialization signal line, and the second electrode of the first sub-transistor is electrically connected to the first electrode of the second sub-transistor; the control electrode of the second sub-transistor is electrically connected to the first reset signal line, and the second electrode of the second sub-transistor is electrically connected to the control electrode of the drive transistor; A first end of the first voltage stabilizing capacitor is electrically connected to the second electrode of the first sub-transistor, and a second end of the first voltage stabilizing capacitor is electrically connected to the first reset signal line.

12. The display panel according to claim 11, wherein: The first voltage stabilization subcircuit further includes at least one second voltage stabilization capacitor; A first end of the second voltage-stabilizing capacitor is electrically connected to the second electrode of the second sub-transistor, and a second end of the second voltage-stabilizing capacitor is electrically connected to the first reset signal line or the gate scanning line.

13. The display panel according to claim 10, wherein: The driving subcircuit includes a driving transistor; the first voltage stabilizing subcircuit includes at least one third voltage stabilizing capacitor and at least one fourth voltage stabilizing capacitor; The first reset sub-circuit includes a first transistor, a control electrode of the first transistor is electrically connected to the first reset signal line, a first electrode of the first transistor is electrically connected to the initialization signal line, and a second electrode of the first transistor is electrically connected to the control electrode of the drive transistor; A first end of the third voltage-stabilizing capacitor is electrically connected to the second electrode of the first transistor, and a second end of the third voltage-stabilizing capacitor is electrically connected to the first reset signal line or the gate scan line; A first end of the fourth voltage-stabilizing capacitor is electrically connected to the first electrode of the first transistor, and a second end of the fourth voltage-stabilizing capacitor is electrically connected to the first reset signal line or the gate scan line.

14. The display panel according to claim 10, wherein: The driving subcircuit includes a driving transistor; the second voltage stabilizing subcircuit includes at least one fifth voltage stabilizing capacitor; The compensation sub-circuit includes a second transistor, which is a dual-gate transistor; The second transistor includes a third sub-transistor and a fourth sub-transistor; the control electrode of the third sub-transistor is electrically connected to the gate scan line, the first electrode of the third sub-transistor is electrically connected to the second electrode of the drive transistor, and the second electrode of the third sub-transistor is electrically connected to the first electrode of the fourth sub-transistor; the control electrode of the fourth sub-transistor is electrically connected to the gate scan line, and the second electrode of the fourth sub-transistor is electrically connected to the control electrode of the drive transistor; A first end of the fifth voltage-stabilizing capacitor is electrically connected to the second electrode of the third sub-transistor, and a second end of the fifth voltage-stabilizing capacitor is electrically connected to the first reset signal line or the gate scan line.

15. The display panel according to claim 14, wherein: The second voltage stabilization sub-circuit further includes at least one sixth voltage stabilization capacitor; A first end of the sixth voltage-stabilizing capacitor is electrically connected to the second electrode of the fourth sub-transistor, and a second end of the sixth voltage-stabilizing capacitor is electrically connected to the first reset signal line or the gate scan line.

16. The display panel according to claim 10, wherein: The driving subcircuit includes a driving transistor; the second voltage stabilizing subcircuit includes at least one seventh voltage stabilizing capacitor and at least one eighth voltage stabilizing capacitor; The compensation sub-circuit includes a second transistor, a control electrode of the second transistor is electrically connected to the gate scan line, a first electrode of the second transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the second transistor is electrically connected to the control electrode of the driving transistor; A first end of the seventh voltage-stabilizing capacitor is electrically connected to the second electrode of the second transistor, and a second end of the seventh voltage-stabilizing capacitor is electrically connected to the first reset signal line or the gate scan line; A first end of the eighth voltage-stabilizing capacitor is electrically connected to the first electrode of the second transistor, and a second end of the eighth voltage-stabilizing capacitor is electrically connected to the first reset signal line or the gate scan line.

17. The display panel according to claim 10, wherein: Also includes: a data writing sub-circuit; the data writing sub-circuit is electrically connected to the gate scanning line, the data line and the driving sub-circuit; The data writing sub-circuit is configured to transmit a data signal received at the data line to the driving sub-circuit in response to a gate scanning signal received at the gate scanning line; The driving sub-circuit and the compensation sub-circuit are further configured to transmit the data signal to the storage sub-circuit; a second reset subcircuit; the second reset subcircuit is electrically connected to the second reset signal line, the initialization signal line, and the light-emitting device; the second reset subcircuit is configured to transmit the initialization signal received at the initialization signal line to the light-emitting device in response to the gate scan signal received at the gate scan line; a first light-emitting control subcircuit; The first light-emitting control subcircuit is electrically connected to a light-emitting control line, the first voltage signal line, and the driving subcircuit, and the first light-emitting control subcircuit is configured to transmit a first voltage signal received at the first voltage signal line to the driving subcircuit in response to a light-emitting control signal received at the light-emitting control line; a second light-emitting control subcircuit; The second light emitting control subcircuit is electrically connected to the light emitting control line, the driving subcircuit and the light emitting device; The second light emitting control sub-circuit is configured to transmit the driving current generated by the driving sub-circuit to the light emitting device to control the light emitting device to emit light.

18. A display device, characterized in that: The device comprises the display panel according to any one of claims 1 to 17.

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