Display device

Abstract

The present application relates to a display device. The display device includes: a base substrate in which a display area and a non-display area positioned around the display area are defined, and includes a substrate connection electrode that passes through the base substrate in a thickness direction; an etching stopper that is disposed on one surface of the base substrate and covers the substrate connection electrode; and a first pad that is disposed on another surface of the base substrate that is opposite to the one surface of the base substrate and is disposed to overlap with the substrate connection electrode, wherein the substrate connection electrode is disposed in the display area, the substrate connection electrode is connected to the etching stopper and the first pad, the etching stopper is electrically connected to the first pad through the substrate connection electrode, and the etching stopper includes a conductive material.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] As multimedia technology develops, the importance of display devices has been increasing. In response to this, various types of display devices, such as organic light emitting displays, liquid crystal displays (LCDs), and the like, have been used.

[0003] The display device is a device for displaying an image, and includes a display panel, such as an organic light-emitting display panel or a liquid crystal display panel. The light-emitting display panel may include a light-emitting element, such as a light-emitting diode (LED), and examples of the light-emitting diode include an organic light-emitting diode (OLED) using an organic material as a fluorescent material and an inorganic light-emitting diode using an inorganic material as a fluorescent material. Summary of the invention

[0004] [Technical issues]

[0005] Aspects of the present disclosure provide a display device in which a driving circuit unit such as a driving chip and / or a chip on film on which the driving chip is mounted is disposed on a rear surface of a base substrate.

[0006] It should be noted that aspects of the present disclosure are not limited thereto, and other aspects not mentioned herein will be apparent to those of ordinary skill in the art from the following description.

[0007] [Technical solution]

[0008] According to an embodiment of the present disclosure, a display device includes: a base substrate, in which a display area and a non-display area positioned around the display area are defined, and the base substrate includes a substrate connecting electrode passing through the base substrate in a thickness direction thereof; an etching stopper, which is arranged on one surface of the base substrate and configured to cover the substrate connecting electrode; and a first pad, which is arranged on another surface of the base substrate opposite to the one surface of the base substrate and is arranged to overlap with the substrate connecting electrode, wherein the substrate connecting electrode is arranged in the display area and is connected to the etching stopper and the first pad, and the etching stopper is electrically connected to the first pad through the substrate connecting electrode and includes a conductive material.

[0009] The display device may further include: a buffer layer disposed on the etch stopper; an active material layer disposed on the buffer layer; and a light blocking layer disposed to overlap with the active material layer, wherein the light blocking layer is disposed to be coplanar with the etch stopper and spaced apart from the etch stopper.

[0010] The display device may also include: a first gate insulating layer, disposed on the active material layer; a data line, disposed on the first gate insulating layer, wherein the data line is connected to the etching stopper through a data connection electrode, and the data connection electrode passes through the first gate insulating layer and the buffer layer in a thickness direction thereof; and a connecting line, disposed on another surface of the base substrate, wherein the connecting line is connected to the first pad.

[0011] The display device may further include: a film chip disposed on the other surface of the base substrate, and a driving chip mounted on the film chip; and a second pad disposed on the other surface of the base substrate, wherein the second pad is connected to the connection line, and the film chip is connected to the second pad.

[0012] The display device may further include: a driving chip disposed on the other surface of the base substrate; and a second pad disposed on the other surface of the base substrate, wherein the second pad is connected to the connection line, and the driving chip is disposed to overlap with the second pad and is connected to the second pad.

[0013] One surface of the base substrate may be in contact with the etch stopper, and the substrate connection electrode may be surrounded by an extension of the other surface of the base substrate, an extension of the one surface of the base substrate, and a side surface of the base substrate.

[0014] The width of the substrate connection electrode may decrease in a direction from an extension portion of the other surface of the base substrate toward an extension portion of the one surface of the base substrate.

[0015] A slope of a side surface of the substrate connection electrode in contact with the side surface of the base substrate may gradually increase in a direction from an extension portion of the other surface of the base substrate toward an extension portion of the one surface of the base substrate.

[0016] The width of the substrate connection electrode may be constant from an extension portion of the other surface of the base substrate to an extension portion of the one surface of the base substrate.

[0017] A portion of one surface of the etch stopper that contacts the substrate connection electrode may have a roughness higher than a roughness of a portion of the one surface of the etch stopper that does not contact the substrate connection electrode.

[0018] An etching residue may also be provided on one surface of the etching stopper in contact with the substrate connection electrode; and the etching residue may include the same material as the base substrate.

[0019] A plurality of pixels may be arranged in the display area, each of the plurality of pixels may include an emission area and a non-emission area positioned around the emission area, an outer bank portion arranged on a data line may be arranged in the non-emission area, a light emitting element may be arranged in the emission area, and the emission area may be surrounded by the outer bank portion in a plan view.

[0020] The substrate connection electrode may be arranged to overlap with the emission region.

[0021] The substrate connection electrode may be disposed to overlap with the outer bank in the non-emission region.

[0022] The display device may also include: a first gate insulating layer, arranged on the active material layer; a first gate connecting electrode, arranged on the first gate insulating layer; a first protective layer, arranged on the first gate connecting electrode; and a data line, arranged on the first protective layer, wherein the data line is connected to the first gate connecting electrode via a data connecting electrode passing through the first protective layer, and the first gate connecting electrode is connected to the etching stopper via a second gate connecting electrode passing through the first gate insulating layer and the buffer layer.

[0023] According to an embodiment of the present disclosure, a display device includes: a base substrate, in which a display area and a non-display area positioned around the display area are defined, and the base substrate includes a substrate through hole passing through the base substrate in a thickness direction thereof; a buffer layer, arranged on one surface of the base substrate, and including a buffer through hole arranged to overlap with the substrate through hole and passing through the buffer layer in a thickness direction thereof; a data line, arranged on the buffer layer; a substrate connecting electrode, configured to fill the substrate through hole and the buffer through hole, wherein the substrate connecting electrode is arranged in the display area and connected to the data line; and a first solder pad, arranged on another surface of the base substrate opposite to one surface of the base substrate, and arranged to overlap with the substrate through hole, wherein the first solder pad is connected to the substrate connecting electrode.

[0024] A surface of the base substrate may be in contact with the buffer layer, the substrate through hole may be surrounded by an extension of the other surface of the base substrate, an extension of one surface of the base substrate, and a side surface of the base substrate, the buffer layer may include a surface in contact with one surface of the base substrate and another surface opposite to one surface of the buffer layer, the buffer through hole may be surrounded by an extension of one surface of the buffer layer, an extension of another surface of the buffer layer, and a side surface of the buffer layer, and an average slope of the side surface of the buffer layer may be greater than an average slope of the side surface of the base substrate.

[0025] The display device may further include a first gate insulating layer directly disposed on another surface of the buffer layer, wherein a portion of one surface of the first gate insulating layer in contact with the substrate connecting electrode has a roughness higher than a portion of one surface of the first gate insulating layer not in contact with the substrate connecting electrode.

[0026] The display device may further include a first gate insulating layer directly disposed on another surface of the buffer layer, wherein an etching residue is further disposed on a surface of the first gate insulating layer in contact with the substrate connection electrode, and the etching residue includes the same material as that of the buffer layer.

[0027] The buffer through hole may be provided to partially overlap one surface of the base substrate in a thickness direction thereof.

[0028] Details of other implementations are included in the detailed description and accompanying drawings.

[0029] [Beneficial Effects]

[0030] In the display device according to one embodiment, a driving circuit unit such as a driving chip and / or a chip on film on which the driving chip is mounted is disposed on the rear surface of a base substrate, thereby reducing a dead zone.

[0031] It should be noted that the objects of the present disclosure are not limited to the objects described above, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0032] The effects according to the embodiments are not limited to the above-exemplified contents, and more various effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a plan view of a display device according to an embodiment.

[0034] Figure 2 It is along Figure 1 A cross-sectional view taken along line II'.

[0035] Figure 3 is a plan view of a display device according to one embodiment, viewed from above.

[0036] Figure 4 yes Figure 3 A magnified plan view of the pixels.

[0037] Figure 5 Shown along Figure 4 Cross-sectional views taken along lines IV-IV', V-V' and VI-VI'.

[0038] Figure 6 is a plan view of a display device according to one embodiment, viewed from below.

[0039] Figure 7 Shown along Figure 3 and Figure 6 Cross-sectional views taken along lines II-II' and III-III'.

[0040] Figure 8 yes Figure 7 An enlarged cross-sectional view of area A.

[0041] Figures 9 to 14 is a cross-sectional view illustrating a process operation of a method of manufacturing a display device according to an embodiment.

[0042] Fig.15 is a cross-sectional view of a display device according to another embodiment.

[0043] Fig.16 is a cross-sectional view of a display device according to still another embodiment.

[0044] Fig.17 is a cross-sectional view of a display device according to still another embodiment.

[0045] Fig.18 is a cross-sectional view of a display device according to still another embodiment.

[0046] Fig.19 is a cross-sectional view of a display device according to still another embodiment.

[0047] Fig. 20 is a cross-sectional view of a display device according to still another embodiment.

[0048] Fig.21 is a plan view of a display device according to still another embodiment, viewed from above.

[0049] Fig. 22 is an enlarged plan view of a pixel of a display device according to still another embodiment.

[0050] Fig.23 is a plan view of a display device according to still another embodiment as viewed from below.

[0051] Fig.24 It is along Fig.23 Cross-sectional views of the display device taken along lines VII-VII' and VIII-VIII'.

[0052] Fig.25 is a plan view of a display device according to still another embodiment as viewed from below.

[0053] Fig.26 is based on Fig.25 A cross-sectional view of a display device.

[0054] Fig. 27 is a cross-sectional view of a display device according to still another embodiment.

[0055] Fig.28 is a cross-sectional view of a display device according to still another embodiment.

[0056] Fig.29 yes Fig.28 An enlarged cross-sectional view of area B.

[0057] Figure 30 to Figure 33 is a cross-sectional view illustrating a process operation of a method of manufacturing a display device according to another embodiment.

[0058] Fig.34 is a cross-sectional view of a display device according to still another embodiment.

[0059] Fig.35 is a cross-sectional view of a display device according to still another embodiment.

[0060] Fig.36 is a cross-sectional view of a display device according to still another embodiment.

[0061] Fig.37 is a plan view of a display device according to still another embodiment. DETAILED DESCRIPTION

[0062] The present invention will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. However, the present invention may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art.

[0063] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification.

[0064] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0065] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0066] Figure 1 is a plan view of a display device according to an embodiment. Figure 2 It is along Figure 1 A cross-sectional view taken along line II'.

[0067] refer to Figure 1 and Figure 2The display device 1 can be applied to various electronic devices, including small and medium-sized electronic devices (such as tablet personal computers (PCs), smart phones, vehicle navigation units, cameras, central information displays (CIDs) provided to vehicles, watch-type electronic devices, personal digital assistants (PDAs), portable multimedia players (PMPs), and game consoles) and large electronic devices (such as televisions, external billboards, monitors, PCs, and laptop computers). However, the various electronic devices are provided only as embodiments, and it is obvious that the display device 1 can be applied to other electronic devices without departing from the concept of the present disclosure.

[0068] In some embodiments, the display device 1 may have a rectangular shape in a plan view. The display device 1 may include two first sides extending in a first direction DR1 and two second sides extending in a second direction DR2 intersecting the first direction DR1. The corners where the first side and the second side of the display device 1 intersect each other may be at right angles, but are not limited thereto. The corners may form a curved surface. In some embodiments, the first side may be longer than the second side, but are not limited thereto. The planar shape of the display device 1 is not limited to the planar shape shown, and a circular shape or other shapes may be applied.

[0069] The display device 1 may include a display area DA in which an image is displayed and a non-display area NDA in which no image is displayed. In some embodiments, the non-display area NDA may be positioned around the display area DA and may surround the display area DA.

[0070] In one embodiment, the display device 1 may include a first display substrate 10 and a second display substrate 20 opposite to the first display substrate 10, and may further include a sealing member SEAL coupling the first display substrate 10 and the second display substrate 20, and a filler FM filling a space between the first display substrate 10 and the second display substrate 20. The sealing member SEAL may be disposed in the non-display area NDA, and may be disposed not to overlap with the display area DA.

[0071] The first display substrate 10 may include elements and circuits for displaying images (e.g., pixel circuits such as switching elements), outer banks for defining emission areas and non-emission areas to be described below in the display area DA, and self-luminous elements. In an embodiment, the self-luminous element may include at least one of an organic light emitting diode (LED), a quantum dot LED, an inorganic-based micron LED (e.g., a micron LED), and an inorganic-based nano LED (e.g., a nano LED).

[0072] The second display substrate 20 may be positioned above the first display substrate 10 and may be opposite to the first display substrate 10. The second display substrate 20 may include a color conversion pattern for converting the color of incident light. In some embodiments, the color conversion pattern may include at least one of a color filter and a color control layer.

[0073] The sealing member SEAL may be positioned between the first display substrate 10 and the second display substrate 20 in the non-display area NDA. The sealing member SEAL may be disposed along the edges of the first display substrate 10 and the second display substrate 20 in the non-display area NDA to surround the display area DA in a plan view. The first display substrate 10 and the second display substrate 20 may be coupled to each other by the sealing member SEAL. In some embodiments, the sealing member SEAL may be made of an organic material. As an example, the sealing member SEAL may be made of an epoxy-based resin, but the present disclosure is not limited thereto.

[0074] The filler FM may be positioned in a space surrounded by a sealing member SEAL between the first display substrate 10 and the second display substrate 20. The filler FM may fill the space between the first display substrate 10 and the second display substrate 20. The filler FM may be made of a material capable of transmitting light. In some embodiments, the filler FM may be made of an organic material. As an example, the filler FM may be made of a silicon-based organic material, an epoxy-based organic material, etc., but the present disclosure is not limited thereto. In addition, in some cases, the filler FM may be omitted.

[0075] Figure 3 is a plan view of a display device according to one embodiment, viewed from above.

[0076] refer to Figure 3 , a plurality of pixels PX may be provided in the display area DA. The plurality of pixels PX may be arranged in a matrix form in the first direction DR1 and the second direction DR2. The plurality of pixels PX arranged in the first direction DR1 may form a pixel row. A plurality of pixel rows may be formed. The plurality of pixel rows may be arranged in the second direction DR2. Similarly, the plurality of pixels PX arranged in the second direction DR2 may form a pixel column. A plurality of pixel columns may be formed. The plurality of pixel columns may be arranged in the first direction DR1.

[0077] The scan driver SP may be disposed in the non-display area NDA. The scan driver SP may include at least one thin film transistor. The scan driver SP may be connected to the scan line SL. A plurality of scan drivers SP may be provided. The scan driver SP may be positioned in each of the non-display area NDA at one side (or right side) of the display area DA in the first direction DR1 and the non-display area NDA at the other side (or left side) of the display area DA in the first direction DR1. In some embodiments, one scan driver SP may be provided. One scan driver SP may be provided in the non-display area NDA at one side or the other side of the display area DA in the first direction DR1. The scan line SL may extend along a pixel row. A plurality of scan lines SL may be provided. A plurality of scan lines SL may be arranged in the second direction DR2. Each of the plurality of scan lines SL arranged in the second direction DR2 may be connected to any one of the plurality of pixel rows.

[0078] The data line DL may extend along the pixel column. A plurality of data lines DL may be provided. The plurality of data lines DL may be arranged in the first direction DR1. Each of the plurality of data lines DL arranged in the first direction DR1 may be connected to any one of the plurality of pixel columns.

[0079] The data line DL may be connected to the substrate connection electrode CNTb. A plurality of substrate connection electrodes CNTb may be provided. Each substrate connection electrode CNTb may correspond to each data line DL. Figure 3 2 and 3. As shown in FIG. 2 , the arrangement of the plurality of substrate connection electrodes CNTb is arranged in the first direction DR1, but the arrangement of the plurality of substrate connection electrodes CNTb is not limited thereto. As will be described below, the data line DL may be connected to the data connection electrode CNTa (see FIG. 2 ). Figure 7 ), etch stop ES (see Figure 7 ) and the substrate connection electrode CNTb is connected to the first pad PAD1 (see Figure 6 and Figure 7 ).

[0080] Each pixel PX may include an emission area EMA and a non-emission area NEA positioned around the emission area EMA. As described above, the non-emission area NEA and the emission area EMA may be formed by the outer bank 45 (see FIG. Figure 7 ) and the light emitting element 30 (see Figure 4 ) are distinguished from each other. The outer bank 45 may be disposed in the non-emission area NEA, and the light emitting element 30 may be disposed in the emission area EMA. The outer bank 45 may not be disposed in the emission area EMA, and the light emitting element 30 may not be disposed in the non-emission area NEA. The substrate connection electrode CNTb and the data connection electrode CNTa may be disposed in the emission area EMA.

[0081] Figure 4 yes Figure 3 A magnified plan view of the pixels. Figure 5 Shown along Figure 4 Cross-sectional views taken along lines IV-IV', V-V' and VI-VI'.

[0082] refer to Figure 4 , any one of the plurality of pixels PX may emit light having a first color, another of the plurality of pixels PX may emit light having a second color, and yet another of the plurality of pixels PX may emit light having a third color. The first color may be red, the second color may be green, and the third color may be blue. However, the present disclosure is not limited thereto, and all pixels PX may emit light having the same color.

[0083] The pixel PX of the display device 1 may include an area defined as an emission area EMA. The emission area EMA may be defined as an area in which the light emitting element 30 included in the display device 1 is arranged to emit light having a specific wavelength. The light emitting element 30 may include an active layer, and the active layer may emit light having a specific wavelength without directionality. The light emitted from the active layer of the light emitting element 30 may be emitted toward both side surfaces of the light emitting element 30. The emission area EMA may include an area in which the light emitting element 30 is arranged and an area adjacent to the light emitting element 30 and in which the light emitted from the light emitting element 30 is emitted.

[0084] The present disclosure is not limited thereto, and the emission area EMA may also include an area in which light emitted from the light emitting element 30 is reflected or refracted by other components and emitted. A plurality of light emitting elements 30 may be provided in each pixel PX, and an area in which the light emitting element 30 is provided and an area adjacent to the light emitting element 30 may be combined to form the emission area EMA.

[0085] As shown in the drawings, each pixel PX of the display device 1 may include a non-emission area NEA defined as an area other than the emission area EMA. The non-emission area NEA may be an area where the light emitting element 30 is not disposed and the light emitted from the light emitting element 30 does not reach and thus does not emit light. The outer bank 45 may be disposed in the non-emission area NEA.

[0086] Combination Figure 4 refer to Figure 5, the display device 1 may include a first substrate 11 or a first base substrate, and a circuit element layer and a display element layer disposed on the first substrate 11. A semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers may be disposed on the first substrate 11, and may constitute a circuit element layer and a display element layer. The plurality of conductive layers may include a first gate conductive layer, a second gate conductive layer, a first data conductive layer, and a second data conductive layer disposed under the first planarization layer 19 to constitute a circuit element layer, and electrodes 21 and 22 and a contact electrode 26 disposed on the first planarization layer 19 to constitute a display element layer. The plurality of insulating layers may include a buffer layer 12, a first gate insulating layer 13, a first protective layer 15, a first interlayer insulating layer 17, a second interlayer insulating layer 18, a first planarization layer 19, a first insulating layer 51, a second insulating layer 52, a third insulating layer 53, and a fourth insulating layer 54.

[0087] Specifically, the first substrate 11 may be an insulating substrate. The first substrate 11 may be made of an insulating material such as glass, quartz or polymer resin. In addition, the first substrate 11 may be a rigid substrate, and may also be a flexible substrate that is bendable, foldable and rollable.

[0088] The light blocking layers BML1 and BML2 may be disposed on the first substrate 11. The first substrate 11 may include one surface on which the light blocking layers BML1 and BML2 are disposed and another surface opposite to one surface of the first substrate 11. The light blocking layers BML1 and BML2 may be directly disposed on one surface of the first substrate 11. The light blocking layers BML1 and BML2 may include a first light blocking layer BML1 and a second light blocking layer BML2. The first light blocking layer BML1 and the second light blocking layer BML2 may overlap at least the first active material layer DT_ACT of the driving transistor DT and the second active material layer ST_ACT of the switching transistor ST, respectively. The light blocking layers BML1 and BML2 may include a material that blocks light, thereby preventing light from being incident on the first active material layer DT_ACT and the second active material layer ST_ACT. As an example, the light blocking layers BML1 and BML2 may be made of an opaque metal material that blocks light transmission. However, the present disclosure is not limited thereto, and in some cases, the light blocking layers BML1 and BML2 may be omitted.

[0089] The buffer layer 12 may be disposed on the entire first substrate 11 on which the light blocking layers BML1 and BML2 are disposed. The buffer layer 12 may be formed on the first substrate 11 to protect the transistors DT and ST of the pixel PX from moisture that penetrates through the first substrate 11 (which is easily permeated by moisture). The buffer layer 12 may perform a surface planarization function. The buffer layer 12 may be provided as a plurality of inorganic layers alternately stacked. For example, the buffer layer 12 may be formed as a multilayer including a silicon oxide (SiO x), silicon nitride (SiN x ) and silicon oxynitride (SiON) are alternately stacked.

[0090] The semiconductor layer is disposed on the buffer layer 12. The semiconductor layer may include a first active material layer DT_ACT of the driving transistor DT and a second active material layer ST_ACT of the switching transistor ST. The first and second active material layers DT_ACT and ST_ACT may be disposed to partially overlap gate electrodes DT_G and ST_G of a first gate conductive layer to be described below.

[0091] In an embodiment, the semiconductor layer may include polycrystalline silicon, monocrystalline silicon, an oxide semiconductor, etc. Polycrystalline silicon may be formed by crystallizing amorphous silicon. When the semiconductor layer includes polycrystalline silicon, the first active material layer DT_ACT may include a first doped region DT_ACTa, a second doped region DT_ACTb, and a first channel region DT_ACTc. The first channel region DT_ACTc may be disposed between the first doped region DT_ACTa and the second doped region DT_ACTb. The second active material layer ST_ACT may include a third doped region ST_ACTa, a fourth doped region ST_ACTb, and a second channel region ST_ACTc. The second channel region ST_ACTc may be disposed between the third doped region ST_ACTa and the fourth doped region ST_ACTb. The first doped region DT_ACTa, the second doped region DT_ACTb, the third doped region ST_ACTa, and the fourth doped region ST_ACTb may be regions in which partial regions of the first active material layer DT_ACT and the second active material layer ST_ACT are doped with impurities.

[0092] In another embodiment, the first active material layer DT_ACT and the second active material layer ST_ACT may include an oxide semiconductor. In this case, each of the doped regions of the first active material layer DT_ACT and the second active material layer ST_ACT may be a conductive region. The oxide semiconductor may be an oxide semiconductor containing indium (In). In some embodiments, the oxide semiconductor may be indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), etc. However, the present disclosure is not limited thereto.

[0093] The first gate insulating layer 13 is disposed on the semiconductor layer and the buffer layer 12. The first gate insulating layer 13 may be disposed on the buffer layer 12 and the semiconductor layer. The first gate insulating layer 13 may be used as a gate insulating film of each of the driving transistor DT and the switching transistor ST. The first gate insulating layer 13 may be formed of a material such as silicon oxide (SiOx ), silicon nitride (SiN x ) or silicon oxynitride (SiON), or may be formed into a structure in which a plurality of inorganic layers are stacked.

[0094] The first gate conductive layer is disposed on the first gate insulating layer 13. The first gate conductive layer may include a first gate electrode DT_G of the driving transistor DT and a second gate electrode ST_G of the switching transistor ST. The first gate electrode DT_G may be disposed to overlap with the first channel region DT_ACTc of the first active material layer DT_ACT in the thickness direction thereof, and the second gate electrode ST_G may be disposed to overlap with the second channel region ST_ACTc of the second active material layer ST_ACT in the thickness direction thereof.

[0095] The first gate conductive layer may be formed as a single layer or multiple layers made of at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, the present disclosure is not limited thereto.

[0096] The first protective layer 15 is disposed on the first gate conductive layer. The first protective layer 15 may be disposed to cover the first gate conductive layer and may perform a function of protecting the first gate conductive layer. The first protective layer 15 may be formed of a material such as silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiON), or may be formed into a structure in which a plurality of inorganic layers are stacked.

[0097] The second gate conductive layer is disposed on the first protective layer 15. The second gate conductive layer may include a first capacitor electrode CE1 of a storage capacitor, which is disposed so that at least a portion of its area overlaps with the first gate electrode DT_G in its thickness direction. The first capacitor electrode CE1 may overlap with the first gate electrode DT_G in the thickness direction, and the first protective layer 15 is interposed between the first capacitor electrode CE1 and the first gate electrode DT_G, and a storage capacitor may be formed by the first capacitor electrode CE1 and the first gate electrode DT_G together with the first protective layer 15 interposed therebetween. The second gate conductive layer may be formed as a single layer or multiple layers made of at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof. However, the present disclosure is not limited thereto.

[0098] The first interlayer insulating layer 17 is disposed on the second gate conductive layer. The first interlayer insulating layer 17 may be used as an insulating film between the second gate conductive layer and other layers disposed thereon. The first interlayer insulating layer 17 may be formed of a material such as silicon oxide (SiOx ), silicon nitride (SiN x ) or silicon oxynitride (SiON), or may be formed into a structure in which a plurality of inorganic layers are stacked.

[0099] The first data conductive layer is disposed on the first interlayer insulating layer 17. The first data conductive layer may include first and second source / drain electrodes DT_SD1 and DT_SD2 of the driving transistor DT and first and second source / drain electrodes ST_SD1 and ST_SD2 of the switching transistor ST.

[0100] The first source / drain electrode DT_SD1 and the second source / drain electrode DT_SD2 of the driving transistor DT may respectively contact the first doped region DT_ACTa and the second doped region DT_ACTb of the first active material layer DT_ACT through contact holes passing through the first interlayer insulating layer 17, the first protective layer 15, and the first gate insulating layer 13. The first source / drain electrode ST_SD1 and the second source / drain electrode ST_SD2 of the switching transistor ST may respectively contact the third doped region ST_ACTa and the fourth doped region ST_ACTb of the second active material layer ST_ACT through contact holes passing through the first interlayer insulating layer 17, the first protective layer 15, and the first gate insulating layer 13. In addition, the first source / drain electrode DT_SD1 of the driving transistor DT and the first source / drain electrode ST_SD1 of the switching transistor ST may respectively be electrically connected to the first light blocking layer BML1 and the second light blocking layer BML2 through other contact holes. Meanwhile, in the first source / drain electrodes DT_SD1 and ST_SD1 and the second source / drain electrodes DT_SD2 and ST_SD2 of the driving transistor DT and the switching transistor ST, any one electrode is a source electrode, and the other electrode may be a drain electrode. However, the present disclosure is not limited thereto, and in the first source / drain electrodes DT_SD1 and ST_SD1 and the second source / drain electrodes DT_SD2 and ST_SD2, any one electrode is a drain electrode, and the other electrode may be a source electrode.

[0101] The first data conductive layer may be formed as a single layer or multiple layers made of at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. However, the present disclosure is not limited thereto.

[0102] The second interlayer insulating layer 18 may be disposed on the first data conductive layer. The second interlayer insulating layer 18 may cover the first data conductive layer, may be disposed on the entire first interlayer insulating layer 17, and may perform a function of protecting the first data conductive layer. The second interlayer insulating layer 18 may be formed of a material such as silicon oxide (SiO x ), silicon nitride (SiNx ) or silicon oxynitride (SiON), or may be formed into a structure in which a plurality of inorganic layers are stacked.

[0103] The second data conductive layer is disposed on the second interlayer insulating layer 18. The second data conductive layer may include a first voltage line VL1, a second voltage line VL2, and a first conductive pattern CDP. A high potential voltage (or a first power voltage) supplied to the driving transistor DT may be applied to the first voltage line VL1, and a low potential voltage (or a second power voltage) supplied to the second electrode 22 may be applied to the second voltage line VL2. In the manufacturing process of the display device 1, an arrangement signal required for arranging the light emitting element 30 may be applied to the second voltage line VL2.

[0104] The first conductive pattern CDP may be electrically connected to the first source / drain electrode DT_SD1 of the driving transistor DT through a contact hole formed in the second interlayer insulating layer 18. The first conductive pattern CDP may also be in contact with a first electrode 21 to be described below, and the driving transistor DT may transmit a first power voltage applied from a first voltage line VL1 to the first electrode 21 through the first conductive pattern CDP. Meanwhile, the second data conductive layer is illustrated in the drawings as including one second voltage line VL2 and one first voltage line VL1, but the present disclosure is not limited thereto. The second data conductive layer may include more first voltage lines VL1 and more second voltage lines VL2.

[0105] The second data conductive layer may be formed as a single layer or multiple layers made of at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. However, the present disclosure is not limited thereto.

[0106] The first planarization layer 19 is disposed on the second data conductive layer. The first planarization layer 19 may include an organic insulating material (eg, an organic material such as polyimide (PI)), and may perform a surface planarization function.

[0107] Inner banks 41 and 42, electrodes 21 and 22, outer banks 45, contact electrodes 26, and light emitting elements 30 are disposed on the first planarization layer 19. In addition, insulating layers 51, 52, 53, and 54 may be further disposed on the first planarization layer 19.

[0108] The inner banks 41 and 42 may be disposed directly on the first planarization layer 19. The inner banks 41 and 42 may include a first inner bank 41 and a second inner bank 42 disposed adjacent to the center of each pixel PX.

[0109] The first inner bank 41 and the second inner bank 42 may be disposed to be separated from each other and face each other in the first direction DR1. The inner banks 41 and 42 may be disposed to be separated from each other and face each other so that a region in which the light emitting element 30 is disposed may be formed therebetween. In addition, the first inner bank 41 and the second inner bank 42 may extend in the second direction DR2, and may be disposed to be spaced apart from each other at a boundary between a plurality of pixels PX so as not to extend to another adjacent pixel PX in the second direction DR2. Therefore, the first inner bank 41 and the second inner bank 42 may be disposed for each pixel PX to form a pattern over the entire display device 1. Although in Figure 4 Only two first inner banks 41 and one second inner bank 42 are shown in FIG. 4 , but the present disclosure is not limited thereto. More inner banks 41 and 42 may be further provided according to the number of electrodes 21 and 22 to be described below.

[0110] The first inner bank 41 and the second inner bank 42 may have a structure in which at least a portion thereof protrudes from the upper surface of the first planarization layer 19. The protruding portions of the inner banks 41 and 42 may have inclined side surfaces, and light emitted from the light emitting element 30 may travel toward the inclined side surfaces. As will be described below, the electrodes 21 and 22 disposed on the inner banks 41 and 42 may include a material having a high reflectivity, and the light emitted from the light emitting element 30 may be reflected from the electrodes 21 and 22 disposed on the side surfaces of the inner banks 41 and 42, and may be emitted in an upward direction of the first planarization layer 19. That is, the first inner bank 41 and the second inner bank 42 may provide a region in which the light emitting element 30 is disposed, and at the same time may function as a reflective partition wall that reflects light emitted from the light emitting element 30 upward. In an embodiment, the inner banks 41 and 42 may include an organic insulating material such as PI, but the present disclosure is not limited thereto.

[0111] A plurality of electrodes 21 and 22 are disposed on the inner banks 41 and 42 and the first planarization layer 19. The plurality of electrodes 21 and 22 may be electrically connected to the light emitting element 30, and a specific voltage may be applied thereto so that the light emitting element 30 emits light having a specific wavelength. In addition, at least a portion of each of the electrodes 21 and 22 may be used to form an electric field in the pixel PX so as to arrange the light emitting element 30.

[0112] The plurality of electrodes 21 and 22 may include a first electrode 21 disposed on the first inner bank 41 and a second electrode 22 disposed on the second inner bank 42 .

[0113] The first electrode 21 and the second electrode 22 may respectively include electrode rods 21S and 22S arranged to extend in the first direction DR1, and respectively include at least one electrode branch 21B and at least one electrode branch 22B branching from the electrode rods 21S and 22S and extending in the second direction DR2, wherein the second direction DR2 is a direction intersecting the first direction DR1.

[0114] The first electrode 21 may include a first electrode rod 21S disposed to extend in the first direction DR1 and at least one first electrode branch 21B branched from the first electrode rod 21S and extending in the second direction DR2 .

[0115] Both ends of the first electrode rod 21S may be disposed between the plurality of pixels PX to be spaced apart from each other, and the first electrode rod 21S may be disposed substantially collinearly with the first electrode rod 21S of adjacent pixels in the same row (e.g., in the first direction DR1). Since both ends of the first electrode rod 21S disposed in the plurality of pixels PX may be spaced apart from each other, different electrical signals may be applied to the first electrode branches 21B, and each of the first electrode branches 21B may be driven individually. The first electrode 21 may contact the first conductive pattern CDP through the first contact hole CT1 passing through the first planarization layer 19, and thus may be electrically connected to the first source / drain electrode DT_SD1 of the driving transistor DT.

[0116] The first electrode branches 21B may be branched from at least a portion of the first electrode rods 21S and may be disposed to extend in the second direction DR2 and may be disposed to be separated from the second electrode rods 22S disposed to face the first electrode rods 21S.

[0117] The second electrode 22 may include second electrode rods 22S extending in the first direction DR1 and facing the first electrode rods 21S, and second electrode branches 22B branched from the second electrode rods 22S and extending in the second direction DR2 .

[0118] The second electrode rod 22S may extend in the first direction DR1 and may be arranged to extend beyond the boundary with another adjacent pixel PX. The second electrode rod 22S crossing a plurality of pixels PX may be connected to the outer peripheral portion of the display area DA or a portion extending from the non-display area NDA in one direction. The second electrode 22 may contact the second voltage line VL2 through the second contact hole CT2 passing through the first planarization layer 19. As shown in the figure, the second electrodes 22 of adjacent pixels PX in the first direction DR1 are connected into one second electrode rod 22S and are electrically connected to the second voltage line VL2 through the second contact hole CT2. However, the present disclosure is not limited thereto, and in some cases, the second contact hole CT2 may also be formed at each pixel PX.

[0119] The second electrode branch 22B may be spaced apart from the first electrode branch 21B and face the first electrode branch 21B, and may be disposed in a state separated from the first electrode rod 21S. The second electrode branch 22B may be connected to the second electrode rod 22S, and one end thereof in the extension direction may be disposed in the pixel PX to be spaced apart from the first electrode rod 21S.

[0120] Meanwhile, although it is shown in the figure that two first electrode branches 21B and one second electrode branch 22B are provided in each pixel PX, the present disclosure is not limited thereto. In some embodiments, more first electrode branches 21B and more second electrode branches 22B may be provided in each pixel PX. In addition, the first electrode 21 and the second electrode 22 provided in each pixel PX may not necessarily have a shape extending in one direction, and may be provided in various structures.

[0121] The first electrode 21 and the second electrode 22 may be disposed on the first inner bank 41 and the second inner bank 42, respectively, and may be spaced apart from each other and face each other. In the first electrode 21 and the second electrode 22, the electrode branches 21B and 22B may be disposed on the first inner bank 41 and the second inner bank 42, respectively, and at least a partial area thereof may be directly disposed on the first planarization layer 19. At least one end portion of the plurality of light emitting elements 30 disposed between the first inner bank 41 and the second inner bank 42 may be electrically connected to the first electrode 21 and the second electrode 22.

[0122] Each of the electrodes 21 and 22 may include a transparent conductive material. For example, each of the electrodes 21 and 22 may include a material such as ITO, IZO, or indium tin zinc oxide (ITZO), but the present disclosure is not limited thereto. In some embodiments, each of the electrodes 21 and 22 may include a conductive material having a high reflectivity. For example, each of the electrodes 21 and 22 may include a metal having a high reflectivity, such as silver (Ag), copper (Cu), or aluminum (Al). In this case, light incident on each of the electrodes 21 and 22 may be reflected and emitted in the upward direction of each pixel PX.

[0123] In addition, each of the electrodes 21 and 22 may have a structure in which each of a transparent conductive material and a metal layer having high reflectivity is stacked as one or more layers, or may be formed as one layer including a transparent conductive material and a metal layer having high reflectivity. In an embodiment, each of the electrodes 21 and 22 may have a stacked structure such as ITO / Ag / ITO / IZO, or may include an alloy including aluminum (Al), nickel (Ni), lanthanum (La), etc. However, the present disclosure is not limited thereto.

[0124] The plurality of electrodes 21 and 22 may be electrically connected to the light emitting element 30, and a specific voltage may be applied thereto so that the light emitting element 30 emits light. For example, the plurality of electrodes 21 and 22 may be electrically connected to the light emitting element 30 through the contact electrode 26 to be described below, and an electrical signal applied to the electrodes 21 and 22 may be transmitted to the light emitting element 30 through the contact electrode 26.

[0125] In an embodiment, the first electrode 21 may be a separate pixel electrode for each pixel PX, and the second electrode 22 may be a common electrode commonly connected to each pixel PX. Any one of the first electrode 21 and the second electrode 22 may be an anode of the light emitting element 30, and the other may be a cathode of the light emitting element 30. However, the present disclosure is not limited thereto, and the opposite case may be possible.

[0126] In addition, each of the electrodes 21 and 22 can be used to form an electric field in the pixel PX to arrange the light emitting element 30. The light emitting element 30 can be disposed between the first electrode 21 and the second electrode 22 through a process of forming an electric field between the first electrode 21 and the second electrode 22 by applying an arrangement signal to the first electrode 21 and the second electrode 22. The light emitting element 30 can be sprayed on the first electrode 21 and the second electrode 22 by an inkjet printing process in a state of being dispersed in ink, and the light emitting element 30 can be arranged between the first electrode 21 and the second electrode 22 by applying an arrangement signal between the first electrode 21 and the second electrode 22 to apply a dielectrophoretic force to the light emitting element 30.

[0127] The first insulating layer 51 is disposed on the first planarization layer 19, the first electrode 21, and the second electrode 22. The first insulating layer 51 is disposed to partially cover the first electrode 21 and the second electrode 22. The first insulating layer 51 is disposed to cover most of the upper surfaces of the first electrode 21 and the second electrode 22, and may expose portions of the first electrode 21 and the second electrode 22. The first insulating layer 51 may be disposed to expose portions of the upper surfaces of the first electrode 21 and the second electrode 22, for example, portions of the upper surfaces of the first electrode branches 21B disposed on the first inner bank 41 and portions of the upper surfaces of the second electrode branches 22B disposed on the second inner bank 42. The first insulating layer 51 may be formed substantially on the entire first planarization layer 19, and may include openings that partially expose the first electrode 21 and the second electrode 22.

[0128] In an embodiment, a portion of the upper surface of the first insulating layer 51 may be recessed to form a step portion between the first electrode 21 and the second electrode 22. In some embodiments, the first insulating layer 51 includes an inorganic insulating material. A portion of the upper surface of the first insulating layer 51, which is provided to cover the first electrode 21 and the second electrode 22, may be recessed due to a step portion of a member provided thereunder. An empty space may be formed between the light emitting element 30 (which is provided on the first insulating layer 51 between the first electrode 21 and the second electrode 22) and the recessed upper surface of the first insulating layer 51. The light emitting element 30 may be provided to be partially separated from the upper surface of the first insulating layer 51, and the material constituting the second insulating layer 52 to be described below may fill the space. However, the present disclosure is not limited thereto. The first insulating layer 51 may have a flat upper surface so that the light emitting element 30 is provided thereon.

[0129] The first insulating layer 51 can protect the first electrode 21 and the second electrode 22, and can insulate the first electrode 21 and the second electrode 22 from each other. In addition, the first insulating layer 51 can prevent the light emitting element 30 disposed on the first insulating layer 51 from being damaged due to direct contact with other components. However, the shape and structure of the first insulating layer 51 are not limited thereto.

[0130] The outer bank 45 may be disposed on the first insulating layer 51. In some embodiments, the outer bank 45 may be disposed on the first insulating layer 51 at a boundary between the pixels PX by surrounding an area in which the inner banks 41 and 42 and the electrodes 21 and 22 are disposed and an area in which the light emitting element 30 is disposed. The outer bank 45 may be disposed in the non-emission area NEA. The outer bank 45 may be disposed to have a shape extending in the first direction DR1 and the second direction DR2 and to form a grid pattern in the entire surface of the display area DA.

[0131] According to one embodiment, the height of the outer bank 45 may be greater than the height of the inner bank 41 and 42. Unlike the inner bank 41 and 42, the outer bank 45 may divide adjacent pixels PX, and at the same time, in the manufacturing process of the display device 1, in the inkjet printing process of arranging the light-emitting element 30, the function of preventing the ink from overflowing to the adjacent pixels PX may be performed. The outer bank 45 may separate the ink in which the different light-emitting elements 30 are dispersed for different pixels PX so as not to mix with each other. Similar to the inner bank 41 and 42, the outer bank 45 may include PI, but the present disclosure is not limited thereto.

[0132] The light emitting element 30 may be disposed between the electrodes 21 and 22. For example, the light emitting element 30 may be disposed between the electrode branches 21B and 22B. A plurality of light emitting elements 30 may be disposed to be separated from each other and may be arranged substantially parallel to each other. The spacing interval between the light emitting elements 30 is not particularly limited. In some cases, a plurality of light emitting elements 30 may be disposed adjacent to each other to form a group, and a plurality of other light emitting elements 30 may form a group in a state where they are spaced apart from each other by a specific spacing, and may be disposed at an uneven density. In addition, in an embodiment, the light emitting element 30 may have a shape extending in one direction, and the extension direction of each of the electrodes 21 and 22 may be substantially perpendicular to the extension direction of the light emitting element 30. However, the present disclosure is not limited thereto, and the light emitting element 30 may be disposed to be inclined to, rather than perpendicular to, the extension direction of each of the electrodes 21 and 22.

[0133] The light emitting element 30 according to one embodiment may include an active layer including different materials emitting light having different wavelengths to the outside. The display device 1 may include the light emitting element 30 emitting light having different wavelengths.

[0134] The light emitting element 30 may be disposed on the first insulating layer 51 between the inner banks 41 and 42 or between the electrodes 21 and 22. For example, the light emitting element 30 may be disposed on a portion of the first insulating layer 51 disposed between the inner banks 41 and 42. Meanwhile, the light emitting element 30 may be disposed such that a partial region thereof overlaps with each of the electrodes 21 and 22 in a thickness direction thereof. One end portion of the light emitting element 30 may overlap with the first electrode 21 in a thickness direction to be disposed on the first electrode 21, and the other end portion of the light emitting element 30 may overlap with the second electrode 22 in a thickness direction to be disposed on the second electrode 22. However, the present disclosure is not limited thereto, and although not shown in the drawings, at least some of the light emitting elements 30 disposed in each pixel PX may be disposed in a region other than a region formed between the inner banks 41 and 42, for example, a region other than a region between the electrode branches 21B and 22B or a region between the inner banks 41 and 42 and the outer bank 45.

[0135] One end portion of the light emitting element 30 may be in contact with the first contact electrode 26a, and the other end portion thereof may be in contact with the second contact electrode 26b. According to one embodiment, since an insulating film is not formed on the surface of the end portion of the light emitting element 30 in the direction in which it extends and a portion of its semiconductor layer is exposed, the exposed semiconductor layer may be in contact with the first contact electrode 26a and the second contact electrode 26b to be described below. However, the present disclosure is not limited thereto. In some cases, in the light emitting element 30, at least a portion of the insulating film may be removed, and the insulating film may be removed to partially expose the side surfaces of the two end portions of the semiconductor layer.

[0136] The second insulating layer 52 may be disposed on a portion of the light emitting element 30 disposed between the first electrode 21 and the second electrode 22. The second insulating layer 52 may be disposed to partially surround the outer surface of the light emitting element 30. In a plan view, the portion of the second insulating layer 52 disposed on the light emitting element 30 may have a shape extending in the second direction DR2 between the first electrode 21 and the second electrode 22. As an example, the second insulating layer 52 may form a stripe or island pattern in each pixel PX.

[0137] The second insulating layer 52 may be disposed on the light emitting element 30 and may expose one end portion and the other end portion of the light emitting element 30. The exposed end portion of the light emitting element 30 may be in contact with the contact electrode 26 to be described below. The shape of the second insulating layer 52 may be formed by a patterning process using a material constituting the second insulating layer 52 using a typical mask process. The mask for forming the second insulating layer 52 may have a width smaller than the length of the light emitting element 30, and the material constituting the second insulating layer 52 may be patterned to expose both end portions of the light emitting element 30. However, the present disclosure is not limited thereto.

[0138] The plurality of contact electrodes 26 are disposed on the first electrode 21, the second electrode 22, and the second insulating layer 52. In addition, the third insulating layer 53 may be disposed on any one of the contact electrodes 26.

[0139] The plurality of contact electrodes 26 may have a shape extending in one direction. The plurality of contact electrodes 26 may contact the light emitting element 30 and the electrodes 21 and 22 , and the light emitting element 30 may receive electrical signals from the first electrode 21 and the second electrode 22 through the contact electrodes 26 .

[0140] The contact electrode 26 may include a first contact electrode 26a and a second contact electrode 26b. The first contact electrode 26a and the second contact electrode 26b may be disposed on the first electrode 21 and the second electrode 22, respectively. Each of the first contact electrode 26a and the second contact electrode 26b may have a shape extending in the second direction DR2. The first contact electrode 26a and the second contact electrode 26b may be spaced apart from each other and face each other in the first direction DR1, and may form a stripe pattern in the emission area EMA of each pixel PX.

[0141] Portions of the upper surfaces of the first and second electrodes 21 and 22 may be exposed, and the first and second contact electrodes 26a and 26b may be in contact with the exposed upper surfaces of the first and second electrodes 21 and 22. For example, the first contact electrode 26a may be in contact with a portion of the first electrode 21 positioned on the first inner bank 41, and the second contact electrode 26b may be in contact with a portion of the second electrode 22 positioned on the second inner bank 42. However, the present disclosure is not limited thereto, and in some cases, the first and second contact electrodes 26a and 26b may be formed to have a smaller width than the first and second electrodes 21 and 22, and thus may be disposed to cover only the exposed portion of the upper surface.

[0142] According to one embodiment, the semiconductor layer may be exposed at the surface of both end portions of the light emitting element 30 in the extension direction, and the first contact electrode 26a and the second contact electrode 26b may be in contact with the light emitting element 30 at the surface of the end portion where the semiconductor layer is exposed. However, the present disclosure is not limited thereto. In some cases, the semiconductor layer may be exposed at the side surface of both end portions of the light emitting element 30, and each of the contact electrodes 26 may be in contact with the exposed semiconductor layer. One end portion of the light emitting element 30 may be electrically connected to the first electrode 21 through the first contact electrode 26a, and the other end portion of the light emitting element 30 may be electrically connected to the second electrode 22 through the second contact electrode 26b.

[0143] Although two first contact electrodes 26a and one second contact electrode 26b are provided in one pixel PX, the present disclosure is not limited thereto. The number of first contact electrodes 26a and second contact electrodes 26b may vary according to the number of first electrode branches 21B and second electrode branches 22B provided in each pixel PX.

[0144] The contact electrode 26 may include a conductive material. For example, the contact electrode 26 may include ITO, IZO, ITZO, aluminum (Al), etc. For example, the contact electrode 26 may include a transparent conductive material, and the light emitted from the light emitting element 30 may pass through the contact electrode 26 to travel toward the electrodes 21 and 22. Each of the electrodes 21 and 22 may include a material having a high reflectivity, and the electrodes 21 and 22 disposed on the inclined side surfaces of the inner bank portions 41 and 42 may reflect the incident light in the upward direction of the first substrate 11. However, the present disclosure is not limited thereto.

[0145] The third insulating layer 53 is disposed on the first contact electrode 26a. The third insulating layer 53 can electrically insulate the first contact electrode 26a and the second contact electrode 26b from each other. The third insulating layer 53 may be disposed to cover the first contact electrode 26a, and may not be disposed on the other end portion of the light emitting element 30, so that the light emitting element 30 can contact the second contact electrode 26b. The third insulating layer 53 may partially contact the first contact electrode 26a and the second insulating layer 52 on the upper surface of the second insulating layer 52. The side surface of the third insulating layer 53 in the direction along which the second electrode 22 is disposed may be aligned with one side surface of the second insulating layer 52. In addition, the third insulating layer 53 may also be disposed in the non-emission area NEA, for example, in the non-emission area NEA on the first insulating layer 51 disposed on the first planarization layer 19. However, the present disclosure is not limited thereto.

[0146] The fourth insulating layer 54 may be disposed on the entire first substrate 11. The fourth insulating layer 54 may serve to protect members disposed on the first substrate 11 from external environments.

[0147] Each of the first insulating layer 51, the second insulating layer 52, the third insulating layer 53, and the fourth insulating layer 54 may include an inorganic insulating material or an organic insulating material. In an embodiment, the first insulating layer 51, the second insulating layer 52, the third insulating layer 53, and the fourth insulating layer 54 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ) or aluminum nitride (AlN). Optionally, the first insulating layer 51, the second insulating layer 52, the third insulating layer 53 and the fourth insulating layer 54 may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, cardo resin, siloxane resin, silsesquioxane resin, polymethyl methacrylate, polycarbonate or polymethyl methacrylate-polycarbonate synthetic resin. However, the present disclosure is not limited thereto.

[0148] Figure 6 is a plan view of a display device according to one embodiment, viewed from below.

[0149] refer to Figure 3 and Figure 6 The data line DL can be connected to the substrate connection electrode CNTb. The data line DL can be connected to the substrate connection electrode CNTa (see Figure 7 ), etch stop ES (see Figure 7 ) and the substrate connection electrode CNTb is connected to the first pad PAD1 (see Figure 6 and Figure 7 ).

[0150] The connection line CL may be disposed on the other surface of the first substrate 11. One end portion of the connection line CL may constitute a first pad PAD1, and the other end portion of the connection line CL may constitute a second pad PAD2. Figure 6 It has been described that one end portion of the connection line CL can constitute the first pad PAD1, and the other end portion of the connection line CL can constitute the second pad PAD2, but it can be understood that the connection line CL is connected to each of the first pad PAD1 and the second pad PAD2. The second pad PAD2 can correspond to the connection line CL one by one. The second pad PAD2 can be set as a plurality of second pads PAD2. The plurality of second pads PAD2 can be arranged in the first direction DR1. Some of the connection lines CL can be connected to the first pad PAD1, extend downward in the second direction DR2, and include at least one bent portion.

[0151] For example, each of the plurality of connection lines CL may include an extension portion extending from one end portion of the connection line CL in the second direction DR2, and a fan-out line disposed between the bent portion and the second pad PAD2. Adjacent connection lines CL may be close to each other on the fan-out line. One end portion of the fan-out line may be connected to the extension portion of the connection line CL, and the other end portion of the fan-out line may be connected to the second pad PAD2.

[0152] The chip on film COF may be disposed on an adjacent second pad PAD2. The chip on film COF may be attached to an adjacent second pad PAD2. The chip on film COF may be disposed as a plurality of chip on film COFs. A plurality of chip on film COFs may be arranged to be separated from each other in the first direction DR1. Adjacent second pads PAD2 may form a pad group. The pad group may be disposed as a plurality of pad groups. A plurality of pad groups may be arranged to be separated from each other in the first direction DR1. Each pad group may be connected to a different chip on film COF. A driver chip IC may be mounted on the chip on film COF. The chip on film COF may be disposed in the display area DA of the display device 1. The chip on film COF may be disposed on another surface of the first substrate 11 of the display device 1, and may be disposed in the display area DA, thereby preventing a dead zone from being generated due to the arrangement of the chip on film COF.

[0153] Figure 7 Shown along Figure 3 and Figure 6 A cross-sectional view taken along lines II-II' and III-III'. Figure 7 In the description of Figure 5 Redundant descriptions of identical components.

[0154] refer to Figure 5 and Figure 7 , the etch stopper ES may be disposed on one surface of the first substrate 11. The etch stopper ES may be disposed coplanar with the light blocking layers BML1 and BML2. The etch stopper ES may be directly disposed on one surface of the first substrate 11. The etch stopper ES may include the same material as the light blocking layers BML1 and BML2. The etch stopper ES may be disposed to be separated from the light blocking layers BML1 and BML2. The etch stopper ES may cover the substrate through hole TH. The width of the etch stopper ES may be greater than the first width W1 of the substrate through hole TH (see Figure 8 ).

[0155] The data line DL can be positioned with reference Figure 5 The data line DL may be disposed coplanar with the first and second source / drain electrodes DT_SD1 and DT_SD2 disposed in the first data conductive layer, and may include the same material as the first and second source / drain electrodes DT_SD1 and DT_SD2.

[0156] The data line DL may be connected to the etch stopper ES through a data connection electrode CNTa passing through the first interlayer insulating layer 17, the first protective layer 15, and the first gate insulating layer 13. The data connection electrode CNTa may include the same material as the data line DL. The data line DL and the etch stopper ES may be electrically connected through the data connection electrode CNTa.

[0157] The first substrate 11 may include a through substrate hole TH. The through substrate hole TH may completely penetrate the first substrate 11 in a thickness direction from one surface to the other surface of the first substrate 11. The through substrate hole TH may be provided in the emission area EMA.

[0158] The substrate connection electrode CNTb may fill the substrate through hole TH. The substrate connection electrode CNTb may completely fill the substrate through hole TH. The substrate connection electrode CNTb may contact the side surface (or inner surface) of the first substrate 11 through which the substrate through hole TH is defined. The substrate connection electrode CNTb may include a conductive material. For example, the substrate connection electrode CNTb may include at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof. The substrate connection electrode CNTb may be formed as a single layer made of the materials described above. In some embodiments, the substrate connection electrode CNTb may be formed as a multilayer made of the materials described above. The substrate connection electrode CNTb may be connected to the etching stopper ES. The substrate connection electrode CNTb may be directly connected to the etching stopper ES. The substrate connection electrode CNTb may be electrically connected to the etching stopper ES.

[0159] The connection line CL may be disposed on the other surface (or rear surface) of the first substrate 11. The connection line CL may be directly disposed on the other surface of the first substrate 11. One end portion of the connection line CL may be connected to the first pad PAD1, and the other end portion of the connection line CL may be connected to the second pad PAD2. The first pad PAD1 may overlap with the substrate connection electrode CNTb in its thickness direction, and may be in direct contact with the substrate connection electrode CNTb. The first pad PAD1 may be electrically connected to the substrate connection electrode CNTb. The connection line CL, the first pad PAD1, and the second pad PAD2 may be disposed to be coplanar with each other, and may include the same material. However, the present disclosure is not limited thereto, and the connection line CL, the first pad PAD1, and the second pad PAD2 may include different materials.

[0160] The connection line CL may include a conductive material. For example, the connection line CL may include at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The connection line CL may be formed as a single layer made of the materials described above. In some embodiments, the connection line CL may be formed as a multilayer made of the materials described above.

[0161] The chip on film COF may be attached to the second pad PAD2. The chip on film COF may include a lead LE. An anisotropic conductive film ACF may be disposed between the lead LE and the second pad PAD2. The lead LE and the second pad PAD2 may be electrically connected to each other through the anisotropic conductive film ACF. A driver chip IC may be mounted on the chip on film COF. The driver chip IC may be mounted on another surface opposite to a surface of the chip on film COF on which the lead LE is disposed, but the present disclosure is not limited thereto. The lead LE and the driver chip IC may be disposed on the same surface of the chip on film COF.

[0162] The driving chip IC may be used to apply a data signal to each data line DL. The data signal provided from the driving chip IC may be transmitted to the data line DL through the second pad PAD2, the connection line CL, the first pad PAD1, the substrate connection electrode CNTb, the etch stopper ES, and the data connection electrode CNTa.

[0163] In the following, reference will be made to Figure 8 The shape of the through-substrate hole TH is described.

[0164] Figure 8 yes Figure 7 An enlarged cross-sectional view of area A.

[0165] refer to Figure 8 , the first substrate 11 may include a reference Figure 7 The first substrate 11 may further include a side surface 11 a through which a through substrate hole TH is defined.

[0166] The substrate through hole TH may be surrounded by an extension of one surface of the first substrate 11, an extension of the other surface 11b of the first substrate 11, and a side surface 11a of the first substrate 11. The extension of one surface of the first substrate 11 may intersect each of one surfaces of the adjacent first substrates 11. The extension of the other surface of the first substrate 11 may intersect each of the other surfaces of the adjacent first substrates 11. Each of the side surfaces 11a of the first substrate 11 may connect a point where the extension of one surface of the first substrate 11 and one surface of the first substrate 11 intersect each other and a point where the extension of the other surface 11b of the first substrate 11 and the other surface 11b of the first substrate 11 intersect each other.

[0167] The width of the through substrate hole TH may gradually decrease in a direction from the extension portion of the other surface 11b of the first substrate 11 toward the extension portion of the one surface of the first substrate 11. The width of the through substrate hole TH may include a first width W1 equal to the length of the extension portion of the one surface of the first substrate 11 and a second width W2 equal to the length of the extension portion of the other surface 11b of the first substrate 11. In one embodiment, the first width W1 may be smaller than the second width W2.

[0168] The side surface 11 a of the first substrate 11 constituting the through-substrate hole TH may form a curved surface CR.

[0169] Each of the curved surfaces CR formed by the side surfaces 11 a of the first substrate 11 may have a cross-sectional shape convex toward the through-substrate hole TH.

[0170] In addition, the slope of the side surface 11a of the first substrate 11 can gradually decrease in a direction from a point where an extension portion of one surface of the first substrate 11 and one surface of the first substrate 11 intersect each other toward a point where an extension portion of the other surface 11b of the first substrate 11 and the other surface 11b of the first substrate 11 intersect each other.

[0171] The through substrate holes TH according to one embodiment may be formed by laser irradiation and wet etching.

[0172] For example, laser light may be irradiated onto a region where the substrate through hole TH is to be formed. The laser light may be a femtosecond laser. In the present specification, a femtosecond laser light may refer to a laser light having a pulse width of 200 femtoseconds or more and 500 femtoseconds or less. However, the present disclosure is not limited thereto, and the femtosecond laser light may be light having a short wavelength from a near infrared (IR) laser light to an ultraviolet (UV) laser light, or may be light having multiple wavelengths (including light having various wavelengths).

[0173] The laser may be irradiated from the other surface 11b of the first substrate 11 to one surface thereof contacting the etching stopper ES. The focus of the laser may be modified variously. In one embodiment, the laser may be focused on one surface of the first substrate 11, but the present disclosure is not limited thereto.

[0174] When laser light is irradiated onto the region where the substrate through hole TH is to be formed, structural deformation may occur in the corresponding region. For example, silicon (Si)-oxygen (O) bonds of the exemplary glass constituting the first substrate 11 may be broken in the corresponding region. Therefore, the etching selectivity of the etching solution to the corresponding region may be greater than the etching selectivity of the etching solution to the region on which the laser light is not irradiated.

[0175] After irradiating the laser, the entire surface of the first substrate 11 is etched. For etching, wet etching can be applied. In the etching operation, as an etching solution, an alkaline solution such as potassium hydroxide (KOH) or sodium hydroxide (NaOH) or an acidic solution such as hydrofluoric acid (HF) can be used. Wet etching can be performed over the entire surface of the first substrate 11.

[0176] As described above, since the etching selectivity of the etching solution to the region on which the laser is irradiated is higher than the etching selectivity of the etching solution to the region on which the laser is not irradiated, as a result of wet etching, the substrate through hole TH can be formed in the region on which the laser is irradiated.

[0177] In the etching operation, the etching selectivity of the etching solution to the first substrate 11 may be much higher than the etching selectivity of the etching solution to the etching stopper ES. Therefore, even when the etching solution contacts the etching stopper ES in the etching operation, one surface ESa of the etching stopper ES may not be substantially etched.

[0178] According to one embodiment, when forming the through substrate hole TH, laser irradiation and etching are performed together, thereby ensuring processing quality, processing speed, and a high aspect ratio (ratio of thickness to width of the through substrate hole TH) of the through substrate hole TH.

[0179] In addition, the width of the etch stopper ES is formed to be larger than the first width W1 of the substrate through hole TH (see Figure 8 ), thereby preventing the etching solution from diffusing into one surface of the first substrate 11 when the through substrate hole TH is formed. Therefore, it is possible to prevent the electrode on the first substrate 11 from being corroded and / or etched due to the etching solution.

[0180] Furthermore, the etch stopper ES is formed simultaneously with the formation of the light blocking layers BML1 and BML2 , thereby simplifying the manufacturing process without adding a separate member and / or component.

[0181] In addition, as described above, since the substrate connection electrode CNTb is disposed in the display area DA, the chip-on-film COF connected to the substrate connection electrode CNTb may be formed on the other surface 11b of the first substrate 11 of the display device 1 and may be disposed in the display area DA. Therefore, the dead zone may be reduced by the arrangement of the chip-on-film COF and the fan-out line.

[0182] Hereinafter, a method of manufacturing the display device 1 according to one embodiment will be described.

[0183] In the following embodiments, the same components as those of the above-described embodiments are denoted by the same reference numerals, and description thereof will be omitted or simplified.

[0184] Figures 9 to 14 is a cross-sectional view illustrating a process operation of a method of manufacturing a display device according to an embodiment.

[0185] First, let’s refer to Fig. 9 , Figure 5 and Figure 7 The above reference is formed on the first substrate 11_1a Figure 5 and Figure 7 The upper structure on the first substrate 11 is described.

[0186] More specifically, light blocking layers BML1 and BML2 and an etch stopper ES may be formed on the first substrate 11_1a, and a reference etch stopper ES may be formed on the light blocking layers BML1 and BML2 and the etch stopper ES. Figure 5 and Figure 7 The buffer layer 12 and the upper structure of the buffer layer 12 described above. The etching stopper ES may be disposed coplanar with the light blocking layers BML1 and BML2. The etching stopper ES may be directly disposed on one surface of the first substrate 11_1a. The etching stopper ES may include the same material as the light blocking layers BML1 and BML2. The etching stopper ES may be disposed to be separated from the light blocking layers BML1 and BML2. The etching stopper ES may cover the substrate through hole TH. The width of the etching stopper ES may be greater than the first width W1 of the substrate through hole TH (see Figure 8 ).

[0187] according to Fig. 9 The thickness of the first substrate 11_1a may be greater than Figure 5 and Figure 7 Thereafter, the thickness of the entire first substrate 11_1a may be reduced by wet etching.

[0188] Then, refer to Fig.10 As described above, the laser LS may be irradiated onto the region where the substrate through hole TH is to be formed. The laser LS may be a femtosecond laser. In the present specification, the femtosecond laser may refer to a laser having a pulse width of 200 femtoseconds or more and 500 femtoseconds or less. However, the present disclosure is not limited thereto, and the femtosecond laser may be light having a short wavelength from an IR laser to a UV laser, or may be light having a multi-wavelength including light having various wavelengths.

[0189] The laser LS can be emitted from the other surface 11b (see Fig. 9 ) is irradiated to one surface thereof in contact with the etching stopper ES. The focus of the laser LS may be modified differently. In one embodiment, the laser LS may be focused on the first substrate 11_1a (see Fig. 9 ), but the present disclosure is not limited thereto.

[0190] When laser light LS is irradiated onto the region where the substrate through hole TH is to be formed, the first substrate 11_1b may be formed. Structural deformation may occur in the region of the first substrate 11_1b on which the laser light LS is irradiated. For example, Si-O bonds of the exemplary glass constituting the first substrate 11_1b may be broken in the corresponding region. Therefore, the etching selectivity of the etching solution to the corresponding region may be higher than the etching selectivity of the etching solution to the region on which the laser light LS is not irradiated.

[0191] After irradiating the laser LS, the entire surface of the first substrate 11_1b is etched. For etching, wet etching can be applied. In the etching operation, as an etching solution, an alkaline solution such as potassium hydroxide (KOH) or sodium hydroxide (NaOH) or an acidic solution such as hydrofluoric acid (HF) can be used. Wet etching can be performed over the entire surface of the first substrate 11_1b.

[0192] Since the first substrate 11_1b is gradually etched from the other surface 11b by the etching solution, the thickness of the first substrate 11_1b can be reduced. As described above, the etching selectivity of the etching solution to the region on which the laser LS is irradiated can be higher than the etching selectivity of the etching solution to the region on which the laser LS is not irradiated. Therefore, as a result of wet etching, Fig.11 and Figure 7 As shown in , the substrate through hole TH can be formed in the region on which the laser light LS is irradiated.

[0193] Next, refer to Fig.12 , the substrate through holes TH are filled with substrate connection electrodes CNTb.

[0194] The substrate connection electrode CNTb may include a conductive material. For example, the substrate connection electrode CNTb may include at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof. The substrate connection electrode CNTb may be formed as a single layer made of the material described above. In some embodiments, the substrate connection electrode CNTb may be formed as a multilayer made of the material described above. The substrate connection electrode CNTb may be connected to the etching stopper ES. The substrate connection electrode CNTb may be directly connected to the etching stopper ES. The substrate connection electrode CNTb may be electrically connected to the etching stopper ES.

[0195] Then, refer to Fig.13 , forming a first pad PAD1, a connection line CL and a second pad PAD2.

[0196] The first pad PAD1, the connection line CL, and the second pad PAD2 may each be disposed on the other surface (or rear surface) of the first substrate 11. One end portion of the connection line CL may be connected to the first pad PAD1, and the other end portion of the connection line CL may be connected to the second pad PAD2. The first pad PAD1 may overlap with the substrate connection electrode CNTb in its thickness direction, and may be in direct contact with the substrate connection electrode CNTb. The first pad PAD1 may be electrically connected to the substrate connection electrode CNTb. The connection line CL, the first pad PAD1, and the second pad PAD2 may be disposed coplanar with each other, and may include the same material. However, the present disclosure is not limited thereto, and the connection line CL, the first pad PAD1, and the second pad PAD2 may include different materials. The connection line CL may include a conductive material. For example, the connection line CL may include at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The connection line CL may be formed as a single layer made of the materials described above. In some embodiments, the connection lines CL may be formed as multiple layers made of the materials described above.

[0197] Next, refer to Fig.14 , the chip on film COF is set on the second pad PAD2 through the anisotropic conductive film ACF.

[0198] The leads LE of the chip on film COF may be electrically connected to the second pads PAD2 through the anisotropic conductive film ACF.

[0199] Hereinafter, other embodiments of the display device according to one embodiment will be described. In the following embodiments, the same components as those of the above-described embodiments are denoted by the same reference numerals, and descriptions thereof will be omitted or simplified.

[0200] Fig.15 is a cross-sectional view of a display device according to another embodiment.

[0201] refer to Fig.15 , the etching stopper ES_1 according to the embodiment and the etching stopper ES_2 according to the embodiment Figure 8 The etch stopper ES_1 is different in that one surface ESa_1 of the etch stopper ES_1 includes a first portion ESa1_1 and a second portion ESa2_1.

[0202] More specifically, one surface ESa_1 of the etching stopper ES_1 according to the embodiment may include a first portion ESa1_1 and a second portion ESa2_1. The surface roughness of the first portion ESa1_1 may be less than the surface roughness of the second portion ESa2_1. The first portion ESa1_1 may be a portion that is not in contact with the substrate connection electrode CNTb, and the second portion ESa2_1 may be a portion in contact with the substrate connection electrode CNTb. One surface of the etching stopper ES_1, where the first substrate 11 is exposed, may be partially etched by the etching solution in the etching operation to form the second portion ESa2_1.

[0203] Since the above reference Figure 8 Other descriptions are made, so redundant descriptions will be omitted.

[0204] Fig.16 is a cross-sectional view of a display device according to still another embodiment.

[0205] refer to Fig.16 , this implementation is similar to Figure 8 The embodiment of FIG. 4 is different in that the etching residue ER may remain on one surface ESa of the etch stopper ES in the through substrate hole TH.

[0206] More specifically, the etching residue ER may remain on one surface ESa of the etching stopper ES in the substrate through hole TH. In an embodiment, after the substrate through hole TH is formed, the etching residue ER may be formed when the first substrate residue remains on one surface ESa of the etching stopper ES and is not completely removed. The first substrate residue (i.e., the etching residue ER) may include the same material as the first substrate 11. The etching residue ER may be in direct contact with the substrate connection electrode CNTb in the substrate through hole TH. However, the structure formed by the material of the etching residue ER may be different from the structure formed by the material of the first substrate 11. For example, at least one of the Si-O bonds in the etching residue ER may be in a destroyed state.

[0207] Since the above reference Figure 8 Other descriptions are made, so redundant descriptions will be omitted.

[0208] Fig.17 is a cross-sectional view of a display device according to still another embodiment.

[0209] refer to Fig.17 , the first substrate 11_2 and the through-substrate hole TH_2 according to the embodiment are different from those according to Figure 8The first substrate 11_2 and the through substrate hole TH are different in that the first substrate 11_2 includes the through substrate hole TH_2, and the inclined cross-sectional shape of the side surface 11a_1 of the first substrate 11_2 by which the through substrate hole TH_2 is defined is a linear shape.

[0210] More specifically, the first substrate 11_2 according to the embodiment includes a through substrate hole TH_2, and the inclined cross-sectional shape of the side surface 11a_1 of the first substrate 11_2 through which the through substrate hole TH_2 is defined may be a linear shape. For example, the inclination angle of the side surface 11a_1 of the first substrate 11_2 may be constant.

[0211] The side surface 11 a_1 of the embodiment may be formed by adjusting an etching solution or an etching time when forming the through substrate hole TH_2.

[0212] In some cases, when the through-substrate hole TH_2 is formed using dry etching, the side surface 11 a_1 of the embodiment may be formed.

[0213] Since the above reference Figure 8 Other descriptions are made, so redundant descriptions will be omitted.

[0214] Fig.18 is a cross-sectional view of a display device according to still another embodiment.

[0215] refer to Fig.18 , the first substrate 11_3 and the through-substrate hole TH_3 according to the embodiment are different from those according to Figure 8 The difference between the first substrate 11_3 and the through substrate hole TH is that the width of the through substrate hole TH_3 of the first substrate 11_3, which is equal to the length of the extension of one surface of the first substrate 11_3, may be the same as the width of the through substrate hole TH_3 of the first substrate 11_3, which is equal to the length of the extension of the other surface 11b of the first substrate 11_3. The side surface 11a_2 of the first substrate 11_3 may be substantially perpendicular to the other surface 11b of the first substrate 11_3.

[0216] More specifically, the through substrate hole TH_3 may have a third width W3, and the third width W3 may be constant from an extension portion of one surface of the first substrate 11_3 to an extension portion of the other surface 11 b of the first substrate 11_3.

[0217] In the embodiment, dry etching is used to form the substrate through hole TH_3. Figure 8 Other descriptions are made, so redundant descriptions will be omitted.

[0218] Fig.19 is a cross-sectional view of a display device according to still another embodiment.

[0219] refer to Fig.19 , the first substrate 11_4 and the substrate through hole TH_4 are connected according to Figure 8 The difference between the first substrate 11_4 and the through substrate hole TH is that the first width W1 of the through substrate hole TH_4 of the first substrate 11_4 is greater than the second width W2.

[0220] More specifically, the first substrate 11_4 and the through-substrate hole TH_4 according to the embodiment are different from those according to Figure 8 The difference between the first substrate 11_4 and the substrate through hole TH_4 is that the slope of the side surface 11a_3 of the first substrate 11_4 can gradually decrease in the direction from the point where the extension portion of the other surface 11b of the first substrate 11_4 and the other surface 11b intersect with each other toward the point where the extension portion of one surface of the first substrate 11_4 and one surface of the first substrate 11_4 intersect with each other.

[0221] Since the above reference Figure 8 Other descriptions are made, so redundant descriptions will be omitted.

[0222] Fig. 20 is a cross-sectional view of a display device according to still another embodiment.

[0223] refer to Fig. 20 , the first substrate 11_5 and the through-substrate hole TH_5 according to the embodiment are different from those according to Fig.19 The first substrate 11_5 and the through substrate hole TH_4 are different in that the curved surfaces formed by the side surfaces 11a_4 of the first substrate 11_5 by which the through substrate hole TH_5 is defined each have a cross-sectional shape convex in a direction away from the through substrate hole TH_5.

[0224] Since the above reference Figure 8 and Fig.19 Other descriptions are made, so redundant descriptions will be omitted.

[0225] Fig.21 is a plan view of a display device according to still another embodiment, viewed from above. Fig. 22 is an enlarged plan view of a pixel of a display device according to still another embodiment. Fig.23 is a plan view of a display device according to still another embodiment as viewed from below. Fig.24 It is along Fig.23 Cross-sectional views of the display device taken along lines VII-VII' and VIII-VIII'.

[0226] refer to Figure 21 to Figure 24 The display device 2 according to the embodiment and the display device according to Figure 3 , Figure 4 , Figure 6 and Figure 7 The display device 1 of FIG. 1 is different in that the substrate connection electrode CNTb is disposed to overlap with the non-emission area NEA of the pixel PX in the display area DA.

[0227] More specifically, in the display device 2 according to the embodiment, the substrate connection electrode CNTb may be disposed to overlap the non-emission area NEA of the pixel PX in the display area DA.

[0228] The substrate connection electrode CNTb may be disposed to overlap the outer bank 45 in a thickness direction thereof. The first pad PAD1 connected to the substrate connection electrode CNTb may be disposed to overlap the non-emission area NEA like the substrate connection electrode CNTb.

[0229] According to the embodiment, since the substrate connection electrode CNTb is formed only in the first substrate 11, it does not cause any interference to the upper structure of the first substrate 11. Therefore, when forming the substrate connection electrode CNTb, the formation area may not be limited regardless of the emission area EMA or the non-emission area NEA.

[0230] Fig.25 is a plan view of a display device according to still another embodiment as viewed from below. Fig.26 is based on Fig.25 A cross-sectional view of a display device.

[0231] refer to Fig.25 and Fig.26 The display device 3 according to the embodiment and the display device according to Figure 6 and Figure 7 The display device 1 is different from the display device 3 in that the driving chip IC of the display device 3 is arranged to overlap with the second pad PAD2 and is connected to the second pad PAD2.

[0232] More specifically, the driving chip IC of the display device 3 according to the embodiment may be disposed to overlap with the second pad PAD2 and may be connected to the second pad PAD2. Figure 6 and Figure 7 The display device 1 is different in that the Figure 6 and Figure 7 Chip-on-film COF.

[0233] According to an embodiment, since the chip-on-film COF (see Figure 6 and Figure 7 ), and the driving chip IC is directly attached to and connected to the second pad PAD2, so the structure of the display device 3 can be simplified.

[0234] Fig. 27is a cross-sectional view of a display device according to still another embodiment.

[0235] refer to Fig. 27 The display device 4 according to the embodiment and the display device according to Figure 7 The display device 1 is different from the display device 4 in that the display device 4 further includes a first gate connection electrode GCE connected to the data line DL and a second gate connection electrode CNTc connecting the first gate connection electrode GCE and the etching stopper ES.

[0236] More specifically, the display device 4 may further include a first gate connection electrode GCE connected to the data line DL and a second gate connection electrode CNTc connecting the first gate connection electrode GCE and the etch stopper ES.

[0237] The first gate connection electrode GCE may be provided at the above reference Figure 5 The second gate connection electrode CNTc may pass through the first gate insulating layer 13 and the buffer layer 12 in the thickness direction thereof.

[0238] In some embodiments, the first gate connection electrode GCE may also be disposed in the second gate conductive layer. In this case, the second gate connection electrode CNTc may pass through the first protection layer 15, the first gate insulating layer 13, and the buffer layer 12 in the thickness direction.

[0239] According to an embodiment, since the first gate connection electrode GCE and the second gate connection electrode CNTc are further formed, the total resistance of the current path from the data line DL to the first pad PAD1 may be reduced.

[0240] Fig.28 is a cross-sectional view of a display device according to still another embodiment. Fig.29 yes Fig.28 An enlarged cross-sectional view of area B.

[0241] refer to Fig.28 and Fig.29 The display device 5 according to the embodiment is different from the display device 1 according to one embodiment at least in that the buffer layer 12_1 is used as the etching stopper ES in the display device 1 according to one embodiment.

[0242] More specifically, in the display device 5 according to the embodiment, the buffer layer 12_1 serves as the etching stopper ES in the display device 1 according to one embodiment.

[0243] The buffer layer 12_1 according to the embodiment may include a buffer through hole THa overlapping the substrate through hole TH. The substrate connection electrode CNTb_1 may fill the substrate through hole TH and the buffer through hole THa. The substrate connection electrode CNTb_1 may be formed by the above reference Fig. 27 The second gate connection electrode CNTc and the first gate connection electrode GCE and the data connection electrode CNTa described are connected to the data line DL. In some embodiments, the second gate connection electrode CNTc and the first gate connection electrode GCE may be omitted. In this case, the data connection electrode CNTa may pass through the first interlayer insulating layer 17, the first protective layer 15, and the first gate insulating layer 13, and the data connection electrode CNTa may be directly connected to the substrate connection electrode CNTb_1.

[0244] The buffer layer 12_1 may include one surface 12b in contact with one surface of the first substrate 11 and another surface opposite to the one surface 12b of the buffer layer 12_1. The other surface of the buffer layer 12_1 may be in direct contact with one surface 13a of the first gate insulating layer 13. The buffer through hole THa may be surrounded by an extension of one surface 12b of the buffer layer 12_1, an extension of the other surface of the buffer layer 12_1, and a side surface 12a of the buffer layer 12_1.

[0245] An average slope of the side surface 12 a of the buffer layer 12_1 may be greater than an average slope of the side surface 11 a of the first substrate 11 .

[0246] In the buffer through hole THa, a width W4 of an extension of one surface 12b of the buffer layer 12_1 or a lower width of the buffer through hole THa may be the same as a width W4 of an extension of the other surface of the buffer layer 12_1 or an upper width of the buffer through hole THa.

[0247] The width W4 of the extension of one surface 12b of the buffer layer 12_1 may be greater than the first width W1 of the through substrate hole TH. For example, the buffer through hole THa may be disposed to overlap the through substrate hole TH in its thickness direction and may be disposed to partially overlap one surface of the first substrate 11.

[0248] According to the embodiment of the present disclosure, when forming the through substrate hole TH, laser irradiation and etching are simultaneously performed, thereby ensuring processing quality, processing speed, and a high aspect ratio (ratio of thickness to width of the through substrate hole TH) of the through substrate hole TH.

[0249] Furthermore, the buffer layer 12_1 functions as an etching stopper, thereby preventing an etching solution from diffusing into one surface of the first substrate 11 when forming the through substrate hole TH. Therefore, the electrode on the first substrate 11 may be prevented from being corroded and / or etched by the etching solution.

[0250] Furthermore, the existing buffer layer 12_1 on the first substrate 11 is used as an etch stopper without any change, thereby simplifying the manufacturing process without adding separate members and / or components.

[0251] In addition, since the substrate connection electrode CNTb_1 is disposed in the display area DA, the chip-on-film COF connected to the substrate connection electrode CNTb_1 may be formed on the other surface 11b of the first substrate 11 of the display device 5 and may be disposed in the display area DA. Therefore, the dead zone may be reduced by the arrangement of the chip-on-film COF and the fan-out line.

[0252] Figure 30 to Figure 33 is a cross-sectional view illustrating a process operation of a method of manufacturing a display device according to another embodiment.

[0253] First, refer to Fig.30 , using the buffer layer 12 as an etching stopper to form a substrate through hole TH. Fig.10 and Fig.11 The formation of the through-substrate hole TH is described, and thus a redundant description will be omitted.

[0254] Then, refer to Fig.31 , forming the buffer through hole THa. The buffer through hole THa may be formed using dry etching. Since the buffer through hole THa is formed by dry etching and the substrate through hole TH is formed by wet etching, the average slope of the side surface 12a of the buffer layer 12_1 may be greater than the average slope of the side surface 11a of the first substrate 11.

[0255] In the case of over-etching, Fig.31 As shown in FIG. 1 , one surface of the first substrate 11 may be partially exposed by the buffer layer 12_1 . For example, the buffer through hole THa may be disposed to overlap with the substrate through hole TH in a thickness direction thereof, and may be disposed to partially overlap with one surface of the first substrate 11 .

[0256] Next, refer to Fig.32 , the substrate through hole TH and the buffer through hole THa are filled with the substrate connection electrode CNTb_1. The substrate connection electrode CNTb_1 can be obtained by referring to the above reference. Fig. 27 The described second gate connection electrode CNTc and the first gate connection electrode GCE and the data connection electrode CNTa are connected to the data line DL.

[0257] Then, refer to Fig.33 , forming a first pad PAD1, a connection line CL and a second pad PAD2.

[0258] The first pad PAD1, the connection line CL, and the second pad PAD2 may each be disposed on the other surface (or rear surface) of the first substrate 11. One end portion of the connection line CL may be connected to the first pad PAD1, and the other end portion of the connection line CL may be connected to the second pad PAD2. The first pad PAD1 may be disposed to overlap with the substrate connection electrode CNTb_1 in its thickness direction, and may be in direct contact with the substrate connection electrode CNTb_1. The first pad PAD1 may be electrically connected to the substrate connection electrode CNTb_1. The connection line CL, the first pad PAD1, and the second pad PAD2 may be disposed to be coplanar with each other, and may include the same material. However, the present disclosure is not limited thereto, and the connection line CL, the first pad PAD1, and the second pad PAD2 may include different materials. The connection line CL may include a conductive material. For example, the connection line CL may include at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The connection line CL may be formed as a single layer made of the material described above. In some embodiments, the connection line CL may be formed as a multi-layer made of the material described above.

[0259] Next, the chip on film COF is disposed on the second pad PAD2 through the anisotropic conductive film ACF. The leads LE of the chip on film COF may be electrically connected to the second pad PAD2 through the anisotropic conductive film ACF.

[0260] Fig.34 is a cross-sectional view of a display device according to still another embodiment.

[0261] refer to Fig.34 The buffer layer 12_2 and the buffer through hole THa_1 according to the embodiment are different from those according to Fig.29 The difference between the buffer layer 12_1 and the buffer through hole THa is that, in the buffer through hole THa_1 of the buffer layer 12_2, the width of the buffer through hole THa_1 gradually decreases in a direction from an extension portion of one surface 12b of the buffer layer 12_2 toward an extension portion of the other surface of the buffer layer 12_2.

[0262] More specifically, in the buffer through hole THa_1 of the buffer layer 12_2 according to the embodiment, the width of the buffer through hole THa_1 may gradually decrease in a direction from an extension of one surface 12 b of the buffer layer 12_2 toward an extension of the other surface of the buffer layer 12_2 .

[0263] According to an embodiment, the inclined cross-sectional shape of the side surface 12a_1 of the buffer layer 12_2 through which the buffer through hole THa_1 is defined may be a linear shape inclined with respect to the third direction DR3. For example, the inclined angle of the side surface 12a_1 of the buffer layer 12_2 may be constant.

[0264] Fig.35 is a cross-sectional view of a display device according to still another embodiment.

[0265] refer to Fig.35 , implementation method and Fig.29 The embodiment of FIG. 1 is different in that the etching residue ER may remain on one surface 13 a of the first gate insulating layer 13 .

[0266] More specifically, the etching residue ER may remain on one surface 13 a of the first gate insulating layer 13 in the buffer through hole THa.

[0267] In an embodiment, after forming the buffer through hole THa, when the buffer layer residue remains on one surface 13a of the first gate insulating layer 13 and is not completely removed, the etching residue ER may be formed. The buffer layer residue (ie, the etching residue ER) may include the same material as the buffer layer 12_1. The etching residue ER may be in direct contact with the substrate connection electrode CNTb_1 in the buffer through hole THa.

[0268] Fig.36 is a cross-sectional view of a display device according to still another embodiment.

[0269] refer to Fig.36 The first gate insulating layer 13_1 according to the embodiment and the Fig.29 The first gate insulating layer 13_1 is different in that one surface 13 a_1 of the first gate insulating layer 13_1 includes a first portion 13 a 1_1 and a second portion 13 a 2_1 .

[0270] More specifically, one surface 13a_1 of the first gate insulating layer 13_1 according to the embodiment may include a first portion 13a1_1 and a second portion 13a2_1. The surface roughness of the first portion 13a1_1 may be less than the surface roughness of the second portion 13a2_1. The first portion 13a1_1 may be a portion that is not in contact with the substrate connection electrode CNTb_1, and the second portion 13a2_1 may be a portion in contact with the substrate connection electrode CNTb_1. One surface 13a_1 of the first gate insulating layer 13_1 that exposes the buffer layer 12_1 may be partially etched by the dry etching solution in the etching operation to form the second portion 13a2_1.

[0271] Since the above reference Fig.29Other descriptions are made, so redundant descriptions will be omitted.

[0272] Fig.37 is a plan view of a display device according to still another embodiment.

[0273] refer to Fig.37 The display device 6 according to the embodiment is different from the display device 1 according to one embodiment in that a spliced ​​display device is applied and the display device 6 includes a plurality of display devices 1 .

[0274] Since the plurality of display devices 1 included in the display device 6 have been described above, a detailed description thereof will be omitted.

[0275] The display device 1 may be arranged by connecting the long sides or the short sides of the display device 1 to each other. Some of the display devices 1 may form one side of the display device 6, some of the display devices 1 may be positioned at the edge of the display device 6 to constitute two adjacent sides of the display device 6, and some of the display devices 1 may be positioned inside the display device 6 to have a structure surrounded by other display devices 1. The plurality of display devices 1 may have different frame shapes according to their positions, or may also have the same frame shape.

[0276] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiment without departing from the principles of the invention in essence. Therefore, the preferred embodiments of the present invention disclosed are used only in an overview and descriptive sense, and not for a limiting purpose.

Claims

1. A display device, comprising: a base substrate in which a display area and a non-display area positioned around the display area are defined, and the base substrate includes a substrate connection electrode passing through the base substrate in a thickness direction thereof; an etch stopper disposed on one surface of the base substrate and configured to cover the substrate connection electrode; as well as a first pad disposed on another surface of the base substrate opposite to the one surface of the base substrate and disposed so as to overlap with the substrate connection electrode, in: The substrate connection electrode is disposed in the display region and is connected to the etching stopper and the first pad; and The etch stopper is electrically connected to the first pad through the substrate connection electrode and includes a conductive material.

2. The display device according to claim 1, further comprising: a buffer layer disposed on the etching stopper; an active material layer, disposed on the buffer layer; as well as a light blocking layer, arranged to overlap with the active material layer, The light blocking layer is arranged to be coplanar with the etching stopper and spaced apart from the etching stopper.

3. The display device according to claim 2, further comprising: a first gate insulating layer, disposed on the active material layer; a data line disposed on the first gate insulating layer, wherein the data line is connected to the etching stopper through a data connection electrode, the data connection electrode passing through the first gate insulating layer and the buffer layer in a thickness direction thereof; and A connection line is disposed on the other surface of the base substrate, wherein the connection line is connected to the first pad.

4. The display device according to claim 3, further comprising: a chip on film, which is disposed on the other surface of the base substrate and on which a driver chip is mounted; as well as a second pad disposed on the other surface of the base substrate, in: The second pad is connected to the connection line; and The chip on film is connected to the second pad.

5. The display device according to claim 3, further comprising: A driving chip, disposed on the other surface of the base substrate; as well as a second pad disposed on the other surface of the base substrate, in: The second pad is connected to the connection line; and The driving chip is disposed to overlap with the second pad and is connected to the second pad.

6. The display device according to claim 3, wherein: The one surface of the base substrate is in contact with the etch stopper; and The substrate connection electrode is surrounded by an extension of the other surface of the base substrate, an extension of the one surface of the base substrate, and a side surface of the base substrate.

7. The display device according to claim 6, wherein: A width of the substrate connection electrode decreases in a direction from the extending portion of the other surface of the base substrate toward the extending portion of the one surface of the base substrate.

8. The display device according to claim 7, wherein: A slope of a side surface of the substrate connection electrode in contact with the side surface of the base substrate gradually increases in the direction from the extension portion of the other surface of the base substrate toward the extension portion of the one surface of the base substrate.

9. The display device according to claim 6, wherein: A width of the substrate connection electrode is constant from the extending portion of the other surface of the base substrate to the extending portion of the one surface of the base substrate.

10. The display device according to claim 6, wherein: A portion of one surface of the etching stopper in contact with the substrate connection electrode has a roughness higher than a roughness of a portion of the one surface of the etching stopper that does not contact the substrate connection electrode.

11. The display device according to claim 6, wherein: An etching residue is also disposed on a surface of the etching stopper in contact with the substrate connection electrode; and The etching residue includes the same material as the base substrate.

12. The display device according to claim 3, wherein: A plurality of pixels are arranged in the display area; Each of the plurality of pixels includes an emissive region and a non-emissive region positioned around the emissive region; An outer bank disposed on the data line is disposed in the non-emitting region; The light emitting element is arranged in the emission area; as well as The emission region is surrounded by the outer bank in a plan view.

13. The display device according to claim 12, wherein: The substrate connection electrode is arranged to overlap with the emission region.

14. The display device according to claim 12, wherein: The substrate connection electrode is disposed to overlap the outer bank in the non-emission region.

15. The display device according to claim 2, further comprising: a first gate insulating layer, disposed on the active material layer; A first gate connecting electrode, disposed on the first gate insulating layer; A first protective layer is disposed on the first gate connecting electrode; and A data line is arranged on the first protective layer, in: The data line is connected to the first gate connection electrode through the data connection electrode passing through the first protection layer; and The first gate connection electrode is connected to the etch stopper through a second gate connection electrode passing through the first gate insulating layer and the buffer layer.

16. A display device comprising: a base substrate in which a display area and a non-display area positioned around the display area are defined, and the base substrate includes a substrate through hole passing through the base substrate in a thickness direction thereof; a buffer layer disposed on one surface of the base substrate and including a buffer through hole disposed to overlap with the substrate through hole and to pass through the buffer layer in a thickness direction thereof; A data line, arranged on the buffer layer; a substrate connection electrode configured to fill the substrate through-hole and the buffer through-hole, wherein the substrate connection electrode is disposed in the display area and connected to the data line; and A first pad is provided on the other surface of the base substrate opposite to the one surface of the base substrate and is provided to overlap with the substrate through hole, wherein the first pad is connected to the substrate connection electrode.

17. The display device according to claim 16, wherein: The one surface of the base substrate is in contact with the buffer layer; The substrate through hole is surrounded by an extension of the other surface of the base substrate, an extension of the one surface of the base substrate, and a side surface of the base substrate; the buffer layer including one surface in contact with the one surface of the base substrate and another surface opposite to the one surface of the buffer layer; The buffer through hole is surrounded by an extension of the one surface of the buffer layer, an extension of the other surface of the buffer layer, and a side surface of the buffer layer; and An average slope of the side surface of the buffer layer is greater than an average slope of the side surface of the base substrate.

18. The display device according to claim 17, further comprising a first gate insulating layer directly disposed on the other surface of the buffer layer, in, A portion of one surface of the first gate insulating layer in contact with the substrate connection electrode has a roughness higher than a roughness of a portion of the one surface of the first gate insulating layer not in contact with the substrate connection electrode.

19. The display device according to claim 17, further comprising a first gate insulating layer directly disposed on the other surface of the buffer layer, in, An etching residue is also disposed on a surface of the first gate insulating layer in contact with the substrate connection electrode, and the etching residue includes a material that is the same as that of the buffer layer.

20. The display device according to claim 17, wherein: The buffer through hole is provided to partially overlap the one surface of the base substrate in the thickness direction thereof.

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