Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device (1) includes: a base (3) including a p-type substrate (4) and an n-type semiconductor layer (5) formed on the p-type substrate (4), and containing an element region (2) having a transistor (40) with the n-type semiconductor layer as a drain; a p-type element isolation region (7) formed in a surface layer portion of the base in a manner to define the element region; and a conductive wiring (25B) disposed on a peripheral portion of the element region and electrically connected to the n-type semiconductor layer. The transistor includes an n + type drain contact region (14) formed in a surface layer portion of the n-type semiconductor layer in the peripheral portion of the element region. The conductive wiring is disposed in a manner to cover at least a portion of an element terminal region (30) between the n + type drain contact region and the p-type element isolation region.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device including a transistor such as a DMOS (Diffused Metal Oxide Semiconductor) transistor and a manufacturing method thereof. BACKGROUND

[0002] Patent Literature 1 discloses a semiconductor device including a p-type element isolation region (p-type well) that separates element regions and a DMOS transistor formed in the element regions. The semiconductor device includes a source region and a drain region selectively formed on a surface of an n-type epitaxial layer (n-type well) of a p-type substrate, and a gate electrode formed on a silicon substrate with a gate oxide film interposed therebetween.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2012-156205 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] In the semiconductor device having the element isolation structure as described in Patent Literature 1, the DMOS transistor is sometimes mixedly mounted with other elements. In such a semiconductor device, not only a wiring electrically connected to the DMOS transistor is formed, but also a plurality of wirings (hereinafter referred to as "other wirings") electrically connected to other elements (hereinafter referred to as "other elements") other than the DMOS transistor are formed. Further, various voltages matched with the corresponding other elements are applied to the plurality of other wirings.

[0008] Therefore, in the DMOS transistor described in Patent Literature 1, when a reverse direction voltage is applied to a parasitic diode existing between the n-type epitaxial layer and the p-type element isolation region, the equipotential distribution is disturbed due to the influence of the potential from the other wirings, and the withstand voltage can be lowered.

[0009] An object of the present application is to provide a semiconductor device capable of suppressing a decrease in withstand voltage due to the influence of the potential of other wirings.

[0010] TECHNICAL MEANS FOR SOLVING THE PROBLEM

[0011] One embodiment of the present application provides a semiconductor device including: a base including a p-type substrate and an n-type semiconductor layer formed on the p-type substrate, and containing an element region having a transistor with the n-type semiconductor layer as a drain; a p-type element isolation region formed in a surface layer portion of the base in a manner to define the element region; and a conductive wiring disposed on a peripheral portion of the element region and electrically connected to the n-type semiconductor layer, the transistor containing an n-type drain contact region formed in a surface layer portion of the n-type semiconductor layer in the peripheral portion of the element region, the conductive wiring being disposed in a manner to cover at least a portion of an element terminal region between the n-type drain contact region and the p-type element isolation region.

[0012] In this structure, a decrease in withstand voltage due to an influence of a potential of another wiring can be suppressed.

[0013] In one embodiment of the present application, a drain wiring electrically connected to the n-type drain contact region is included, the drain wiring having an extension portion extending into the element terminal region in plan view, and the conductive wiring is constituted by the extension portion.

[0014] In one embodiment of the present application, the n-type drain contact region and the drain wiring are each formed in a ring shape in plan view, and the extension portion is formed so as to surround the n-type drain contact region over the entire length of the drain wiring in plan view.

[0015] In one embodiment of the present application, in the element terminal region, an n-type contact region for the conductive wiring is formed in a surface layer portion of the n-type semiconductor layer, and the conductive wiring is electrically connected to the n-type contact region via a conductive member.

[0016] In one embodiment of the present application, the n-type drain contact region is formed in a ring shape in plan view, and the n-type contact region and the conductive wiring are each formed in a ring shape in plan view so as to surround the n-type drain contact region.

[0017] In one embodiment of the present application, a drain wiring electrically connected to the n-type drain contact region is included, and the conductive wiring is electrically connected to the drain wiring via a conductive member.

[0018] In one embodiment of the present application, the conductive wiring is formed on the n-type semiconductor layer with an insulating layer interposed in the element terminal region, the drain wiring has an overlapping portion overlapping a portion of the conductive wiring in plan view, and a lower surface of the overlapping portion and an upper surface of the conductive wiring are electrically connected by the conductive member.

[0019] In one embodiment of the present application, the n-type drain contact region and the drain wiring are formed in a ring shape in plan view, the conductive wiring is formed in a ring shape so as to surround the n-type drain contact region in plan view, the drain wiring has the overlapping portion at an outer peripheral portion thereof, and a lower surface of the overlapping portion is electrically connected to an inner peripheral portion of an upper surface of the conductive wiring via the conductive member.

[0020] In one embodiment of the present application, the conductive wiring is composed of polysilicon.

[0021] In one embodiment of the present application, an n-type buried layer is formed so as to straddle a boundary between the p-type substrate and the n-type semiconductor layer in a central portion of the element region in plan view.

[0022] In one embodiment of the present application, the p-type element separation region is formed in a ring shape so as to surround the element region in plan view, and the n-type drain contact region is formed in a ring shape along the p-type element separation region in plan view.

[0023] In one embodiment of the present application, the transistor includes a p-type well region formed in a surface layer portion of the n-type semiconductor layer, an n-type source region formed in a surface layer portion of the p-type well region, an n-type source contact region formed in a surface layer portion of the n-type source region and having a higher n-type impurity concentration than the n-type source region, and an n-type drain region formed in a surface layer portion of the n-type semiconductor layer in a ring shape so as to surround the p-type well region, the n-type drain contact region being formed in a surface layer portion of the n-type drain region so as to surround the p-type well region and having a higher n-type impurity concentration than the n-type drain region.

[0024] In one embodiment of the present application, the transistor further includes a gate insulating film formed so as to cover a channel region between the source contact region and the drain contact region, and a gate electrode formed on the gate insulating film and facing the channel region via the gate insulating film.

[0025] In one embodiment of the present application, a source wiring is electrically connected to the n-type source contact region.

[0026] The above and other objects, features and effects of the present application will become clearer from the following description of the embodiments thereof, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a diagrammatic plan view for explaining a structure of a semiconductor device according to a first embodiment of the present application.

[0028] Figure 2 is a diagrammatic plan view for explaining a structure of a semiconductor device according to a first embodiment of the present application. Figure 1Fig. 2 is a diagrammatic sectional view along the line II-II of Fig. 1.

[0029] Figure 3 Fig. 3 is a diagrammatic sectional view showing an example of a simulation model for the comparative example.

[0030] Figure 4 Fig. 4 is a graph showing simulation results for the comparative example.

[0031] Figure 5 Fig. 5 is a graph showing simulation results for the present embodiment.

[0032] Figure 6A Fig. 6 is a diagrammatic plan view for explaining the structure of a semiconductor device of a second embodiment of the present application. Figure 1 Fig. 7 is a diagrammatic sectional view along the line VII-VII of Fig. 6. Figure 2 Fig. 8 is a diagrammatic sectional view along the line VIII-VIII of Fig. 6. Figure 2 Fig. 9 is a diagrammatic sectional view along the line IX-IX of Fig. 6.

[0033] Figure 6B Fig. 10 is a diagrammatic sectional view showing a next step of Fig. 9. Figure 6A

[0034] Fig. 11 is a diagrammatic sectional view showing a next step of Fig. 10. Figure 6C Figure 6B Fig. 12 is a diagrammatic sectional view showing a next step of Fig. 11.

[0035] Figure 6D Figure 6C Fig. 13 is a diagrammatic sectional view showing a next step of Fig. 12.

[0036] Figure 6E Fig. 14 is a diagrammatic sectional view showing a next step of Fig. 13. Figure 6D

[0037] Fig. 15 is a diagrammatic sectional view showing a next step of Fig. 14. Figure 6F Figure 6E Fig. 16 is a diagrammatic sectional view showing a next step of Fig. 15.

[0038] Figure 6G Figure 6F Fig. 17 is a diagrammatic plan view for explaining the structure of a semiconductor device of a second embodiment of the present application.

[0039] Figure 7 Fig. 18 is a diagrammatic sectional view along the line VIII-VIII of Fig. 17.

[0040] Figure 8 Fig. 19 is a diagrammatic sectional view along the line IX-IX of Fig. 17. Figure 7 Fig. 20 is a diagrammatic sectional view along the line X-X of Fig. 17.

[0041] Figure 9A Fig. 21 is a diagrammatic sectional view showing a next step of Fig. 19. Figure 7 Figure 8 Figure 8 Fig. 22 is a diagrammatic sectional view showing a next step of Fig. 21.

[0042] ​​​​​​Figure 9B is a sectional view showing the next step of Figure 9A

[0043] Figure 9C is a sectional view showing the next step of Figure 9B

[0044] Figure 9D is a sectional view showing the next step of Figure 9C

[0045] Figure 9E is a sectional view showing the next step of Figure 9D

[0046] Figure 10 is a diagrammatic plan view for explaining the structure of the semiconductor device of the third embodiment of the present application.

[0047] Figure 11 is a diagrammatic sectional view along XI-XI line of Figure 10

[0048] Figure 12A is a sectional view showing an example of the manufacturing steps of the semiconductor device shown in Figure 10 and Figure 11 corresponding to the sectional view of Figure 11

[0049] Figure 12B is a sectional view showing the next step of Figure 12A

[0050] Figure 12C is a sectional view showing the next step of Figure 12B DETAILED DESCRIPTION

[0051] Figure 1 is a diagrammatic plan view for explaining the structure of the semiconductor device of the first embodiment of the present application. Figure 2 is a diagrammatic sectional view along II-II line of Figure 1 Figure 1 The interlayer insulating film 21 and the source wiring 26 shown in Figure 2 are omitted in Figure 1 . However, the drain wiring 25 shown in Figure 2 is illustrated in

[0052] Hereinafter, the lateral direction of the paper of Figure 1 is referred to as the lateral direction, and the vertical direction of the paper of Figure 1 is referred to as the vertical direction.

[0053] ​​​​​​​​​The semiconductor device 1 has a base 3. The base 3 includes a p-type semiconductor substrate 4 and an n - type epitaxial layer 5 formed on the p-type semiconductor substrate 4. In this embodiment, the p-type semiconductor substrate 4 is a silicon substrate. The p-type semiconductor substrate 4 is an example of the "p-type substrate" of the present application, and the n - type epitaxial layer 5 is an example of the "n-type semiconductor layer" of the present application.

[0054] n - The film thickness of the n-type epitaxial layer 5 is, for example, 3.0 μm to 10 μm. A p-type element isolation region 7 that defines the element region 2 is formed in the surface layer portion of the base 3. In this embodiment, the element region 2 is a quadrangular shape that is longer in the longitudinal direction in plan view. In the element region 2, a DMOS transistor 40 that uses the n - type epitaxial layer 5 as a drain is formed.

[0055] The p-type element isolation region 7 is annular in plan view. In this embodiment, the p-type element isolation region 7 is a rectangular annular shape in plan view, but can be a circular annular shape, an elliptical annular shape, or the like. The p-type element isolation region 7 has a lower side isolation region 8 that is connected to the p-type semiconductor substrate, and an upper side isolation region 9 that is formed on the lower side isolation region 8.

[0056] Thus, in the base 3, the element region 2 that is composed of a part of the n - type epitaxial layer 5 is defined on the p-type semiconductor substrate 4 surrounded by the p-type element isolation region 7. Although not shown, the p-type element isolation region 7 and the p-type semiconductor substrate 4 are grounded.

[0057] In the element region 2, a boundary portion between the p-type semiconductor substrate 4 and the n - type epitaxial layer 5 is selectively formed with an n - type buried layer 6 having a higher impurity concentration than the n - type epitaxial layer 5. The n + type buried layer 6 is selectively formed in the boundary portion between the p-type semiconductor substrate 4 and the n + type epitaxial layer 5. The n + type buried layer 6 is formed in a central region surrounded by the peripheral portion of the element region 2 in plan view. The film thickness of the n

[0058] In addition, in the base 3, in a peripheral region of the element region 2, an element region (not shown) that forms another element different from the DMOS transistor 40 in the element region 2 is defined.

[0059] A field insulating film 11, which appears annular when viewed from above, is formed on the surface of the p-type element separation region 7. The field insulating film 11 is formed as a quadrilateral annular shape when viewed from above, surrounding the region enclosed by the periphery of the element region 2. The field insulating film 11 is wider than the p-type element separation region 7, and is formed to completely cover the p-type element separation region 7. For example, the field insulating film 11 is designed to make n... - The surface of the epitaxial layer 5 is selectively oxidized to form a LOCOS film.

[0060] DMOS transistor 40 includes n - The surface portion of the epitaxial layer 5 has an n-type drain region 13 and a p-type well region 15 formed at intervals. In this embodiment, the p-type well region 15 is a long, narrow quadrilateral shape in the longitudinal direction when viewed from above, and is formed in the center of the transverse direction of the element region 2.

[0061] The n-type drain region 13 has a higher density than n - The epitaxial layer 5 has a high impurity concentration. The n-type drain region 13, when viewed from above, is formed in a ring shape surrounding the p-type well region 15. In this embodiment, the n-type drain region 13, when viewed from above, is formed in a quadrilateral ring shape along the field insulating film 11. On the surface portion of the n-type drain region 13, an n-type drain layer with a higher impurity concentration than the p-type drain region 15 is formed. + Type Drain Contact Region 14.

[0062] In the surface portion of the p-type well region 15, a layer with a density greater than n is formed. - The epitaxial layer 5 has an n-type source region 16 with a high impurity concentration. On the surface portion of the n-type source region 16, an n-type source region with a higher impurity concentration than the n-type source region 16 is formed. + Type source electrode contact region 17.

[0063] The n-type source region 16 is formed, for example, at the same concentration and depth as the n-type drain region 13. + The outer periphery of the source electrode contact region 17 is arranged at intervals from the outer periphery of the p-type well region 15 toward the inward side. + Type source contact region 17, for example, with n + Type 14 drain contact regions are formed with the same concentration and the same depth.

[0064] In n - On the surface of the epitaxial layer 5, in n + A field insulating film 12, which is quadrilateral in shape when viewed from above, is formed in the portion between the p-type drain contact region 14 and the p-type well region 15. The field insulating film 12 is a LOCOS film formed through the same process as the aforementioned field insulating film 11. Figure 1 In the figure, the inner periphery of the field insulating film 12 is indicated by reference numeral 12a.

[0065] The inner periphery 12a of the field insulating film 12 is arranged outwardly apart from the outer periphery of the p-type well region 15, and the outer periphery of the field insulating film 12 is arranged on the inner periphery of the n + type drain contact region 14. The n + type drain contact region 14 is formed in a region sandwiched by the outer periphery of the field insulating film 12 and the inner periphery of the field insulating film 11.

[0066] In addition, on the surface of the n - type epitaxial layer 5, a gate insulating film 18 is formed in a manner so as to straddle between the n - type epitaxial layer 5 and the p-type well region 15. The gate insulating film 18 is formed in a quadrangular ring shape in a manner so as to surround the n + type source region 16 in plan view. The gate electrode 19 is formed in a manner so as to selectively cover a portion of the gate insulating film 18 and a portion of the field insulating film 12.

[0067] The gate electrode 19 is composed of, for example, polysilicon. The gate insulating film 18 is, for example, a silicon oxide film formed by oxidizing the surface of the n - type epitaxial layer 5.

[0068] The region of the p-type well region 15 opposite to the gate electrode 19 via the gate insulating film 18 is a channel region 20 of the DMOS transistor 40. The formation of the channel of the channel region 20 is controlled by the gate electrode 19.

[0069] An interlayer insulating film 21 is formed in a manner so as to cover the entire element region 2. The interlayer insulating film 21 is formed of, for example, an insulating film such as an oxide film, a nitride film, or the like.

[0070] A drain contact plug 22, a source contact plug 23, and a gate contact plug 24 are embedded in the interlayer insulating film 21. The lower end of the drain contact plug 22 is electrically connected to the n + type drain contact region 14. The lower end of the source contact plug 23 is electrically connected to the n + type source contact region 17. The gate contact plug 24 is electrically connected to the gate electrode 19.

[0071] On the interlayer insulating film 21, a drain wiring 25, a source wiring 26, and a gate wiring (omitted from illustration) are formed. In the drawing, Figure 1 , a region of the drain wiring 25 is indicated as a hatched region of a dot. The drain wiring 25 is electrically connected to the n + type drain contact region 14 via a plurality of drain contact plugs 22. The source wiring 26 is electrically connected to the n +source contact region 17. The gate wire is electrically connected to both end portions of the gate electrode 19 via a plurality of gate contact plugs 24.

[0072] The source wire 26 is not depicted in FIG. 1, and is a quadrangular shape longer in the longitudinal direction in plan view, covering the middle portion of the length between both end portions of the gate electrode 19. A plurality of portions of the width central portion of the source wire 26 are electrically connected to the n Figure 1 The source wire 26 is not depicted in FIG. 1, and is a quadrangular shape longer in the longitudinal direction in plan view, covering the middle portion of the length between both end portions of the gate electrode 19. A plurality of portions of the width central portion of the source wire 26 are electrically connected to the n + source contact region 17. The gate wire is electrically connected to both end portions of the gate electrode 19 via a plurality of gate contact plugs 24.

[0073] The drain wire 25 is formed in a quadrangular ring shape so as to surround the field insulating film 12 in plan view. The inner periphery of the drain wire 25 is located substantially directly above the n + type drain contact region 14. The outer periphery of the drain wire 25 is located outward of the outer periphery of the n + type drain contact region 14. The drain wire 25 is composed of a main wire portion 25A disposed directly above the n + type drain contact region 14 and an extension portion 25B extending outward from the outer periphery of the main wire portion 25A. In the first embodiment, this extension portion 25B constitutes the "conductive wire" of the present application (hereinafter sometimes referred to as "voltage withstand improvement wire").

[0074] The extension portion (voltage withstand improvement wire) 25B is a quadrangular ring shape in plan view, extending from the n + type drain contact region 14 to the p-type element separation region 7 outside of the outer periphery thereof. In this embodiment, the extension portion 25B extends from the n + type drain contact region 14 to the n + type drain contact region 14 to the inner periphery of the p-type element separation region 7 outside of the outer periphery thereof.

[0075] That is, the extension portion (voltage withstand improvement wire) 25B is a peripheral portion region of the element region 2, disposed so as to cover a portion of the element terminal region 30 between the outer periphery of the n + type drain contact region 14 and the inner periphery of the p-type element separation region 7 outside of the outer periphery thereof.

[0076] The extension portion 25B extends to the n + type drain contact region 14. Therefore, the extension portion 25B extends, for example, from the n + type drain contact region 14 to the n +The location can be anywhere between the outer periphery of the drain contact region 14 and the inner periphery of the p-type element separation region 7 on its outer side, or it can extend to a position further outward than the inner periphery of the p-type element separation region 7.

[0077] When wiring of components other than DMOS transistor 40 (hereinafter referred to as "other wiring") passes above component region 2, the potential of the other wiring affects the potential of n. - When a reverse voltage is applied to the parasitic diode between the p-type epitaxial layer 5 and the p-type element separation region 7, the equipotential distribution will become disordered, potentially leading to a decrease in withstand voltage. If the potential of other wirings is the same as the potential (drain voltage) of element region 2, the aforementioned equipotential distribution will not be disordered. However, if the potential of other wirings is grounded, the aforementioned equipotential distribution will become disordered.

[0078] In this embodiment, an extension (voltage-enhancing wiring) 25B covering at least a portion of the component terminal region 30 is formed on the drain wiring 25. This allows for a structure where the wiring (voltage-enhancing wiring) at the same potential as the component region 2 is disposed on the component terminal region 30, thus suppressing the influence of the potential of other wirings even when their potentials are grounded. Therefore, when the potentials of other wirings are grounded, the aforementioned disturbances in the equipotential distribution can be suppressed, and the decrease in the breakdown voltage of the DMOS transistor 40 can be suppressed, or the breakdown voltage can be increased.

[0079] Will Figure 1 and Figure 2 The semiconductor device 1 is referred to as "this embodiment" and will be used in this embodiment. Figure 1 and Figure 2 In the semiconductor device 1, the structure in which the drain wiring 25 does not have an extension portion 25B is called a "comparative example". That is, in the comparative example, the drain wiring 25 is only composed of the main wiring portion 25A of this embodiment.

[0080] First, such as Figure 3 As shown, regarding the comparative example, the withstand voltage of the comparative example was calculated using a first simulation model 101 with an additional wiring 50 (hereinafter referred to as "GND wiring") having a potential of ground on the component terminal region 30. Figure 3 In the middle, regarding the above-mentioned Figure 2 Corresponding annotations and Figure 2 The same reference numerals are used to indicate the components. Additionally, regarding the comparative example, a second simulation model without a GND wiring on the component terminal area 30 was used to calculate the withstand voltage of the comparative example.

[0081] Specifically, make the application to n - Type epitaxial layer 5(n) +the reverse voltage of the parasitic diode present between the p-type drain contact region 14) and the p-type element separation region 7 is V epi [V]. In addition, the reverse current flowing in the parasitic diode is I epi [A] when the reverse voltage V epi is gradually increased. The reverse current I epi .

[0082] Similarly, with respect to the present embodiment, the withstand voltage of the present embodiment was calculated using a third simulation model in which a GND wiring was provided on the element terminal region 30. In addition, with respect to the present embodiment, the withstand voltage of the present embodiment was calculated using a fourth simulation model in which no GND wiring was provided.

[0083] Figure 4 is a graph showing the simulation results with respect to the comparative example. In Figure 4 , the dashed line is a graph showing the simulation results in the case where the GND wiring is present, and the solid line is a graph showing the simulation results in the case where the GND wiring is not present.

[0084] Figure 5 is a graph showing the simulation results with respect to the present embodiment. In Figure 5 , the dashed line is a graph showing the simulation results in the case where the GND wiring is present, and the solid line is a graph showing the simulation results in the case where the GND wiring is not present.

[0085] Referring to Figure 4 , in the comparative example, the breakdown voltage in the case where the GND wiring is present is lower than in the case where the GND wiring is not present. In addition, in the comparative example, the absolute value difference of the breakdown voltage in the case where the GND wiring is present and the breakdown voltage in the case where the GND wiring is not present is large.

[0086] On the other hand, referring to Figure 5 , in the present embodiment, the breakdown voltage in the case where the GND wiring is present and the breakdown voltage in the case where the GND wiring is not present become approximately equal. Furthermore, the breakdown voltage in the case where the GND wiring is not present in the present embodiment is higher than the breakdown voltage in the case where the GND wiring is not present in the comparative example.

[0087] That is, in the present embodiment, the withstand voltage in the case where the other wiring of the ground potential is present and the withstand voltage in the case where the other wiring of the ground potential is not present are approximately equal. In other words, in the present embodiment, the withstand voltage of the DMOS transistor does not decrease much even if the other wiring of the ground potential is present.

[0088] Furthermore, in this embodiment, the withstand voltage is higher than that of the comparative example when other wiring has a ground potential. Also, in this embodiment, the withstand voltage is higher than that of the comparative example when other wiring does not have a ground potential.

[0089] Furthermore, the same simulation was performed by varying the outward protrusion of the extension portion (voltage-enhancing wiring) 25B in this embodiment. The result was that, in both cases, the absolute difference in breakdown voltage between the presence and absence of the GND wiring was smaller compared to the comparative example. Additionally, when viewed from above, n + When the distance from the outer periphery of the drain contact area 14 to the inner periphery of the p-type element separation area 7 is L, the withstand voltage becomes maximum when the outward protrusion of the extension (voltage-enhancing wiring) 25B is half of L (0.5L).

[0090] Next, refer to Figures 6A-6G The manufacturing process of semiconductor device 1 will be explained. Figures 6A-6G This is a cross-sectional view illustrating an example of the manufacturing process of semiconductor device 1, and is related to... Figure 2 The cross-sectional view corresponding to the cutting section.

[0091] When manufacturing semiconductor device 1, such as Figure 6A As shown, a p-type semiconductor substrate 4 is prepared. Next, n-type impurities and p-type impurities are selectively implanted onto the surface of the p-type semiconductor substrate 4. Furthermore, silicon is epitaxially grown on the p-type semiconductor substrate 4 while adding n-type impurities, for example, under a heating condition of 1100°C or higher. Thus, as... Figure 6B As shown, a p-type semiconductor substrate 4 and an n-type semiconductor substrate are formed. - The substrate 3 of the epitaxial layer 5.

[0092] During epitaxial growth, n-type impurities and p-type impurities implanted into the p-type semiconductor substrate 4... - The epitaxial layer 5 diffuses along its growth direction. This forms a layer spanning the p-type semiconductor substrate 4 and the n-type substrate 5. - n of the boundary of the type epitaxial layer 5 + The p-type embedded layer 6 and the lower separation region 8 are also present. Furthermore, examples of p-type impurities include B (boron) and Al (aluminum), and examples of n-type impurities include P (phosphorus) and As (arsenic).

[0093] Next, as Figure 6C As shown, in n - An ion implantation mask (not shown) is selectively formed on the epitaxial layer 5 in the region of the upper separation region 9 where the p-type impurity is to be formed. Furthermore, p-type impurities are implanted into the n-type epitaxial layer via this ion implantation mask. -P-type epitaxial layer 5. This forms a p-type element separation region 7, consisting of a lower separation region 8 and an upper separation region 9, with two layers. Then, the ion implantation mask is removed.

[0094] Next, in n - A hard mask 51, selectively having openings in the regions where field insulating films 11 and 12 are to be formed, is formed on the epitaxial layer 5. Furthermore, via the hard mask 51, in n - The surface of the epitaxial layer 5 is subjected to thermal oxidation treatment to form field insulating films 11 and 12. Afterwards, the hard mask 51 is removed.

[0095] Next, as Figure 6D As shown, in n - A gate insulating film 18 is formed by thermal oxidation of the surface of the epitaxial layer 5. At this time, the gate insulating film 18 is formed in connection with the field insulating films 11 and 12. Next, in the n... - Polysilicon for the gate electrode 19 is deposited on the epitaxial layer 5 to form a polysilicon layer 52.

[0096] Next, as Figure 6E As shown, a photoresist mask (not shown) with selective openings is formed on the polysilicon layer 52 in the region where the gate electrode 19 is to be formed. Unwanted portions of the polysilicon layer 52 are removed by etching through this photoresist mask. Thus, the gate electrode 19 is formed. Afterward, the photoresist mask is removed.

[0097] Next, in order to remove the unwanted portions of the gate insulating film 18, in n - A hard mask with selective openings (not shown) is formed on the epitaxial layer 5. Unwanted portions of the gate insulating film 18 are then etched through this hard mask. This forms the desired gate insulating film 18. The hard mask is then removed. Alternatively, the process of selectively etching the gate insulating film 18 can be omitted.

[0098] Next, as Figure 6F As shown, in n - A p-type well region 15 is formed on the surface portion of the epitaxial layer 5. When forming the p-type well region 15, firstly, an ion implantation mask (not shown) is formed in the region where the p-type well region 15 is to be formed. Then, n... - A p-type impurity is implanted into the epitaxial layer 5. Then, the p-type impurity is thermally diffused at a temperature of, for example, 900°C to 1100°C. This forms a p-type well region 15. Afterward, the ion implantation mask is removed.

[0099] Alternatively, it can be done before forming the gate insulating film 18 and the gate electrode 19 ( Figure 6C In the stage of ), p-type impurities are selectively injected into n- The epitaxial layer 5 forms a p-type well region 15.

[0100] Next, in n - While an n-type drain region 13 is formed on the surface portion of the epitaxial layer 5, an n-type source region 16 is formed in the inner region (surface portion) of the p-type well region 15. When forming the n-type drain region 13 and the n-type source region 16, firstly, ion implantation masks (not shown) are formed, selectively having openings in the regions where the n-type drain region 13 and the n-type source region 16 are to be formed. Furthermore, the n-type source region 16 is then implanted through these ion implantation masks. - An n-type impurity is implanted into the epitaxial layer 5. This forms an n-type drain region 13 and an n-type source region 16. The ion implantation mask is then removed.

[0101] Next, n-type drain region 13 and n-type source region 16 are selectively formed in their inner regions (surface layers). + Type Drain Contact Regions 14 and n + Source electrode contact region 17. In forming n + Type Drain Contact Regions 14 and n + When the source electrode contact region is 17, firstly, n is formed in the area to be formed. + Type Drain Contact Regions 14 and n + The n-type source contact region 17 is selectively equipped with an ion implantation mask (not shown). Furthermore, n-type impurities are implanted into the n-type drain region 13 and the n-type source region 16 via this ion implantation mask. This forms an n-type source contact region 16. + Type Drain Contact Regions 14 and n + Source contact region 17. Then, the ion implantation mask is removed.

[0102] Next, as Figure 6G As shown, an interlayer insulating film 21 is formed by depositing insulating material to cover the gate electrode 19. Next, a drain contact plug 22, a source contact plug 23, and a gate contact plug 24 are formed to penetrate the interlayer insulating film 21. The drain contact plug 22, the source contact plug 23, and the gate contact plug 24 are respectively connected to n... + Type Drain Contact Region 14, n + The source contact region 17 and the gate electrode 19 are electrically connected respectively.

[0103] Finally, a drain wiring 25, a source wiring 26, and a gate wiring (omitted from illustration) are selectively formed on the interlayer insulating film 21 so as to be electrically connected to the drain contact plug 22, the source contact plug 23, and the gate contact plug 24, respectively. In forming the drain wiring 25, the source wiring 26, and the gate wiring, for example, a wiring material layer is formed on the interlayer insulating film 21. Also, the wiring material layer is selectively removed by photolithography and etching, thereby forming the drain wiring 25, the source wiring 26, and the gate wiring. Through the above procedures, the semiconductor device 1 of the first embodiment can be manufactured.

[0104] Next, with reference to Figure 7 and Figure 8 , the semiconductor device 1A of the second embodiment of the present application will be described. Figure 7 is a diagrammatic plan view for explaining the structure of the semiconductor device of the second embodiment of the present application. Figure 8 is a diagrammatic cross-sectional view along the line VIII-VIII of Figure 7 . In Figure 7 , the interlayer insulating film 21, the drain wiring 25, and the source wiring 26 shown in Figure 8 are omitted. However, the voltage improvement wiring 65 shown in Figure 7 is illustrated in Figure 8 .

[0105] In Figure 7 , the same reference numerals as those of Figure 1 are attached to portions corresponding to respective parts of Figure 1 to indicate. In Figure 8 , the same reference numerals as those of Figure 2 are attached to portions corresponding to respective parts of Figure 2 to indicate.

[0106] In the semiconductor device 1A of the second embodiment, the structure of the voltage improvement wiring is different from that of the semiconductor device 1 of the first embodiment described above. In the semiconductor device 1 of the first embodiment, the voltage improvement wiring is constituted by the extension portion 25B of the drain wiring 25. In the semiconductor device 1A of the second embodiment, the voltage improvement wiring is provided separately from and independently of the drain wiring 25.

[0107] In the second embodiment, the inner periphery of the field insulating film 11 covering the surface of the p-type element separation region 7 is located, in plan view, at a position outward of the outer periphery of the n + -type drain contact region 14 by only a certain distance.

[0108] In plan view, in a region between the n-type drain region 13 and the field insulating film 11, the n - -type epitaxial layer 5 is formed with the n-type region 61 spaced apart from the n-type drain region 13.

[0109] When viewed from above, the n-type region 61 is formed in a quadrilateral ring shape along the field insulating film 11, surrounding the n-type drain region 13. The impurity concentration of the n-type region 61 is approximately equal to that of the n-type drain region 13. On the surface of the n-type region 61, an n-type region with a higher impurity concentration than the n-type region 61 is formed for improving withstand voltage and wiring. + Type contact area 62. n + The impurity concentration in contact region 62 and n + The impurity concentrations in the drain contact region 14 are approximately equal.

[0110] In n - On the surface of the epitaxial layer 5, in n + Type contact area 62 and n + A field insulating film 63, which is quadrilateral-shaped when viewed from above, is formed in the portion between the drain contact regions 14. The field insulating film 63 is a LOCOS film formed in the same process as the field insulating films 11 and 12 described above.

[0111] In the interlayer insulating film 21, in addition to the drain contact plug 22, the source contact plug 23, and the gate contact plug 24, a contact plug 64 for improving withstand voltage wiring is also embedded. The lower end of the contact plug 64 is connected to n + Type 62 contact area is electrically connected.

[0112] On the interlayer insulating film 21, not only are drain wiring 25, source wiring 26, and gate wiring (not shown), but also breakdown voltage improvement wiring 65 is formed. Figure 7 In the diagram, the area of ​​the voltage-enhancing wiring 65 is represented by a shaded area. In the second embodiment, the drain wiring 25 is composed only of the main wiring portion 25A of the drain wiring 25 in the first embodiment. The voltage-enhancing wiring 65 is electrically connected to n via a plurality of contact plugs 64. + Type contact area 62.

[0113] When viewed from above, the withstand voltage improved wiring 65 is formed as a quadrilateral ring surrounding the field insulation film 63. In this embodiment, the inner periphery of the withstand voltage improved wiring 65 is located at n + The inner periphery of the contact area 62 is approximately directly above n. The inner periphery of the voltage-enhanced wiring 65, when viewed from above, can also be located closer to n. + The location of the outer periphery of the drain contact area 14. The outer periphery of the withstand voltage improvement wiring 65 is located at a position greater than n. + The outer periphery of the contact area 62 is located towards the outer edge. In this embodiment, the outer periphery of the withstand voltage improvement wiring 65, when viewed from above, is located at n... + The position between the outer periphery of the contact area 62 and the inner periphery of the p-type element separation area 7 on its outer side.

[0114] That is, the withstand voltage improved wiring 65 is the peripheral area of ​​component region 2, to cover n + The component terminal region 30 is configured such that a portion (in this example, the middle of the width) between the outer periphery of the p-type drain contact region 14 and the inner periphery of the outer p-type component separation region 7 is connected.

[0115] In this embodiment, a withstand voltage improvement wiring 65 is provided that covers at least a portion of the component terminal region 30. This allows for a structure where the withstand voltage improvement wiring 65, with the same potential as component region 2, is disposed on the component terminal region 30. Therefore, even if the potential of other wirings is grounded, the influence of the potential of other wirings can be suppressed. Thus, even if the potential of other wirings is grounded, the influence of the potential of n can be suppressed. - The parasitic diode existing between the p-type epitaxial layer and the p-type element separation region 7 causes equipotential distribution disturbance when a reverse voltage is applied. This can suppress the decrease in the breakdown voltage of the DMOS transistor 40 or increase its breakdown voltage.

[0116] Next, refer to Figures 9A-9E The manufacturing process of semiconductor device 1A is explained. Figures 9A-9E This is a cross-sectional view illustrating an example of the manufacturing process of semiconductor device 1A, and is related to... Figure 8 The cross-sectional view corresponding to the cutting section.

[0117] In the manufacturing method of this semiconductor device 1A, similarly to the manufacturing method of the semiconductor device 1 described above, as follows: Figure 6A A p-type semiconductor substrate 4 is prepared as shown. Furthermore, after selectively implanting n-type and p-type impurities onto the surface of the p-type semiconductor substrate 4, silicon is epitaxially grown on the p-type semiconductor substrate 4 while adding n-type impurities, for example, under a heating environment of 1100°C or higher. Thus, as... Figure 6B As shown, a p-type semiconductor substrate 4 and an n-type semiconductor substrate are formed. - The substrate 3 of the p-type epitaxial layer 5. Furthermore, a transp-type semiconductor substrate 4 and an n-type semiconductor substrate 5 are thus formed. - n of the boundary of the type epitaxial layer 5 + Type 6 buried layer and type 8 lower separation area.

[0118] Next, as Figure 9A As shown, in n - An ion implantation mask (not shown) is selectively formed on the epitaxial layer 5 in the region of the upper separation region 9 where the p-type is to be formed. Furthermore, the n-type is then implanted through this ion implantation mask. - A p-type impurity is implanted into the epitaxial layer 5. This forms a p-type element separation region 7, consisting of a lower separation region 8 and an upper separation region 9, which are two layers in total. The ion implantation mask is then removed.

[0119] Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed. - Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed. - Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed.

[0120] Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed. Figure 9B Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed. - Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed. - Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed.

[0121] Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed. Figure 9C Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed.

[0122] Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed. - Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed.

[0123] Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed. Figure 9D Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed. - Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed. - Next, as shown in Fig. 1, a hard mask 71 having an opening selectively in a region where the field insulating film 11, 12, 63 is to be formed is formed on the n-type epitaxial layer 5. Further, an unnecessary portion of the n-type epitaxial layer 5 is removed by etching through the hard mask 71. Thus, the n-type well region 10 is formed. Thereafter, the hard mask 71 is removed.

[0124] Further, the p-type well region 15 can be formed by selectively implanting the p-type impurity into the n-type epitaxial layer 5 at a stage prior to formation of the gate insulating film 18 and the gate electrode 19. Figure 9A - Further, the p-type well region 15 can be formed by selectively implanting the p-type impurity into the n-type epitaxial layer 5 at a stage prior to formation of the gate insulating film 18 and the gate electrode 19. Further, the p-type well region 15 can be formed by selectively implanting the p-type impurity into the n-type epitaxial layer 5 at a stage prior to formation of the gate insulating film 18 and the gate electrode 19.

[0125] Next, in the n - The n-type drain region 13 and the n-type region 61 are formed in the surface layer portion of the n

[0126] That is, first, ion implantation masks (not shown) having openings are formed selectively in regions where the n - type epitaxial layer 5. Thus, the n-type drain region 13, the n-type region 61, and the n

[0127] Next, in the inner regions (surface layer portions) of the n + type drain contact region 14, the n + type contact region 62, and the n + type source contact region 17 are formed selectively. The n + type drain contact region 14, the n + type contact region 62, and the n + type source contact region 17 are formed, for example, as follows.

[0128] That is, first, ion implantation masks (not shown) having openings are formed selectively in regions where the n + type drain contact region 14, the n + type contact region 62, and the n + type source contact region 17 are formed. Then, n-type impurities are implanted into the n + type drain contact region 14, the n + type contact region 62, and the n + type source contact region 17. Thereafter, the ion implantation masks are removed.

[0129] Next, as shown in Figure 9E The interlayer insulating film 21 is formed by depositing an insulating material so as to cover the gate electrode 19. Then, the contact plug 64, the drain contact plug 22, the source contact plug 23, and the gate contact plug 24 are formed so as to penetrate the interlayer insulating film 21. The contact plug 64, the drain contact plug 22, the source contact plug 23, and the gate contact plug 24 are electrically connected to the n + type contact region 62, the n +p-type drain contact region 14, n + p-type source contact region 17 and each of gate electrode 19.

[0130] Finally, a voltage sustaining improving wiring 65, a drain wiring 25, a source wiring 26 and a gate wiring (omitted from illustration) which are electrically connected to the contact plug 64, the drain contact plug 22, the source contact plug 23 and the gate contact plug 24, respectively, are selectively formed on the interlayer insulating film 21. In forming the voltage sustaining improving wiring 65, the drain wiring 25, the source wiring 26 and the gate wiring, for example, a wiring material layer is formed on the interlayer insulating film 21. Then, the wiring material layer is selectively removed by photolithography and etching, thereby forming the voltage sustaining improving wiring 65, the drain wiring 25, the source wiring 26 and the gate wiring. Through the above processes, the semiconductor device 1A of the second embodiment can be manufactured.

[0131] Next, with reference to Figure 10 and Figure 11 , the semiconductor device 1B of the third embodiment of the present application will be described. Figure 10 is a diagrammatic plan view for explaining the structure of the semiconductor device of the third embodiment of the present application. Figure 11 is a diagrammatic cross-sectional view along XI-XI line of Figure 10 In Figure 10 , the interlayer insulating film 21, the drain wiring 25 and the source wiring 26 shown in Figure 11 are omitted. However, the voltage sustaining improving wiring 81 shown in Figure 10 is indicated in Figure 11 .

[0132] In Figure 10 , the same reference numerals as those of Figure 1 are attached to portions corresponding to each part of the above-mentioned Figure 1 . In Figure 11 , the same reference numerals as those of Figure 2 are attached to portions corresponding to each part of the above-mentioned Figure 2 .

[0133] In the semiconductor device 1B of the third embodiment, the structure of the voltage sustaining improving wiring is different from that of the semiconductor device 1 of the above-mentioned first embodiment. In the semiconductor device 1 of the first embodiment, the voltage sustaining improving wiring is constituted by the extension portion 25B of the drain wiring 25. In the semiconductor device 1B of the third embodiment, the voltage sustaining improving wiring is provided separately from and independently of the drain wiring 25. However, in this third embodiment, the drain wiring 25 has the extension portion 25B which functions also as the voltage sustaining improving wiring, like the first embodiment.

[0134] In the third embodiment, a withstand voltage improved wiring 81 is formed on the field insulating film 11. Figure 10 In the diagram, the area of ​​the voltage-strength improved wiring 81 is represented by the shaded area of ​​the point. When viewed from above, the voltage-strength improved wiring 81 is surrounded by a circle. + The drain contact region 14 is formed in a quadrilateral ring shape along the p-type element separation region 7. In this embodiment, the withstand voltage improvement wiring 81 is made of polysilicon. The withstand voltage improvement wiring 81 is covered by an interlayer insulating film 21.

[0135] The voltage-resistant improved wiring 81 forms a shape that is more than n when viewed from above. + The drain contact area 14 is located on the outer side. In this embodiment, the inner periphery of the withstand voltage improvement wiring 81 is located from n when viewed from above. + The drain contact area 14 is located only a certain distance away from the outside. Furthermore, the inner periphery of the withstand voltage improvement wiring 81 can also be located at n... + The outer periphery of the p-type drain contact area 14 is directly above it. On the other hand, the outer periphery of the withstand voltage improvement wiring 81 is located inside the inner periphery of the p-type component separation area 7.

[0136] That is, the withstand voltage improved wiring 81 is the peripheral area of ​​component region 2, to cover n + The component terminal region 30 is configured such that a portion (in this example, the middle of the width) between the outer periphery of the p-type drain contact region 14 and the inner periphery of the outer p-type component separation region 7 is connected.

[0137] Drain wiring 25 is configured in n + The main wiring portion 25A is located directly above the drain contact area 14, and an extension portion 25B extends outward from the outer periphery of the main wiring portion 25A. When viewed from above, the extension portion 25B has an overlap portion that overlaps with the surface of the withstand voltage improvement wiring 81. Multiple contact plugs 82 are embedded in the interlayer insulating film 21 for electrically connecting the overlap portion of the extension portion 25B to the withstand voltage improvement wiring 81.

[0138] The withstand voltage improvement wiring 81 is electrically connected to the drain wiring 25 via multiple contact plugs 82. Therefore, the withstand voltage improvement wiring 81 is electrically connected to n via contact plugs 82, drain wiring 25, and drain contact plugs 22. - Type epitaxial layer 5.

[0139] In this embodiment, a withstand voltage improvement wiring 81 is provided that covers at least a portion of the component terminal region 30. This allows for a structure where the withstand voltage improvement wiring 81, with the same potential as component region 2, is disposed on the component terminal region 30. Therefore, even if the potential of other wirings is grounded, the influence of the potential of other wirings can be suppressed. Thus, even if the potential of other wirings is grounded, the influence on n can be suppressed. -The parasitic diodes present between the p-type epitaxial layer and the p-type element separation region 7 exhibit equipotential distribution disturbances when a reverse voltage is applied. This allows for the suppression of voltage reduction or the increase of voltage withstand capability in the DMOS transistor 40.

[0140] Next, refer to Figures 12A-12C The manufacturing process of semiconductor device 1B will be explained. Figures 12A-12C This is a cross-sectional view illustrating an example of the manufacturing process of semiconductor device 1B, and is related to... Figure 11 The cross-sectional view corresponding to the cutting section.

[0141] The above Figures 6A-6D The same process applies to the manufacturing method of semiconductor device 1B. Through Figure 6D The process involves polycrystalline silicon being deposited on n - When a polysilicon layer 52 is formed on the epitaxial layer 5, such as Figure 12A As shown, resist masks (not shown) are selectively formed on the polysilicon layer 52 in the regions where the gate electrode 19 is to be formed and the breakdown voltage improvement wiring 81 is to be formed, respectively. Then, unwanted portions of the polysilicon layer 52 are removed by etching through the resist mask. Thus, the gate electrode 19 and the breakdown voltage improvement wiring 81 are formed simultaneously. Afterward, the resist mask is removed.

[0142] Next, in order to remove the unwanted portions of the gate insulating film 18, in n - A hard mask with selective openings (not shown) is formed on the epitaxial layer 5. Unwanted portions of the gate insulating film 18 are then etched through this hard mask. This forms the desired gate insulating film 18. The hard mask is then removed. Alternatively, the selective etching process of the gate insulating film 18 can be omitted.

[0143] Next, as Figure 12B As shown, in n - A p-type well region 15 is formed on the surface of the epitaxial layer 5. When forming the p-type well region 15, firstly, an ion implantation mask (not shown) is formed in the region where the p-type well region 15 is to be formed. Then, an ion implantation mask is applied to the n-type epitaxial layer through this ion implantation mask. - A p-type impurity is implanted into the epitaxial layer 5. Then, for example, at a temperature of 900°C to 1100°C, the p-type impurity is thermally diffused. This forms a p-type well region 15. Afterward, the ion implantation mask is removed.

[0144] Alternatively, it can be done before forming the gate insulating film 18 and the gate electrode 19 ( Figure 6C In the stage of ), p-type impurities are selectively injected into n - The epitaxial layer 5 forms a p-type well region 15.

[0145] Next, in n - While an n-type drain region 13 is formed on the surface portion of the epitaxial layer 5, an n-type source region 16 is formed in the inner region (surface portion) of the p-type well region 15. When forming the n-type drain region 13 and the n-type source region 16, firstly, ion implantation masks (not shown) are formed, selectively having openings in the regions where the n-type drain region 13 and the n-type source region 16 are to be formed. Then, the n-type source region 16 is implanted through these ion implantation masks. - An n-type impurity is implanted into the epitaxial layer 5. This forms an n-type drain region 13 and an n-type source region 16. The ion implantation mask is then removed.

[0146] Next, n-type drain region 13 and n-type source region 16 are selectively formed in their inner regions (surface layers). + Type Drain Contact Regions 14 and n + Source electrode contact region 17. In forming n + Type Drain Contact Regions 14 and n + When the source electrode contact region is 17, firstly, n is formed in the area to be formed. + Type Drain Contact Regions 14 and n + The n-type source contact region 17 is selectively equipped with an ion implantation mask (not shown). Furthermore, n-type impurities are implanted into the n-type drain region 13 and the n-type source region 16 via this ion implantation mask. This forms an n-type source contact region 16. + Type Drain Contact Regions 14 and n + Source contact region 17. Then, the ion implantation mask is removed.

[0147] Next, as Figure 12C As shown, an interlayer insulating film 21 is formed by depositing insulating material to cover the gate electrode 19 and the withstand voltage improvement wiring 81. Next, a drain contact plug 22, a source contact plug 23, a gate contact plug 24, and a contact plug 82 are formed through the interlayer insulating film 21. The drain contact plug 22, source contact plug 23, gate contact plug 24, and contact plug 82 are electrically connected to n... + Type Drain Contact Region 14, n + Each of the source contact region 17, the gate electrode 19, and the withstand voltage improvement wiring 81.

[0148] Finally, a drain wiring 25, a source wiring 26, and a gate wiring (omitted from illustration) are selectively formed on the interlayer insulating film 21. The drain wiring 25 is electrically connected to the drain contact plug 22 and the voltage-withstanding improvement wiring contact plug 82. The source wiring 26 and the gate wiring are electrically connected to the source contact plug 23 and the gate contact plug 24, respectively. Through the above procedures, the semiconductor device 1B of the third embodiment can be manufactured.

[0149] The embodiments of the present application have been described in detail, but these are only specific examples used to make the technical contents of the present application clear, the present application is not limited to these specific examples for explanation, the scope of the present application is only defined by the scope of the appended technical solutions.

[0150] This application corresponds to Japanese Patent Application No. 2020-44368 filed with the Japan Patent Office on March 13, 2020, the entire disclosure of which is hereby incorporated by reference.

[0151] Explanation of Reference Signs

[0152] 1, 1A, 1B Semiconductor device

[0153] 2 Element region

[0154] 3 Base

[0155] 4 P-type semiconductor substrate

[0156] 5 N - type epitaxial layer

[0157] 6 N + type buried layer

[0158] 7 P-type element separation region

[0159] 8 Lower side separation region

[0160] 9 Upper side separation region

[0161] 11 Field insulating film

[0162] 12 Field insulating film

[0163] 13 N-type drain region

[0164] 14 N + type drain contact region

[0165] 15 P-type well region

[0166] 16 N-type source region

[0167] 17 N + type source contact region

[0168] 18 gate insulating film

[0169] 19 gate electrode

[0170] 20 channel region

[0171] 21 interlayer insulating film

[0172] 22 contact plug for drain

[0173] 23 contact plug for source

[0174] 24 contact plug for gate

[0175] 25 drain wiring

[0176] 25A main wiring portion

[0177] 25B extension portion (voltage improvement wiring)

[0178] 26 source wiring

[0179] 30 element terminal region

[0180] 40 DMOS transistor

[0181] 51, 71 hard mask

[0182] 52, 72 polysilicon layer

[0183] 61 n-type region

[0184] 62 n + type contact region

[0185] 63 field insulating film

[0186] 64, 82 contact plug

[0187] 65, 81 voltage improvement wiring

Claims

1. A semiconductor device, characterized by, including: a base including a p-type substrate and an n-type semiconductor layer formed on the p-type substrate, and including an element region having a transistor with the n-type semiconductor layer as a drain; a p-type element isolation region formed in a surface layer portion of the base in a manner of defining the element region; and a conductive wiring disposed on a peripheral portion of the element region and electrically connected to the n-type semiconductor layer, the transistor includes an n-type drain contact region formed in a surface layer portion of the n-type semiconductor layer in a peripheral portion of the element region, the semiconductor device further includes a drain wiring electrically connected to the n-type drain contact region, the conductive wiring is disposed in a manner of covering at least a portion of an element terminal region between the n-type drain contact region and the p-type element isolation region, and is disposed in a manner of being spaced apart from the drain wiring by a gap, in the element terminal region, an n-type contact region for the conductive wiring is formed in a surface layer portion of the n-type semiconductor layer, the conductive wiring is electrically connected to the n-type contact region via a conductive member.

2. The semiconductor device according to claim 1, wherein: the n-type drain contact region is formed in a ring shape in plan view, the n-type contact region and the conductive wiring are each formed in a ring shape in plan view in a manner of surrounding the n-type drain contact region.

3. A semiconductor device, characterized by, including: a base including a p-type substrate and an n-type semiconductor layer formed on the p-type substrate, and including an element region having a transistor with the n-type semiconductor layer as a drain; a p-type element isolation region formed in a surface layer portion of the base in a manner of defining the element region; and a conductive wiring disposed on a peripheral portion of the element region and electrically connected to the n-type semiconductor layer, the transistor includes an n-type drain contact region formed in a surface layer portion of the n-type semiconductor layer in a peripheral portion of the element region, the conductive wiring is disposed in a manner of covering at least a portion of an element terminal region between the n-type drain contact region and the p-type element isolation region, the semiconductor device includes a drain wiring electrically connected to the n-type drain contact region, the conductive wiring is formed on the n-type semiconductor layer within the element terminal region via an insulating layer, the drain wiring has an overlapping portion overlapping a portion of the conductive wiring in plan view, the semiconductor device further includes a conductive member electrically connecting a lower surface of the overlapping portion of the drain wiring and an upper surface of the conductive wiring.

4. The semiconductor device according to claim 3, wherein: the n-type drain contact region and the drain wiring are formed in a ring shape in plan view, the conductive wiring is formed in a ring shape in plan view in a manner of surrounding the n-type drain contact region, the drain wiring has the overlapping portion in an outer peripheral portion thereof, a lower surface of the overlapping portion and an inner peripheral portion of an upper surface of the conductive wiring are electrically connected by the conductive member.

5. The semiconductor device according to claim 3 or 4, wherein: the conductive wiring is constituted by polysilicon.

6. The semiconductor device according to any one of claims 1 to 4, wherein: an n-type buried layer is formed across a boundary between the p-type substrate and the n-type semiconductor layer in a central portion of the element region in plan view.

7. The semiconductor device according to any one of claims 1 to 4, wherein: the p-type element isolation region is formed in a ring shape surrounding the element region in plan view, and the n-type drain contact region is formed in a ring shape along the p-type element isolation region in plan view.

8. The semiconductor device according to any one of claims 1 to 7, comprising: a base including a p-type substrate and an n-type semiconductor layer formed on the p-type substrate, and including an element region having a transistor with the n-type semiconductor layer as a drain; a p-type element isolation region formed in a surface layer portion of the base in a manner defining the element region; and a conductive wiring disposed on a peripheral portion of the element region and electrically connected to the n-type semiconductor layer, the transistor including an n-type drain contact region formed in a surface layer portion of the n-type semiconductor layer in a peripheral portion of the element region, the semiconductor device further including a drain wiring electrically connected to the n-type drain contact region, the conductive wiring being disposed in a manner covering at least a portion of an element terminal region between the n-type drain contact region and the p-type element isolation region, and being disposed in a manner spaced apart from the drain wiring, the transistor including: a p-type well region formed in a surface layer portion of the n-type semiconductor layer; an n-type source region formed in a surface layer portion of the p-type well region; an n-type source contact region formed in a surface layer portion of the n-type source region and having a higher n-type impurity concentration than the n-type source region; and an n-type drain region formed in a surface layer portion of the n-type semiconductor layer in a ring shape surrounding the p-type well region, the n-type drain contact region being formed in a surface layer portion of the n-type drain region in a manner surrounding the p-type well region, and having a higher n-type impurity concentration than the n-type drain region.

9. The semiconductor device according to claim 8, wherein: the transistor further includes: a gate insulating film formed in a manner covering a channel region between the source contact region and the drain contact region; and a gate electrode formed on the gate insulating film and opposing the channel region through the gate insulating film.

10. The semiconductor device according to claim 8 or 9, comprising a source wiring electrically connected to the n-type source contact region.

8. A semiconductor device, characterized by ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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