FPGA-Based DDR3 Physical Layer Calibration Method

Abstract

A DDR3 physical layer calibration method based on FPGA, which relates to integrated circuit technology. The present invention includes the following steps: (1) Recover the read sampling clock: Extract the read sampling clock that is of the same frequency and phase as the read DQS from the DQS sent by the chip and the divided-by-two clock obtained by dividing it; (2) Determine the delay period between sending a read command to the chip and receiving data; (3) Calibrate the trace delay difference; (4) Write regular numbers to the chip; (5) Read channel training calibration: Read the regular numbers written in step (4) from the chip, adjust the read sampling clock and the delay of each bit within the DQ group so that each bit of the DQ data is right-aligned and the read sampling clock is at the center of the stable region port. The technology of the present invention has wide applications and high calibration accuracy.

Description

Technical Field

[0001] The present invention relates to integrated circuit technology, and particularly to FPGA. Background Art

[0002] The multi-purpose register (MPR) function is used to read a predefined sequence of timing calibration bits with a predefined 01010101 sequence. The physical layer phy calibration scheme of the DDR3 controller core on the market is also based on this technology to achieve calibration in the read direction. Specifically, the controller at the FPGA end reads the predefined sequence from the DDR3 chip, and then adjusts the phase of the physical layer on the FPGA to align the trigger edge of the read sampling clock signal with the center of the read data window. This calibration method not only requires configuring the mode register and relying on the MPR mode entering the DDR3 chip, but also because the continuously read-back data changes once every half of the chip working clock cycle, if the adjustment of the delay chain of the read-back data is too large, in the case of leading or lagging the read sampling clock by N cycles, the sampled data is the same, and it is not easy to feedback the position of the sampling clock in the read data window by controlling the data delay chain and the sampling clock delay amount; and for some types of chips, only the MPR sequence read-back data exists on DQ[0] of the data in the MPR mode, and other bit positions are 0; to adjust the skew (offset) between data bits, it is necessary to complete the skew calibration between bits by reading back the data written into the DDR3 chip after the write direction calibration is completed. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a complete calibration process for the DDR3 physical layer on the FPGA that does not rely on the MPR mode, so as to achieve more efficient and accurate training of the read and write data channels of the DDR3 physical layer, and to adjust the skew between the read and write data bits.

[0004] The technical solution adopted by the present invention to solve the above technical problem is a DDR3 physical layer calibration method based on FPGA, which is characterized by including the following steps:

[0005] (1) Recover the read sampling clock: Extract the read sampling clock with the same frequency and phase as the read DQS from the DQS sent by the chip and the divided-by-two clock obtained by dividing it.

[0006] (2) Determine the delay period between sending a read command to the chip and receiving the data.

[0007] (3) Calibrate the difference in trace delay.

[0008] (4) Write regular numbers to the chip.

[0009] (5) Read channel training and calibration: Read the regular numbers written in step 4) from the particles, and adjust the read sampling clock and the delay of each bit within the DQ group to make each bit of the DQ data right-aligned, and the read sampling clock is at the central position of the stable region;

[0010] (6) Write channel calibration: Adjust the data write clock and the position of the data to make the write point at the center of the write window;

[0011] The DQ is data, and the DQS is the data clock.

[0012] Further, in step 4), by using a preset large delay between the write command sending and the write data sending, write data of all 1s or all 0s to the same address in burst multiple times.

[0013] The said step 5) includes:

[0014] 5.1 Read the written fixed numbers,

[0015] 5.2 Adjust the delay of the DQS to find the stable region of the DQ level,

[0016] 5.3 Calculate the central position of the stable region as the sampling point.

[0017] The said step 6) includes:

[0018] 6.1 Write the jump feature numbers to the particles. The jump feature numbers refer to the data that can identify the offset. For example, for 01110110, when it is shifted one bit to the left to become 1110110X (X is any number), and shifted one bit to the right to become X0111011. By comparing the original number with the number formed after the offset, the offset direction can be judged. Regular numbers such as 00000000, 11111111 or 10101010 do not have this feature. For example, when 10101010 is shifted one bit to the left to form 0101010N, and shifted one bit to the right to form M1010101. If N is 1 and M is 0, the left and right cannot be distinguished.

[0019] 6.2 Read the particle data, and adjust the write delay value according to the offset to make the write DQS at the center of the DQ window.

[0020] In the calibration scheme of the present invention, it does not rely on the DDR3 particles entering the MPR mode, and proposes a complete calibration process to realize the physical layer data training and calibration. The read direction calibration does not rely on the write direction calibration. While completing the calibration of the phase relationship between the sampling clock and the data in the read and write directions, the skew adjustment between the data bits is also achieved, making the effective sampling window interval of the data larger. Even in the case where the differences of external devices and the uncertainty of the routing delay between the data signal lines are more severe, the data channel training can be well carried out, and its technical application is more extensive and the calibration accuracy is higher. Description of the Drawings

[0021] Figure 1 It is a block diagram of the read and write data channels according to an embodiment of the present invention.

[0022] Figure 2 It is a schematic diagram of the waveform change of the input serial-parallel converter clock before and after dqsfd in the second calibration step of the present invention.

[0023] Figure 3 It is a schematic diagram of the regular numbers in the present invention.

[0024] Figure 4 It is a schematic diagram of step 5a.

[0025] Figure 5 It is a schematic diagram of step 5b.

[0026] Figure 6 It is a schematic diagram of step 5c.

[0027] Figure 7 It is a schematic diagram of the position of the FUZZ area before the offset adjustment in step 5d.

[0028] Figure 8 It is a schematic diagram of the position of the FUZZ area after the offset adjustment in step 5d.

[0029] Figure 9 It is a schematic diagram of the write channel delay calibration process.

[0030] Figure 10 It is a simulation waveform of writing regular numbers.

[0031] Figure 11 It is a simulation waveform before the read channel calibration.

[0032] Figure 12 It is a simulation waveform after the read channel calibration.

[0033] Figure 13 It is the write direction DQS and DQ test eye diagram. Detailed Implementation Manner

[0034] The present invention is divided into read and write data channels as a whole. The read data channel is composed of an input buffer, an input serial-parallel converter, and an input delay unit, and the input phase adjuster provides a clock and control signals for the calibration of the read data channel; the write data channel is composed of an output buffer, an output parallel-serial converter, and an output delay unit, and the output phase adjuster provides a clock and control signals for the calibration of the write data channel; the entire calibration step is divided into six steps and carried out sequentially:

[0035] The first step: Restore the read sampling clock

[0036] This step requires receiving the DQS sent by the particle, and restoring the read sampling clock isd_clk and the divided-by-2 clock isd_divclk with the same frequency and phase as the read DQS through the input phase adjuster of the FPGA; isd_clk is used for sampling the read serial data, and isd_divclk is used for parallel transmission of the integrated sampling data.

[0037] Step 2: Determine the read_offeset_delay period

[0038] This step requires finding the delay period read_offeset_delay from sending the read command to the data being read out in the read calibration mode of the input phase adjuster, and after determining the read_offeset_delay period, exiting the read calibration mode of the input phase adjuster. Subsequently, when adjusting the input phase adjuster before sampling the read data, it will be based on the phases of the clocks isd_clk and isd_divclk restored from the read DQS.

[0039] Step 3: write_leveling

[0040] This step is used for phase adjustment between the DQS and CK in the write direction. The output phase adjuster is used to adjust the write DQS delay chain to meet the timing relationship with CK, achieving the purpose of aligning the rising edge of DQS with the rising edge of CK.

[0041] Step 4: Write the regular number to the particle

[0042] This step completes the writing of the regular number when the write data channel is not calibrated, there is a delay between sending the write command and sending the write data due to differences between devices, and there are also differences in the delays between the command channel and the data channel, and the phase relationship between the write data DQ and the accompanying clock write DQS is not calibrated.

[0043] Step 5: Read channel training

[0044] This step is not carried out in the MPR mode. Instead, the written regular number is read out. While calibrating the phase between the read sampling clock and the read data, the skew difference between the data is adjusted so that the read sampling clock is located at the center of a larger valid window of the read data.

[0045] Step 6: Write channel calibration

[0046] This step is used to calibrate the delay period write_offeset_delay from sending the write command to writing the data to the particle, as well as the phase relationship between the write DQS and the write data DQ and the skew adjustment between the DQs.

[0047] Embodiment

[0048] The connection relationship of the physical layer data read / write channel is as follows Figure 1 as shown

[0049] For the read data channel, the input phase adjuster on the FPGA provides the sampling clock isd_clk for the input serial-to-parallel converter, the parallel transmission clock for the input serial-to-parallel converter, and the read clock isd_divclk for the input buffer. The read data is read out from the DDR3 chip, sent to the input delay line through the IOB, and the data delayed by the input delay line is sent to the input serial-to-parallel converter, and the input serial-to-parallel converter converts the serial data to parallel and sends it to the input buffer to complete the data reading.

[0050] For the write data channel, the output phase adjuster on the FPGA provides the sampling clock for the output parallel-to-serial converter and the read clock osd_divclk for the output buffer, and the data serial transmission clock osd_clk for the output parallel-to-serial converter. The write data is sent to the output parallel-to-serial converter through the output buffer, and the output parallel-to-serial converter converts the parallel data to serial and sends it to the output delay line, and the data delayed by the output delay line is sent to the IOB and finally sent to the DDR3 chip to complete the data writing.

[0051] Calibration steps:

[0052] The first step: Restore the read sampling clock

[0053] In this step, by receiving the DQS sent by the chip, the input phase adjuster restores the read sampling clock isd_clk and the divided-by-2 clock isd_divclk that are of the same frequency and phase as the read DQS, with PHASELOCKED as the flag; and the two generated clocks are given to the input serial-to-parallel converter used to sample data to achieve serial-to-parallel conversion. isd_clk is used for sampling the serial data for reading back, and isd_divclk is used for integrating and parallel transmitting the sampled data.

[0054] The second step: Determine the read_offeset_delay period

[0055] This step is to set different read command transmission delays (read_offeset_delay) until data returns in the input phase adjuster read calibration mode. Four consecutive read burst commands are sent periodically. If the input phase adjuster samples the DQS preamble (one cycle of low level) after the read_offeset_dealy cycle, the dqsfd of the input phase adjuster will be pulled high to exit the read calibration mode. After dqsfd is pulled high, the input phase adjuster remembers this read_offeset_dealy delay. When a read command is received again, the phases of isd_clk and isd_divclk will be adjusted before data sampling to facilitate sampling the complete DQ data with isd_clk and integrating and parallelly transmitting the sampled data with isd_divclk.

[0056] After dqsfd is pulled high, the phases of isd_clk and isd_divclk will change. Figure 2 As shown, in the one or two cycles before the read data arrives, isd_clk remains low and is pulled high at the start cycle of arrival to restore the periodic clock. At the same time, isd_divclk is pulled low immediately after isd_clk goes low and is pulled high after waiting for about half a cycle to facilitate parallel transmission of the sampled data.

[0057] Step 3: write_leveling

[0058] This step fully describes this process in the JESD79 protocol. The core is to configure the mode register to make the DDR3 die enter the write_leveling mode. Then, in the write calibration mode of the output phase adjuster, the write DQS signal is sent through the differential output, and the tap chain of the output phase adjuster is used to adjust the phase of DQS. By sampling the data, the change of the CK value sampled by DQS from 0 to 1 is recorded. Meeting the phase relationship between the write DQS and CK (rising edge alignment) is used to calibrate the trace delay difference between CK and DQS caused by the FLY_BY topology.

[0059] Step 4: Die write regulation number

[0060] This step is carried out when the write data channel is not calibrated; the delay between sending the write command and sending the write data is due to the differences between the FPGA device and the DDR3 particles, as well as the delay differences between the command channel and the data channel, and here it is not calibrated; moreover, the phase relationship between the write data DQ and the accompanying write clock DQS is also not calibrated; on this premise, by using a preset large delay write_offeset_delay between sending the write command and sending the write data, writing all 1s or all 0s to the same address multiple times to avoid these uncalibrated differences; so that regular data for read direction calibration is written into the fixed address inside the DDR3 particles.

[0061] Write the regular data correctly in advance. Here, the delay between the write command and the write data needs to be set greater than the actual delay value, and then continuously burst write to the same address 3 times. The required number of times is determined according to the actually set write delay value write_offeset_delay, which is CWL + AL + X and the ideal delay value CWL + AL required by the particle. In this way, the first burst write to the same address will not be able to provide the required DQS and DQ in advance because the timing does not meet the requirements of the particle, resulting in the inability to write the desired all 0s or all 1s data. The data written the second time may be correct or incorrect, which is not important here. It is just to provide the required DQS and data DQ in advance for the third burst write. The data written the third time will overwrite the data written the first two times. And because the DQS and DQ are provided in advance for the third burst write command, all the relevant timing requirements of this write command can be fully met inside the particle. In this way, as shown by the flag in the figure, the valid command 1 for writing addresses 0 - 7 is the last burst write command, and all 0s are written to the particle; the valid command 2 for writing addresses 8 - 15 is the last burst write command, and all 1s are written to the particle. After writing one row of the particle, this process ends.

[0062] Step 5: Read channel training

[0063] In this step, burst read commands are continuously sent first, and the regular data written is continuously read out from the DQ data line of the particle. A group of DQ[7:0] data with a bit width of 8 is accompanied by a companion clock DQS. Each data line presents continuous regular data such as 1111_1111, 0000_0000, 1111_1111, 0000_0000... as Figure 3 shown. Then the entire read channel training process is completed by the following steps (i represents the group order, and j represents the bit order in each group of data):

[0064] Step 1 is as attached Figure 4As shown in 101, the input delay device is used to delay the data DQ so that the rising edge of the trigger at the start of the sampling clock is in the stable area on the left side of the FUZZ interval (unstable area). (At this time, the definition standard of the stable area is continuous sampling for N times and continuous adjustment of the IDLEAY precision twice, and the data read by the input buffer is stable at 8'b1111_1110 or 8'b0000_0001)

[0065] Step 2: Since the input phase adjuster provides a delay chain of half a cycle of the sampling clock in the read direction, the fine delay chain of the input phase adjuster can be increased to delay the sampling clock isd_clk so that the sampling clock finds the left edge left_fuzz_dq[i][j] of the FUZZ interval of each bit data in each group of data, and records the minimum delay tap that first enters and exits the stable interval and enters the FUZZ interval in each group of data, denoted as left_tap_group[i], as shown in Figure 5 102 in. (At this time, the definition standard of the stable area is continuous sampling for N times and continuous adjustment of the input phase adjuster tap three times, and the data of all output ports of the input buffer is stable at 8'b1111_1110 or 8'b0000_0001)

[0066] Step 3: Continue to increase the tap value of the fine delay chain of the input phase adjuster to delay the sampling clock isd_clk so that the trigger edge of the sampling clock crosses the FUZZ interval, find the right edge right_fuzz_dq[i][j] of the FUZZ interval of each bit DQ in each group of data, and record the maximum delay tap value that finally exits the FUZZ interval and enters the stable data interval in each group of data, denoted as right_tap_group[i] (as shown in Figure 6 103 in). (At this time, the definition standard of the stable area is continuous sampling for N times and continuous adjustment of the input phase adjuster tap value three times, and the data of all output ports of the input buffer is stable at 8'b1111_1111 or 8'b0000_0000)

[0067] Step 4: Adjust the per bit skew

[0068] As shown in Figure 7 106 in, the difference between right_tap_group[i] and left_tap_group[i] is the FUZZ interval fuzz_group_befor[i] of each group of data before adjusting the skew. The whole process also records the FUZZ interval range fuzz_dq[i][j] of each bit DQ data in their respective groups, and can calculate the delay distance distance_fuzz][i][j] between each bit data in each group and the bit that finally exits the FUZZ interval in its group (as shown inFigure 7 As shown by the double arrows in Figure 7 The double arrows indicated by 104 are the maximum delay distance distance_fuzz][i][7] of the i-th group of data before skew adjustment when it exits the FUZZ interval. Figure 7 As indicated by 105, the delay distance distance_fuzz][i][5] of the i-th group of data exiting the FUZZ interval is at least 0, and DQ[5] is the data bit that exits the FUZZ interval the latest in the i-th group of data.

[0069] If the distance is greater than or equal to the delay chain tap accuracy of the input delayer, the input delayer tap value can be adjusted to adjust the delay of the corresponding data. This allows each data set to be aligned as close as possible and not exceed the DQ bit position of the last data set to exit the fuzzy interval and enter the stable interval, thereby adjusting the skew between the DQ bits of each data set.

[0070] Finally, adjust the input delay chain and update the delay distance between each bit in each group of data and the bit that exits the FUZZ interval last in the group: justed_distance_fuzz][i][j]. The FUZZ interval and position changes after data skew adjustment are as follows: Figure 8 As shown in FIG. 107, the interval indicated by the double arrow is the maximum delay distance difference [justed_distance_fuzz] [i] [6] of the i-th group of data exiting the FUZZ interval after skew adjustment.

[0071] See also Figure 7 (before adjustment) and Figure 8 (After adjustment), among the 8 bits in parallel DQ[0] to DQ[7], the one with the right edge furthest to the right (and the largest delay) is DQ[5]. Using its right edge as the reference line, the delay of other bits is adjusted as follows: increase the delay, that is, shift it to the right, until "if it shifts to the right again, it will exceed the reference line."

[0072] Alternatively, other bits may be adjusted in the manner of "shifting right until the right edge coincides with or crosses the reference line for the first time" to achieve concentration of the bits in the time domain.

[0073] Step 4 Calculate the center position of the window

[0074] The sum of fuzz_dq[i][j] and justed_distance_fuzz][i][j] is the FUZZ interval of each bit in each group of data after skew adjustment between data. The FUZZ interval of DQ[6] in the i-th group of data is the largest, and this maximum value is the FUZZ interval fuzz_group_after[i] of the i-th group after skew adjustment. After finding the maximum FUZZ interval, adjust the isd_clk delay according to the tap delay chain of the input phase adjuster and move it to the center center_tap_group[i] of each group of data windows. This value becomes the final tap value of the delay chain of the input phase adjuster for each group of data. By writing the tap value, the read sampling clock can be moved to the center of the read data valid window.

[0075] The calculation formula of center_tap_group[i] is as follows:

[0076]

[0077] (Note: dqs_cycle is the period of DQS, pi_fine_tap is the unit tap accuracy of the delay chain of the input phase adjuster, fuzz_group_after[i] is the size of the FUZZ interval of each group of data after read channel skew adjustment, and right_tap_group[i] is the maximum input phase adjuster delay tap value when all data in each group exits the FUZZ interval and enters the right stable data interval)

[0078] Step 6: Write channel calibration

[0079] The phases of the write DQS and the write DQ can be adjusted by the output phase adjuster. The phase relationship between them is set to 90 degrees before the start of the write_leveling stage to ensure that the data can be correctly written during the write channel calibration. However, the previously set 90-degree phase is under the ideal condition that the DQS is defaulted to be at the center of the window of a group of write data DQ[7:0]. In actual situations, since one write DQS is used as the write clock for 8-bit write DQ[7:0], there are trace skews between each DQ bit and the situation that the DQS and the data DQ channel delays are inconsistent. Finally, the write DQS reaching inside the die may not be at the center of the window of a group of write data DQ[7:0], and there may be a certain deviation, but basically it can ensure that the data is correctly written. The accurate window center still needs to use the output delay device to change the delay chain of each DQ bit for calibration. The following is the detailed calibration process:

[0080] Step 1: write_offeset_delay calibration

[0081] AsFigure 9 As shown, the FPGA writes the serial data 01110110 to the die. If the configured write_offeset_delay value is one cycle smaller than the actual value, the data will be sent to the die in advance, resulting in the loss of the first two bits of data and the uncertainty of the last two bits of data. The data written into the die is 1101_10xx. Similarly, if the write_offeset_delay is configured one cycle larger, the data written into the die is xx011_1101. Since the read channel has been calibrated in the above steps, by sending a read command for the data written with different write_offeset_delay delay values, the calibration of write_offeset_delay can be accurately judged from the read-back data.

[0082] Step 2: Calibration of write channel DQ skew

[0083] Since the phase between CK and DQS is basically aligned at the rising edge (close to 0 degrees) after write_levleing is completed, according to the timing specification, DQS only needs to be within the range of plus or minus 90 degrees of CK, and there is still adjustment margin between the two phases. Therefore, the phase of the write direction DQS can be adjusted by adjusting the stage3 delay chain of the output phase adjuster without changing the phase of the write direction DQ.

[0084] The calibration process is similar to that of the read direction calibration. First, the data of each bit in each group of the write direction is delayed by the output delay device until an error occurs in the read-back data of each group and enters the left stable area of the FUZZ interval of the whole group of data (at this time, the definition standard of the stable area is continuous N samplings and continuous two ODLEAY precision adjustments, and the serial data written into the die is 0111_1111 or 1000_0000, and the read data of the input buffer is stable at 8’b1111_1110 or 8’b0000_0001). Then, stop the delay of the data output delay device of this group and record the tap value odly_tap_frist[i] of the delay chain of the output delay device of each group.

[0085] Then, increase the output phase adjuster stage3 fine delay chain to move DQS to find the delay chain tap value wr_left_tap_group[i] when the entire group of data just exits the left stable region and enters the FUZZ interval, as well as the delay chain tap value wr_left_tap_dq[i][j] for each bit of data in each group when it just exits the left stable region and enters the FUZZ interval, and the delay chain tap value wr_right_tap_group[i] when the entire group of data just exits the FUZZ interval and enters the right stable region, and the delay chain tap value wr_right_tap_dq[i][j] for each bit of data in each group when it just exits the FUZZ interval and enters the right stable region; then calculate the skew between bits of each group of data, and use the output delay to adjust the skew between bits, and update the FUZZ interval wr_fuzz_group_after[i] of each group of data after adjusting the skew between the write direction data bits. The process is similar to the read direction calibration steps 2, 3, and 4, and the differences are as follows: 1. It is necessary to write data of all 0s or all 1s; 2. Each time a burst is written, the address is incremented by 8, and each time the data is only written to a certain row of the die to complete the alternating burst write of all 0s and all 1s, and the number of writes is N times (the sampling amount for one adjustment); 3. The written data needs to be read back and judged. When reading back, it starts from the initial address of the write and is incremented by 8, and reads back N times to achieve the data of 1111_1111, 0000_0000 alternating continuously on all data lines. After reading back, use the tap delay chain of stage3 of the output phase adjuster to adjust the delay of the write direction DQS, and its adjustment logic is the same as that of the read calibration; the data skew calibration is to use the ODLEAYE delay chain to adjust the delay of each bit of DQ data in the write direction.

[0086] Step 3: Find the center of the write data valid window

[0087] After finding the FUZZ interval, it is necessary to callback the output delay, that is, the delay of each bit of data in each group is moved forward as a whole by the initial delay value odly_tap_frist[i]. After that, calculate the size of the write direction data window, and moving the stage3 delay chain of the output phase adjuster can adjust the write DQS to the center wr_center_tap[i] of the valid window of each group of DQs. The calculation formula is as follows:

[0088]

[0089] Note:

[0090] dqs_cycle is the period of DQS,

[0091] po_stage3_fine_tap is the unit tap accuracy of the stage3 delay chain of the output phase adjuster,

[0092] odly_tap is the precision value of a single tap in the delay chain of the output delay device,

[0093] odly_tap_frist is the tap value of the delay chain of the output delay device called back in Step 3,

[0094] r_right_tap_group[i] is the tap value of the right stable area of the FUZZ interval for each group of data in the write channel,

[0095] wr_fuzz_group_after[i] is the FUZZ interval of each group of data after the skew adjustment between write data bits.

[0096] In the present invention, for the calibration step four, the number of regularities of particle writing. Without calibrating the write data channel, by using a preset large delay between the write command sending and the write data sending, writing all 1s or all 0s to the same address in bursts multiple times to avoid those uncalibrated differences, the purpose of continuously writing regular data for read direction calibration to the DDR3 particles in bursts is achieved, as shown in the simulation waveform of Figure 10 shown.

[0097] For the calibration step five, read channel training, the calibration of the phase relationship between the read data sampling clock and the data is completed, so that the read data sampling clock is located at the center of the valid window of a group of data. At the same time, the skew adjustment between the data bits in the read direction is also completed. The read data sampling is carried out on the FPGA, and the simulation waveforms before and after the read channel calibration are as shown in Figure 11 and Figure 12 shown.

[0098] For the calibration step six, write channel calibration, the calibration of the phase relationship between the write DQS and the data DQ in the write direction is completed, so that each group of write DQS is located at the center of the valid window of its respective data group. At the same time, the skew adjustment between the data bits in the write direction is also completed. The purpose of the write direction calibration is to have a larger write direction sampling data window inside the DDR3 particles. The eye diagrams of the particle DQS and DQ after the write channel calibration are as shown in Figure 13 shown.

Claims

1. A DDR3 physical layer calibration method based on FPGA, characterized in that, Including the following steps: (1) Restore the read sampling clock: Extract the read sampling clock with the same frequency and phase as the read DQS from the DQS sent by the die, and the divided-by-two clock obtained by dividing it; (2) Determine the latency period from sending a read command to the die to receiving data; (3) Calibrate the trace delay difference; (4) Write regular numbers to the die. This step is performed when the write data channel is not calibrated; The delay between sending the write command and sending the write data is due to the differences between the FPGA device and the DDR3 die, as well as the delay difference between the command channel and the data channel, and here it is not calibrated; Moreover, the phase relationship between the write data DQ and the write DQS accompanying the clock is also not calibrated; Under such a premise, using the preset delay write_offeset_delay between sending the write command and sending the write data, write all 1s or all 0s to the same address multiple times to avoid these uncalibrated differences; So that regular data for read direction calibration is written into the internal fixed address of the DDR3 die; (5) Read channel training calibration: Read the regular numbers written in step 4) from the die, and adjust the read sampling clock and the latency of each bit within the DQ group to make each bit of the DQ data right-aligned, and the read sampling clock is at the center position of the stable region; (6) Write channel calibration: Adjust the data write clock and the position of the data to make the clock sampling point at the center of the write window; The DQ is data, and the DQS is the data clock; The step (6) includes: 6.1 Write jump feature numbers to the die, 6.2 Read the die data, and adjust the write latency value according to the offset to make the write DQS at the center of the DQ window.

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