Method for modular design of logic control chip module and logic control chip

Abstract

The application discloses a method for modular design of a logic control chip and the logic control chip. The logic control chip comprises at least two first-level submodules, each first-level submodule comprises at least one second-level submodule and at least one macro unit, the first-level submodule controls the macro unit through the second-level submodule to perform read and write operations on a storage chip, and the storage chip is connected with the logic control chip in three-dimensional heterogeneous integration. The processing capacity of the first-level submodule is determined based on the storage capacity of the storage chip, and the processing capacity of the second-level submodule is determined based on the processing capacity of the first-level submodule to which the second-level submodule belongs. The logic control chip is modularized, the second-level submodule realizes self timing and physical convergence, the first-level submodule calls and judges whether the second-level submodule converges in the first-level submodule, the first-level submodule realizes self timing and physical convergence, and the top layer calls and judges whether the first-level submodule converges in the top layer, thereby realizing parallel design, increasing design redundancy and solving problems such as a large number of timing violations and difficult physical convergence of a large-scale chip.

Description

Technical Field

[0001] This application relates to the field of logic control chips, and in particular to a method for modular design of logic control chips and a logic control chip. Background Technology

[0002] In 3D integrated circuit applications, to improve chip performance, logic control chips typically reach tens of millions of gates. With the increase in process size, chip size becomes larger, power consumption requirements are higher, and the number of logic multiplexing units increases, introducing many challenges to digital back-end operations.

[0003] In logic control chips, the fixed positions and typically large widths (>800µm) of HB macro cells (hybrid-bonded with DRAM) place high demands on chip layout planning. Simultaneously, data must traverse multiple modules to reach the corresponding cell, and the synchronization clock of large-scale chips needs to span multiple regions, leading to numerous timing violations, a large number of long lines, and difficulties in physical convergence. This, in turn, results in low optimization efficiency for EDA (Electronic Design Automation) tools and extended project cycles. Furthermore, due to the increased DRAM storage capacity and high-bandwidth data processing requirements, the area design of essential logic chip components such as NOC (Network On Chip), Memory Controller, and Process Engine is large, and their frequent data interactions and numerous data paths also easily cause timing violations and long-line crosstalk problems. Summary of the Invention

[0004] This application provides at least one method for modular design of logic control chips and a logic control chip, which is used to solve the problems of numerous timing violations, large number of long lines, difficulty in physical convergence, and long line crosstalk caused by large-scale chips.

[0005] The first aspect of this application provides a logic control chip, which includes at least two primary sub-modules. Each primary sub-module includes at least one secondary sub-module and at least one macro unit. The primary sub-module controls the macro unit through the secondary sub-module to perform read and write operations on a memory chip. The memory chip and the logic control chip are three-dimensionally heterogeneously integrated.

[0006] The processing capacity of the first-level submodule is determined based on the storage capacity of the storage chip, and the processing capacity of the second-level submodule is determined based on the processing capacity of the first-level submodule to which the second-level submodule belongs.

[0007] Optionally, the total processing capacity of the first-level submodules is equal to the storage capacity of the storage chip, and the total processing capacity of the second-level submodules is equal to the processing capacity of their respective first-level submodules.

[0008] Optionally, the first-level submodule also includes at least one port, through which the first-level submodule performs interactive functions with other first-level submodules;

[0009] The port is located on the side of the first-level submodule closest to other first-level submodules.

[0010] Optionally, the first-level submodule also includes at least one asynchronous unit, which is set at a port to control the clocks of multiple first-level submodules to be asynchronous with each other;

[0011] The asynchronous unit is located near the port.

[0012] Optionally, the logic control chip also includes on-chip network circuitry, which is distributed across multiple first-level sub-modules to enable data communication between the multiple first-level sub-modules.

[0013] A second aspect of this application provides a method for modular design of a logic control chip, the method comprising:

[0014] The logic control chip is divided into multiple primary sub-modules;

[0015] The memory controller of the logic control chip is divided into multiple secondary sub-modules;

[0016] Multiple first-level sub-modules are physically implemented separately, so that each first-level sub-module includes at least one macro unit and at least one second-level sub-module;

[0017] Perform timing and physical repairs on multiple primary sub-modules;

[0018] Extract the data models of multiple first-level sub-modules and achieve unified convergence through the top layer of the logic control chip;

[0019] The first-level submodule controls the macrocell through the second-level submodule to perform read and write operations on the memory chip. The memory chip and the logic control chip are connected in a three-dimensional heterogeneous integration. The processing capacity of the first-level submodule is determined based on the storage capacity of the memory chip, and the processing capacity of the second-level submodule is determined based on the processing capacity of the first-level submodule to which the second-level submodule belongs.

[0020] Optionally, the steps of physically implementing multiple first-level sub-modules separately include:

[0021] A comprehensive netlist is obtained based on multiple first-level sub-modules;

[0022] Physical implementation and data convergence are performed based on the integrated netlist.

[0023] Optionally, the step of dividing the memory controller of the logic control chip into multiple secondary sub-modules includes:

[0024] Physical implementation and data convergence are performed on multiple secondary sub-modules respectively;

[0025] Multiple second-level submodules are instantiated based on the comprehensive netlist, so that the first-level submodule can call at least one instantiated second-level submodule.

[0026] Optionally, the data models of multiple first-level sub-modules are extracted, and a unified convergence step is achieved through the top layer of the logic control chip, including:

[0027] The top layer of the logic control chip is synthesized to obtain the top-level synthesized netlist;

[0028] The top-level time series and layout are assessed based on the top-level integrated network table;

[0029] Top-level physical implementation is based on multiple data models;

[0030] Determine whether the overall design of the logic control chip has converged;

[0031] If so, then the top-level unified convergence is completed.

[0032] Optionally, the method further includes:

[0033] Determine whether at least one second-level submodule called by the first-level submodule has completed data convergence;

[0034] In response to at least one second-level submodule completing data convergence, determine whether multiple first-level submodules called by the top-level module have completed data convergence;

[0035] In response to the completion of data convergence by multiple first-level sub-modules, the step of determining whether the overall design of the logic control chip has converged is executed.

[0036] The beneficial effects of this application are as follows: Unlike the prior art, this application modularizes the logic control chip, designing it independently by a separate first-level sub-module, reducing the difficulty of repairing timing violations and physical implementation errors, and solving the problem of difficult physical convergence; at the same time, the second-level sub-module achieves its own timing and physical convergence, and the first-level sub-module calls and determines whether it has converged within the first-level sub-module. The first-level sub-module achieves its own timing and physical convergence, and the top-level module calls and determines whether it has also converged at the top level, realizing parallel design without setting a large number of long lines, solving the problems of many timing violations, large number of long lines, and long line crosstalk caused by large-scale chips, while increasing design redundancy to reduce the optimization time of EDA tools.

[0037] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the structure of an embodiment of a prior art logic control chip;

[0040] Figure 2 This is a schematic diagram of the structure of an embodiment of the logic control chip of this application;

[0041] Figure 3 This is a schematic diagram of the design logic of an embodiment of the logic control chip of this application;

[0042] Figure 4 This is a flowchart illustrating an embodiment of the method for modular design of logic control chips according to this application;

[0043] Figure 5 yes Figure 4 A detailed flowchart of step S12 is shown below;

[0044] Figure 6 yes Figure 4 A detailed flowchart of step S13 is shown below;

[0045] Figure 7 yes Figure 4 A detailed flowchart of step S15 is shown below;

[0046] Figure 8 yes Figure 7 A schematic diagram of the specific process before step S154. Detailed Implementation

[0047] To enable those skilled in the art to better understand the technical solutions of this application, the method for modular design of logic control chips and the logic control chip provided in this application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It is understood that the described embodiments are merely some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0048] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0049] In 3D integrated circuit applications, to improve chip performance, logic control chips typically reach tens of millions of gates. Furthermore, with the increase in process size, chip size becomes larger, power consumption requirements become higher, and the number of logic multiplexing units increases.

[0050] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of a prior art logic control chip, as shown below. Figure 1 As shown, in the logic control chip, the macrocell HB (Hybrid Bonding) that is hybrid-bonded with DRAM (this macrocell is mainly used for data transmission, such as transmitting the processed signals of the logic control chip to the memory chip; this macrocell includes the PHY (Physical Layer), data transmission interface, level conversion module, etc.) has a fixed position and is usually large in width (>800um). Typically, when implementing a flattened physical design for the chip, the various logic functional modules of the logic control chip are evenly distributed according to the DRAM capacity connected to the logic control chip. The NOC (Network On Chip) unit and the memory controller are usually evenly placed in the center of the logic control chip to achieve a more equal length of data processing paths and balance the data transmission rate.

[0051] To optimize timing issues caused by the large number of combinational logic levels in the data path, a pipeline is typically added between the NOC unit and other unit modules. This means the NOC unit is connected to various computation modules via a pipeline, for example... Figure 1 The IP1 or IP2 shown are examples of this. A pipeline includes multiple combinational logic units with strong driving capabilities. Specifically, a pipeline is a pipelined operation, i.e., periodically capturing packets, which is a method for processing data in chip signal processing. Adding bounds to the layout restricts the position of the pipeline combinational logic units to accelerate data transmission and optimize timing.

[0052] However, the large size of the logic control chip makes it difficult to achieve convergence in overall timing and physical verification, resulting in a long design cycle. Furthermore, EDA (Electronic Design Automation) tools are inefficient when balancing optimizations across large areas of violations. Simultaneously, the large area of ​​the NOC (Normally Injectable Cell) and control units, limited by the storage capacity of the DRAM connected to the logic control chip, leads to a high risk of timing violations at the top-level boundary, and the increased pipeline path increases the utilization of standard cells within the chip, significantly impacting routing efficiency.

[0053] This application provides a logic control chip to solve the problems of numerous timing violations, large number of long lines, difficulty in physical convergence, and long-line crosstalk caused by large-scale chips.

[0054] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of an embodiment of the logic control chip of this application. Figure 2 As shown, the logic control chip 1 is divided into multiple first-level sub-modules 10. Each first-level sub-module 10 includes at least one second-level sub-module 11, at least one macro unit 12, at least one port 13, and at least one asynchronous unit 14.

[0055] Among them, macro unit 12 is the unit that enables the logic control chip 1 to connect with the memory chip (not shown). The secondary submodule 11 can specifically be a control module, as shown in the figure. Figure 1 The control unit shown is disassembled, with a primary submodule 10 controlling a macrocell 12 via a secondary submodule 11 to perform read and write operations on the memory chip. The memory chip and the logic control chip 1 are three-dimensionally heterogeneously integrated. Specifically, in this embodiment, the memory chip is a DRAM memory wafer.

[0056] The processing capacity of the first-level submodule 10 is determined based on the storage capacity of the storage chip, and the processing capacity of the second-level submodule 11 is determined based on the processing capacity of the first-level submodule 10 to which the second-level submodule 11 belongs.

[0057] Specifically, the total processing capacity of the multiple first-level submodules 10 is equal to the storage capacity of the memory chip, and the total processing capacity of at least one second-level submodule 11 is equal to the processing capacity of its respective first-level submodule 10. The processing capacities of all at least one second-level submodule 11 included in a single first-level submodule 10 are equal. For example, when a single first-level submodule 10 includes two second-level submodules 11, the processing capacities of the two second-level submodules 11 are equal.

[0058] Optionally, in this embodiment, based on the processing capacity of the logic control chip 1 and the location of the multiple macrocells 12, the logic control chip 1 is divided into multiple first-level sub-modules 10 with equal area and equal data processing capacity. For example, when the storage capacity of the DRAM wafer is 12G, the corresponding processing capacity of the logic control chip 1 is 12G. The logic control chip 1 can be divided into six 2G first-level sub-modules 10, or it can be divided into twelve 1G first-level sub-modules 10, etc. The number of divisions can be designed as needed.

[0059] Optionally, in this embodiment, based on the processing capacity of a single first-level submodule 10, the following... Figure 1 The control unit shown is divided into multiple secondary sub-modules 11 with equal processing capacity. For example, when the processing capacity of a single primary sub-module 10 is 2G, the control unit can be divided into four 512Mb secondary sub-modules 11, or it can be divided into two 1G secondary sub-modules 11, and so on. The number of divisions can be designed according to needs. That is, in a primary sub-module 10, the sum of the processing capacities of the secondary sub-modules 11 is equal to the processing capacity of the primary sub-module 10.

[0060] Second-level submodule 11 compared to Figure 1 The control module in the middle is small in area and has a single processing capacity. The logic control chip 1 performs read and write operations on the DRAM wafer through a specific secondary sub-module 11, which reduces the difficulty of timing optimization of the logic control chip 1 and reduces the difficulty of overall timing and physical verification convergence of the logic control chip 1.

[0061] In this embodiment, a comprehensive netlist is obtained based on the division of multiple first-level sub-modules 10. Each first-level sub-module 10 instantiates at least one of its contained second-level sub-modules 11 at least once within the comprehensive netlist to name at least one second-level sub-module 11. Specifically, referencing another module within a module and making related connections to its ports is called module instantiation. Signal ports can be associated by location or name. In this embodiment, by instantiating at least one second-level sub-module 11 at least once, the first-level sub-module 10 calls the corresponding second-level sub-module 11.

[0062] For example, if a single primary submodule 10 contains two secondary submodules 11, then the two secondary submodules 11 are instantiated in the comprehensive netlist and named secondary submodule a and secondary submodule b respectively to distinguish them. When the logic control chip 1 performs read / write operations, the corresponding secondary submodule 11 is selected based on its different names, and then the macrocell 12 connected to the secondary submodule 11 performs read / write operations on the DRAM wafer.

[0063] This embodiment divides the logic control chip 1 into multiple primary sub-modules 10. Each primary sub-module 10 can perform its own timing and physical corrections, enabling independent design among the sub-modules. When a timing violation or physical implementation error occurs in one primary sub-module 10, only that primary sub-module 10 needs to be corrected, reducing the EDA optimization load and significantly improving the efficiency of digital back-end design. Simultaneously, based on the principle of parallel implementation, the logic control chip 1 can run multiple primary sub-modules 10 simultaneously, improving operating efficiency and reducing EDA runtime.

[0064] Port 13 is located on the side adjacent to another first-level submodule 10, enabling the first-level submodule 10 to interact with the other first-level submodule 10 via port 13. Specifically, in this embodiment, port 13 is located on the side of the first-level submodule 10 closer to other first-level submodules 10. This reduces the wiring length and corresponding timing path length of the connection between the first-level submodule 10 and other first-level submodules 10 via port 13, thereby reducing signal delay, optimizing path timing, reducing wiring congestion risk, and improving the utilization rate of the logic control chip 1.

[0065] Specifically, a primary submodule 10 may be provided with multiple ports 13. In one embodiment, the number of ports 13 is determined based on the number of primary submodules 10 adjacent to the primary submodule 10. Optionally, the number of ports 13 is equal to the number of primary submodules 10 adjacent to the primary submodule 10. For example, if the number of primary submodules 10 adjacent to the primary submodule 10 is 1, then a port 13 is provided on the side of the primary submodule 10 closest to the adjacent primary submodule 10. As another example, if the number of primary submodules 10 adjacent to the primary submodule 10 is 4, and the primary submodule 10 is surrounded by adjacent primary submodules 10, then a port 13 is provided on each of the four sides of the primary submodule 10 closest to the adjacent primary submodules 10. By providing the same number of ports 13, the primary submodule 10 can interact with other primary submodules 10 adjacent to it through multiple ports 13.

[0066] Optionally, two, three, or four primary submodules 10 may be arranged around a primary submodule 10, and the positions of the ports 13 of the different primary submodules 10 may be the same or different. For example, the primary submodule 10 is... Figure 2 When the first-level submodule 10 is set in the upper left corner of the logic control chip 1, the first-level submodule 10 is set on the right side and the lower side of the first-level submodule 10 respectively, and the first-level submodule 10 has ports 13 on the right side and the lower side of the first-level submodule 10 respectively.

[0067] The asynchronous unit 14 is used to control the clock of the first-level submodule 10 to be asynchronous with the clocks of other first-level submodules 10, which can directly optimize the efficiency of timing convergence. When multiple first-level submodules 10 are equipped with asynchronous units 14, the clocks of the multiple first-level submodules 10 are asynchronous with each other.

[0068] Optionally, the asynchronous unit 14 is located on the side of the first-level submodule 10 near the port 13, which can specifically be the port 13 for inputting control signals to the logic control chip 1.

[0069] This embodiment sets an asynchronous unit 14 in each first-level submodule 10, thereby changing the clock of its corresponding first-level submodule 10, making it asynchronous with the clocks of other first-level submodules 10. Furthermore, this embodiment sets the asynchronous unit 14 at the port 13 where the logic control chip 1 inputs control signals, thereby reducing the wiring distance between multiple first-level submodules 10. Since the asynchronous unit 14 processes clock signals, it can also reduce clock signal delay.

[0070] Optionally, the logic control chip 1 may further include on-chip network circuitry, which is distributed across multiple primary sub-modules 10 in a flattened configuration. The logic control chip 1 transmits control signals to the corresponding primary sub-modules 10 via the on-chip network circuitry to drive the secondary sub-modules 11, which serve as control modules within the primary sub-modules 10, to operate. Simultaneously, the logic control chip 1 enables data communication between the multiple primary sub-modules 10 via the on-chip network circuitry.

[0071] In this embodiment, the on-chip network circuitry is flattened and distributed across multiple first-level sub-modules 10, so that each first-level sub-module 10 is provided with a signal output port of the on-chip network circuitry. Each first-level sub-module 10 only needs to configure wiring (timing paths) to connect to this signal output port, significantly reducing the number of connections between the first-level sub-module 10 and the on-chip network circuitry. Figure 1 The wiring of the NOC unit at the fixed position shown significantly reduces the length of the timing path corresponding to the first-level submodule 10, reduces the application of the pipeline circuit, optimizes the timing of the path, reduces the risk of wiring congestion, improves the utilization rate of the logic control chip 1, and increases the redundancy of the modular reuse of the logic control chip 1.

[0072] Combination Figure 2 For further information Figure 3 , Figure 3 This is a schematic diagram of the design logic of an embodiment of the logic control chip of this application. Figure 3 As shown, the logic control chip 1 includes multiple first-level sub-modules 10, multiple second-level sub-modules 11, and a top-level module 30.

[0073] Among them, multiple secondary sub-modules 11 perform physical implementation and data convergence respectively to obtain the corresponding data model, which includes a time series model and a physical model.

[0074] The first-level submodule 10 contains one or more second-level submodules 11. Based on the data model of the connected second-level submodule 11, the first-level submodule 10 calls the corresponding second-level submodule 11 and determines whether the timing and physical rules of that second-level submodule 11 have converged. If convergence is not achieved, the non-convergence signal is returned to the corresponding second-level submodule 11, causing that second-level submodule 11 to perform timing and / or physical repair, until the first-level submodule 10 determines that the timing and physical rules of all its included second-level submodules 11 are correct. Optionally, physical repair may include formal verification and physical verification.

[0075] After multiple first-level submodules 10 complete the timing and physical rule judgments with their contained second-level submodules 11, they further perform individual convergence and extract the data model corresponding to the first-level submodule 10. The data model includes a timing model and a physical model. After completing the above data convergence, the low-level design of the logic control chip 1 is completed. The low-level design is the design of specific functional logic circuits. The layout design of the logic control chip 1 also includes the top-level design, which refers to the high-level abstract functional module-level design, and is a general design.

[0076] Specifically, the top-level design involves data convergence performed by the top-level module of logic control chip 1; the top-level module is... Figure 3 The top layer 30 shown is composed of multiple first-level sub-modules 10. The top layer 30 acquires the data models of the multiple first-level sub-modules 10, calls the corresponding first-level sub-modules 10 based on their data models, and judges whether the timing and physical rules of that first-level sub-module 10 have converged. The specific judgment rules are the same as those used by the first-level sub-modules 10 to judge the convergence of the timing and physical rules of the second-level sub-modules 11. After the top layer 30 completes the convergence judgment of the timing and physical rules of all first-level sub-modules 10, it further achieves unified convergence to form the logic control chip 1. Optionally, the top layer 30 is further used to check the timing of the asynchronous unit 14 set on port 13 of the first-level sub-module 10.

[0077] In this embodiment, the top-level 30 is further synthesized to obtain a top-level synthesized netlist. The top-level 30 is then physically implemented based on this netlist, and data convergence is performed on it according to the constraint file. Specifically, the physical implementation of the top-level 30 includes setting the placement positions of multiple first-level sub-modules 10 and configuring the connection relationships between multiple ports 13. The data convergence of the top-level 30 includes verifying and determining the convergence of the timing of the multiple ports 13.

[0078] In this application, each first-level submodule 10 only needs to fix its internal physical and timing convergence, while the top-level 30 only needs to fix the timing at the port 13 connection, without needing to fix register-level timing violations. This greatly optimizes design efficiency, and the layout of different first-level submodules 10 is more flexible. The placement of cells in each first-level submodule 10 can be flexibly adjusted for timing repair and physical verification without considering the convergence degree of the top-level 30 and other first-level submodules 10, thus enhancing design redundancy. At the same time, the clock of each first-level submodule 10 is relatively independent and asynchronous to each other. Compared with the overall flattened synchronous clock design of the logic control chip 1, timing convergence is easier.

[0079] This application also provides a method for modular design of logic control chips, the flowchart of which is shown below. Figure 4 As shown. Please refer to... Figure 2-3 See Figure 4 , Figure 4 This is a flowchart illustrating an embodiment of the modular design method for a logic control chip according to this application. Specifically, the modular design method for a logic control chip in this embodiment may include the following steps:

[0080] Step S11: Divide the logic control chip into multiple first-level sub-modules with the same processing capacity.

[0081] The logic control chip 1 can be divided into N rows, and each row includes N columns of first-level sub-modules 10. Optionally, N is a natural number greater than zero. Specifically, the number of rows and columns of the logic control chip 1 can be the same or different.

[0082] Step S12: Divide the memory controller of the logic control chip into multiple secondary sub-modules.

[0083] The processing capacity of the secondary submodule 11 is the same as that of the macrocell 12. Optionally, when the processing capacity of a single secondary submodule 11 is the same as that of a single macrocell 12, the single secondary submodule 11 performs read and write operations on the memory chip through a single macrocell 12. When the processing capacity of a single secondary submodule 11 is not the same as that of a single macrocell 12, for example, when the processing capacity of a single secondary submodule 11 is equal to the processing capacity of two macrocells 12, the secondary submodule 11 can perform read and write operations on the memory chip through two macrocells 12.

[0084] Optionally, in this embodiment, multiple secondary sub-modules 11 are physically implemented according to capacity division and instantiated sequentially, so that the primary sub-module 10 calls the corresponding number and functions of secondary sub-modules 11 according to the processing capacity.

[0085] Please refer to the detailed classification process. Figure 5 , Figure 5 yes Figure 4 A detailed flowchart of step S12 is provided. Specifically, it includes the following steps:

[0086] Step S121: Physically implement each of the multiple secondary sub-modules.

[0087] According to the pre-design, the memory controller of the logic control chip 1 is divided into two-level sub-modules 11 of the required capacity, and each sub-module 11 is laid out so that it is connected to the macro unit 12. The macro unit 12 is set according to the specific location of the memory chip.

[0088] Step S122: Instantiate multiple second-level sub-modules according to the comprehensive netlist, so that the first-level sub-module can call at least one instantiated second-level sub-module.

[0089] In this embodiment, multiple secondary sub-modules 11 are instantiated based on a comprehensive netlist so that each secondary sub-module 11 has a corresponding label or name, and the primary sub-module 10 calls the corresponding secondary sub-module 11 through the label or name.

[0090] Step S13: Perform physical implementation on each of the multiple first-level sub-modules.

[0091] Please refer to the following for details on the physical implementation process. Figure 6 , Figure 6 yes Figure 4 A detailed flowchart of step S13 is provided. Specifically, it includes the following steps:

[0092] Step S131: Obtain the comprehensive netlist based on multiple first-level sub-modules.

[0093] The integrated netlist includes the distribution of multiple first-level sub-modules 10, the number and specific names of the second-level sub-modules 11 contained in each first-level sub-module 10, and the number of macro units 12 contained in each first-level sub-module 10.

[0094] Step S132: Perform physical implementation and data convergence based on the integrated netlist.

[0095] Data convergence includes temporal convergence and physical convergence. In this embodiment, placement and routing are performed on each primary submodule 10 based on the integrated netlist, and the data model of the corresponding secondary submodule 11 is obtained. It is then determined whether the secondary submodule 11 has completed data convergence. Specifically, the physical implementation performed by the primary submodule 10 includes calling the corresponding number of secondary submodules 11 and setting the location of at least one secondary submodule 11. The data model of the secondary submodule 11 includes its temporal logic data and physical implementation data.

[0096] The first-level submodule 10 includes one or more second-level submodules 11. Based on the data model of its included second-level submodules 11, it determines whether the timing and physical rules of the second-level submodules 11 have converged. If convergence is not determined, the signal indicating non-convergence is returned to the corresponding second-level submodule 11 for timing repair and / or physical repair, until the first-level submodule 10 determines that the timing and physical rules of all its included second-level submodules 11 have converged.

[0097] Step S14: Perform timing and physical repairs on multiple first-level sub-modules.

[0098] After the physical implementation of multiple first-level sub-modules 10 is completed, each first-level sub-module 10 needs to test its own timing and layout.

[0099] Specifically, after the first-level submodule 10 completes its physical implementation, it forms its own data model. The timing logic and physical logic design of the first-level submodule 10 can be judged based on the data model to determine whether they converge.

[0100] Step S15: Extract the data models of multiple first-level sub-modules and achieve unified convergence through the top layer of the logic control chip.

[0101] Among them, after completing physical implementation, timing repair and physical repair, multiple first-level sub-modules 10 converge themselves to obtain their own data models, which include physical models and timing models.

[0102] For details on the process of achieving unified convergence at the top level, please refer to [link / reference needed]. Figure 7 , Figure 7 yes Figure 4 A detailed flowchart of step S15 is provided. Specifically, it includes the following steps:

[0103] Step S151: Synthesize the top layer of the logic control chip to obtain the top layer synthesized netlist.

[0104] In this embodiment, the top layer 30 is synthesized separately to obtain a hierarchical top-level synthesized netlist.

[0105] Step S152: Evaluate the top-level timing and layout based on the top-level integrated netlist.

[0106] In this embodiment, timing and layout evaluation of the top-level 30 are performed based on the top-level integrated netlist. This is mainly used to evaluate the timing of ports 13 of each first-level sub-module 10 and the convergence of physical verification of each first-level sub-module 10.

[0107] Step S153: Perform top-level physical implementation based on multiple data models.

[0108] The top-level 30 performs top-level physical implementation based on the data models of multiple first-level sub-modules 10. Specifically, the top-level physical implementation includes setting the placement positions of the multiple first-level sub-modules 10 and setting the connection relationships between the multiple ports 13.

[0109] Specifically, before executing step S154, the following can also be executed: Figure 8 Steps S21-S23 are shown. Figure 8 yes Figure 7 A flowchart illustrating the process preceding step S154. Specifically, it includes the following steps:

[0110] Step S21: Determine whether at least one second-level submodule called by the first-level submodule has completed data convergence.

[0111] In step S122, multiple secondary sub-modules 11 are instantiated. Since the primary sub-module 10 calls at least one secondary sub-module 11, it is necessary to determine whether the data of the secondary sub-module 11 called by the primary sub-module 10 has converged. Specifically, determining whether the data has converged includes judging whether the timing and physical rules of the secondary sub-module 11 have converged. If convergence is not determined, the primary sub-module 10 returns the non-convergence signal to the corresponding secondary sub-module 11, causing the secondary sub-module 11 to perform timing repair and / or physical repair until the primary sub-module 10 determines that the timing and physical rules of all its included secondary sub-modules 11 are correct. Optionally, physical repair may include formal verification and physical verification.

[0112] Step S22: In response to at least one second-level submodule completing data convergence, determine whether the multiple first-level submodules called by the top-level module have completed data convergence.

[0113] In step S21, when the first-level submodule 10 determines that all its second-level submodules 11 have completed data convergence, the top-level 30 further determines whether the multiple first-level submodules 10 it integrates have completed data convergence. The specific judgment rules are the same as those of the first-level submodule 10 in determining the convergence of the timing and physical rules of the second-level submodules 11, and will not be repeated here.

[0114] Step S23: In response to the completion of data convergence by multiple first-level sub-modules, execute the step of determining whether the overall design of the logic control chip has converged.

[0115] In step S21, when the top-level 30 determines that the multiple first-level sub-modules 10 it integrates have completed data convergence, it further determines whether the overall design of the logic control chip 1 has converged, and then steps S154 can be executed.

[0116] Step S154: Determine whether the overall design of the logic control chip has converged.

[0117] After the top-level physical implementation is completed, it is necessary to verify whether the overall design of the logic control chip 1 has converged. If yes, proceed to step S155; otherwise, return to step S153.

[0118] When the overall design of the judgment logic control chip 1 fails to converge, the top-level 30 performs top-level physical implementation and continues to complete the timing and physical convergence by adopting the principle of flattening repair.

[0119] Specifically, the data model of the corresponding repaired first-level sub-module 10 is returned to the first-level sub-module 10 so that it can perform timing repair and / or physical repair until the top-level 30 determines that the timing and physical rules of all first-level sub-modules 10 have converged, and further determines whether the overall design of the logic control chip 1 has converged.

[0120] Step S155: Complete top-level unified convergence.

[0121] When the overall design of the logic control chip 1 converges, it proves that the top layer 30 has achieved unified convergence, and the design is complete.

[0122] The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A logic control chip, characterized in that, The logic control chip includes at least two primary sub-modules. Each primary sub-module includes at least one secondary sub-module, at least one macrocell, at least one port, and at least one asynchronous unit, thus dividing the logic control chip into multiple primary sub-modules. The memory controller of the logic control chip is also divided into multiple secondary sub-modules. The port is located on the side of a primary sub-module closest to other primary sub-modules, and the asynchronous unit is located on the side of a primary sub-module closest to the port. The primary sub-modules control the macrocells through the secondary sub-modules to perform read and write operations on the memory chip. The memory chip and the logic control chip are three-dimensionally heterogeneously integrated. The processing capacity of the first-level submodule is determined based on the storage capacity of the memory chip, and the processing capacity of the second-level submodule is determined based on the processing capacity of the first-level submodule to which the second-level submodule belongs; the total processing capacity of the first-level submodules is equal to the storage capacity of the memory chip, and the total processing capacity of the second-level submodules is equal to the processing capacity of the first-level submodule to which they belong.

2. The logic control chip according to claim 1, characterized in that, The first-level submodule also includes at least one port, through which the first-level submodule performs interactive functions with other first-level submodules.

3. The logic control chip according to claim 1, characterized in that, The at least one asynchronous unit is connected to the port, and controls the clocks of the multiple first-level sub-modules to be asynchronous with each other through the port.

4. The logic control chip according to claim 1, characterized in that, The logic control chip also includes an on-chip network circuit, which is distributed in multiple first-level sub-modules and is used to realize data communication between the multiple first-level sub-modules.

5. A method for modular design of a logic control chip, characterized in that, include: The logic control chip is divided into multiple primary sub-modules; The storage controller of the logic control chip is divided into multiple secondary sub-modules; The multiple first-level sub-modules are physically implemented respectively, such that each first-level sub-module includes at least one macro unit, at least one second-level sub-module, at least one port, and at least one asynchronous unit; Timing and physical repairs are performed on multiple primary sub-modules. The data models of multiple first-level sub-modules are extracted and unified converged through the top layer of the logic control chip; The primary submodule controls the macrocell through the secondary submodule to perform read and write operations on the memory chip. The memory chip and the logic control chip are three-dimensionally heterogeneously integrated. The processing capacity of the primary submodule is determined based on the storage capacity of the memory chip, and the processing capacity of the secondary submodule is determined based on the processing capacity of the primary submodule to which the secondary submodule belongs. The step of extracting the data models of multiple first-level sub-modules and achieving unified convergence through the top layer of the logic control chip includes: The top layer of the logic control chip is synthesized to obtain the top-level synthesized netlist; Evaluate the top-level timing and layout based on the aforementioned top-level integrated netlist; Top-level physical implementation is performed based on multiple data models described above; Determine whether the overall design of the logic control chip has converged; If so, then the top-level unified convergence is completed.

6. The method according to claim 5, characterized in that, The step of physically implementing each of the multiple first-level sub-modules includes: A comprehensive netlist is obtained based on the multiple first-level sub-modules described above; The physical implementation and data convergence are performed based on the comprehensive netlist.

7. The method according to claim 6, characterized in that, The step of dividing the memory controller of the logic control chip into multiple secondary sub-modules includes: Physical implementation and data convergence are performed on multiple secondary sub-modules respectively, wherein, according to a pre-design, the storage controller of the logic control chip is correspondingly divided into secondary sub-modules of the required capacity size; The multiple second-level sub-modules are instantiated according to the comprehensive netlist, so that the first-level sub-module calls at least one of the instantiated second-level sub-modules.

8. The method according to claim 5, characterized in that, The method further includes: Determine whether at least one of the second-level submodules called by the first-level submodule has completed data convergence; In response to at least one of the secondary sub-modules completing data convergence, it is determined whether the multiple primary sub-modules called by the top layer have completed data convergence; In response to the completion of data convergence by multiple first-level sub-modules, the step of determining whether the overall design of the logic control chip has converged is executed.

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