A plm-14t anti-radiation sram memory cell circuit

Abstract

The application relates to a PLM-14T anti-radiation SRAM memory cell circuit. The PLM-14T anti-radiation SRAM memory cell circuit comprises ten NMOS transistors N1-N10 and four PMOS transistors P1-P4; P1 and P2 and P3 and P4 are cross-coupled, N1 and N2 correspond to P1 and P2 as pull-down tubes, N3 and N4 correspond to P3 and P4 as pull-down tubes, and N5 and N6 constitute a feedback loop for regulating a storage node; a main storage node Q and QB are connected with a bit line BL and BLB through N7 and N8 respectively, and a redundant storage node S1 and S0 are connected with the bit line BL and BLB through N9 and N10 respectively. The storage node of the application adopts a double pull-down loop to play a feedback regulation role, and the anti-flipping capability of the circuit storage node is enhanced. Meanwhile, the circuit uses four transfer transistors for reading and writing, and the data writing speed and the write noise margin of the unit are improved.

Description

Technical Field

[0001] This invention relates to the field of static random access memory (SRAM) technology, and in particular to a cell circuit structure that can improve the read / write speed of memory cells and enhance the cell's resistance to single-event upsets, namely the PLM-14T radiation-resistant SRAM memory cell circuit. Background Technology

[0002] When radiated particles pass through a metal-oxide-semiconductor (MOS) device, their incident path generates a large number of electron-hole pairs, resulting in energy loss. Due to the influence of the electric field and concentration gradient, radiation-induced carrier drift and diffusion occur, eventually being collected by the depletion region of the reverse-biased junction, generating transient pulses. This increases the probability of Single Event Upsets (SEUs) in SRAMs due to Single Event Effects (SETs). SEUs are a major reliability failure mechanism that can cause electronic system failures by temporarily altering stored values. When a charged particle strikes a sensitive node of an integrated circuit, the induced charge along its path can be effectively collected and accumulated through a drift process. Once the instantaneous voltage pulse generated by the accumulated charge exceeds the circuit's switching threshold, the stored value in this sensitive node changes. Currently, SRAM circuits in electronic systems undertake a large amount of data exchange and storage tasks; the normal operation of the entire electronic system relies on the support of SRAM, which plays a crucial role. Therefore, to reduce or even eliminate the impact of radiation effects on electronic systems, radiation hardening of SRAM becomes critical. Summary of the Invention

[0003] Based on this, it is necessary to improve traditional SRAM to address the problem caused by changes in memory cell information due to SEU protection. This invention provides a PLM-14T radiation-resistant SRAM memory cell circuit.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A PLM-14T radiation-resistant SRAM memory cell circuit, comprising:

[0006] PMOS transistor P1, the gate of P1 is electrically connected to the drain of P2, and the drain of P1 is electrically connected to the drain of N1.

[0007] PMOS transistor P2, the gate of P2 is electrically connected to the drain of P1, and the drain of P2 is electrically connected to the gate of P1.

[0008] PMOS transistor P3, the gate of P3 is electrically connected to the drain of P4, and the drain of P3 is electrically connected to the gate of P4.

[0009] PMOS transistor P4, the gate of P4 is electrically connected to the drain of P3, and the drain of P4 is electrically connected to the gate of P3.

[0010] NMOS transistor N1, the drain of N1 is electrically connected to the drain of P1, and the gate of N1 is electrically connected to the drain of P3.

[0011] NMOS transistor N2, the drain of N2 is electrically connected to the drain of P2, the gate of N2 is electrically connected to the drain of P4, and the source of N2 is electrically connected to the source of N1.

[0012] NMOS transistor N3, the drain of N3 is electrically connected to the gate of P4 and the drain of P3, and the gate of N3 is electrically connected to the gate of P3 and the drain of P4.

[0013] NMOS transistor N4, the drain of N4 is electrically connected to the gate of P3 and the drain of P4, the gate of N4 is electrically connected to the drain of N3, and the source of N4 is electrically connected to the source of N3.

[0014] NMOS transistor N5, the drain of N5 is electrically connected to the gate of P3 and the drain of P4, and the gate of N5 is electrically connected to the drain of P2 and the drain of N2.

[0015] NMOS transistor N6, the drain of N6 is electrically connected to the gate of P4 and the drain of P3, the gate of N6 is electrically connected to the drain of P1 and the drain of N1, and the source of N6 is electrically connected to the source of N5.

[0016] NMOS transistor N7, the drain of N7 is electrically connected to the drain of N1, the gate of N7 is electrically connected to the word line WL, and the source of N7 is electrically connected to the bit line BL.

[0017] NMOS transistor N8, the drain of N8 is electrically connected to the drain of N2, the source of N8 is electrically connected to the bit line BLB, and the gate of N8 is electrically connected to the word line WL.

[0018] NMOS transistor N9, the drain of N9 is electrically connected to the drain of P4, the gate of N9 is electrically connected to the word line WL, and the source of N9 is electrically connected to the bit line BL.

[0019] NMOS transistor N10, the drain of N10 is electrically connected to the drain of P3, the source of N10 is electrically connected to the bit line BLB, and the gate of N10 is electrically connected to the word line WL.

[0020] The sources of transistors P1 to P4 are electrically connected to VDD, the sources of transistors N1 to N6 are grounded, storage nodes Q and QB are connected to bit lines BL and BLB through N7 and N8 respectively, and storage nodes S1 and S0 are connected to bit lines BL and BLB through N9 and N10 respectively; transistors N5 and N6 form a feedback loop for adjusting the storage nodes.

[0021] Furthermore, the gate length of transistors N1-N10 and P1-P4 is 65nm, the gate width of transistors N1-N4 is 280nm, the gate width of transistors N5 and N6 is 420nm, and the gate width of transistors N7-N10 and P1-P4 is 140nm.

[0022] Furthermore, storage nodes Q and QB are primary storage nodes, and storage nodes S1 and S0 are redundant storage nodes.

[0023] In one embodiment, when the radiation-resistant SRAM memory cell is in the hold phase, the bit lines BL and BLB are precharged to a high level, the word line WL is at a low level, and the circuit maintains its initial state.

[0024] In one embodiment, when the radiation-resistant SRAM memory cell is in the data read phase, bit lines BL and BLB are precharged to a high level, word line WL is at a high level, and transistors N7 to N10 are turned on.

[0025] Furthermore, if the data stored in the radiation-resistant SRAM memory cell is '0', then "Q = S1 = 0, QB = S0 = 1"; the bit line BL discharges to ground through discharge path 1: transistors N9 and N5, discharge path 2: transistors N7 and N1, and discharge path 3: transistors N9 and N4, causing a voltage difference between the bit lines BL and BLB, and the data is read out through a sensitive amplifier.

[0026] Furthermore, if the data stored in the radiation-resistant SRAM memory cell is '1', then "Q = S0 = 1, QB = S1 = 0"; the bit line BLB discharges to ground through discharge path 1: transistors N8 and N2, discharge path 2: transistors N10 and N6, and discharge path 3: transistors N10 and N3, causing a voltage difference between the bit lines BLB and BL, and the data is read out through a sensitive amplifier.

[0027] In one embodiment, when the radiation-resistant SRAM memory cell is in the data writing phase, the word line WL is at a high level.

[0028] Furthermore, if bit line BL is high and bit line BLB is low, then transistors N7 and N9 write '1' to memory node Q and S1 respectively; if bit line BL is low and bit line BLB is high, then transistors N8 and N10 write '1' to memory node QB and S1 respectively.

[0029] The technical solution provided by this invention has the following beneficial effects:

[0030] This invention enhances the anti-flip capability of storage nodes by setting up a dual pull-down loop for feedback regulation. Simultaneously, the storage cell uses four transmission transistors for reading and writing. During data writing, the bit lines simultaneously write data to internal nodes Q, S1 and QB, S0 via transmission transistors N7, N8, N9, and N10, making the storage node easier to write data to. This improves the cell's data writing speed and write noise tolerance, providing a good balance between performance, area, power, and reliability for storage operating in radiated environments. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the structure of a DICE circuit in the prior art provided by the present invention;

[0032] Figure 2 A schematic diagram of the structure of the QUATRO 10T circuit in the prior art provided by the present invention;

[0033] Figure 3 This is a schematic diagram of the RHD-12T circuit in the prior art provided by the present invention;

[0034] Figure 4 This is a schematic diagram of the structure of the S4P8N circuit in the prior art provided by the present invention;

[0035] Figure 5 This is a schematic diagram of the RHPD-12T circuit in the prior art provided by the present invention;

[0036] Figure 6 This is a schematic diagram of the structure of a PLM-14T radiation-resistant SRAM memory cell circuit according to the present invention;

[0037] Figure 7 For based on Figure 6 A comparison chart of the number of failures in 2000 Monte Carlo simulations;

[0038] Figure 8 For based on Figure 6 The circuit waveform simulation diagram of normal read / write operation;

[0039] Figure 9 For based on Figure 6 The transient waveform simulation diagram of the PLM-14T radiation-resistant SRAM memory cell circuit under different time and different nodes subjected to pulse injection from a double exponential current source.

[0040] Figure 10 For based on Figure 6The PLM-14T radiation-resistant SRAM memory cell circuit and Figures 1-5 Comparison diagram of HSNM, RSNM, and WSNM of unit circuits; Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] To improve the resistance of cells to SEU (Self-Enhancing Usage), existing technologies mainly include the following solutions: such as... Figure 1 The diagram shows a DICE 12T circuit resistant to single-event upsets (SEUs). It has four memory nodes and four transfer transistors. When a single memory node experiences an SEU, that node will eventually be recovered by the remaining nodes. However, when any two memory nodes experience an SEU, the stored information in that node will be flipped and cannot be recovered, resulting in erroneous data.

[0043] like Figure 2 The diagram shows a Soft Error Tolerant 10T SRAM BitCell (QUATRO 10T) circuit. Compared to the traditional six-transistor cell structure, it has better SEU resistance, but the write capability of this cell is poor, and its hold static noise margin (HSNM) and read static noise margin (RSNM) are also poor.

[0044] like Figure 3 The circuit shown is an RHD-12T circuit, which can resist four-node and partial two-node switching, but it has the disadvantages of relatively high power consumption and low critical charge.

[0045] like Figure 4 The diagram shows an S4P8N circuit, which is an improvement on the DICE circuit, enhancing its radiation resistance. However, it has significant shortcomings in layout area, read delay, and static noise margin (SNM).

[0046] like Figure 5The circuit shown is a Radiation Hardened By Polar Design (RHPD-12T), which can resist both single-node switching and partial two-node switching, but at the cost of lower HSNM and RSNM.

[0047] This embodiment addresses the issues of reduced write speed and high power consumption in existing memory cells due to SEU (Self-Enhancing Unstable Memory) protection by providing a PLM-14T radiation-hardened SRAM memory cell circuit. This embodiment employs a dual pull-down loop for feedback regulation of the memory nodes, enhancing the memory node's anti-flip capability. Furthermore, the circuit uses four transfer transistors for read and write operations, improving the cell's data write speed and write noise tolerance.

[0048] like Figure 6 As shown, the PLM-14T radiation-hardened SRAM memory cell circuit includes ten NMOS transistors and four PMOS transistors; the ten NMOS transistors are denoted as N1 to N10, and the four PMOS transistors are denoted as P1 to P4; PMOS transistors P1 and P2, as well as P3 and P4, are cross-coupled and act as pull-up transistors; NMOS transistors N1 and N2 act as pull-down transistors corresponding to P1 and P2, and similarly, NMOS transistors N3 and N4 act as pull-down transistors corresponding to P3 and P4; NMOS transistors N5 and N6 form a feedback loop for adjusting the memory nodes; the two main memory nodes Q and QB are connected to the bit lines BL and BLB respectively through two NMOS transistors N7 and N8; the two redundant memory nodes S1 and S0 are connected to the bit lines BL and BLB respectively through two NMOS transistors N9 and N10; among them, the four NMOS transistors N7, N8, N9, and N10 are controlled by the word line WL.

[0049] All MOS transistors have a gate length of 65nm. Among them, the gate widths of NMOS transistors N1 to N4 are all 280nm, the gate widths of NMOS transistors N5 and N6 are 420nm, and the gate widths of the remaining transistors are all 140nm.

[0050] Bit line BL is electrically connected to the source of transmission transistors N7 and N9; bit line BLB is electrically connected to the source of transistors N8 and N10; word line WL is electrically connected to the gate of transmission transistors N7, N8, N9, and N10; the drain of transmission transistor N7 is electrically connected to the drain of NMOS transistor N1; the drain of transmission transistor N8 is electrically connected to the drain of NMOS transistor N2; the drain of transmission transistor N9 is electrically connected to the drain of PMOS transistor P4; the drain of transmission transistor N10 is electrically connected to the drain of PMOS transistor P3; VDD is electrically connected to the source of PMOS transistors P1, P2, P3, and P4; the sources of NMOS transistors N1 to N6 are grounded.

[0051] The specific connection methods between transistors are as follows:

[0052] The drain of PMOS transistor P1 is electrically connected to the drain of NMOS transistor N1 and the drain of NMOS transistor N7, and the gate of PMOS transistor P1 is electrically connected to the drain of PMOS transistor P2 and the drain of NMOS transistor N8.

[0053] The drain of PMOS transistor P2 is electrically connected to the drain of NMOS transistor N2 and the drain of NMOS transistor N8, and the gate of PMOS transistor P2 is electrically connected to the drain of PMOS transistor P1 and the drain of NMOS transistor N7.

[0054] The drain of PMOS transistor P3 is electrically connected to the drain of NMOS transistor N3, the drain of NMOS transistor N6, and the drain of NMOS transistor N10. The gate of PMOS transistor P3 is electrically connected to the drain of NMOS transistor N5, the drain of NMOS transistor N4, and the drain of NMOS transistor N9.

[0055] The drain of PMOS transistor P4 is electrically connected to the drain of NMOS transistor N4, the drain of NMOS transistor N5, and the drain of NMOS transistor N9. The gate of PMOS transistor P4 is electrically connected to the drain of NMOS transistor N6, the drain of NMOS transistor N3, and the drain of NMOS transistor N10.

[0056] The drain of NMOS transistor N1 is electrically connected to the drain of PMOS transistor P1 and the drain of NMOS transistor N7, and the gate of NMOS transistor N1 is electrically connected to the drain of PMOS transistor P3 and the drain of NMOS transistor N3.

[0057] The drain of NMOS transistor N2 is electrically connected to the drain of PMOS transistor P2 and the drain of NMOS transistor N8, and the gate of NMOS transistor N2 is electrically connected to the drain of PMOS transistor P4 and the drain of NMOS transistor N4.

[0058] The drain of NMOS transistor N3 is electrically connected to the gate of PMOS transistor P4, the drain of PMOS transistor P3, and the drain of NMOS transistor N6. The gate of NMOS transistor N3 is also electrically connected to the gate of PMOS transistor P3, the drain of PMOS transistor P4, the drain of NMOS transistor N5, and the drain of NMOS transistor N4.

[0059] The drain of NMOS transistor N4 is electrically connected to the gate of PMOS transistor P3, the drain of PMOS transistor P4, and the drain of NMOS transistor N5. The gate of NMOS transistor N4 is also electrically connected to the gate of PMOS transistor P4, the drain of PMOS transistor P3, the drain of NMOS transistor N3, and the drain of NMOS transistor N6.

[0060] The drain of NMOS transistor N5 is electrically connected to the drain of NMOS transistor N9, the gate of PMOS transistor P3, and the drain of PMOS transistor P4. The gate of NMOS transistor N5 is electrically connected to the drain of PMOS transistor P2, the drain of NMOS transistor N2, and the drain of NMOS transistor N8.

[0061] The drain of NMOS transistor N6 is electrically connected to the drain of NMOS transistor N10, the gate of PMOS transistor P4, and the drain of PMOS transistor P3. The gate of NMOS transistor N6 is electrically connected to the drain of PMOS transistor P1, the drain of NMOS transistor N1, and the drain of NMOS transistor N7.

[0062] The principle of the PLM-14T radiation-resistant SRAM memory cell circuit provided in this embodiment is as follows: During the holding phase, bit lines BL and BLB are precharged to a high level, word line WL is at a low level, the circuit maintains its initial state, and the circuit does not work.

[0063] During the data reading phase, bit lines BL and BLB are pre-charged to a high level, word line WL is high, and transmission transistors N7 to N10 are turned on. If the data stored in this unit circuit is '0', then "Q = S1 = 0, QB = S0 = 1". BL then discharges to ground through discharge path 1: transistors N9 and N5, discharge path 2: transistors N7 and N1, and discharge path 3: transistors N9 and N4, creating a voltage difference in the bit lines, which is then read out by the sensitive amplifier. If the data stored in this unit circuit is '1', then "Q = S0 = 1, QB = S1 = 0". BLB then discharges to ground through discharge path 1: transistors N8 and N2, discharge path 2: transistors N10 and N6, and discharge path 3: transistors N10 and N3, creating a voltage difference in the bit lines, which is then read out by the sensitive amplifier.

[0064] During the data writing phase, the word line WL is high. If BL is high and BLB is low, then '1' is written to memory nodes Q and S1 respectively via transmission transistors N7 and N9. If BL is low and BLB is high, then '1' is written to memory nodes QB and S1 respectively via transmission transistors N8 and N10. During the writing process, because transmission transistors N7 and N9 and N8 and N10 simultaneously write data to internal nodes Q\S0 and QB\S1, the memory nodes are easier to write data to, greatly enhancing the write capability. Simultaneously, the significantly increased write speed reduces the circuit's power consumption.

[0065] When only considering the improvement of the circuit structure's radiation resistance, if the circuit's storage nodes are bombarded by particles, the storage nodes S0 and S1 are each regulated by two pull-down networks, and the pull-down transistors are larger than the pull-up transistors. Therefore, when spatial particles bombard sensitive nodes S0 and S1, the generation of "0-1" voltage pulses at the nodes can be effectively mitigated. Simultaneously, the stability of the data at nodes S0 and S1 ensures that internal nodes Q and QB can recover to their initial state after a flip, thus improving the circuit's resistance to SEUs (Self-Suspension Unstable Events). Furthermore, for single-node flip recovery, all four storage nodes can achieve node recovery. For dual-node recovery, Q-S0, QB-S0, and S1-S0 can all achieve node recovery. In subsequent layout design, placing the Q and QB storage nodes further apart can also effectively alleviate the flip resistance of these two storage nodes.

[0066] The PLM-14T radiation-hardened SRAM memory cell circuit of this embodiment was simulated and verified. An average current value was set, the simulation temperature was 27 degrees Celsius, and the sources of PMOS transistors P1, P2, P3, and P4 were connected to a 1.2V operating voltage. Simulation was performed under these conditions. Figures 1-5 The existing SRAM memory cell was subjected to 2000 Monte Carlo simulations to restore its initial state after the main memory node was injected with a double exponential current source pulse at the same time. The comparison results are shown in Figure 7. The PLM-14T radiation-resistant SRAM memory cell circuit provided in this embodiment had 0 failures. The timing waveforms of word line WL, bit lines BL and BLB, and memory nodes Q, QB, S0, and S1 obtained through simulation experiments are shown in Figure 7. Figure 8 As shown. This embodiment's PLM-14T radiation-resistant SRAM memory cell circuit and... Figures 1-5 Transient simulation experiments were conducted on existing SRAM memory cells at different times and at different nodes under the influence of double exponential current source pulse injections. The transient waveform simulation results of memory nodes Q, QB, S0, and S1 are as follows: Figure 9 As shown. With Figures 1-5A comparison of existing SRAM memory cells using HSNM, RSNM, and WSNM is presented, with the results as follows: Figure 10 As shown, it has a high WSNM.

[0067] Will Figures 1-5 The existing SRAM cell circuit and the PLM-14T radiation-resistant SRAM memory cell circuit of this embodiment were compared and verified by simulation in terms of cell area, read delay, write delay and power consumption. The simulation comparison table is shown below. It can be seen from the simulation comparison table that the read delay, write delay and power consumption have been improved. The write speed of the cell has been greatly improved while sacrificing a smaller cell area, and the power consumption of the cell has been reduced.

[0068] Simulation Comparison Table

[0069] unit <![CDATA[Area (μm 2 )]]> Read latency (ps) Write delay (ps) Power consumption (μW) DICE 7.65 40.74 22.15 3.52 Quatro 6.7 80.32 34.14 9.14 RHD-12T 8.52 50.97 25.13 5.9 S4P8N 10.65 52.03 26.79 3.58 RHPD-12T 7.98 32.79 13.39 3.49 PLM-14T 9.25 24.17 27.81 3.91

[0070] Will Figures 1-5 The critical charge comparison table is obtained by comparing the existing SRAM cell circuit and the PLM-14T radiation-resistant SRAM memory cell circuit of this embodiment with the critical charge. As shown in the table below, it can be seen from the critical charge comparison table that the critical charge value of the PLM-14T radiation-resistant SRAM memory cell circuit provided in this embodiment is higher.

[0071] Critical Charge Reference Table

[0072] Circuit Name Critical charge (fC) Quatro 9.96 RHD-12T 33.05 PLM-14T 34.53 RHPD-12T 42.01 DICE >50 S4P8N >50

[0073] As can be seen from the simulation results, the sensitive nodes in the PLM-14T radiation-resistant SRAM memory cell circuit provided in this embodiment can automatically recover their correct state from soft errors caused by single-event effects. The trade-off between latency, area and power consumption can effectively improve its stability. The memory working in a radiation environment provides a good balance between performance, area, power and reliability.

[0074] The PLM-14T radiation-resistant SRAM memory cell circuit generates cell symbols, making it easy for those skilled in the art to use quickly. They only need to refer to the product manual to connect the circuit, which facilitates its promotion and application in the market.

[0075] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A PLM-14T radiation-resistant SRAM memory cell circuit, characterized in that, It includes: Ten NMOS transistors N1~N10 and four PMOS transistors P1~P4; The sources of transistors P1 to P4 are electrically connected to VDD, and the sources of transistors N1 to N6 are grounded. Transistors P1 and P2, as well as P3 and P4, are cross-coupled. The drain of transistor N1 is electrically connected to the drain of P1, the gate of P2, the gate of N6, and the drain of N7. The gate of N1 is electrically connected to the drain of P3, the gate of P4, the drain of N3, the gate of N4, the drain of N6, and the drain of N10. The drain of transistor N2 is electrically connected to the gate of P1, the drain of P2, the gate of N5, and the drain of N8. The gate of N2 is electrically connected to the gate of P3, the drain of P4, the gate of N3, the drain of N4, the drain of N5, and the drain of N9. Bit line BL is electrically connected to the source of N7 and N9; bit line BLB is electrically connected to the source of N8 and N10; word line WL is electrically connected to the gate of N7, N8, N9, and N10; memory nodes Q and QB are connected to bit lines BL and BLB via N7 and N8 respectively; memory nodes S1 and S0 are connected to bit lines BL and BLB via N9 and N10 respectively; transistors N5 and N6 form a feedback loop for adjusting the memory nodes. Among them, Q is connected to BL through N7; QB is connected to BLB through N8; S1 is connected to BL through N9; and S0 is connected to BLB through N10. N1 and N2 correspond to P1 and P2 as pull-down transistors; N3 and N4 correspond to P3 and P4 as pull-down transistors.

2. The PLM-14T radiation-resistant SRAM memory cell circuit according to claim 1, characterized in that, The gate length of transistors N1~N10 and P1~P4 is 65nm, the gate width of transistors N1~N4 is 280nm, the gate width of transistors N5 and N6 is 420nm, and the gate width of transistors N7~N10 and P1~P4 is 140nm.

3. The PLM-14T radiation-resistant SRAM memory cell circuit according to claim 1, characterized in that, Storage nodes Q and QB are primary storage nodes, and storage nodes S1 and S0 are redundant storage nodes.

4. The PLM-14T radiation-resistant SRAM memory cell circuit according to claim 1, characterized in that, The transistors N7 to N10 are transmission transistors and are controlled by the word line WL.

5. The PLM-14T radiation-resistant SRAM memory cell circuit according to claim 4, characterized in that, When the radiation-resistant SRAM memory cell is in the hold phase, the bit lines BL and BLB are precharged to a high level, the word line WL is at a low level, and the circuit maintains its initial state.

6. The PLM-14T radiation-resistant SRAM memory cell circuit according to claim 4, characterized in that, When the radiation-resistant SRAM memory cell is in the data read phase, the bit lines BL and BLB are precharged to a high level, the word line WL is at a high level, and transistors N7 to N10 are turned on.

7. The PLM-14T radiation-resistant SRAM memory cell circuit according to claim 6, characterized in that, If the data stored in the radiation-resistant SRAM memory cell is '0', then "Q=S1=0, QB=S0=1"; the bit line BL discharges to ground through discharge path 1: transistors N9 and N5, discharge path 2: transistors N7 and N1, and discharge path 3: transistors N9 and N4, causing a voltage difference between the bit lines BL and BLB, and the data is read out through the sensitive amplifier.

8. The PLM-14T radiation-resistant SRAM memory cell circuit according to claim 6, characterized in that, If the data stored in the radiation-resistant SRAM memory cell is '1', then "Q=S0=1、QB=S1=0"; the bit line BLB discharges to ground through discharge path 1: transistors N8 and N2, discharge path 2: transistors N10 and N6, and discharge path 3: transistors N10 and N3, causing a voltage difference between the bit lines BLB and BL, and the data is read out through the sensitive amplifier.

9. The PLM-14T radiation-resistant SRAM memory cell circuit according to claim 4, characterized in that, When the radiation-resistant SRAM memory cell is in the data writing stage, the word line WL is at a high level.

10. The PLM-14T radiation-resistant SRAM memory cell circuit according to claim 9, characterized in that, If bit line BL is high and bit line BLB is low, then transistors N7 and N9 write '1' to memory nodes Q and S1 respectively; if bit line BL is low and bit line BLB is high, then transistors N8 and N10 write '1' to memory nodes QB and S1 respectively.

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