Apparatus and methods for intermittent dynamic start voltage and program verify sampling in memory subsystems

Abstract

The present disclosure relates to intermittent dynamic start voltage and program verify sampling in a memory sub-system. Control logic in a memory device identifies a first word line group associated with a first subset of memory cells of a set of memory cells to be programmed. A first dynamic start voltage operation including a first set of program pulses and a first set of program verify operations is performed on a first portion of the first subset of memory cells to identify a first dynamic start voltage level, the performance of the first dynamic start voltage operation including causing the first set of program pulses to be applied to at least a portion of the first word line group. A second set of program pulses including at least one program pulse having the first dynamic start voltage level is caused to be applied to the first word line group to program a second portion of the first subset of memory cells of the set of memory cells.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to intermittent dynamic start voltage and program verify sampling in a memory sub-system. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at and retrieve data from the memory devices. SUMMARY

[0003] The present disclosure provides a memory device including a memory array comprising a set of memory cells, and control logic operably coupled with the memory array to perform operations including identifying a first group of word lines associated with a first subset of memory cells of the set of memory cells to be programmed, performing a first dynamic start voltage operation comprising a first set of program pulses and a first set of program verify operations on a first portion of the first subset of memory cells of the set of memory cells to identify a first dynamic start voltage level, the performing of the first dynamic start voltage operation including causing the first set of program pulses to be applied to at least a portion of the first group of word lines, causing a second set of program pulses comprising at least one program pulse having the first dynamic start voltage level to be applied to the first group of word lines to program a second portion of the first subset of memory cells, identifying a second group of word lines associated with a second subset of memory cells of the set of memory cells to be programmed, and performing a second dynamic start voltage operation comprising a third set of program pulses and a second set of program verify operations on a first portion of the second subset of memory cells to identify a second dynamic start voltage level, the performing of the second dynamic start voltage operation including causing the second set of program pulses to be applied to at least a portion of the second group of word lines.

[0004] The present disclosure provides a memory device including a memory array comprising a plurality of memory cells; and control logic operably coupled with the memory array to perform operations including identifying a set of memory cells in a memory device configured as single level cell (SLC) memory to be programmed during a program operation; performing the program operation including a first sampling operation on a first portion of a first subset of memory cells of the set of memory cells to identify a first magnitude of a first dynamic start voltage level, the performing of the first sampling operation including causing a first set of program pulses to be applied to at least a portion of a first word line group associated with the first portion of the first subset of memory cells; causing a first program pulse of a second set of program pulses to be applied to the first word line group to program a second portion of the first subset of memory cells of the set of memory cells, wherein the first program pulse has the first magnitude of the first dynamic start voltage level; and performing a second sampling operation on a first portion of a second subset of memory cells of the set of memory cells to identify a second magnitude of a second dynamic start voltage level, the performing of the second sampling operation including causing a third set of program pulses to be applied to at least a portion of a second word line group associated with the first portion of the second subset of memory cells.

[0005] The present disclosure provides a method including identifying a first word line group associated with a first subset of memory cells of a set of memory cells to be programmed; performing a first dynamic start voltage operation including a first set of program pulses and a first set of program verify operations on a first portion of the first subset of memory cells of the set of memory cells to identify a first dynamic start voltage level, the performing of the first dynamic start voltage operation including causing the first set of program pulses to be applied to at least a portion of the first word line group; causing a second set of program pulses including at least one program pulse having the first dynamic start voltage level to be applied to the first word line group to program a second portion of the first subset of memory cells of the set of memory cells; identifying a second word line group associated with a second subset of memory cells of the set of memory cells of a memory array to be programmed; and performing a second dynamic start voltage operation including a third set of program pulses and a second set of program verify operations on a first portion of the second subset of memory cells of the set of memory cells to identify a second dynamic start voltage level, the performing of the second dynamic start voltage operation including causing the second set of program pulses to be applied to at least a portion of the second word line group. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure will become more fully understood from the detailed description provided hereinafter and the accompanying drawings of various embodiments of the disclosure.

[0007] Figure 1An example computing system including a memory sub-system according to some embodiments of the disclosure is illustrated.

[0008] Figure 2 is a block diagram of a memory device in communication with a memory sub-system controller of a memory sub-system according to embodiments.

[0009] Figure 3 is a flow diagram of an example method of dynamic start voltage (DSV) programming of all levels of a memory device in a memory sub-system according to some embodiments of the disclosure.

[0010] Figure 4 A portion of an example memory block of a memory device including a plurality of memory cell sub-blocks and a plurality of word lines grouped into a plurality of word line groups according to one or more embodiments of the disclosure is illustrated.

[0011] Figures 5A-5C An example dynamic start voltage (DSV) sampling operation according to some embodiments of the disclosure is illustrated, as well as using an identified DSV for a remainder of a word line group.

[0012] Figure 6A and 6B An example data structure according to some embodiments of the disclosure is illustrated, which illustrates an operation performed to sample a first portion of a respective word line group in order to identify a dynamic start voltage for use in programming a remainder of the respective word line group.

[0013] Figure 7 is a block diagram of an example computer system in which embodiments of the disclosure can operate. DETAILED DESCRIPTION

[0014] Aspects of the disclosure are directed to intermittent dynamic start voltage (DSV) and program verify sampling in a memory sub-system. The memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. In conjunction with Figure 1 Examples of storage devices and memory modules are described. Generally, a host system can utilize a memory sub-system including one or more components, such as a memory device that stores data. The host system can provide data to store at the memory sub-system, and can request data to be retrieved from the memory sub-system.

[0015] The memory sub-system can include high density non-volatile memory devices, where retention of data is required when no power is supplied to the memory device. One example of a non-volatile memory device is a NAND memory device. Examples of storage devices and memory modules are described below in conjunction with Figure 1Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks and sub-blocks. Each sub-block includes a set of pages. Each page is composed of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more binary bits of information and have various logic states related to the number of bits stored. The logic states can be represented by binary values (e.g., “0” and “1” or combinations of such values).

[0016] A memory device can be composed of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (also referred to below as bit lines) and rows (also referred to below as word lines). A word line can refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes an address for a memory cell. Hereinafter, a sub-block refers to a unit of a memory device for storing data and can include a group of memory cells, a group of word lines, a word line, or an individual memory cell.

[0017] A set of one or more memory cells of a memory array can be programmed according to a request from a host system. A program operation can be performed to store information in one or more of the memory devices. During a program operation, a series of program pulses are applied to one or more word lines associated with the memory cells to increase the voltage of the memory cells to a corresponding program level. A first pulse corresponding to a first program level is applied to all cells of a word line (e.g., all cells of a word line) being programmed. Next, a program verify operation is performed to verify that memory cells intended to be programmed to the first program level reach a corresponding target voltage level. Those cells that pass the program verify operation are inhibited while a second pulse corresponding to a second program level is applied to the remaining cells. Another program verify operation is performed, and this sequence continues with additional pulses and program verify operations until programming is complete.

[0018] During a program operation of a set of target memory cells (e.g., single level cells (SLC)), a dynamic start voltage (DSV) process can be initiated to perform a sampling operation on a first page or sub-block corresponding to each word line to be programmed to identify a dynamic start voltage (e.g., an initial voltage level) of an initial program pulse (Vpgm_0) applied to program the remaining pages or sub-blocks of each word line. The DSV process (e.g., a successive prediction DSV process or other suitable process for dynamically adjusting a start voltage in conjunction with a step program pulse process) includes a sampling operation that includes applying a set of program pulses and associated program verify operations to a sampled portion of memory cells. Based on the results of the sampling operation, offset information (e.g., a voltage offset level, also referred to as a “DSV offset”) is determined and used to dynamically adjust the start voltage of the initial program pulse of a series of program pulses applied to one or more word lines associated with memory cells to be programmed. In this approach, a program pulse and a DSV sampling including program verify operations are performed for the sampled portion.

[0019] After identifying the start voltage for the initial program pulse, a series of program pulses are applied and corresponding program verify operations are performed for all remaining pages or sub-blocks of each respective word line. Accordingly, for a given word line having four sub-blocks (e.g., sub-block 0, sub-block 1, sub-block 2, and sub-block 3), a DSV sampling operation including corresponding program verify operations are applied to each sub-block of the given word line, followed by applying a program pulse associated with the identified DSV level and corresponding program verify operations to all memory cells in the remaining sub-blocks (e.g., sub-block 1, sub-block 2, and sub-block 3). Performing a respective program verify operation for each of a plurality of program pulses for each of the remaining portions of a word line after performing a DSV sampling operation results in an increase in program time (Tprog) associated with the memory device. Additionally, the consumption of memory subsystem overhead associated with storing a DSV offset for each word line increases. Furthermore, this approach and the use of program verify operations associated with each program pulse for each word line results in over-programming of memory cells, which causes a decrease in endurance levels due to stress in the electrical media (e.g., oxide) layers of the memory cells.

[0020] Aspects of the disclosure address the above and other deficiencies by implementing programming operations that include an intermittent dynamic start voltage (DSV) operation and a corresponding program verify (PV) operation applied to a portion of a target set of memory cells to be programmed. In embodiments, an intermittent DSV operation and a corresponding set of PV operations are performed on a sampled or first portion of a set of word lines (e.g., a set of N word lines), such as a first page of a sub-block. The intermittent DSV operation identifies a starting value of a program voltage level (Vpgm_0) of a program pulse applied to a remaining portion (e.g., a sub-block or page) of a group of word lines (e.g., a group of N word lines). In embodiments, a program pulse at the identified Vpgm is applied without a corresponding program verify operation. In this regard, the program verify operation is skipped during programming of the remaining pages of the group of word lines.

[0021] In embodiments, the DSV is resampled (e.g., due to word line variations) on a first portion of a next group of word lines to recalculate Vpgm to confirm a higher program verify level for the next group of word lines. Accordingly, the DSV operation and corresponding PV operation are sampled in an intermittent manner such that the sampling or resampling of a portion of a group of word lines is performed on only a first portion of each group of word lines. In embodiments, each N word line group represents a corresponding interval (e.g., portion) in which the DSV sampling or resampling is performed for a first portion of each group of word lines.

[0022] Advantageously, the program verify operation is performed in conjunction with the sampling of the initial or first portion of the group of word lines and can be skipped during programming of the remaining portion of the group of word lines. Skipping the program verify operation results in a reduction in programming time without reducing the read window budget (i.e., valley margin) for the program level of the memory cells. Advantages of this approach include, but are not limited to, an increase in performance of the memory sub-system. Since fewer program verify operations are performed, latency associated with program verify start and recovery times is minimized. Additionally, the programming operations including the intermittent DSV operation enable the use of the same DSV offset for the entire group of word lines, which reduces system overhead.

[0023] Figure 1 An example computing system 100 including a memory sub-system 110 in accordance with some embodiments of the present disclosure is illustrated. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such.

[0024] The memory sub-system 110 can be a storage device, a memory module, or a mix of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controller (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked consumer device), or such computing device that includes a memory and a processing device.

[0026] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1 One example of a host system 120 coupled to one memory sub-system 110 is described. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0027] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory sub-system 110, e.g., to write data to the memory sub-system 110 and to read data from the memory sub-system 110.

[0028] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a double data rate (DDR) memory bus, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface that supports double data rate (DDR)), etc. The physical host interface can be used to transmit data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize an NVM Express (NVMe) interface to access the memory components (e.g., the memory devices 130). The physical host interface can provide an interface for communicating control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 The memory sub-system 110 is illustrated as an example. In general, a host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0029] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory devices 140) can be, but are not limited to, random access memories (RAMs) such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0030] Some examples of non-volatile memory devices (e.g., the memory devices 130) include “not- and” (NAND) type flash memory and in-place write memory such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory can incorporate stackable cross-gridded data access arrays to store bits based on changes in bulk resistance. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLCs), can store one bit of data per cell. Other types of memory cells, such as multi-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), and five-to-level cells (PLCs), can store multiple bits of data per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLCs, MLCs, TLCs, QLCs, or any combination of such arrays of memory cells. In some embodiments, a particular memory device can include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory devices 130 can be grouped into pages, which can refer to a logical unit of the memory device for storing data. For some types of memory, such as NAND, pages can be grouped to form blocks. In one embodiment, the term “MLC memory” can be used to refer to any type of memory cell that stores more than one bit of data per cell, such as 2 bits, 3 bits, 4 bits, or 5 bits per cell.

[0032] While non-volatile memory components are described, such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memory (e.g., 2D NAND, 3D NAND), the memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non- (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0033] The memory sub-system controller 115 (controller 115 for simplicity) can communicate with the memory devices 130 to perform operations, such as reading data, writing data, or erasing data at the memory devices 130, and other such operations. The memory sub-system controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuits with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory sub-system controller 115 can be a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0035] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing microcode. Although the example memory sub-system 110 in Figure 1 In another embodiment of the disclosure, the memory sub-system 110 does not include the memory sub-system controller 115, but instead can rely upon external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system).

[0036] In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) associated with the memory devices 130. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 130, as well as convert responses associated with the memory devices 130 into information for the host system 120.

[0037] The memory sub-system 110 can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive and decode addresses from the memory sub-system controller 115 to access the memory devices 130.

[0038] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory sub-system controller 115 to perform operations on one or more memory units of the memory device 130. An external controller (e.g., the memory system controller 115) can externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory sub-system 110 is a managed memory device that includes a raw memory device 130 with control logic on-die (e.g., the local media controller 135) and a controller (e.g., the memory sub-system controller 115) within the same memory device package that performs media management. An example of a managed memory device is a managed NAND (MNAND) device.

[0039] In one embodiment, the memory sub-system 110 includes a memory interface component 113. The memory interface component 113 is responsible for handling the interaction of the memory sub-system controller 115 with the memory devices (e.g., memory device 130) of the memory sub-system 110. For example, the memory interface component 113 can send memory access commands corresponding to requests received from the host system 120 to the memory device 130, such as program commands, read commands, or other commands. Additionally, the memory interface component 113 can receive data from the memory device 130, such as data retrieved in response to a read command or confirmation of successful execution of a program command. For example, the memory sub-system controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0040] In one embodiment, the memory device 130 includes a program manager 134 configured to perform corresponding memory access operations in response to receiving memory access commands from the memory interface 113. In some embodiments, the local media controller 135 includes at least a portion of the program manager 134 and is configured to perform the functionality described herein. In some embodiments, the program manager 134 is implemented on the memory device 130 using firmware, hardware components, or a combination thereof. In one embodiment, the program manager 134 receives a request from a requester, such as the memory interface 113, to program data to a memory array of the memory device 130. The memory array can include an array of memory cells formed at the intersection of word lines and bit lines. In one embodiment, the memory cells are grouped into blocks, which can be further divided into sub-blocks, with a given word line shared across a number of sub-blocks. In one embodiment, each sub-block corresponds to a separate plane in the memory array. A group of memory cells associated with a word line within a sub-block is referred to as a physical page. In one embodiment, the sub-blocks are configured as SLC memory.

[0041] According to embodiments, the program manager 134 is configured to implement a program operation that includes an intermittent DSV sampling operation and a corresponding program verify (PV) operation applied to a sampled portion (e.g., a first page) of a target set of memory cells to be programmed. In embodiments, the intermittent DSV sampling operation and a corresponding set of PV operations are performed on a sampled or first portion (e.g., a first page of a sub-block) of a set of word lines (e.g., a word line group including N word lines). The program manager 134 performs the intermittent DSV operation to identify a starting value of a program voltage level (Vpgm_0) of a program pulse applied to a remaining portion (e.g., a sub-block or page) of the word line group (e.g., a group of N word lines). In embodiments, the program manager 134 causes a program pulse at the identified Vpgm to be applied to the remaining portion of the word line group (e.g., a remaining page of N-1 word lines in the group of N word lines) but without a corresponding program verify operation. In this regard, the program manager 134 skips the performance of a program verify operation during the programming of the remaining page of the word line group.

[0042] In embodiments, the program manager 134 resamples the DSV on the first portion of the next word line group (e.g., due to word line variation) to recalculate the Vpgm_0 for the next word line group. Accordingly, the DSV operation and corresponding PV operation are sampled in an intermittent manner such that only a first portion (e.g., a first page) of each word line group is performed for the sampling or resampling of a portion of the word line group. In embodiments, each N word line group represents a corresponding interval (e.g., portion) in which the DSV sampling or resampling is performed for the first portion of each word line group. Additional details regarding the operation of the program manager 134 are described below.

[0043] Figure 2 is a simplified block diagram of a first device in the form of a memory device 130 in communication with a second device in the form of a memory subsystem controller 115 (e.g., a memory subsystem 110) according to embodiments. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) can be a memory controller or other external host device. Figure 1

[0044] ​Memory device 130 includes an array of memory cells 250 logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (e.g., word line), while memory cells in a logical column are typically selectively connected to the same data line (e.g., bit line). A single access line can be associated with more than one logical row of memory cells, and a single data line can be associated with more than one logical column. Memory cells of at least a portion of array of memory cells 250 (not shown in FIG. 1) are capable of being programmed to one of at least two target data states. Figure 2

[0045] Row decode circuitry 208 and column decode circuitry 210 are provided to decode address signals. Address signals are received and decoded to access array of memory cells 250. Memory device 130 also includes input / output (I / O) control circuitry 212 to manage the input of commands, addresses and data to memory device 130 and the output of data and status information from memory device 130. Address registers 214 are in communication with I / O control circuitry 212 and row decode circuitry 208 and column decode circuitry 210 to latch address signals prior to decoding. Command registers 224 are in communication with I / O control circuitry 212 and local media controller 135 to latch incoming commands.

[0046] A controller (e.g., local media controller 135 internal to memory device 130) controls access to array of memory cells 250 in response to commands and generates status information for external memory subsystem controller 115, i.e., local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on array of memory cells 250. Local media controller 135 is in communication with row decode circuitry 208 and column decode circuitry 210 to control row decode circuitry 208 and column decode circuitry 210 in response to addresses. In one embodiment, local media controller 134 includes a program manager 134 that can implement program operations including intermittent dynamic start voltage (DSV) sampling of memory device 130, as described herein.

[0047] ​The local media controller 135 also communicates with a cache register 218. The cache register 218 latches incoming or outgoing data as directed by the local media controller 135 to temporarily store the data while the memory cell array 250 is busy writing or reading other data, respectively. During a program operation (e.g., a write operation), data can be transferred from the cache register 218 to the data register 220 for transfer to the memory cell array 250; new data can then be latched from the I / O control circuit 212 into the cache register 218. During a read operation, data can be transferred from the cache register 218 to the I / O control circuit 212 for output to the memory sub-system controller 115; new data can then be transferred from the data register 220 to the cache register 218. The cache register 218 and / or the data register 220 can form a page buffer (e.g., can form part of) of the memory device 130. The page buffer can additionally include a sense device (not shown in FIG. 1) to sense a data state of a memory cell connected to the memory cell array 250, for example, by sensing a state of a data line of the memory cell. Figure 2 The state register 222 can communicate with the I / O control circuitry 212 and the local memory controller 135 to latch state information for output to the memory sub-system controller 115.

[0048] The memory device 130 receives control signals at the memory sub-system controller 115 from the local media controller 135 via a control link 232. For example, the control signals can include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) can additionally be received via the control link 232 depending on the nature of the memory device 130. In one embodiment, the memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory sub-system controller 115 via a multiplexed input / output (I / O) bus 234, and outputs data to the memory sub-system controller 115 via the I / O bus 234.

[0049] For example, a command can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then can be written into command register 224. An address can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then can be written into address register 214. Data can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then can be written into cache register 218. The data can then be written into data register 220 for programming memory cell array 250.

[0050] In embodiments, cache register 218 can be omitted and data can be written directly into data register 220. Data can also be outputted by input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While reference can be made to I / O pins, they can include any electrically conductive node that enables electrical connection to memory device 130 by an external device (e.g., memory sub-system controller 115), such as commonly used electrically conductive pads or electrically conductive bumps.

[0051] Those of skill in the art will appreciate that additional circuitry and signals can be provided and that the Figure 2 memory device 130 has been simplified Figure 2 It will be recognized that the functionality of the various block components described with reference to Figure 2 may not necessarily be separated in accordance with the various components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device can be adapted to perform the functionality of more than one block component described Figure 2 Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform the functionality of a single block component described

[0052] Figure 3is a flow diagram of an example method of intermittent dynamic start voltage (DSV) sampling of a portion of a group of word lines (also referred to as a word line group) of a memory device in a memory sub-system in accordance with some embodiments of the present disclosure. The method 300 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by a program manager 134 of Figure 1 and Figure 2 Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, it is to be understood that the illustrated embodiments are merely examples, and that the illustrated processes can be performed in different orders, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0053] At operation 310, a first word line group is identified. For example, the processing logic identifies a first word line group associated with a first subset of memory cells of a set of memory cells to be programmed. In an embodiment, the processing logic (e.g., the program manager 134) can receive a request from a requester (e.g., a memory interface 113 of a memory sub-system controller 115) to perform a memory access operation on a memory array (e.g., the memory array 250) of a memory device (e.g., the memory device 130). In one embodiment, the memory access operation includes a program operation directed to a particular address. In one embodiment, the processing logic can identify a first group of N word lines associated with a first subset of memory cells (e.g., a first subset of memory cells of the memory array 250, such as those memory cells associated with a particular word line or multiple word lines of the memory array 250) of a set of memory cells to be programmed. The first word line group can be similar or identical to the exemplary first word line group (WL group 1) of the memory block 400 depicted in FIG. 4 and described in greater detail below. In an embodiment, the first subset of memory cells can include memory cells associated with the first word line group (e.g., the WL group 1 shown in FIG. 4). Figure 4 In an embodiment, the first word line group includes a set of N word lines, where N is a predetermined or default non-zero integer (e.g., N = 1, N = 2,..., N = 10) value (e.g., a trim value). In one embodiment, the set of memory cells is configured as SLC memory. Figure 4 In an embodiment, the first word line group includes a set of N word lines, where N is a predetermined or default non-zero integer (e.g., N = 1, N = 2,..., N = 10) value (e.g., a trim value). In one embodiment, the set of memory cells is configured as SLC memory.

[0054] Figure 4Illustrates a portion of an example memory block 400 of a memory device including a plurality of memory cell sub-blocks (e.g., sub-block 0, sub-block 1, sub-block 2, and sub-block 3) and a plurality of word lines (e.g., WL i , WL i+1 , …, WL 2N ) grouped into a plurality of word line groups (e.g., WL group 1, WL group 2, WL group 3). In embodiments, each word line group can include N word lines (e.g., N = 10). For example, as shown, a first word line group (WL group 1) includes WL i to WL i+N-1 , a second word line group (WL group 2) includes WL N to WL 2N-1 , a third word line group (WL group 3) includes WL 2N to WL 2N-1 ), and so on.

[0055] Referring back to Figure 3 , at operation 320, operations are performed. For example, the processing logic can perform a first dynamic start voltage (DSV) operation including a first set of program pulses and a first set of program verify operations on a first portion of a first subset of memory cell subsets of a set of memory cells to identify a first DSV level, the performing of the first dynamic start voltage operation including causing the first set of program pulses to be applied to at least a portion of a first word line group. In embodiments, the processing logic performs the first DSV operation to determine a program pulse magnitude for a subsequent program event. In embodiments, the determined program pulse magnitude is, for example, a first DSV level (Vpgm_0) that will be used for the subsequent program event. In embodiments, the first DSV sampling operation is performed using the first portion of the first word line group to determine the first DSV level. For example, the first set of program pulses and the first set of PV operations are applied using the first portion of the first word line group to determine the first DSV level. As described later at operation 330, the determined first DSV level is used to program a second portion of the first subset of memory cell subsets associated with one or more remaining portions of the first word line group.

[0056] In embodiments, as shown in Figure 4 , the first portion of the first subset of memory cells includes memory cells of a first page of the first word line group. As shown, the first portion of the first subset of memory cells (also referred to as the "sampled portion") includes memory cells in sub-block 0 associated with WL i of WL group 1 410. In embodiments, the sampled portion 410 of the first word line group (WL group 1) corresponds to a first page of the first word line group (WL group 1).

[0057] Figure 5A and 5Bto illustrate the first DSV operation described above. As shown, the first DSV operation includes a first set of program pulses (e.g., Vpgm0, Vpgm1, Vpgm k ) and corresponding program verify operations (pv0, pv1... pv k ). In embodiments, as shown in Figure 5A , a subset of memory cells (e.g., the first subset of memory cells described above) perform the DSV operation. For example, with reference to Figure 4 and 5A , the illustrated DSV sampling operation is applied to a first sampled portion 410 that includes memory cells associated with WL group 1 (e.g., memory cells of the first page of WL group 1). As shown in Figure 5A , the DSV operation includes the application of a series of program pulses having stepped program voltage levels (e.g., Vpgm0, Vpgm1, Vpgm k ).

[0058] In embodiments, the processing logic can perform the DSV operation to determine a value of Voffset (e.g., an offset voltage) that is offset information that the processing logic can use to adjust (e.g., increase or decrease) a value of a first DSV level (e.g., the voltage Vpgm_0) of a first program pulse used for a subsequent program event (e.g., the programming of the remaining pages in WL group X, as shown in Figure 5C ). In embodiments, the processing logic determines Voffset based on a count value of memory cells that undergo the first DSV operation (e.g., the count value of memory cells of the sampled portion 410 of Figure 4 , such as memory cells in page 1 of sub-block 0 that pass the corresponding program verify level (e.g., using a suitable technique, such as the continuous predictive DSV method)). In embodiments, the processing logic identifies the first DSV level (Vpgm_0) that corresponds to a condition satisfaction. In embodiments, the condition is satisfied if the number of memory cells (e.g., the number of passed cells) that undergo the first DSV operation with threshold voltages (Vt) higher than the program verify level is greater than a threshold count level.

[0059] For example, as shown in Figure 5A and 5B , the condition is satisfied (e.g., the cell count of the sampled portion of memory cells associated with WL group X is greater than or equal to a cell count threshold) after the application of program pulse Vpgm k . In embodiments, the processing logic identifies the first DSV level (Vpgm_0) that corresponds to the application of Vpgm kVoffset. In an embodiment, Voffset corresponds to a threshold voltage (Vt) level for which the program verify operation identifies a cell count through the memory cells greater than or equal to a threshold level (e.g., a threshold cell count).

[0060] Determining the magnitude of the program pulse at operation 320 includes, for example, the processing logic determining (e.g., identifying) a first DSV level (Vpgm_0) for subsequent programming of the remaining portion of the WL group X, as shown in Figures 5A-5C Particularly, in this example, Vpgm_0 is calculated according to the following expression:

[0061] Vpgm_0 = Vpgm K + V offset + a correction factor (CF);

[0062] where the correction factor is a factor to adjust for word line variation. In an embodiment, the correction factor (CF) can be used to fine tune Vpgm in view of the ratio variation of Vg and Vt in the N word line group. In an embodiment, the correction factor can be determined using linear interpolation to compensate for expected Vg Vt variation within the group of N word lines. In an embodiment, the correction coefficient can be determined based on the slope of Vg Vt. In an embodiment, the correction factor can be expressed as follows:

[0063] CF = -dVg Vt / N.

[0064] In an embodiment, Vpgm_0 identified for use in programming the remaining pages in the WL group can be determined with or without using CF.

[0065] Returning to Figure 3 At operation 330, a program pulse is applied. For example, the processing logic can cause a second set of program pulses including at least one program pulse having a first DSV level to be applied to the first word line group to program a second portion of the first subset of memory cells. In an embodiment, at least one program pulse having the first DSV level (Vpgm_0, as determined at operation 320) is applied to each word line of the second portion of the first word line group. In an embodiment, the second set of program pulses includes a plurality of program pulses having the first DSV level (Vpgm_0, as determined at operation 320). Figure 4 In the example shown, the first DSV level (Vpgm_0) is applied to the WL group 1 to program a second portion of the first subset of memory cells (e.g., memory cells of the remaining pages of the sub-blocks associated with the N word lines in the first word line group (WL group 1)).

[0066] In an embodiment, operation 330 is performed with respect to the programming of the remaining memory cells of the first subset of memory cells and without performing a corresponding program verify operation. As shown by Figure 5Cdashed lines in FIG. 4A indicate that a program verify operation is skipped in conjunction with the application of a set of program pulses when programming the remaining memory cells associated with a particular word line group (e.g., WL group X). Advantageously, skipping the program verify operation for the remaining memory cells associated with a word line group reduces program time and improves memory cell endurance. In an embodiment, the program verify operation is not performed during a first time period during which the remaining portion of the memory cells associated with the first word line group are programmed.

[0067] At operation 340, a second word line group is identified. For example, the processing logic identifies a second word line group associated with a second subset of memory cells of the set of memory cells to be programmed. In one embodiment, the processing logic can identify a second group of N word lines associated with a second subset of memory cells of the set of memory cells to be programmed (e.g., a second subset of memory cells of memory array 250, such as those memory cells associated with a particular word line or multiple word lines of memory array 250). The second word line group can be similar or identical to the exemplary second word line group (WL group 2) of memory block 400 depicted in FIG. 4A and described in greater detail below. In an embodiment, the second subset of memory cells can include memory cells associated with the second word line group (e.g., WL group 2) shown in FIG. 4A. In an embodiment, the second word line group includes a set of N word lines (e.g., WL Figure 4 Figure 4 N to the set of N word lines (e.g., WL 2N-1 ) of the second word line group (e.g., WL group 2) shown in FIG. 4A, where N is a predetermined or default non-zero integer (e.g., N = 1, N = 2,..., N = 10) value (e.g., trim value).

[0068] At operation 350, an operation is performed. For example, the processing logic can perform a second DSV operation including a third set of program pulses on a first portion of the second subset of memory cells and a second set of program verify operations to identify a second dynamic start voltage level, the performance of the second DSV operation including causing the second set of program pulses to be applied to at least a portion of the second word line group. In an embodiment, the processing logic performs the second DSV operation to determine a program pulse magnitude for a subsequent programming event. In an embodiment, the determined program pulse magnitude is, for example, the second DSV level to be used for the subsequent programming event. In an embodiment, the first DSV sampling operation is performed using the first portion of the second word line group to determine a first DSV level. For example, the third set of program pulses and the second set of PV operations are applied using the first portion of the second word line group to determine the second DSV level. In an embodiment, the determined second DSV level is used to program a second portion of the second subset of memory cells associated with one or more remaining portions of the second word line group.

[0069] In an embodiment, as Figure 4 ​​As shown, the first portion of the second word line group (WL group 2) contains memory cells in sub-block 0 associated with the second word line group. As shown, the first portion or sampled portion 420 contains a subset of the second memory cells associated with WL group 2 (e.g., with WL...). N (Memory cells in associated sub-block 0). For example... Figure 4 As shown, the second word line group contains WL N To WL 2N-1 (For example, a second set or group of N word lines). In an embodiment, the sampled portion 420 of the second word line group (WL group 2) corresponds to the first page of the second word line group (WL group 2).

[0070] In an embodiment, the processing logic is executed for each word line group (e.g., Figure 4 The new DSV operation is performed on a portion of WL group 1, WL group 2, WL, group 3, etc. In an embodiment, a first DSV operation is performed on a portion of WL group 1, a second DSV operation on a portion of WL group 2, a third DSV sampling operation on a portion of WL group 3, and so on until the DSV level (Vpgm_0) of each corresponding word line group has been identified. Advantageously, the DSV operation and corresponding programming verification operation are performed only on the sampled portion of the memory cell associated with each word line group, so as to avoid performing additional programming verification operations in relation to the remaining portion of the memory cell associated with each word line group.

[0071] Figure 6A and 6B Describe a data structure (e.g., a table) that illustrates the operations performed with respect to the set of memory cells associated with the corresponding word lines of each word line group having N word lines. Figure 6A In the example shown, N = 1 (for example, a word line group contains 1 word line). Figure 6B In the example shown, N = 10 (for example, the word line group contains 10 word lines). For example... Figure 6A As shown, for the first portion of the first subset of memory cells (e.g., WL) i The processing logic causes one or more programming pulses (PP) to be applied as part of a DSV operation (DSV / PV) to identify the DSV level (Vpgm_0) for use when programming the remainder of the word lines in each word line group. For example, for Figure 6A WL i The DSV sampling operation performed on sub-block 0 is determined for word line group 1 (i.e., PP). DSV1The programming pulse (PP) of sub-blocks 1, 2, and 3 (e.g., the remainder) is Vpgm_0 (first DSV voltage level or DSV1). Figure 6A As shown, for the first part of the second word line group (e.g., WL) i+1 The memory cell in the first page or sub-block 0) performs a second DSV operation (e.g., resampling) to identify the word line group 2 (i.e., PP). DSV2 The second DSV level (e.g., DSV2) of the programming pulses (PP) for sub-blocks 1, 2, and 3 (e.g., the remaining portions) of the memory cell. In an embodiment, a sampling or resampling operation is performed for each first portion of the memory cell associated with each corresponding word line group to identify the DSV level of the programming pulse to be applied to the remaining portion of the memory cell associated with each corresponding word line group, without performing a corresponding programming verification operation.

[0072] Figure 6B This illustrates another instance of a word line group with 10 word lines (e.g., N=10). As shown, the DSV operation is applied to the word line group (containing WL). i To Wl i+N-1 The first part of WL group 1 (e.g., WL) i The memory cells of sub-block 0 (first page). In this example, the DSV operation identifier will be used for the programming pulse (PP) to program the remaining portion of the memory cells associated with WL group 1 (e.g., WL). i The memory cells of sub-blocks 1 to 3 and WL i+1 To WL i+N-1 The starting voltage (e.g., DSV1) of all sub-blocks. For example... Figure 6B As shown, for the second word line group (e.g., from WL) N The second DSV operation is performed on the first portion of the second group of the initial 10 word lines. In an embodiment, programming of the word lines in each of the respective word line groups continues until the programming operation is complete. In an embodiment, the DSV operation and the corresponding programming verification operation are performed on the first portion of the subset of memory cells associated with each word line group, such that the execution of the programming verification operation can be skipped or eliminated when programming the remaining portion of the subset of memory cells associated with each word line group.

[0073] Figure 7 This describes an instance machine of computer system 700, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 700 corresponds to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1memory subsystem 110) or can be used to perform operations of the controller (e.g., to execute an operating system to perform operations corresponding to Figure 1

[0074] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a

[0075] Example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0076] Processing device 702 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or

[0077] ​The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium, such as a non-transitory computer-readable medium) on which one or more instruction sets 726 or software embodying any or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially in main memory 704 and / or processing device 702 during execution by computer system 700, the main memory 704 and processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0078] In one embodiment, instruction 726 includes instructions for implementing the corresponding Figure 1 The programming manager 114 provides functional instructions. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods disclosed herein. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0079] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0080] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0081] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0082] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0083] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.

[0084] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made to the disclosure without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A memory device comprising: a memory array comprising a set of memory cells; and control logic operably coupled with the memory array to perform operations comprising: identifying a first word line group associated with a first subset of memory cells of the set of memory cells to be programmed; performing a first dynamic start voltage operation comprising a first set of program pulses and a first set of program verify operations on a first portion of the first subset of memory cells of the set of memory cells to identify a first dynamic start voltage level, the performing of the first dynamic start voltage operation comprising causing the first set of program pulses to be applied to at least a portion of the first word line group; causing a second set of program pulses comprising at least one program pulse having the first dynamic start voltage level to be applied to the first word line group to program a second portion of the first subset of memory cells; identifying a second word line group associated with a second subset of memory cells of the set of memory cells to be programmed; and performing a second dynamic start voltage operation comprising a third set of program pulses and a second set of program verify operations on a first portion of the second subset of memory cells to identify a second dynamic start voltage level, the performing of the second dynamic start voltage operation comprising causing the second set of program pulses to be applied to at least a portion of the second word line group.

2. The memory device of claim 1, the operations further comprising: in response to the first set of program pulses being applied, performing the first set of program verify operations to verify whether the first portion of the first subset of memory cells of the set of memory cells is programmed to a respective program level of a plurality of program levels.

3. The memory device of claim 1, wherein no program verify operations are performed during the application of the second set of program pulses to the first word line group to program the second portion of the first subset of memory cells of the set of memory cells.

4. The memory device of claim 1, wherein the first dynamic start voltage operation comprises identifying the first dynamic start voltage level based on a first voltage offset and a first correction factor corresponding to the first portion of the first subset of memory cells of the set of memory cells.

5. The memory device of claim 1, wherein the first portion of the first subset of memory cells comprises a first page associated with a first word line of the first word line group.

6. The memory device of claim 1, the operations further comprising: causing a fourth set of program pulses comprising at least one program pulse having the second dynamic start voltage level to be applied to the second word line group to program a second portion of the second subset of memory cells of the set of memory cells.

7. The memory device of claim 6, wherein no program verify operations are performed during the application of the fourth set of program pulses to the second word line group to program the second portion of the second subset of memory cells of the set of memory cells.

8. A memory device comprising: ​ A memory array comprising a plurality of memory cells; and Control logic operably coupled with the memory array to perform operations comprising: identifying a set of memory cells in a memory device configured as single level cell (SLC) memory to be programmed during a program operation; performing the program operation comprising a first sampling operation on a first portion of a first subset of memory cells of the set of memory cells to identify a first magnitude of a first dynamic start voltage level, the performing of the first sampling operation comprising causing a first set of program pulses to be applied to at least a portion of a first word line group associated with the first portion of the first subset of memory cells; causing a first program pulse of a second set of program pulses to be applied to the first word line group to program a second portion of the first subset of memory cells of the set of memory cells, wherein the first program pulse has the first magnitude of the first dynamic start voltage level; and performing a second sampling operation on a first portion of a second subset of memory cells of the set of memory cells to identify a second magnitude of a second dynamic start voltage level, the performing of the second sampling operation comprising causing a third set of program pulses to be applied to at least a portion of a second word line group associated with the first portion of the second subset of memory cells.

9. The memory device of claim 8, wherein the first portion of the first subset of memory cells comprises a first memory page associated with a first word line of the first word line group, and wherein the second portion of the first word line group comprises a remaining set of memory pages associated with the first word line group.

10. The memory device of claim 8, wherein performing the first sampling operation comprises: during a first time period, performing a dynamic start voltage process comprising performing a first set of program verify operations to identify a first voltage offset level, wherein the first dynamic start voltage level is determined based at least in part on the first voltage offset level.

11. The memory device of claim 10, wherein performing the second sampling operation comprises: during a second time period, performing the dynamic start voltage process comprising performing a second set of program verify operations to identify a second voltage offset level, wherein the second dynamic start voltage level is determined based at least in part on the second voltage offset level.

12. The memory device of claim 11, wherein no program verify operations are performed during a time period between an end of the first time period and a start of the second time period.

13. The memory device of claim 8, wherein the first set of program pulses are applied to the first portion of the first subset of memory cells to program the first portion of the first subset of memory cells to respective program levels of a plurality of program levels.

14. The memory device of claim 9, the operations further comprising: ​ causing a first program pulse of a third set of program pulses to be applied to a remainder of the second word line group, wherein the first program pulse of the third set of program pulses has a second magnitude corresponding to the second dynamic start voltage level.

15. A method for intermittent dynamic start voltage and program verify sampling in a memory sub-system, comprising: identifying a first word line group associated with a first subset of memory cells of a set of memory cells to be programmed; performing a first dynamic start voltage operation comprising a first set of program pulses and a first set of program verify operations on a first portion of the first subset of memory cells of the set of memory cells to identify a first dynamic start voltage level, the performing of the first dynamic start voltage operation including causing the first set of program pulses to be applied to at least a portion of the first word line group; causing a second set of program pulses comprising at least one program pulse having the first dynamic start voltage level to be applied to the first word line group to program a second portion of the first subset of memory cells of the set of memory cells; identifying a second word line group associated with a second subset of memory cells of the set of memory cells of a memory array to be programmed; and performing a second dynamic start voltage operation comprising a third set of program pulses and a second set of program verify operations on a first portion of the second subset of memory cells of the set of memory cells to identify a second dynamic start voltage level, the performing of the second dynamic start voltage operation including causing the second set of program pulses to be applied to at least a portion of the second word line group.

16. The method of claim 15, further comprising: in response to the first set of program pulses being applied, performing the first set of program verify operations to verify whether the first portion of the first subset of memory cells of the set of memory cells is programmed to respective program levels of a plurality of program levels.

17. The method of claim 15, wherein no program verify operations are performed during the applying of the second set of program pulses to the first word line group to program the second portion of the first subset of memory cells of the set of memory cells.

18. The method of claim 15, wherein the first dynamic start voltage operation comprises identifying the first dynamic start voltage level based on a first voltage offset and a first correction factor corresponding to the first portion of the first subset of memory cells of the set of memory cells.

19. The method of claim 15, further comprising causing a fourth set of program pulses comprising at least one program pulse having the second dynamic start voltage level to be applied to the second word line group to program a second portion of the second subset of memory cells of the set of memory cells.

20. The method of claim 19, wherein no program verify operations are performed during the applying of the fourth set of program pulses to the second word line group to program the second portion of the second subset of memory cells of the set of memory cells.

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