A semiconductor package structure

Abstract

Disclosed is a semiconductor packaging structure, comprising: a bottom plate comprising a substrate and a first conductive layer on the substrate; a frame comprising a frame body and a first inlay embedded in the frame body, the frame body and the first inlay both being annular, and the first inlay being exposed to two end faces of the frame body; and a top cover comprising a top cover body and a second inlay embedded in the top cover body, the second inlay being exposed to a second surface of the top cover body; wherein the first inlay is sealingly connected to the first conductive layer on the substrate at a second end of the frame, and the first inlay is sealingly connected to the second inlay of the top cover at a first end of the frame, and the substrate, the frame and the top cover enclose a cavity. The semiconductor packaging structure comprises a bottom plate, a frame and a top cover, and the two ends of the frame are sealingly connected to the bottom plate and the top cover via welding, so as to improve the sealing property of the semiconductor packaging structure and prevent electric leakage and breakdown.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor package structure. BACKGROUND

[0002] The semiconductor package structure includes a substrate, a shell and at least one chip or semiconductor device, wherein the at least one chip or semiconductor device is arranged on the substrate, and the substrate is glued or mechanically connected with the shell, wherein the shell is integrally arranged or includes a plurality of separately arranged parts. The shell needs to be provided with slots / holes / holes for the pins to pass through, but the slots / holes / holes lead to poor air tightness of the shell; the air tightness of the connection between the shell and the substrate or the connection between the separately arranged shells is also poor.

[0003] The conductive structure for electrical connection inside the semiconductor package structure, such as the bonding wire, is usually made of metal material (for example, copper, silver, etc.), and in a corrosive environment, corrosive gas (such as hydrogen sulfide, hydrochloric acid) can easily enter the inside of the semiconductor package structure through the hole of the shell or the connection between the shell and the substrate, etc. Corrosion layer or dendrite is generated by corrosion of metal material, which affects the resistivity of the material, and if the dendrite is too long, it will cause the circuit to leak or even break down. SUMMARY

[0004] In view of the above problems, the purpose of the present application is to provide a semiconductor package structure to improve the sealing performance of the semiconductor package structure and prevent leakage and breakdown.

[0005] The present application provides a semiconductor package structure, comprising:

[0006] a bottom plate including a substrate and a first conductive layer on the substrate;

[0007] a frame including a frame body and a first inlay embedded in the frame body, the frame body and the first inlay are annular, and the first inlay is exposed to two end faces of the frame body; and

[0008] a top cover including a top cover body and a second inlay embedded in the top cover body, the second inlay being exposed to a second surface of the top cover body;

[0009] wherein the first inlay is sealingly connected with the first conductive layer on the substrate at the second end of the frame, the first inlay is sealingly connected with the second inlay of the top cover at the first end of the frame, and the substrate, the frame and the top cover form a cavity.

[0010] Preferably, the substrate further includes:

[0011] a second conductive layer on the first surface of the substrate; and

[0012] a semiconductor device on the second conductive layer and electrically connected with the second conductive layer.

[0013] Preferably, the first conductive layer is on the first surface of the substrate, the first conductive layer is annular, surrounds the second conductive layer, and a gap is formed between the inner sidewall of the first conductive layer and the outer sidewall of the second conductive layer.

[0014] Preferably, the distance d1 between the inner sidewall of the first conductive layer and the outer sidewall of the second conductive layer satisfies:

[0015]

[0016] wherein, is the working voltage of the semiconductor device packaged in the semiconductor packaging structure, is the minimum value of the breakdown electric field strength in the medium surrounding the semiconductor device.

[0017] Preferably, the first conductive layer is on the second surface of the substrate, the first conductive layer is plate-shaped, wherein the second surface of the substrate is opposite to the first surface of the substrate; the area of the first conductive layer is greater than the area of the substrate, and the substrate is located in the cavity after the first conductive layer is sealingly connected with the first inlay.

[0018] Preferably, further comprising a pin, one end of the pin is electrically connected with the second conductive layer, and the other end of the pin extends to the outside of the semiconductor packaging structure.

[0019] Preferably, the top cover further comprises a first through hole, and the end of the pin not electrically connected with the second conductive layer extends to the outside of the semiconductor packaging structure through the first through hole.

[0020] Preferably, on the second surface of the top cover, the sidewall of the first through hole extends into the cavity.

[0021] Preferably, the thickness of the sidewall of the first through hole extending into the cavity satisfies:

[0022]

[0023] wherein, is the working voltage of the semiconductor device packaged in the semiconductor packaging structure, is the breakdown electric field strength of the material of the top cover body.

[0024] Preferably, a third filling layer is filled between the pins and the sidewall of the first through hole.

[0025] Preferably, the first inlaid body is a one-piece structure and extends through the height direction of the frame body.

[0026] Preferably, part of the pins are embedded in the frame body.

[0027] Preferably, the first inlaid body includes two parts arranged separately, one part of the first inlaid body is exposed to the surface of the second end of the frame body, and the other part of the first inlaid body is exposed to the surface of the first end of the frame body.

[0028] Preferably, the distance d4 between one part of the first inlaid body and the pins satisfies:

[0029]

[0030] The distance d5 between the other part of the first inlaid body and the pins satisfies:

[0031]

[0032] wherein, is the working voltage of a semiconductor device packaged in the semiconductor packaging structure, is the breakdown field strength of the frame body material.

[0033] Preferably, the top cover further comprises:

[0034] a second through hole located on one side close to the second surface of the top cover body;

[0035] a third through hole located on one side close to the first surface of the top cover body;

[0036] The aperture of the third through hole is larger than the aperture of the second through hole, and the second through hole and the third through hole are in communication through the top cover body;

[0037] On one end in communication with the third through hole, an annular third inlaid body is embedded on the outside of the outer wall of the second through hole, the third inlaid body is exposed to the bottom of the third through hole, and the third inlaid body surrounds the second through hole; the top cover further comprises a sealing plate, the sealing plate is located in the third through hole and is in sealing connection with the third inlaid body exposed to the bottom of the third through hole.

[0038] Preferably, the top cover further comprises:

[0039] a second through hole, the second through hole extending through the top cover body;

[0040] A third inlay is embedded outside the outer wall of the second through hole, the third inlay is exposed to the first surface of the top cover body, and the third inlay surrounds the second through hole;

[0041] The top cover further comprises a sealing plate located at the first surface of the top cover body and sealingly connected with the third inlay exposed to the first surface of the top cover body.

[0042] Preferably, the side wall of the second through hole extends into the cavity at the second surface of the top cover body.

[0043] Preferably, a second filling layer is covered on the semiconductor device and the second conductive layer.

[0044] Preferably, the second surface of the top cover body is covered with a first filling layer; the second inlay surrounds the first filling layer and is separated from the first filling layer at the second surface of the top cover.

[0045] Preferably, a gap is provided between the first filling layer and the second filling layer.

[0046] Preferably, the first filling layer is a soft material layer, and the soft material layer contains metal oxide.

[0047] Preferably, the distance between the surface of the first filling layer away from the top cover and the end face of the first through hole extending into the cavity is satisfies:

[0048]

[0049] wherein, is the distance between the inner side wall of the first conductive layer and the outer side wall of the second conductive layer, is the thickness of the side wall of the first through hole extending into the cavity.

[0050] The semiconductor packaging structure provided by the application comprises a bottom plate, a frame and a top cover, and the two ends of the frame are sealingly connected with the bottom plate and the top cover via welding, so that there is no gas diffusion path at the connection of the bottom plate, the frame and the top cover, ensuring the sealing of the semiconductor packaging structure, effectively preventing corrosive gas (such as hydrogen sulfide, hydrochloric acid, etc.) from diffusing into the cavity from the connection of the bottom plate, the frame and the top cover, avoiding the corrosion of the semiconductor device inside the semiconductor packaging structure by the corrosive gas, and ensuring the normal operation of the semiconductor device.

[0051] Further, the frame and the top cover are both provided with a structure of an insulating body covering a metal inlay. On one hand, the metal inlay can realize the solder sealing of the semiconductor packaging structure, and the insulating body covering the metal inlay can avoid the corrosion of the metal inlay in a corrosive environment; on the other hand, the insulating body can improve the insulation between the metal inlay and other conductive structures inside the semiconductor packaging structure, effectively prevent the growth of dendrites in the cavity, and further prevent the formation of a conductive path.

[0052] In a preferred embodiment, the first conductive layer and the second conductive layer are located on the first surface of the substrate, and there is a gap between the first conductive layer and the second conductive layer to reduce the risk of affecting the voltage resistance characteristics of the product introduced by the first conductive layer.

[0053] In a preferred embodiment, the first conductive layer and the second conductive layer are located on the opposite surfaces of the substrate, the first conductive layer is used to realize the sealing connection with the frame and support the substrate, and the first conductive layer can attenuate the electromagnetic wave conducted through the first conductive layer and has a certain electromagnetic shielding effect.

[0054] In a preferred embodiment, the first inlay is a one-piece structure extending through the height direction of the frame, facilitating processing.

[0055] In a preferred embodiment, the first inlay includes two separate parts, and the two separate parts of the first inlay are connected by an insulating frame body, which can improve the insulation of the frame and provide space for the setting of the pins.

[0056] In a preferred embodiment, on the second surface of the top cover, the sidewall of the first through hole extends into the cavity to prevent the sidewall of the first through hole extending into the cavity from being punctured, and a third filling layer is filled between the first through hole and the pin to reduce the diffusion speed of corrosive gas molecules.

[0057] In a preferred embodiment, a first filling layer is covered on the second surface of the top cover body, and the first filling layer is a soft filling material containing metal oxide powder, which can absorb corrosive gas in the cavity and avoid corrosion of the semiconductor device.

[0058] In a preferred embodiment, the second filling layer has a gap with the first filling layer, the gap is a buffer zone, air in the buffer zone is used to dilute the corrosive gas diffused into the cavity through the first via, and to enlarge the contact area of the diluted corrosive gas with the first filling layer, since the solubility of the corrosive gas in the first filling layer is greater than that in the second filling layer, the corrosive gas entering the cavity will be more easily absorbed by the first filling layer.

[0059] In a preferred embodiment, a second via is formed in the top cover, and a sealing plate is added on the second via, and the sealing plate is connected with the third inlay in the top cover by a sealing welding, to block the diffusion path of the corrosive gas. BRIEF DESCRIPTION OF DRAWINGS

[0060] The above and other objects, features and advantages of the present application will become more apparent from the following description of the preferred embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0061] Figure 1 A sectional view of a semiconductor package structure of a first embodiment of the present application is shown;

[0062] Figure 2 A sectional view of a bottom plate of the first embodiment of the present application is shown;

[0063] Figure 3 A sectional view of a frame of the first embodiment of the present application is shown;

[0064] Figure 4 A sectional view of a top cover of the first embodiment of the present application is shown;

[0065] Figure 5 A sectional view of a semiconductor package structure of a second embodiment of the present application is shown. DETAILED DESCRIPTION

[0066] The present application will be described in more detail with reference to the accompanying drawings. In the drawings, like reference numerals refer to like elements throughout. For clarity, not all of the elemental constituents of the application are shown in each drawing. Furthermore, certain prior art can not be shown to assist in a description of the present application.

[0067] The present application can take form in various aspects of which the following descriptions are some examples.

[0068] In existing technologies, semiconductor packaging structures typically employ metal enclosures to provide electromagnetic shielding for the semiconductor devices encapsulated within. To improve shielding efficiency, these metal enclosures are usually integrally formed. However, existing metal enclosures generally require pre-drilled slots / holes / apertures, resulting in poor hermeticity. Furthermore, in corrosive environments (such as hydrogen sulfide and hydrochloric acid), dendrites can grow on the metal enclosure, reducing the distance between the enclosure and its internal leads and / or other conductive structures. Conductive defects at any point within the leads and / or other conductive structures inside the enclosure can cause it to become charged, creating additional conductive and leakage paths and ultimately leading to product failure.

[0069] Figure 1 A cross-sectional view of the semiconductor packaging structure according to a first embodiment of the present invention is shown; as follows: Figure 1 As shown, the semiconductor package structure 100 includes a base plate 110, a frame 120, and a top cover 130. The base plate 110 is combined with the frame 120 at the second end of the frame 120, and the top cover 130 is combined with the frame 130 at the first end of the frame 130. The base plate 110, the frame 120, and the top cover 130 are combined together to form a cavity 140. The first end of the frame 120 is opposite to the second end of the frame 120.

[0070] Figure 2 A cross-sectional view of the base plate according to the first embodiment of the present invention is shown, as follows. Figure 1 and Figure 2 As shown, the base plate 110 includes a substrate 111 and a first conductive layer 112 and a second conductive layer 113 covering a first surface of the substrate 111. The first conductive layer 112 is annular and surrounds the edge of the first surface of the substrate 111. The substrate 111 supports the first conductive layer 112 and the second conductive layer 113, and the first conductive layer 112 provides a sealed connection with the frame 120, so that the base plate 110 is sealed to the frame 120 at a second end. In this embodiment, the substrate 111 is, for example, a copper-clad ceramic (DBC) substrate, and the first conductive layer 112 is, for example, a copper conductive layer covering the first surface of the substrate 111.

[0071] Figure 3 A cross-sectional view of the frame according to a first embodiment of the present invention is shown, as follows. Figure 1 and Figure 3As shown, the frame 120 comprises a frame body 121 and a first inlay 122 embedded inside the frame body 121, the frame body 121 and the first inlay 122 are annular to form the annular frame 120. In the height direction of the frame body 121, the first inlay 122 penetrates the frame body 121 and is exposed to the first end surface and the second end surface of the frame body 121. Wherein, the frame body 121 is molded by thermoplastic material (such as PBT material, TPU material, etc.), and the first inlay 122 is punched by metal material (such as copper). The frame body 121 is used to wrap the first inlay 122 to avoid the first inlay 122 made of metal material from being corroded to produce dendrites in a corrosive environment, resulting in electric leakage and even product failure; the frame body 121 can improve the insulation performance between the first inlay 122 and other conductive structures, and can effectively prevent the growth of dendrites in the cavity 140 to form a conductive path.

[0072] Figure 4 A cross-sectional view of the top cover of the first embodiment of the application is shown in FIG. 2. Figure 1 and Figure 4 As shown, the top cover 130 comprises a top cover body 131 and a second inlay 132 embedded inside the top cover body 131, the top cover body 131 is plate-shaped, and the second inlay 132 is annular, and the top cover body 131 and the second inlay 132 form the plate-shaped top cover 130. The second inlay 132 is exposed to the second surface of the top cover body 131, and the first surface and the second surface are opposite. The top cover body 131 is molded by thermoplastic material (such as PBT material, TPU material, etc.), and the second inlay 132 is punched by metal material (such as copper). Wherein, the thickness of the top cover body 131 is greater than the thickness of the second inlay 132, so that the second inlay 132 is only exposed to the second surface of the top cover body 131.

[0073] In this embodiment, the first conductive layer 112, the first inlay 122 and the second inlay 132 are all annular, and have the same shape and size. At the first end of the frame 120, the first inlay 122 of the frame 120 and the second inlay 132 of the top cover 130 are connected by welding to form a sealed connection; at the second end of the frame 120, the first inlay 122 of the frame 120 and the first conductive layer 112 of the bottom plate 110 are connected by welding to form a sealed connection, so that the bottom plate 110, the frame 120 and the top cover 130 enclose a sealed cavity 140. In this embodiment, the first conductive layer 112 and the first inlay 122 and the first inlay 122 and the second inlay 132 are connected by low-temperature reflow soldering using solder paste, and the welding temperature is below 200°C, so as to prevent the first inlay 122 and the frame body 121 and the second inlay 132 and the top cover body 131 from being deformed by delamination. After welding, it can be ensured that there is no gas diffusion path at the connection between the bottom plate 110 and the frame 120 and the connection between the frame 120 and the top cover 130, and the corrosive gas is prevented from diffusing into the cavity 140 from the connection between the separate parts.

[0074] Further, in this embodiment, at the second end of the frame 120, the frame body 121 covers the outer sidewall of the bottom plate 110, facilitating the alignment and installation of the bottom plate 110.

[0075] Further, after the frame 120 and the top cover 130 are connected, an elastic glue 174 (such as glass glue) is used to connect between the frame 120 and the top cover 130, which is used to absorb external tensile stress and relieve stress creep aging of the welding point between the second inlay 132 and the first inlay 122.

[0076] The semiconductor device 150 (or semiconductor chip) is packaged in the cavity 140. Preferably, the semiconductor device 150 (or semiconductor chip) is a power semiconductor device (or power semiconductor chip), and the semiconductor packaging structure 100 is a packaging structure of a power module. Continue to refer to Figure 1 and Figure 2 The bottom plate 110 further includes a second conductive layer 113. The second conductive layer 113 is located at the center region of the first surface of the substrate 111, and the first conductive layer 112 surrounds the second conductive layer 113 on the first surface of the substrate 111. The second conductive layer 113 is used to realize the conductive connection of the semiconductor device 150. In this embodiment, the second conductive layer 113 is, for example, a copper conductive layer covering the first surface of the substrate 111.

[0077] The semiconductor device 150 is located on the first surface of the substrate 111, and is electrically connected with the second conductive layer 113 of the first surface of the substrate 111 via the connecting layer 114 and / or the bonding wire 115. The pin 160 is connected on the second conductive layer 113, and the semiconductor device 150 is electrically connected with the outside world via the second conductive layer 113 and the pin 160. The connecting layer 114 is, for example, soft solder, silver paste, etc., and can also be insulating glue; the bonding wire 115 is, for example, copper wire, silver wire, etc.

[0078] Further, the inner wall of the first conductive layer 112 and the outer wall of the second conductive layer 113 have a gap therebetween, so that the second conductive layer 113 and the first conductive layer 112 are separated from each other. The gap between the inner wall of the first conductive layer 112 and the outer wall of the second conductive layer 113 insulates the first conductive layer 112 and the second conductive layer 113, reducing the risk of affecting the voltage withstand characteristic of the product introduced by the first conductive layer 112. In a specific embodiment, the distance between the inner wall of the first conductive layer 112 and the outer wall of the second conductive layer 113 is greater than 0.1 mm, for example, greater than 0.2 mm, greater than 0.3 mm, greater than 0.4 mm, greater than 0.5 mm, greater than 0.6 mm, greater than 0.7 mm, greater than 0.8 mm, greater than 0.9 mm, greater than 1 mm, greater than 1.1 mm, greater than 1.2 mm, greater than 1.3 mm, greater than 1.4 mm, greater than 1.5 mm, greater than 1.6 mm, greater than 1.7 mm, greater than 1.8 mm, greater than 1.9 mm, greater than 2 mm, greater than 2.1 mm, greater than 2.2 mm, greater than 2.3 mm, greater than 2.4 mm, greater than 2.5 mm, greater than 2.6 mm, greater than 2.7 mm, greater than 2.8 mm, greater than 2.9 mm, greater than 3 mm, greater than 3.1 mm, greater than 3.2 mm, greater than 3.3 mm, greater than 3.4 mm, greater than 3.5 mm, greater than 3.6 mm, greater than 3.7 mm, greater than 3.8 mm, greater than 3.9 mm, greater than 4 mm, greater than 4.1 mm, greater than 4.2 mm, greater than 4.3 mm, greater than 4.4 mm, greater than 4.5 mm, greater than 4.6 mm, greater than 4.7 mm, greater than 4.8 mm, greater than 4.9 mm, greater than 5 mm, greater than 5.1 mm, greater than 5.2 mm, greater than 5.3 mm, greater than 5.4 mm, greater than 5.5 mm, greater than 5.6 mm, greater than 5.7 mm, greater than 5.8 mm, greater than 5.9 mm, greater than 6 mm, greater than 6.1 mm, greater than 6.2 mm, greater than 6.3 mm, greater than 6.4 mm, greater than 6.5 mm, greater than 6.6 mm, greater than 6.7 mm, greater than 6.8 mm, greater than 6.9 mm, greater than 7 mm, greater than 7.1 mm, greater than 7.2 mm, greater than 7.3 mm, greater than 7.4 mm, greater than 7.5 mm, greater than 7.6 mm, greater than 7.7 mm, greater than 7.8 mm, greater than 7.9 mm, greater than 8 mm, greater than 8.1 mm, greater than 8.2 mm, greater than 8.3 mm, greater than 8.4 mm, greater than 8.5 mm, greater than 8.6 mm, greater than 8.7 mm, greater than 8.8 mm, greater than 8.9 mm, greater than 9 mm, greater than 9.1 mm, greater than 9.2 mm, greater than 9.3 mm, greater than 9.4 mm, greater than 9.5 mm, greater than 9.6 mm, greater than 9.7 mm, greater than 9.8 mm, greater than 9.9 mm, greater than 10 mm, etc.

[0079]

[0080] wherein, is the working voltage of the semiconductor device 150, is the minimum value of the breakdown electric field strength in the medium (air or filling layer covering the semiconductor device 150) surrounding the semiconductor device 150. Specifically, is greater than 1 mm, for example.

[0081] Further, the top cover 130 is provided with a first through hole 133, which is used for the pin 160 to pass through, so that one end of the pin 160 extends to the outside of the semiconductor packaging structure 100. Specifically, after the bottom plate 110, the frame 120 and the top cover 130 are combined together, one end of the pin 160 is electrically connected with the second conductive layer 113, and the other end passes through the first through hole 133 and extends to the outside of the semiconductor packaging structure 100 through the first through hole 133. The diameter of the first through hole 133 is greater than or equal to the diameter of the pin 160, so that the pin 160 can pass through the first through hole 133.

[0082] ​The sidewall of the first through hole 133 extends from the second surface of the top cover 130 into the cavity 140. In order to prevent the sidewall of the first through hole 133 from being punctured when it extends into the cavity 140, the thickness of the sidewall of the first through hole 133 that extends into the cavity 140 should be greater than or equal to the thickness of the sidewall of the first through hole 133 that is located on the second surface of the top cover 130. The following conditions should be met:

[0083]

[0084] wherein, is the working voltage of the semiconductor device 150, is the breakdown field strength of the material of the top cover body 131.

[0085] The length of the first through hole 133 that extends into the cavity 140 determines the diffusion speed of the corrosive gas that diffuses into the cavity 140 through the first through hole 133. The length can be designed according to requirements.

[0086] The second surface of the top cover body 131 is covered with a first filling layer 171. The second inlay 132 surrounds the first filling layer 171 on the second surface of the top cover body 131 and does not contact the first filling layer 171. The shape of the first filling layer 171 is not particularly limited. The first filling layer 171 is, for example, a soft filling material that contains metal oxide powder, wherein the metal oxide is, for example, copper oxide, zinc oxide, aluminum oxide, etc., and the soft filling material is, for example, silica gel, etc. The first filling layer 171 is encapsulated in the cavity 140 and absorbs the corrosive gas in the cavity 140, so that the air in the cavity 140 is almost free of corrosive gas, the concentration of corrosive gas on the surface of the semiconductor device 150 in the cavity 140 is reduced, and the sensitive metal (for example, copper, silver) in the semiconductor device 150 is prevented from being corroded.

[0087] The distance between the surface of the first filling layer 171 that is farthest from the top cover 130 and the end surface of the first through hole 133 that extends into the cavity 140 should be greater than or equal to the thickness of the sidewall of the first through hole 133 that extends into the cavity 140. The following conditions should be met:

[0088]

[0089] Further, the center region of the top cover body 131 is provided with a second through hole 134 and a third through hole 135, the second through hole 134 and the third through hole 135 are concentric and communicate with each other, wherein the second through hole 134 is located on the side close to the second surface of the top cover body 131, the third through hole 135 is located on the side close to the first surface of the top cover body 131, the second through hole 134 and the third through hole 135 communicate with each other and penetrate the top cover body 131. On the second surface of the top cover body 131, the side wall of the second through hole 134 extends into the cavity 140. Preferably, the second through hole 134 extends into the cavity 140 by a distance greater than or equal to the thickness of the first filling layer 171 to form a barrier wall.

[0090] In the embodiment, the first through hole 134 is located in the center region of the top cover body 131, and in other embodiments, it can be provided at other positions of the top cover body 131 according to specific needs. And the number of the first through hole 134 can be arbitrarily set, and when the first through hole 134 is multiple, it is usually arranged symmetrically about the center of the top cover body 131.

[0091] The second through hole 134 is used to pour filling material into the cavity 140 after the bottom plate 110, the frame 120 and the top cover 130 are combined together. Specifically, soft material is filled into the cavity 140 through the second through hole 134 to form a second filling layer 172 to protect the semiconductor device 150, wherein the second filling layer 172 covers the semiconductor device 150, the bonding wire 115 and part of the pin 160, and covers the surface of the second conductive layer 113. The height of the second filling layer 172 is greater than the height of the semiconductor device 150, and the second filling layer 172 does not contact the end surface of the first through hole 133 and the second through hole 134 extending into the cavity 140.

[0092] The second filling layer 172 is a soft filling material, such as silicone glue, silicone rubber, etc. The second filling layer 172 is filled with silicon dioxide to reduce the solubility and diffusion coefficient of various impurities in silicone glue, silicone rubber, etc. Further, the first filling layer 171 can also be doped with silicon dioxide, and the doping amount of silicon dioxide in the second filling layer 172 is greater than that in the first filling layer 171.

[0093] Further, the second filling layer 172 has a gap with the first filling layer 171, the gap is a buffer zone, the air in the buffer zone is used to dilute the corrosive gas diffused into the cavity 140 through the first through hole 133, the second through hole 134 and the third through hole 135, and to expand the contact area of the diluted corrosive gas with the first filling layer 171. Since the content of silicon dioxide in the first filling layer 171 is lower than the content of silicon dioxide in the second filling layer 172, the solubility of the corrosive gas in the first filling layer 171 is greater than the solubility in the second filling layer 172 (the concentration of silicon dioxide increases, the solubility of hydrogen sulfide decreases), and the corrosive gas entering the cavity 140 will be more easily absorbed by the first filling layer 171.

[0094] In addition, after filling the second filling layer 172 into the cavity 140, a third filling layer 173 is filled between the inner wall of the first through hole 133 and the outer wall of the pin 160, and the third filling layer 173 is wrapped around the pin 160 to block the corrosive gas from entering the cavity 140. The material of the third filling layer 173 is a soft filling material, such as silicone glue, silicone rubber, etc.

[0095] The third through hole 135 is used to install a sealing plate 180. After the filling material is injected through the second through hole 134, the sealing plate 180 is installed in the third through hole 135 to block the port of the second through hole 134 close to the end of the third through hole 135. Specifically, at the end in communication with the third through hole 135, the outer wall of the second through hole 134 is embedded with a ring-shaped third inlay 136, which surrounds the second through hole 134 and is exposed to the bottom of the third through hole 135. The sealing plate 180 is placed in the third through hole 135 and is sealingly connected with the third inlay 136 exposed to the bottom of the third through hole 135 to achieve the blocking of the second through hole 134. The sealing plate 180 is, for example, a metal plate (e.g., copper, aluminum, iron, etc.), which is sealingly connected with the third inlay 136 by low-temperature reflow soldering.

[0096] Further, the diameter of the third through hole 135 is greater than the diameter of the second through hole 134, and the diameter of the sealing plate 180 is equal to the diameter of the third through hole 135, and further the diameter of the sealing plate 180 is greater than the diameter of the second through hole 134, so that the sealing plate 180 fully blocks the port of the second through hole 134 close to the end of the third through hole 135. Preferably, the depth of the third through hole 135 is equal to the thickness of the sealing plate 180, so that the first surface of the top cover body 131 is flush with the surface of the sealing plate 180.

[0097] In the embodiment, a third through hole 135 is provided, and in other embodiments, the third through hole 135 can also not be provided. The second through hole 134 penetrates the thickness direction of the top cover body 131, the third inlay 136 is exposed to the first surface of the top cover body 131, and the sealing plate 180 is located on the first surface of the top cover body 131 and is sealingly connected with the third inlay 136 exposed to the first surface of the top cover body 131. At this time, the sealing plate 180 protrudes from the first surface of the top cover body 131.

[0098] In the embodiment, the method for forming the semiconductor packaging structure comprises:

[0099] S10: Forming a substrate 111 with a first conductive layer 112 and a second conductive layer 113.

[0100] The first surface of the substrate 111 has the first conductive layer 112 and the second conductive layer 113, the first conductive layer 112 surrounds the second conductive layer 113, and the inner wall of the first conductive layer 112 and the outer wall of the second conductive layer 113 have a gap therebetween, so that the first conductive layer 112 and the second conductive layer 113 are separated from each other.

[0101] Then, a semiconductor device 150 is fixed on the second conductive layer 113. The semiconductor device 150 is electrically connected to the second conductive layer 113 via a connecting layer 114 and a bonding wire 115, respectively. The connecting layer 114 is made of, for example, soft solder, silver paste, or the like, and can also be insulating glue. The bonding wire 115 is, for example, a copper wire or a silver wire. That is, the semiconductor device 150 is connected to the second conductive layer 113 via the connecting layer 114 and the bonding wire 115.

[0102] S20: Forming a frame 120 with a first inlay 122, and at the second end of the frame 120, welding the first inlay 122 and the first conductive layer 112 together.

[0103] In the embodiment, a thermoplastic material is molded around the first inlay 122 to form a frame body 121 wrapping the first inlay 122. Further, the first conductive layer 112 and the first inlay 122 are welded together using solder paste low-temperature reflow, and the welding temperature is below 200°C, so as to prevent delamination and deformation between the first inlay 122 and the frame body 121.

[0104] After the frame is installed, a pin 160 is welded on the second conductive layer 113.

[0105] S30: Forming the top cover 130 with the second inlay 132 and the third inlay 136, and welding the first inlay 122 and the second inlay 132 together at the first end of the frame 120.

[0106] In this embodiment, the top cover body 131 wrapping the second inlay 132 is formed by molding with thermoplastic material around the second inlay 132 and the third inlay 136.

[0107] The first through hole 133 is formed on the top cover 130 for the pin 160 to pass through so that one end of the pin 160 extends outside the semiconductor package structure 100. The outer wall of the first through hole 133 extends away from the second surface of the top cover 130 on the second surface of the top cover 130 (i.e. the surface covering the first filling layer 171). The second through hole 134 and the third through hole 135 are formed in the central region of the top cover body 131, and the second through hole 134 and the third through hole 135 are concentric and communicate with each other, wherein the second through hole 134 is located on the side close to the second surface of the frame body 131, and the third through hole 135 is located on the end close to the first surface of the frame body 131, and the second through hole 134 and the third through hole 135 communicate with each other and pass through the top cover body 131. On the second surface of the top cover 130, the outer wall of the second through hole 134 extends away from the second surface of the top cover 130. On the end communicating with the third through hole 135, the outer wall of the second through hole 134 is embedded with the annular third inlay 136, and the third inlay is exposed to the bottom of the third through hole 135.

[0108] Further, the first filling layer 171 is formed on the second surface of the top cover 130. Wherein on the second surface of the top cover body 131, the second inlay 132 surrounds the first filling layer 171 and does not contact the first filling layer 171. During the formation of the first filling layer 171, the part of the outer wall of the first through hole 133 and the part of the outer wall of the second through hole 134 extending out of the second surface of the top cover 130 block the material forming the first filling layer 171 to prevent the material forming the first filling layer 171 from plugging the first through hole 133 and the second through hole 134.

[0109] Further, at the first end of the frame 120, the frame 120 and the top cover 130 are welded together. Specifically, the second inlay 132 and the first inlay 122 are welded using solder paste low-temperature reflow welding, and the welding temperature is below 200°C to prevent delamination deformation between the second inlay 132 and the top cover body 131.

[0110] Specifically, after the bottom plate 110, the frame 120, and the top cover 130 are combined together, one end of the pin 160 is electrically connected to the second conductive layer 113, and the other end passes through the first through hole 133 and extends to the outside of the semiconductor package structure 100 through the first through hole 133. The diameter of the first through hole 133 is greater than or equal to the diameter of the pin 160, so that the pin 160 can pass through the first through hole 133.

[0111] S40: Fill the cavity 140 with a filling material through the second through hole 134 to form a second filling layer 172. The second filling layer 172 covers the semiconductor device 150, the bonding wire 115, and part of the pin 160. The second filling layer 172 is a soft filling material, such as silicone glue, silicone rubber, etc. The height of the second filling layer 172 is greater than the height of the semiconductor device 150, and the second filling layer 172 does not contact the end surface of the first through hole 133 and the second through hole 134 extending into the cavity 140.

[0112] Further, the second filling layer 172 and the first filling layer 171 have a gap, which is a buffer zone. The air in the buffer zone is used to dilute the corrosive gas diffused into the cavity 140 through the first through hole 133, the second through hole 134, and the third through hole 135, and to increase the contact area of the diluted corrosive gas with the first filling layer 171. Because the solubility of the corrosive gas in the first filling layer 171 is greater than that in the second filling layer 172, the corrosive gas entering the cavity 140 will be more easily absorbed by the first filling layer 171.

[0113] Further, after filling the cavity 140 with a filling material to form a second filling layer 172, a filling material is filled between the inner wall of the first through hole 133 and the outer wall of the pin 160 to form a third filling layer 173, which wraps around the pin 160.

[0114] S50: A sealing plate 180 is installed within the third through hole 135 to seal one end of the second through hole 134 near the third through hole 135. Specifically, the sealing plate 180 is placed within the third through hole 135 and is sealed to a third insert 136 exposed at the bottom of the third through hole 135 to seal the second through hole 134. The sealing plate 180 is, for example, a metal plate, and is sealed to the third insert 136 by welding.

[0115] Furthermore, an elastic adhesive 174 (e.g., glass glue) is used to connect the frame 120 and the top cover 130 to absorb external tensile stress and alleviate stress creep aging at the weld point between the second insert 132 and the first insert 122.

[0116] Figure 5 A cross-sectional view of a semiconductor packaging structure according to a second embodiment of the present invention is shown; as follows: Figure 5 As shown, the semiconductor packaging structure 200 includes a base plate 210, a frame 220, and a top cover 230. When the base plate 210, frame 220, and top cover 230 are combined together, they form a cavity 240 inside the semiconductor packaging structure 200. The semiconductor device 250 (or semiconductor chip) is packaged in the cavity 240 formed by the base plate 210, frame 220, and top cover 230.

[0117] In this embodiment, the base plate 210 includes a substrate 211, a first conductive layer 212 covering the second surface of the substrate 211, and a second conductive layer 213 covering the first surface of the substrate 211. The first conductive layer 212 is plate-shaped. In this embodiment, the first conductive layer 212 serves two purposes: firstly, to achieve a sealed connection with the frame 220; and secondly, to support the substrate 211. Furthermore, the first conductive layer 212 can attenuate electromagnetic waves conducted through it, providing a certain degree of electromagnetic shielding. The second conductive layer 213 is used to fix and conductively connect the semiconductor device 250. The substrate 211 is, for example, a copper-clad ceramic substrate (DBC), the first conductive layer 212 is, for example, a metal conductive layer, and the second conductive layer 213 is a copper conductive layer covering the first surface of the substrate 211.

[0118] The semiconductor device 250 is located on the first surface of the bottom plate 210, and the semiconductor device 250 is electrically connected with the second conductive layer 213 on the first surface of the substrate 211 via the connecting layer 214 and / or the bonding wire 215. The pin 260 is also connected on the second conductive layer 213 via the bonding wire 215, and the semiconductor device 250 realizes electrical connection with the outside via the second conductive layer 213 and the pin 260. The connecting layer 214 is, for example, soft solder, silver paste, etc., and can also be insulating glue; the bonding wire 215 is, for example, copper wire, silver wire, etc.

[0119] Further, the area of the first conductive layer 212 is greater than the area of the substrate 211, so that after the first conductive layer 212 is sealingly connected with the frame 220, the substrate 211 is packaged inside the cavity 240.

[0120] The frame 220 includes a frame body 221 and a first embedded body embedded inside the frame body 221. In the embodiment, the first embedded body includes a first embedded body 2221 and a first embedded body 2222 arranged separately, and the first embedded body 2221 and the first embedded body 2222 are located at two ends of the frame body 221 respectively, wherein the first embedded body 2221 is exposed to the surface of the second end of the frame body 221, the first embedded body 2222 is exposed to the surface of the first end of the frame body 221, and the first embedded body 2221 and the first embedded body 2222 are isolated by the frame body 221. The frame body 221 is molded by a thermoplastic material (such as PBT material, TPU material, etc.), and the first embedded body 222 is stamped by a metal material (such as copper).

[0121] The pin 260 is embedded inside the frame body 221. One end of the pin 260 is exposed inside the cavity 240 and is electrically connected with the second conductive layer 213 on the substrate 211 via the bonding wire 215, and the other end extends to the outside of the frame body 221.

[0122] Specifically, in the embodiment, the pin 260 is in an L shape, one end of the L-shaped pin 260 is exposed inside the cavity 240 at the inner side wall of the frame body 221, and the other end of the L-shaped pin 260 extends to the outside of the frame body 221 at the surface of the first end of the frame body 221. There is a certain gap between the first embedded body 2221 and the pin 260, and the first embedded body 2221 and the pin 260 are insulated and isolated by the frame body 221, and there is a certain gap between the first embedded body 2222 and the pin 260, and the first embedded body 2222 and the pin 260 are insulated and isolated by the frame body 221.

[0123] Further, the distance d4 between the first embedded body 2221 and the pin 260 should satisfy:

[0124]

[0125] The distance d5 between the first inlay 2222 and the pin 260 should satisfy:

[0126]

[0127] Wherein, is the working voltage of the semiconductor device 250, is the breakdown field strength of the frame body 221 material.

[0128] In this embodiment, the first inlay 2221 and the first inlay 2222 are only located at the two end faces of the frame body 221, and the frame body 221 between the first inlay 2221 and the first inlay 2222 is insulating, which on the one hand improves the insulation of the frame 220, and on the other hand provides space for the setting of the pin 260.

[0129] The top cover 230 includes a top cover body 231 and a second inlay 232 embedded in the inside of the top cover body 231. The top cover body 231 is in the form of a plate, and the second inlay 232 is in the form of a ring. The top cover body 231 and the second inlay 232 constitute a plate-shaped top cover 230. The second inlay 232 is exposed to the second surface of the top cover body 231. The top cover body 231 is molded by using a thermoplastic material (such as PBT material, TPU material, etc.), and the second inlay 232 is stamped by using a metal material (such as copper). Wherein, the thickness of the top cover body 231 is greater than the thickness of the second inlay 232, so that the second inlay 232 is only exposed to the second surface of the top cover body 231.

[0130] The distance d6 between the top end of the second inlay 232 and the first surface of the top cover body 231 should satisfy:

[0131]

[0132] Wherein, is the working voltage of the semiconductor device 250, is the breakdown field strength in the air.

[0133] The second surface of the top cover body 231 is covered with a first filling layer 271. The second insert 232 surrounds the first filling layer 271 on the second surface of the top cover body 231 and is not in contact with the first filling layer 271. The first filling layer 271 is, for example, a soft filling material containing metal oxide powder, wherein the metal oxide is, for example, copper oxide, zinc oxide, aluminum oxide, etc., and the soft filling material is, for example, silica gel, etc. The first filling layer 271 absorbs corrosive gas.

[0134] The second filling layer 272 covers the semiconductor device 250, the bonding wire 215, and part of the pin 260, and covers the surface of the second conductive layer 213 to absorb mechanical impact energy and block the diffusion of corrosive gas. The second filling layer 272 is a soft filling material, for example, silicone glue, silicone rubber, etc. The height of the second filling layer 272 is greater than the height of the semiconductor device 250.

[0135] After the bottom plate 210, the frame 220, and the top cover 230 are combined together, the second filling layer 272 and the first filling layer 271 are both located in the cavity 240, and there is a gap between the second filling layer 272 and the first filling layer 271, which is a buffer zone. The air in the buffer zone is used to dilute the corrosive gas that diffuses into the cavity 240, and to increase the contact area of the diluted corrosive gas with the first filling layer 271. Since the solubility of corrosive gas in the first filling layer 271 is greater than that in the second filling layer 272, the corrosive gas entering the cavity 240 will be more easily absorbed by the first filling layer 271.

[0136] In this embodiment, the first conductive layer 212 is plate-shaped, and the first insert 2221, 2222 and the second insert 232 are all ring-shaped. At the second end of the frame body 221, the first insert 2221 is welded and sealed to the first conductive layer 212. At the first end of the frame body 221, the first insert 2222 is welded and sealed to the second insert 232 of the top cover 230, so that the bottom plate 210, the frame 220, and the top cover 230 form a sealed cavity 240. This ensures that there is no gas diffusion path at the connection between the bottom plate 210 and the frame 220, and at the connection between the frame 220 and the top cover 230, thereby preventing corrosive gas from diffusing into the cavity 240 from the connections of the separate components.

[0137] The substrate 211 is encapsulated inside the cavity 240, and there is a gap between the sidewall of the substrate 211 and the sidewall of the first insert 2221. Further, the sidewall of the substrate 211 and the sidewall of the first insert 2221 are insulated and isolated by the insulating second filling layer 272 and / or the frame body 221.

[0138] Further, in the embodiment, the frame body 221 covers the outer sidewall of the substrate 211 at the second end of the frame 220, facilitating alignment installation of the bottom plate 210.

[0139] The first conductive layer 212 and the first embedded body 2221 can be further fixed by screws or glue, and the top cover body 231 can be further fixed by the buckle or screws to increase the connection strength.

[0140] In the embodiment, the method for forming the semiconductor packaging structure comprises:

[0141] S100: providing the substrate 211, wherein the first surface of the substrate 211 has a second conductive layer 213. A semiconductor device 250 is fixed on the second conductive layer 213. The semiconductor device 250 is respectively electrically connected to the second conductive layer 213 via a connecting layer 214 and a bonding wire 215. The material of the connecting layer 214 is, for example, soft solder, silver paste, or the like, and can also be insulating glue. The second conductive layer 213 is a copper conductive layer covering the first surface of the substrate 211. The bonding wire 215 is, for example, a copper wire or a silver wire. That is, the semiconductor device 250 is respectively welded on the second conductive layer 213 via the connecting layer 214 and the bonding wire 215.

[0142] S200: after the bonding is completed, the first conductive layer 212 and the second surface of the substrate 211 are welded together. The area of the first conductive layer 212 is greater than the area of the bottom plate 210, so that after the first conductive layer 212 is sealingly connected with the frame 220, the substrate 211 is packaged inside the cavity 240. The first conductive layer 212 is in the form of a plate, for example, a metal conductive layer.

[0143] S300: forming the frame 220 with a first embedded body and a pin 260, and at the second end of the frame 220, welding the first embedded body 2221 and the first conductive layer 212 together, and in the cavity 240, electrically connecting the pin 260 and the second conductive layer 213.

[0144] In the embodiment, a thermoplastic material is molded around the first embedded body and the pin 260 to form the frame body 221 wrapping the first embedded body and the pin 260.

[0145] In this embodiment, the first inlaid body includes a first inlaid body 2221 and a first inlaid body 2222, which are respectively located at two ends of the frame body 221. The first inlaid body 2221 is exposed to the second end surface of the frame body 221, and the first inlaid body 2222 is exposed to the first end surface of the frame body 221. The first inlaid body 2221 and the first inlaid body 2222 are isolated by the frame body 221. The frame body 221 is molded by a thermoplastic material (such as PBT material, TPU material, etc.), and the first inlaid body 222 is made of a conductive material (such as copper).

[0146] One end of the pin 260 is exposed inside the cavity 240, and the other end extends to the outside of the frame body 221. In this embodiment, the pin 260 is L-shaped. One end of the L-shaped pin 260 is exposed inside the cavity 240 on the inner side wall of the frame body 221, and the other end of the L-shaped pin 260 extends to the outside of the frame body 221 on the first end surface of the frame body 221. There is a gap between the first inlaid body 2221 and the pin 260, and the first inlaid body 2222 and the pin 260 are insulated and isolated by the frame body 221.

[0147] Further, the first conductive layer 212 and the first inlaid body 2221 are connected by low-temperature reflow soldering using solder paste, and the soldering temperature is below 200°C, so as to prevent the first inlaid body 2221 and the frame body 221 from being deformed.

[0148] Further, the end of the pin 260 exposed in the cavity 240 is electrically connected to the second conductive layer 213 on the substrate 211 through the bonding wire 215.

[0149] Further, a filling material is filled to form a second filling layer 272. The second filling layer 272 covers the semiconductor device 250, the bonding wire 215, and part of the pin 260. The second filling layer 272 is a soft filling material, such as silicone glue, silicone rubber, etc. The height of the second filling layer 272 is greater than the height of the semiconductor device 250.

[0150] S400: Form a top cover 230 with a second inlaid body 232, and weld the first inlaid body 2222 and the second inlaid body 232 together at the first end of the frame 220.

[0151] In this embodiment, the second inlay 232 is molded around by a thermoplastic material to form a top cover body 231 wrapping the second inlay 232.

[0152] Further, a first filling layer 271 is formed on the second surface of the top cover 230. Wherein, the second inlay 232 surrounds the first filling layer 271 on the second surface of the top cover body 231, and does not contact the first filling layer 271.

[0153] Further, the frame 220 and the top cover 230 are welded together at the first end of the frame 220. Specifically, the second inlay 232 and the first inlay 2222 are welded together by using solder paste low-temperature reflow welding, and the welding temperature is below 200℃, so as to prevent delamination deformation between the second inlay 232 and the top cover body 231.

[0154] The semiconductor packaging structure provided by the application comprises a bottom plate, a frame and a top cover, and the two ends of the frame are respectively connected to the bottom plate and the top cover through welding sealing, so that there is no gas diffusion channel at the connection of the bottom plate, the frame and the top cover, the sealing property of the semiconductor packaging structure is ensured, the corrosive gas (such as hydrogen sulfide, hydrochloric acid, etc.) is effectively prevented from diffusing into the cavity from the connection of the bottom plate, the frame and the top cover, the semiconductor device inside the semiconductor packaging structure is prevented from being corroded by the corrosive gas, and the normal work of the semiconductor device is ensured.

[0155] Further, the frame and the top cover both adopt the structure of an insulating body wrapping a metal inlay. On the one hand, the metal inlay can realize welding sealing of the semiconductor packaging structure, and the insulating body wrapping the metal inlay can prevent the metal inlay from being corroded in a corrosive environment; on the other hand, the insulating body can improve the insulation between the metal inlay and other conductive structures inside the semiconductor packaging structure, effectively prevent the growth of dendrites in the cavity, and further prevent the generation of conductive channels.

[0156] In the preferred embodiment, the first conductive layer and the second conductive layer are both located on the first surface of the substrate, and there is a gap between the first conductive layer and the second conductive layer, so as to reduce the risk of affecting the voltage resistance property of the product by the introduced first conductive layer.

[0157] In the preferred embodiment, the first conductive layer and the second conductive layer are located on the opposite surfaces of the substrate, the first conductive layer is used to realize sealing connection with the frame and support the substrate, and the first conductive layer can attenuate the electromagnetic wave conducted through the first conductive layer, and has a certain electromagnetic shielding effect.

[0158] In a preferred embodiment, the first inlay is a unitary structure, extending through the height of the frame, facilitating processing.

[0159] In a preferred embodiment, the first inlay comprises two separate parts, with an insulating frame body between the two separate parts, on the one hand improving the insulation of the frame, and on the other hand providing space for the pin.

[0160] In a preferred embodiment, on the second surface of the top cover, the sidewall of the first through hole extends into the cavity, preventing the sidewall of the first through hole extending into the cavity from breakdown, and the first through hole and the pin are filled with a third filling layer to reduce the diffusion speed of corrosive gas molecules.

[0161] In a preferred embodiment, the second surface of the top cover body is covered with a first filling layer, which is a soft filling material containing metal oxide powder, absorbing corrosive gas in the cavity to avoid corrosion of the semiconductor device.

[0162] In a preferred embodiment, the second filling layer has a gap with the first filling layer, which is a buffer zone, the air in the buffer zone is used to dilute corrosive gas diffusing into the cavity through the first through hole, and the contact area of the diluted corrosive gas with the first filling layer is enlarged, since the solubility of corrosive gas in the first filling layer is greater than that in the second filling layer, the corrosive gas entering the cavity will be more easily absorbed by the first filling layer.

[0163] In a preferred embodiment, a second through hole is formed in the top cover, and a sealing plate is added to the second through hole, and the sealing plate and the third inlay in the top cover are connected by welding sealing, blocking the diffusion path of corrosive gas.

[0164] The embodiments of the present application as described above are not exhaustive in describing all details, nor are they limited to the specific embodiments described. It is obvious that many modifications and changes can be made according to the above description. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses based on the present application. The present application is limited only by the claims and their entire scope and equivalents.

Claims

1. A semiconductor packaging structure, characterized in that, include: A base plate, the base plate comprising a substrate and a first conductive layer located on the substrate; A frame, comprising a frame body and a first insert embedded within the frame body, both the frame body and the first insert being annular, the first insert being exposed at two end faces of the frame body; and A top cover, the top cover including a top cover body and a second insert embedded inside the top cover body, the second insert being exposed on a second surface of the top cover body; Wherein, the first insert is sealed to the first conductive layer on the substrate at the second end of the frame, and the first insert is sealed to the second insert of the top cover at the first end of the frame, and the substrate, the frame and the top cover surround to form a cavity.

2. The semiconductor packaging structure according to claim 1, characterized in that, The substrate also includes: A second conductive layer, the second conductive layer being located on a first surface of the substrate; and A semiconductor device is located on the second conductive layer and is electrically connected to the second conductive layer.

3. The semiconductor packaging structure according to claim 2, characterized in that, The first conductive layer is located on the first surface of the substrate. The first conductive layer is annular and surrounds the second conductive layer, and there is a gap between the inner sidewall of the first conductive layer and the outer sidewall of the second conductive layer.

4. The semiconductor packaging structure according to claim 3, characterized in that, The distance d1 between the inner wall of the first conductive layer and the outer wall of the second conductive layer satisfies: in, This refers to the operating voltage of a semiconductor device encapsulated within a semiconductor package structure. This represents the minimum breakdown electric field strength in the dielectric surrounding the semiconductor device.

5. The semiconductor packaging structure according to claim 2, characterized in that, The first conductive layer is located on the second surface of the substrate. The first conductive layer is plate-shaped, wherein the second surface of the substrate is opposite to the first surface of the substrate. The area of ​​the first conductive layer is larger than the area of ​​the substrate. After the first conductive layer is sealed and connected to the first insert, the substrate is located in the cavity.

6. The semiconductor packaging structure according to claim 4, characterized in that, It also includes pins, one end of which is electrically connected to the second conductive layer, and the other end of which extends to the outside of the semiconductor package structure.

7. The semiconductor packaging structure according to claim 6, characterized in that, The top cover also includes a first through hole, and one end of the pin that is not electrically connected to the second conductive layer extends through the first through hole to the outside of the semiconductor package structure.

8. The semiconductor packaging structure according to claim 7, characterized in that, On the second surface of the top cover, the sidewall of the first through hole extends into the cavity.

9. The semiconductor packaging structure according to claim 8, characterized in that, The thickness of the first through hole extending to the sidewall inside the cavity satisfy: in, This refers to the operating voltage of a semiconductor device encapsulated within a semiconductor package structure. The breakdown electric field strength of the main material of the top cover is given.

10. The semiconductor packaging structure according to claim 7, characterized in that, A third filler layer is filled between the pin and the sidewall of the first through hole.

11. The semiconductor packaging structure according to claim 7, characterized in that, The first inlay is an integral structure that extends through the height of the main frame body.

12. The semiconductor packaging structure according to claim 6, characterized in that, Some of the pins are embedded within the frame body.

13. The semiconductor packaging structure according to claim 12, characterized in that, The first inlay comprises two separate parts, one part of which is exposed on the surface of the second end of the frame body, and the other part of which is exposed on the surface of the first end of the frame body.

14. The semiconductor packaging structure according to claim 13, characterized in that, The distance d4 between the first inlay and the pin in one of the portions satisfies: The distance d5 between the first inlay and the pin in another part satisfies: in, This refers to the operating voltage of a semiconductor device encapsulated within a semiconductor package structure. The breakdown electric field strength is the value of the main material of the frame.

15. The semiconductor packaging structure according to claim 1, characterized in that, The top cover also includes: The second through hole is located on one side of the second surface near the main body of the top cover; The third through hole is located on one side near the first surface of the top cover body; The diameter of the third through hole is larger than the diameter of the second through hole, and the second through hole and the third through hole are interconnected and penetrate the top cover body; At one end communicating with the third through hole, an annular third insert is embedded on the outer side of the outer wall of the second through hole, the third insert being exposed at the bottom of the third through hole and surrounding the second through hole; The top cover also includes a sealing plate located within the third through hole and sealed to a third insert exposed at the bottom of the third through hole.

16. The semiconductor packaging structure according to claim 1, characterized in that, The top cover also includes: The second through hole penetrates the main body of the top cover; An annular third insert is embedded on the outer side of the outer wall of the second through hole, the third insert being exposed on the first surface of the top cover body, and the third insert surrounding the second through hole; The top cover further includes a sealing plate located on a first surface of the top cover body and sealed to the third insert exposed on the first surface of the top cover body.

17. The semiconductor packaging structure according to claim 15 or 16, characterized in that, On the second surface of the top cover body, the sidewall of the second through hole extends into the cavity.

18. The semiconductor packaging structure according to claim 9, characterized in that, A second filling layer is applied to the semiconductor device and the second conductive layer.

19. The semiconductor packaging structure according to claim 18, characterized in that, The second surface of the top cover body is covered with a first filling layer; on the second surface of the top cover, the second insert surrounds the first filling layer and is separate from the first filling layer.

20. The semiconductor packaging structure according to claim 19, characterized in that, There is a gap between the first filler layer and the second filler layer.

21. The semiconductor packaging structure according to claim 19, characterized in that, The first filler layer is a soft material layer, wherein the soft material layer contains metal oxide.

22. The semiconductor packaging structure according to claim 19, characterized in that, The distance between the surface of the first filling layer away from the top cover and the end face of the first through hole extending into the cavity. satisfy: in, This is the distance between the inner wall of the first conductive layer and the outer wall of the second conductive layer. The thickness of the sidewall extending from the first through hole into the cavity.

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