A DBC structure for hybrid package PIM module and PIM module
By employing an upper copper layer design of varying thicknesses in the Si IGBT/SiC MOSFET hybrid packaged PIM module, the issues of high junction temperature of Si IGBT and short short-circuit time of SiC MOSFET were resolved, thereby improving the reliability of the module.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIYI SEMICON TECH (GUANGDONG) CO LTD
- Filing Date
- 2022-07-27
- Publication Date
- 2026-05-22
AI Technical Summary
The existing DBC structure of Si IGBT/SiC MOSFET hybrid packaged PIM modules suffers from high junction temperature of Si IGBT and short short-circuit time of SiC MOSFET, resulting in low module reliability.
By employing copper layer designs of varying thicknesses, a thin copper layer is used at the Si IGBT chip location to reduce thermal resistance, while a thick copper layer is used at the SiC MOSFET chip location to increase thermal capacity. This reduces the junction temperature of the Si IGBT chip and increases the short-circuit time of the SiC MOSFET chip, respectively.
By optimizing the copper layer thickness, the thermal resistance of the Si IGBT chip is reduced and the short-circuit time of the SiC MOSFET chip is increased, thereby improving the reliability of the hybrid package module.
Smart Images
Figure CN115295503B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic device technology, and in particular to a DBC structure and a PIM module suitable for Si IGBT / SiC MOSFET hybrid packaged PIM module. Background Technology
[0002] A PIM (Power Integrated Module) integrates power chips such as IGBTs, MOSFETs, and diodes into a module with a specific topology. This reduces distributed inductance from wiring, increases circuit power density, simplifies installation, and facilitates maintenance. Common PIM module topologies include half-bridge, H-bridge, three-phase bridge, and seven-unit modules.
[0003] Photovoltaic inverters are a typical application scenario for PIM modules, and single-phase photovoltaic inverters typically employ a full-bridge circuit structure. To minimize the losses of switching devices, PWM (Pulse Width Modulation) control strategies sometimes set the switching frequency of the upper bridge arm IGBT1 / IGBT3 to the grid frequency (e.g., 50Hz), while the lower bridge arm IGBT2 / IGBT4 operates at a higher switching frequency to achieve a sine wave output. This operating mode places different performance requirements on the four IGBT units in the full-bridge inverter. Since the upper bridge arm operates at the grid frequency, IGBT1 / IGBT3 requires a low saturation voltage drop V0. ce(sat) To reduce system conduction losses and minimize diode reverse recovery losses, the diodes must have fast recovery times or be implemented using SiC Schottky barrier diodes (SBDs). Since the IGBT units in the lower bridge arm operate at high frequencies, IGBT2 / IGBT4 require low switching losses and high-speed switching capability.
[0004] Si-based IGBT chips, as bipolar devices, have a saturation voltage drop V. ce(sat) While SiC-based MOSFETs offer low switching losses, they are unsuitable for high-frequency applications. As single-stage devices, SiC-based MOSFETs, with their low switching losses, are well-suited for high-frequency applications. Based on these characteristics, Vincotech's newly launched Flowsol-Bi (P896-E01) photovoltaic inverter module utilizes a hybrid Si IGBT + SiC MOSFET package. The boost circuit within the module consists of SiC MOSFETs and SiC Schottky barrier diodes. The upper half of the H-bridge circuit comprises Si IGBTs and SiC Schottky barrier diodes, while the lower half consists of SiC MOSFETs. Experimental results show that photovoltaic inverters using this hybrid Si IGBT + SiC MOSFET + SiC SBD module achieve a 2% speedup compared to inverters using pure Si IGBT modules.
[0005] In a hybrid Si IGBT / SiC MOSFET PIM module, the two types of chips have different characteristics, thus exhibiting two different typical failure modes. Si IGBT chips are bipolar devices with higher inherent losses and lower current density than SiC MOSFETs, with a typical short-circuit time of 10μs. In contrast, SiC MOSFET chips are unipolar devices with lower inherent losses and higher current density, with a typical short-circuit time of 2-3μs. Short-circuit failure is a type of overheating failure. During a short circuit, the chip absorbs the power dissipation generated by the bus voltage multiplied by the short-circuit current, ultimately leading to chip failure due to overheating.
[0006] Double-sided copper-clad laminate (DBC) is a commonly used insulating material in PIM modules. It possesses excellent thermal conductivity, high insulation, high current carrying capacity, excellent solderability, and high adhesion strength. Like PBC, it can be etched with various circuit patterns. In applications, one copper side of the DBC is etched to form the designed circuit pattern, while the other copper side connects to the heatsink. Currently, in existing PIM modules and IGBT modules, the top and bottom copper layers of the DBC structure are implemented using copper layers of the same thickness. Figure 1 As shown. However, existing PIM modules mainly have the following drawbacks: 1. When a thin copper layer is used for the chip bonding layer, the SiCMOSFET chip has insufficient heat capacity and low short-circuit withstand capability. The drive protection circuit cannot effectively detect and operate on short circuits, resulting in a high short-circuit failure rate for the SiCMOSFET chip; 2. When a thick copper layer is used for the chip bonding layer, the Si IGBT chip has high thermal resistance. The heat generated by the chip cannot be dissipated in time, resulting in a high chip junction temperature and a high overheat failure rate for the Si IGBT chip. Summary of the Invention
[0007] The purpose of this invention is to provide a DBC structure suitable for Si IGBT / SiC MOSFET hybrid packaged PIM modules, thereby solving the technical problem of high failure rate in existing hybrid packaged PIM module DBC structure products. The various technical effects of the preferred solutions among the many technical solutions provided by this invention are detailed below.
[0008] To achieve the above objectives, the present invention provides the following technical solution:
[0009] The present invention provides a DBC structure suitable for Si IGBT / SiC MOSFET hybrid packaged PIM module, including a ceramic layer, a lower copper layer located below the ceramic layer, and an upper copper layer located above the ceramic layer. The upper copper layer includes a first upper copper layer disposed at the location where the Si IGBT chip is soldered and a second upper copper layer disposed at the location where the SiC MOSFET chip is soldered, and the thickness of the first upper copper layer is less than the thickness of the second upper copper layer.
[0010] According to a preferred embodiment, the thickness of the first upper copper layer is 0.25 to 0.4 mm, and the thickness of the second upper copper layer is 0.4 to 1 mm.
[0011] According to a preferred embodiment, the thickness of the first upper copper layer is 0.3 mm, and the thickness of the second upper copper layer is 1 mm.
[0012] According to a preferred embodiment, the upper copper layer further includes a module current output terminal, and the thickness of the copper layer of the module current output terminal is consistent with the thickness of the second upper copper layer.
[0013] According to a preferred embodiment, the first upper copper layer is disposed on the upper surface of the ceramic layer corresponding to the bottom of the Si IGBT chip, and the second upper copper layer is disposed on the upper surface of the ceramic layer corresponding to the bottom of the SiC MOSFET chip.
[0014] According to a preferred embodiment, the first upper copper layer is disposed on the upper surface of the ceramic layer corresponding to the bottom of the Si IGBT chip, the second upper copper layer is disposed on the upper surface of the ceramic layer corresponding to the periphery of the SiC MOSFET chip, and a cavity for accommodating the SiC MOSFET chip is formed in the center of the second upper copper layer.
[0015] According to a preferred embodiment, the first upper copper layer is disposed on the upper surface of the ceramic layer corresponding to the bottom of the Si IGBT chip, the second upper copper layer is disposed on the upper surface of the ceramic layer corresponding to the bottom of the SiC MOSFET chip, and a third upper copper layer is also disposed at the top position corresponding to the SiC MOSFET chip, the thickness of the third upper copper layer being the same as the thickness of the second upper copper layer.
[0016] According to a preferred embodiment, the thickness of the third upper copper layer is 0.4 to 1 mm.
[0017] The present invention also provides a PIM module suitable for Si IGBT / SiC MOSFET hybrid packaging, characterized in that it includes a Si IGBT chip, a SiC MOSFET chip and a DBC structure, wherein the Si IGBT chip is soldered to the upper surface of the first upper copper layer of the DBC structure, the SiC MOSFET chip is soldered to the upper surface of the second upper copper layer of the DBC structure, or the SiC MOSFET chip is soldered within a cavity formed in the center of the second upper copper layer for accommodating the SiC MOSFET chip, or the SiC MOSFET chip is soldered between the upper surface of the second upper copper layer and the lower surface of the third upper copper layer of the DBC structure.
[0018] According to a preferred embodiment, the Si IGBT chip and the SiC MOSFET chip are respectively connected to the module current output terminal.
[0019] Based on the above technical solution, the DBC structure and PIM module of the present invention, applicable to Si IGBT / SiC MOSFET hybrid packaged PIM modules, have at least the following technical effects:
[0020] The present invention discloses a DBC structure for a Si IGBT / SiC MOSFET hybrid packaged PIM module, comprising a ceramic layer, a lower copper layer below the ceramic layer, and an upper copper layer above the ceramic layer. The upper copper layer includes a first upper copper layer corresponding to the Si IGBT chip bonding location and a second upper copper layer corresponding to the SiC MOSFET chip bonding location, with the thickness of the first upper copper layer being less than the thickness of the second upper copper layer. By using a relatively thin copper layer at the Si IGBT chip location, the thermal resistance of the Si IGBT chip is reduced, the chip's operating junction temperature is lowered, and the reliability of the Si IGBT chip is improved. Conversely, by using a relatively thick copper layer at the SiC MOSFET chip location, the heat capacity is increased, allowing the heat generated by the SiC MOSFET chip during short-circuit operation to be rapidly absorbed by the thick copper layer, reducing the chip junction temperature, increasing the short-circuit time of the SiC MOSFET chip, and improving the reliability of the SiC MOSFET chip. This solves the problems of high Si IGBT junction temperature and short SiC MOSFET chip short-circuit time in hybrid packaged PIM modules, thus improving the reliability of the hybrid packaged module. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 This is a schematic diagram of the DBC structure of an existing hybrid packaged PIM module;
[0023] Figure 2 This is a schematic diagram of the DBC structure of the hybrid packaged PIM module of the present invention;
[0024] Figure 3 This is a schematic diagram of the DBC structure of a hybrid packaged PIM module according to another preferred embodiment of the present invention;
[0025] Figure 4 This is a schematic diagram of the DBC structure of a hybrid packaged PIM module according to another preferred embodiment of the present invention.
[0026] In the diagram: 101 - First upper copper layer; 102 - Second upper copper layer; 103 - Module current output terminal; 104 - Ceramic layer; 105 - Lower copper layer; 106 - Third upper copper layer. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be described in detail below. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other implementation methods obtained by those skilled in the art without creative effort are within the scope of protection of this invention.
[0028] Example 1
[0029] This invention provides a DBC structure suitable for a Si IGBT / SiC MOSFET hybrid packaged PIM module, including a ceramic layer 104, a lower copper layer 105 below the ceramic layer 104, and an upper copper layer above the ceramic layer 104. The upper copper layer includes a first upper copper layer 101 corresponding to the Si IGBT chip bonding location and a second upper copper layer 102 corresponding to the SiC MOSFET chip bonding location, with the thickness of the first upper copper layer 101 being less than the thickness of the second upper copper layer 102. Preferably, the first upper copper layer 101 and the second upper copper layer 102 are spaced apart on the upper surface of the ceramic layer 104. By using a relatively thin copper layer at the Si IGBT chip location, the thermal resistance of the Si IGBT chip is reduced, lowering the chip's junction temperature; while using a relatively thick copper layer at the SiC MOSFET chip location increases the heat capacity, allowing the heat generated by the SiC MOSFET chip during short circuits to be rapidly absorbed by the thick copper layer, reducing the chip junction temperature and increasing the short circuit time of the SiC MOSFET chip. This solves the problems of high junction temperature of SiIGBT and short short-circuit time of SiC MOSFET chip in hybrid packaged PIM modules, thus improving the reliability of hybrid packaged modules.
[0030] More preferably, the thickness of the first upper copper layer 101 is 0.25–0.4 mm. The thickness of the second upper copper layer 102 is 0.4–1 mm. Preferably, the thickness of the first upper copper layer 101 is 0.3 mm, and the thickness of the second upper copper layer 102 is 1 mm. Therefore, in the DBC structure of the SiIGBT / SiC MOSFET hybrid packaged PIM module, by using copper layers of different thicknesses, the Si IGBT chip uses a thin copper sheet to reduce the chip's thermal resistance, lower the chip's operating junction temperature, and improve the reliability of the Si IGBT chip. For the SiC MOSFET chip, a thick copper layer is used to increase the heat capacity, reduce the chip temperature when the SiC MOSFET chip is short-circuited, increase the short-circuit time of the SiC MOSFET chip, and thus improve the reliability of the SiC MOSFET chip.
[0031] More preferably, the upper copper layer further includes a module current output terminal 103, the thickness of which is the same as the thickness of the second upper copper layer 102. The module current output terminal 103 is used for chip current output.
[0032] More preferably, such as Figure 1 As shown, the first upper copper layer 101, corresponding to the bottom of the Si IGBT chip, is disposed on the upper surface of the ceramic layer 104, and the second upper copper layer 102, corresponding to the bottom of the SiC MOSFET chip, is disposed on the upper surface of the ceramic layer 104. That is, in this embodiment, the Si IGBT chip is disposed on the upper surface of the first upper copper layer 101, and the SiC MOSFET chip is disposed on the upper surface of the second upper copper layer 102. This DBC structure can be achieved through two etching processes, and the fabrication process is not particularly difficult.
[0033] This invention addresses the issue of hybrid packaging of Si IGBT and SiC MOSFET chips by employing copper layers of varying thicknesses. It solves the problems of high Si IGBT junction temperature and short short-circuit time of SiC MOSFETs in Si IGBT / SiC MOSFET hybrid packaged PIM modules, achieving low thermal resistance of Si IGBT chips and high short-circuit withstand capability of SiC MOSFET chips, thereby improving the reliability of SiIGBT / SiC MOSFET hybrid packaged PIM modules.
[0034] Example 2
[0035] like Figure 3 As shown, the difference between this embodiment and Embodiment 1 is that:
[0036] The first upper copper layer 101 is disposed on the upper surface of the ceramic layer 104, corresponding to the bottom of the Si IGBT chip. The second upper copper layer 102 is disposed on the upper surface of the ceramic layer 104, corresponding to the periphery of the SiC MOSFET chip, and a cavity for accommodating the SiC MOSFET chip is formed in the center of the second upper copper layer 102. That is, in this embodiment, the second upper copper layer 102 is disposed around the periphery of the SiC MOSFET chip, so that the SiC MOSFET chip is soldered in the central cavity of the second upper copper layer. Preferably, in this embodiment, the thickness of the first upper copper layer 101 is 0.25-0.4 mm, and the thickness of the second upper copper layer 102 is 0.4-1 mm. Preferably, the thickness of the first upper copper layer 101 is 0.3 mm, and the thickness of the second upper copper layer 102 is 1 mm.
[0037] In this embodiment, the heat generated by the SiC MOSFET chip can be rapidly absorbed by the relatively thick second upper copper layer, reducing the junction temperature of the SiC MOSFET chip, increasing the short-circuit time of the SiC MOSFET chip, and thus improving the reliability of the SiC MOSFET chip.
[0038] Example 3
[0039] like Figure 4 As shown, the difference between this embodiment and Embodiment 1 is that:
[0040] The first upper copper layer 101, corresponding to the bottom of the Si IGBT chip, is disposed on the upper surface of the ceramic layer 104. The second upper copper layer 102, corresponding to the bottom of the SiC MOSFET chip, is disposed on the upper surface of the ceramic layer 104. A third upper copper layer 106 is also disposed at the top position corresponding to the SiC MOSFET chip, and the thickness of the third upper copper layer 106 is the same as the thickness of the second upper copper layer 102. In this embodiment, the thickness of the first upper copper layer 101 is 0.25–0.4 mm, and the thickness of the second upper copper layer 102 is 0.4–1 mm. Preferably, the thickness of the third upper copper layer 106 is 0.4–1 mm. Preferably, the thickness of the first upper copper layer 101 is 0.3 mm, the thickness of the second upper copper layer 102 is 1 mm, and the thickness of the third upper copper layer 106 is 1 mm.
[0041] In this embodiment, the fabrication process of the third upper copper layer requires depositing solderable metal on the surface of the SiC MOSFET chip. By providing thick copper layers on both the top and bottom surfaces of the SiC MOSFET chip, the heat generated by the SiC MOSFET chip can be rapidly absorbed, thereby reducing the junction temperature of the SiC MOSFET chip, increasing the short-circuit time of the SiC MOSFET chip, and improving the reliability of the SiC MOSFET chip.
[0042] This invention can be packaged based on different DBC structures. The process of implementing different DBC structures is simple, and it will not change the original packaging process and technology of the packaging plant's PIM module.
[0043] Example 4
[0044] This embodiment provides a PIM module suitable for a Si IGBT / SiC MOSFET hybrid package, including a SiIGBT chip, a SiC MOSFET chip, and a DBC structure as described in any of embodiments 1 to 3. The Si IGBT chip is soldered to the upper surface of the first upper copper layer 101 of the DBC structure, and the SiC MOSFET chip is soldered to the upper surface of the second upper copper layer 102 of the DBC structure to form the hybrid packaged PIM module. Alternatively, preferably, a third upper copper layer 104 can be soldered to the upper surface of the SiMOSFET chip located on the upper surface of the second upper copper layer 102 to form another preferred hybrid packaged PIM module, thereby increasing the heat capacity around the SiC MOSFET chip and improving the short-circuit time of the SiC MOSFET chip.
[0045] Alternatively, preferably, when the second upper copper layer is disposed around the periphery of the SiC MOSFET chip, the SiC MOSFET chip is soldered into the cavity formed at the center of the second upper copper layer 102 for accommodating the SiC MOSFET chip, thereby forming another preferred hybrid packaged PIM module.
[0046] Preferably, such as Figures 2 to 4 As shown, the Si IGBT chip and the SiC MOSFET chip are connected to the module current output terminal 103, respectively, to realize the current output.
[0047] The PIM module uses a double-sided copper-clad laminate (DBC) for chip connection and insulation. This invention improves the DBC structure of the Si IGBT / SiC MOSFET hybrid packaged PIM module to enhance module reliability. Si IGBT chips are bipolar devices with higher inherent losses and lower current density than SiC MOSFETs, typically with a short-circuit time of 10μs. Therefore, applications require reducing the chip's thermal resistance to lower the junction temperature and improve Si IGBT chip reliability. SiC MOSFET chips are unipolar devices with lower inherent losses and higher current density, typically with a short-circuit time of 2-3μs. Therefore, applications require increasing the short-circuit time to improve SiC MOSFET chip reliability. This invention addresses the differences between Si IGBT and SiC MOSFET chips by using a thin copper layer to reduce the thermal resistance and junction temperature of Si IGBT chips, and a thick copper layer to increase the heat capacity of SiC MOSFET chips, reducing the chip temperature during short circuits and increasing the short-circuit time, thus solving the problems existing in the aforementioned chip applications.
[0048] In the description of this invention, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," "front end," "rear end," "head," "tail," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0049] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0050] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A DBC structure suitable for hybrid packaged PIM modules, characterized in that, The system includes a ceramic layer (104), a lower copper layer (105) below the ceramic layer (104), and an upper copper layer above the ceramic layer (104). The upper copper layer includes a first upper copper layer (101) corresponding to the location of the Si IGBT chip and a second upper copper layer (102) corresponding to the location of the SiC MOSFET chip. The thickness of the first upper copper layer (101) is less than the thickness of the second upper copper layer (102). The thickness of the first upper copper layer (101) is 0.25~0.4mm, and the thickness of the second upper copper layer (102) is 0.4~1mm.
2. The DBC structure for hybrid packaged PIM modules according to claim 1, characterized in that, The thickness of the first upper copper layer (101) is 0.3 mm, and the thickness of the second upper copper layer (102) is 1 mm.
3. The DBC structure for hybrid packaged PIM modules according to claim 2, characterized in that, The upper copper layer also includes a module current output terminal (103), and the thickness of the copper layer of the module current output terminal (103) is consistent with the thickness of the second upper copper layer (102).
4. The DBC structure for hybrid packaged PIM modules according to claim 1, characterized in that, The first upper copper layer (101) is disposed on the upper surface of the ceramic layer (104) corresponding to the bottom of the Si IGBT chip, and the second upper copper layer (102) is disposed on the upper surface of the ceramic layer (104) corresponding to the bottom of the SiC MOSFET chip.
5. The DBC structure for hybrid packaged PIM modules according to claim 1, characterized in that, The first upper copper layer (101) is disposed on the upper surface of the ceramic layer (104) corresponding to the bottom of the Si IGBT chip, and the second upper copper layer (102) is disposed on the upper surface of the ceramic layer (104) corresponding to the periphery of the SiC MOSFET chip, and a cavity for accommodating the SiC MOSFET chip is formed in the center of the second upper copper layer (102).
6. The DBC structure for hybrid packaged PIM modules according to claim 1, characterized in that, The first upper copper layer (101) is disposed on the upper surface of the ceramic layer (104) corresponding to the bottom of the Si IGBT chip, the second upper copper layer (102) is disposed on the upper surface of the ceramic layer (104) corresponding to the bottom of the SiC MOSFET chip, and a third upper copper layer (106) is also disposed at the top position corresponding to the SiC MOSFET chip. The thickness of the third upper copper layer (106) is the same as the thickness of the second upper copper layer (102).
7. The DBC structure for hybrid packaged PIM modules according to claim 6, characterized in that, The thickness of the third upper copper layer (106) is 0.4~1mm.
8. A PIM module suitable for Si IGBT / SiC MOSFET hybrid packaging, characterized in that, The invention includes a Si IGBT chip, a SiC MOSFET chip, and a DBC structure according to any one of claims 1 to 7, wherein the Si IGBT chip is soldered to the upper surface of the first upper copper layer (101) of the DBC structure, the SiC MOSFET chip is soldered to the upper surface of the second upper copper layer (102) of the DBC structure, or the SiC MOSFET chip is soldered into a cavity formed in the center of the second upper copper layer (102) for accommodating the SiC MOSFET chip; or the SiC MOSFET chip is soldered between the upper surface of the second upper copper layer (102) and the lower surface of the third upper copper layer (106) of the DBC structure.
9. The PIM module suitable for Si IGBT / SiC MOSFET hybrid packaging according to claim 8, characterized in that, The Si IGBT chip and the SiC MOSFET chip are respectively connected to the module current output terminal (103).