Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel comprises a display area and a non-display area, the display area and the non-display area are covered by an encapsulation layer of the display panel, the non-display area comprises a driving circuit arrangement area and an organic film clearance area, the driving circuit arrangement area is provided with a scan driving circuit, the scan driving circuit comprises a transistor, and the organic film clearance area is free of other organic film layers except an organic film layer in the encapsulation layer; wherein the organic film clearance area at least partially overlaps with the driving circuit arrangement area, and the driving circuit arrangement area comprises a first region overlapping with the organic film clearance area and a second region not overlapping with the organic film clearance area. Embodiments of the present application can reduce the occupation of the organic film clearance area to the non-display area space and reduce the frame size.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display, and particularly relates to a display panel and a display device. BACKGROUND

[0002] Organic light-emitting diode (OLED) display panels and display panels using light emitting diode (LED) devices are widely used in mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, desktop computers and other consumer electronic products due to their high image quality, power saving, thin body and wide application range, and have become the mainstream of display panels. Currently, the frame of the display panel is required to be higher and higher, and the display panel is required to be ultra-narrow frame or even frameless. However, the current design of the display panel still occupies a large space of the non-display area, which is not conducive to the design of the narrow frame. SUMMARY

[0003] The display panel and the display device provided by the embodiments of the present application can reduce the occupation of the non-display area space and reduce the frame size.

[0004] In a first aspect, the embodiments of the present application provide a display panel, the display panel comprising a display area and a non-display area, the display area and the non-display area being covered by an encapsulation layer of the display panel, the non-display area comprising a driving circuit arrangement area and an organic film clearance area, the driving circuit arrangement area being provided with a scan driving circuit, the scan driving circuit comprising a transistor, and the organic film clearance area being free of other organic film layers except an organic film layer in the encapsulation layer; wherein the organic film clearance area at least partially overlaps the driving circuit arrangement area, and the driving circuit arrangement area comprises a first region overlapping the organic film clearance area and a second region not overlapping the organic film clearance area.

[0005] In a second aspect, the embodiments of the present application provide a display device, the display device comprising the display panel provided in the first aspect.

[0006] The display panel and the display device provided by the embodiments of the present application make the organic film clearance area at least partially overlap the driving circuit arrangement area, that is, the organic film clearance area reuses at least part of the driving circuit arrangement area, thereby reducing the occupation of the non-display area space by the organic film clearance area, reducing the frame size, and being conducive to the design of the narrow frame. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced. For those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0008] Figure 1 A structural schematic diagram of a display panel;

[0009] Figure 2 A structural schematic diagram of a display panel provided by an embodiment of the present application;

[0010] Figure 3 Another structural schematic diagram of a display panel provided by an embodiment of the present application;

[0011] Figure 4 Still another structural schematic diagram of a display panel provided by an embodiment of the present application;

[0012] Figure 5 Still another structural schematic diagram of a display panel provided by an embodiment of the present application;

[0013] Figure 6 Still another structural schematic diagram of a display panel provided by an embodiment of the present application;

[0014] Figure 7 A circuit schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0015] Figure 8 Still another structural schematic diagram of a display panel provided by an embodiment of the present application;

[0016] Figure 9 Still another structural schematic diagram of a display panel provided by an embodiment of the present application;

[0017] Figure 10 Still another structural schematic diagram of a display panel provided by an embodiment of the present application;

[0018] Figure 11 A sectional schematic diagram of a display panel provided by an embodiment of the present application;

[0019] Figure 12 A structural schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0020] The features and exemplary embodiments of various aspects of the present application will be described below in detail, in order to make the purposes, technical solutions and advantages of the present application more clear and apparent, the present application will be further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, but not to limit the present application. The present application can be implemented without some of these specific details by those skilled in the art. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0021] It should be noted that the relational terms herein such as first and second and the like are used solely to distinguish one from another entity or action, without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0022] It should be understood that the term "and / or" used herein only describes an association relationship of associated objects, which means that there can be three relationships, for example, A and / or B can represent three cases of A existing alone, A and B existing together, and B existing alone. In addition, the character " / " herein generally represents an "or" relationship between the front and rear associated objects.

[0023] It should be noted that the transistors in the embodiments of the present application are taken as P-type transistors for illustration, but are not limited to P-type transistors, and can be replaced by N-type transistors. For N-type transistors, the on level is high level and the off level is low level. That is, when the gate of the N-type transistor is high level, the first pole and the second pole are turned on, and when the gate of the N-type transistor is low level, the first pole and the second pole are turned off. For P-type transistors, the on level is low level and the off level is high level. That is, when the control pole of the P-type transistor is low level, the first pole and the second pole are turned on, and when the control end of the P-type transistor is high level, the first pole and the second pole are turned off. In specific implementation, the gate of each transistor is taken as the control pole thereof, and according to the signal of the gate of each transistor and the type thereof, the first pole can be taken as the source pole and the second pole as the drain pole, or the first pole can be taken as the drain pole and the second pole as the source pole, which is not distinguished herein. In addition, the on level and the off level in the embodiments of the present application are generic, the on level refers to any level capable of turning on the transistor, and the off level refers to any level capable of turning off / turning off the transistor.

[0024] In the embodiments of the present application, the term "electrically connected" can refer to direct electrical connection between two components, or can refer to electrical connection between two components via one or more other components.

[0025] In the embodiments of the present application, the first node and the second node are only defined for the convenience of describing the circuit structure, and the first node and the second node are not an actual circuit unit.

[0026] Various modifications and changes can be made to the present application in matters of form and detail without departing from the spirit and scope of the application. It is intended that the application cover all such modifications and changes as fall within the scope of the corresponding claims (technical solutions claimed to be protected) and their equivalents. It should be noted that the embodiments provided by the present application can be combined with each other as long as they do not contradict each other.

[0027] Before describing the technical solutions provided by the embodiments of the present application, the problems existing in the related art will be specifically described in order to facilitate the understanding of the embodiments of the present application:

[0028] Figure 1 A structural schematic diagram of a display panel. As shown in Figure 1 , the display panel can include a display area AA and a non-display area NA. The display area AA can be provided with pixel units (not shown in the figure) arranged in an array, for displaying a picture. The non-display area NA can include a driving circuit arrangement area NA1, which can be provided with a scan driving circuit (not shown in the figure), which can be used to provide a scan signal to the pixel circuit in the display area AA to control the conduction / cutoff of the transistor in the pixel circuit. In order to ensure that the display panel has a good packaging effect, such as preventing water and oxygen from entering the display area AA through the organic film layer in the non-display area NA, the non-display area NA can also include an organic film clearance area NA2, that is, the organic film clearance area NA2 is removed from the other organic film layers in the packaging layer except the organic film layer in the packaging layer, thereby blocking the path of water and oxygen spreading from the non-display area NA to the display area AA.

[0029] However, the inventors of the present application have found that in the related art, the organic film clearance area NA2 is usually located on the side of the driving circuit arrangement area NA1 away from the display area AA, that is, along the first direction X (the width direction of the non-display area NA), the organic film clearance area NA2 and the driving circuit arrangement area NA1 are arranged in sequence without overlapping. In this way, a certain width (such as 100 μm) of the area of the frame (i.e. the non-display area NA) of the display panel needs to be reserved for the organic film clearance area NA2, which will occupy a large space of the non-display area NA, which is not conducive to the design of narrow frame. Figure 1

[0030] In view of the above research findings of the inventors, the embodiments of the present application provide a display panel and a display device, which can solve the technical problem that the organic film clearance area occupies a large space of the non-display area in the related art, which is not conducive to the design of narrow frame.

[0031] ​The technical concept of the embodiments of the present application is to make the organic film clearance area and the driving circuit arrangement area at least partially overlap, that is, the organic film clearance area reuses at least part of the driving circuit arrangement area, thereby reducing the occupation of the organic film clearance area for the non-display area space, reducing the frame size, and facilitating the design of a narrow frame.

[0032] The following first introduces the display panel provided in the embodiment of the present application.

[0033] Figure 2 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 2 As shown, the display panel 20 provided in the embodiment of the present application may include a display area AA and a non-display area NA. The display area AA and the non-display area NA are covered by the encapsulation layer 210 of the display panel 20. The display area AA may be provided with pixel units arranged in an array (not shown in the figure) for displaying pictures. The non-display area NA may include a drive circuit arrangement area NA1 and an organic film clearance area NA2. The drive circuit arrangement area NA1 may be provided with a scan drive circuit (not shown in the figure). The scan drive circuit may be used to provide a scan signal to the pixel circuit in the display area AA to control the on / off of the transistor in the pixel circuit. The scan drive circuit may include transistors, such as a plurality of transistors electrically connected to each other. The encapsulation layer 210 may include an inorganic film layer and an organic film layer stacked together. The specific structure will be described below. The embodiment of the present application does not limit the specific film layer structure of the encapsulation layer 210. There is no organic film layer other than the organic film layer in the encapsulation layer 210 in the organic film clearance area NA2, that is, the organic film layers other than the organic film layer in the encapsulation layer 210 in the organic film clearance area NA2 are removed, thereby blocking the path for water and oxygen to spread from the non-display area NA to the display area AA.

[0034] Continue to see Figure 2 In this embodiment of the present application, the organic film clearance area NA2 at least partially overlaps with the drive circuit arrangement area NA1. That is, the organic film clearance area NA2 reuses at least a portion of the drive circuit arrangement area NA1. The drive circuit arrangement area NA1 may include a first region a1 that overlaps with the organic film clearance area NA2 and a second region a2 that does not overlap with the organic film clearance area NA2.

[0035] In the display panel of the embodiment of the present application, since the organic film clearance area NA2 at least partially overlaps with the driving circuit arrangement area NA1, that is, the organic film clearance area NA2 reuses at least part of the driving circuit arrangement area NA1, the space occupied by the organic film clearance area NA2 in the non-display area NA can be reduced, thereby reducing the frame size, which is conducive to the design of a narrow frame.

[0036] Figure 3 This is another structural diagram of the display panel provided in the embodiment of the present application. Figure 3As shown, according to some embodiments of the present application, optionally, the encapsulation layer 210 is a thin-film encapsulation layer formed by a thin-film encapsulation (TFE) process. The encapsulation layer 210 at least includes a first inorganic layer 31, an organic film layer 32, and a second inorganic layer 33, which are arranged in a stacked manner to provide protection for the display panel. The inorganic layer generally has good compactness and can isolate water vapor and oxygen, and the organic film layer has a flexible feature. Application of the organic film layer as one layer of the encapsulation layer 210 can buffer stress from the outside, avoid the display panel from being affected by the external stress to affect the display effect, and also reduce the risk of encapsulation failure caused by the fracture of the inorganic layer.

[0037] Continuing to refer to Figure 2 , according to some embodiments of the present application, optionally, along the first direction X, the second area a2 can be located between the first area a1 and the display area AA. Wherein the first direction X is a direction parallel to the plane on which the display panel is located, and specifically can be the width direction of the non-display area NA. That is, the second area a2 in the drive circuit arrangement area NA1 which does not overlap with the organic film clearance area NA2 can be adjacent to the display area AA, and the first area a1 in the drive circuit arrangement area NA1 which overlaps with the organic film clearance area NA2 can be away from the display area AA.

[0038] In this way, since the second area a2 is also provided with other organic film layers in addition to the organic film layer in the encapsulation layer 210, when the other organic film layers are provided, the other organic film layers can extend from the display area AA to the second area a2, and no other organic film layer is laid in the first area a1, avoiding laying other organic film layers in the first area a1 and then removing the other organic film layers, that is, saving the process of removing the other organic film layers in the first area a1, which is conducive to the simplification of the preparation process of the organic film clearance area, thereby improving the production efficiency of the display panel and reducing the production cost.

[0039] It should be noted that in other embodiments, along the first direction X, the first area a1 can also be located between the second area a2 and the display area AA, which is not limited in the embodiments of the present application.

[0040] Figure 4 Another structural schematic diagram of a display panel provided by the embodiments of the present application is shown in FIG. 4. As shown in Figure 4 , according to some embodiments of the present application, optionally, the display panel 20 can include a drive device layer 40, a first conductive layer 41, and a second conductive layer 42 arranged in a stacked manner. The scan drive circuit in the drive circuit arrangement area NA1 can be located in the drive device layer 40.

[0041] The display panel 20 may further include a first power signal line L. For example, the first power signal line L may be a negative voltage power signal line PVEE for providing a negative voltage signal. The first power signal line L may include a first sub-power signal line L1 and a second sub-power signal line L2. The first sub-power signal line L1 may be located on the first conductive layer 41 of the display panel, and the second sub-power signal line L2 may be located on the second conductive layer 42 of the display panel.

[0042] In the second region a2, along a direction Z perpendicular to the plane of the display panel, a first insulating layer 43 may be provided between the driver device layer 40 and the first conductive layer 41, and a second insulating layer 44 may be provided between the first conductive layer 41 and the second conductive layer 42. A first via h1 is provided in the second insulating layer 44, and the first sub-power signal line L1 and the second sub-power signal line L2 can be electrically connected via the first via h1. It should be noted that the number of first vias h1 can be one or more, and this is not limited in this embodiment of the present application.

[0043] In this way, by setting the second insulating layer 44 between the first conductive layer 41 and the second conductive layer 42, and connecting the first sub-power signal line L1 and the second sub-power signal line L2 through the first via h1, the first sub-power signal line L1 and the second sub-power signal line L2 can be connected in parallel, thereby reducing the impedance of the first power signal line L.

[0044] According to some embodiments of the present application, optionally, the materials of the first insulating layer 43 and the second insulating layer 44 may both be organic materials. That is, the first insulating layer 43 and the second insulating layer 44 may both be organic insulating layers.

[0045] Continue to see Figure 4 According to some embodiments of the present application, optionally, in the first area a1, along the direction Z perpendicular to the plane of the display panel, the first insulating layer 43 is not provided between the driving device layer 40 and the first conductive layer 41, and the second insulating layer 44 is not provided between the first conductive layer 41 and the second conductive layer 42, and the first sub-power signal line L1 and the second sub-power signal line L2 can be in contact and connected.

[0046] In this way, by not setting the first insulating layer 43 and the second insulating layer 44 in the first area a1, an organic film clearance area can be formed in the first area a1, thereby reducing the occupation of the organic film clearance area in the non-display area space, reducing the frame size, and facilitating the design of a narrow frame.

[0047] like Figure 4As shown, since the first insulating layer 43 is no longer provided in the first area a1, the distance between the first power signal line L and the driver device layer 40 is shortened along the direction Z perpendicular to the plane of the display panel. Since the first power signal line L is a constant voltage signal line, even if the distance between the first power signal line L and the driver device layer 40 is shortened, there will be no problem of coupling interference between the first power signal line L and the electronic devices or traces in the driver device layer 40.

[0048] However, in order to avoid the possible coupling interference problem, the embodiment of the present application further proposes the following solution.

[0049] Figure 5 This is another structural diagram of a display panel provided in an embodiment of the present application. Figure 5 As shown, according to some embodiments of the present application, the display panel 20 may optionally further include a third insulating layer 50. The material of the third insulating layer 50 may be an inorganic material, that is, the third insulating layer 50 may be an inorganic insulating layer. Along a direction Z perpendicular to the plane of the display panel, the third insulating layer 50 may be located between the driving device layer 40 and the first conductive layer 41. Exemplarily, the third insulating layer 50 may cover the entire non-display area. At least in the first region a1, the thickness of the third insulating layer 50 is greater than 2000 angstroms, with the thickness being the minimum distance along a direction perpendicular to the plane of the display panel.

[0050] In the related art, inorganic insulating layers are generally around 2000 angstroms thick. However, in the present embodiment, the thickness of the third insulating layer 50, at least in the first region a1, is increased to above 2000 angstroms, for example, to between 2000 and 5000 angstroms. In other words, by increasing the thickness of the third insulating layer 50, the distance between the first power signal line L and the driver device layer 40 is increased, further reducing or even eliminating potential coupling interference between the first power signal line L and the electronic devices or traces in the driver device layer 40.

[0051] It should be noted that in some examples, the thickness of the third insulating layer 50 in the first region a1 may be increased to more than 2000 angstroms. In other examples, the thickness of the third insulating layer 50 in the entire non-display area may be increased to more than 2000 angstroms, which is not limited in the present embodiment.

[0052] Figure 6 This is another structural diagram of a display panel provided in an embodiment of the present application. Figure 6As shown, according to some embodiments of the present application, the drive circuit arrangement area NA1 may optionally include a first drive circuit arrangement area 60 and a second drive circuit arrangement area 61. The first drive circuit arrangement area 60 is provided with a light emission control scan drive circuit, which is used to provide a light emission control signal to the pixel circuit in the display area. The second drive circuit arrangement area 61 is provided with a gate scan drive circuit, which is used to provide a gate scan signal to the pixel circuit in the display area.

[0053] To better illustrate the present application with reference to the accompanying drawings, the following explanation is given using a pixel circuit including seven transistors and one storage capacitor (i.e., a 7T1C pixel circuit). It should be understood that this is not intended to limit the present application, and the pixel circuit may also adopt other circuit structures, such as a 7T2C pixel circuit, a 9T1C pixel circuit, or a 9T2C pixel circuit. A 7T2C pixel circuit is a pixel circuit including seven transistors and two storage capacitors, and the same applies to other types of pixel circuits.

[0054] Figure 7 A circuit diagram of a pixel circuit in a display panel provided in an embodiment of the present application. Figure 7 As shown, the pixel circuit may include a driving transistor M1, a threshold compensation transistor M2, a data write transistor M3, a first reset transistor M4, a second reset transistor M5, a first emission control transistor M6, a second emission control transistor M7, and a storage capacitor Cst. The gate of the driving transistor M1 is electrically connected to the first node N1, the first electrode of the driving transistor M1 is electrically connected to the second node N2, and the second electrode of the driving transistor M1 is electrically connected to the light-emitting element D via the second emission control transistor M7, for providing a driving current to the light-emitting element D. The gate of the threshold compensation transistor M2 is electrically connected to the second scan signal line S2, the first electrode of the threshold compensation transistor M2 is electrically connected to the first node N1, and the second electrode of the threshold compensation transistor M2 is electrically connected to the second electrode of the driving transistor M1, for compensating the threshold voltage of the driving transistor M1. The gate of the data write transistor M3 is electrically connected to the second scan signal line S2, the first electrode of the data write transistor M3 is electrically connected to the data signal line data, and the second electrode of the data write transistor M3 is electrically connected to the second node N2 for data writing.

[0055] The first reset transistor M4 has a gate electrically connected to the first scan signal line S1, a first electrode electrically connected to the reference voltage signal line Vref, and a second electrode electrically connected to the first node N1 for resetting the first node N1. The second reset transistor M5 has a gate electrically connected to the first scan signal line S1, a first electrode electrically connected to the reference voltage signal line Vref, and a second electrode electrically connected to the anode of the light-emitting element D for resetting the anode of the light-emitting element D.

[0056] The gate of the first emission control transistor M6 is electrically connected to the emission control signal line Emit, the first electrode of the first emission control transistor M6 is electrically connected to the second power supply signal line PVDD, and the second electrode of the first emission control transistor M6 is electrically connected to the second node N2. The gate of the second emission control transistor M7 is electrically connected to the emission control signal line Emit, the first electrode of the second emission control transistor M7 is electrically connected to the second electrode of the drive transistor M1, and the second electrode of the second emission control transistor M7 is electrically connected to the anode of the light-emitting element D. The first emission control transistor M6 and the second emission control transistor M7 are used to control the emission of the light-emitting element D.

[0057] The first plate of the storage capacitor Cst is electrically connected to the second power signal line PVDD, and the second plate of the storage capacitor Cst is electrically connected to the first node N1 for storing the potential of the first node N1. The cathode of the light emitting element D is electrically connected to the negative voltage power signal line PVEE.

[0058] Combine Figure 6 and Figure 7 As shown, the light emission control scan driving circuit can be electrically connected to the light emission control signal line Emit, thereby providing the light emission control signal to the pixel circuit. The gate scan driving circuit can be electrically connected to the first scan signal line S1 and / or the second scan signal line S2, thereby providing the first scan signal and / or the second scan signal to the pixel circuit.

[0059] Continue to see Figure 6 In some examples, the organic film clearance area NA2 may be a portion of the drive circuit arrangement area NA1. Specifically, the organic film clearance area NA2 (i.e., the first area a1) may be at least a portion of the first drive circuit arrangement area 60. That is, in some examples, the range of the organic film clearance area NA2 may be less than or equal to the range of the first drive circuit arrangement area 60, and the organic film clearance area NA2 may be a portion of the first drive circuit arrangement area 60.

[0060] Figure 8 This is another structural diagram of a display panel provided in an embodiment of the present application. Figure 8 As shown, Figure 6Different from the embodiments shown in FIG. 1A and FIG. 1B, according to some embodiments of the present application, optionally, the first region a1 can include part of the first driving circuit arrangement region 60 and the second driving circuit arrangement region 61. That is, the organic film clearance region NA2 can reuse part of the entire first driving circuit arrangement region 60 and the second driving circuit arrangement region 61. Of course, in other embodiments, the organic film clearance region NA2 can also reuse part of the first driving circuit arrangement region 60 and part of the second driving circuit arrangement region 61, which is not limited in the embodiments of the present application.

[0061] Figure 9 Another structural schematic diagram of a display panel provided by the embodiments of the present application is shown in FIG. 1C. As shown in FIG. 1C, according to some embodiments of the present application, optionally, the non-display region NA can further include a barrier wall region NA3, which can be located on the side of the driving circuit arrangement region NA1 away from the display region AA. The barrier wall region NA3 can be provided with a barrier wall structure 101, and the organic film layer 32 in the encapsulation layer 210 extends to the barrier wall structure NA3 in the direction X1 of the center of the display panel pointing to the edge of the display panel. Since the organic film layer 32 usually exhibits a fluid or colloidal form in the process, by setting the barrier wall structure 101 in the barrier wall region NA3, the overflow of the organic film layer 32 in the direction X1 of the center of the display panel pointing to the edge of the display panel can be effectively avoided, thereby preventing encapsulation failure. Figure 9 Figure 6 Different from the embodiments shown in FIG. 1A and FIG. 1B, according to some embodiments of the present application, optionally, the first region a1 can include part of the first driving circuit arrangement region 60 and the second driving circuit arrangement region 61. That is, the organic film clearance region NA2 can reuse part of the entire first driving circuit arrangement region 60 and the second driving circuit arrangement region 61. Of course, in other embodiments, the organic film clearance region NA2 can also reuse part of the first driving circuit arrangement region 60 and part of the second driving circuit arrangement region 61, which is not limited in the embodiments of the present application. Figure 8

[0062] In this way, no other organic film layer except the organic film layer in the encapsulation layer 210 is arranged in the entire first driving circuit arrangement region 60 where the light-emitting control scanning driving circuit is located, the entire first driving circuit arrangement region 60 is reused to form the organic film clearance region NA2, which can greatly reduce the occupation of the non-display region space by the organic film clearance region, reduce the frame size, and is conducive to the design of narrow frame.

[0063] Figure 10 Another structural schematic diagram of a display panel provided by the embodiments of the present application is shown in FIG. 1C. As shown in FIG. 1C, according to some embodiments of the present application, optionally, the non-display region NA can further include a barrier wall region NA3, which can be located on the side of the driving circuit arrangement region NA1 away from the display region AA. The barrier wall region NA3 can be provided with a barrier wall structure 101, and the organic film layer 32 in the encapsulation layer 210 extends to the barrier wall structure NA3 in the direction X1 of the center of the display panel pointing to the edge of the display panel. Since the organic film layer 32 usually exhibits a fluid or colloidal form in the process, by setting the barrier wall structure 101 in the barrier wall region NA3, the overflow of the organic film layer 32 in the direction X1 of the center of the display panel pointing to the edge of the display panel can be effectively avoided, thereby preventing encapsulation failure. Figure 10 In some examples, the barrier wall structure 101 can include a first barrier wall 101a and a second barrier wall 101b, the first barrier wall 101a is used to define the boundary of the organic film layer 32 in the encapsulation layer 210, and the first inorganic layer 31 and the second inorganic layer 33 can extend to the second barrier wall 101b, further improving the effect of the encapsulation layer 210 in blocking water and oxygen.

[0064] Continuing to refer to

[0065] Figure 10 ​​​According to some embodiments of the present application, the non-display area NA may optionally further include an edge encapsulation area NA4. The edge encapsulation area NA4 may be located on a side of the retaining wall area NA3 away from the display area AA. The width of the edge encapsulation area NA4 may be greater than the width of the retaining wall area NA3, and the width is the minimum distance along the direction X1 from the center of the display panel to the edge of the display panel. For example, in some examples, the width of the edge encapsulation area NA4 may be 270 μm, and the width of the retaining wall area NA3 may be 120 μm.

[0066] In this way, by setting a wider edge packaging area NA4 on the side of the retaining wall area NA3 away from the display area AA, on the one hand, when the display panel is cut from the motherboard of the display panel, the edge packaging area NA4 can fully cool the heat generated by the cutting, thereby preventing the heat generated by the cutting from being transferred to the driving circuit arrangement area and the display area to damage the electronic devices; on the other hand, it can effectively extend the path for water vapor and oxygen to invade the display area from the side of the display panel.

[0067] For ease of understanding, the film layer structure of the display panel provided in the embodiments of the present application is illustrated below with reference to some specific application examples.

[0068] Figure 11 A cross-sectional schematic diagram of a display panel provided in an embodiment of the present application. Figure 11 As shown, according to some embodiments of the present application, optionally, in the first region a1, the display panel 20 may include a stacked substrate 01, a driver device layer 40, a third insulating layer 50, a first conductive layer 41, a second conductive layer 42, and an encapsulation layer 210. The substrate 01 may be flexible, and thus stretchable, foldable, bendable, or rollable, so that the display panel can be stretchable, foldable, bendable, or rollable. The substrate 01 may also be rigid, such as a glass substrate, thereby forming a rigid touch display panel. In some examples, the display panel 20 may further include a buffer layer 02 located between the substrate 01 and the driver device layer 40. The driver device layer 40 may include multiple metal layers for providing electronic devices such as transistors. The third insulating layer 50 may be an inorganic insulating layer, for example, the material of the third insulating layer 50 may be at least one selected from inorganic materials such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. The first conductive layer 41 can be used to set the first sub-power signal line L1, and the second conductive layer 42 can be used to set the second sub-power signal line L2. The encapsulation layer 210 includes at least a first inorganic layer 31, an organic layer 32, and a second inorganic layer 33. The inorganic and organic layers are stacked to provide protection for the display panel.

[0069] In the display area AA and the second area a2, the display panel 20 can include the substrate 01, the driver device layer 40, the third insulating layer 50, the first insulating layer 43, the first conductive layer 41, the second insulating layer 44, the second conductive layer 42, the fourth insulating layer 45 and the encapsulation layer 210 which are arranged in a stack. Among them, the materials of the first insulating layer 43, the second insulating layer 44 and the fourth insulating layer 45 are all organic materials. That is, in some examples, the organic film net space area NA2 (i.e. the first area a1) lacks three layers of organic film layers, i.e. the first insulating layer 43, the second insulating layer 44 and the fourth insulating layer 45, compared with the display area AA and the second area a2. The material of the first insulating layer 43, the second insulating layer 44 and the fourth insulating layer 45 can include at least one selected from acrylic resin, methacrylic resin, polyisoprene, vinyl-based resin, epoxy-based resin, urethane-based resin, cellulose-based resin and perylene-based resin, which is not limited in the embodiments of the present application.

[0070] Continuing to refer to Figure 11 , according to some embodiments of the present application, optionally, the display panel 20 can further include a second power signal line PVDD and a light emitting element (not shown in the figure), the second power signal line PVDD can be located in the display area AA and disposed on the first conductive layer 41, and the anode RE of the light emitting element can be located in the display area AA and disposed on the second conductive layer 42. That is, in some examples, the first conductive layer 41 can be arranged in the same layer as the film layer of the second power signal line PVDD arranged in the display area AA, that is, prepared in the same process as the film layer of the second power signal line PVDD arranged in the display area AA. The second conductive layer 42 can be arranged in the same layer as the anode layer in the display area AA, that is, prepared in the same process as the anode layer in the display area AA.

[0071] Continuing to refer to Figure 11 , according to some embodiments of the present application, optionally, the driver device layer 40 can include the first metal layer M1, the second metal layer MC and the third metal layer M2 which are arranged in a stack, the gate g of the transistor can be located in the first metal layer M1, and the source s and the drain d of the transistor can be located in the third metal layer M2. The display panel 20 can further include a capacitor, the first plate of the capacitor can be located in the first metal layer M1, and the second plate of the capacitor can be located in the second metal layer MC. In the display area AA, the third insulating layer 50 can cover the third metal layer M2, that is, the third insulating layer 50 is located between the third metal layer M2 and the first conductive layer 41. The fourth insulating layer 45 is provided with a pixel opening for arranging the light emitting element. That is, the fourth insulating layer 45 can be a pixel definition layer PDL.

[0072] Based on the display panel 20 provided in the above embodiments, accordingly, the present application further provides a display device including the display panel provided by the present application. Please refer to Figure 12 , Figure 12is a structural schematic diagram of a display device provided in an embodiment of the present application. Figure 12 The display device 1000 provided in the present application includes the display panel 20 provided in any of the above embodiments of the present application. Figure 12 The display device 1000 is described by taking a mobile phone as an example in the embodiment. It can be understood that the display device provided in the embodiments of the present application can be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices having a display function, and the present application does not make a specific limitation thereon. The display device provided in the embodiments of the present application has the beneficial effects of the display panel 20 provided in the embodiments of the present application, and specific descriptions can be made with reference to the specific descriptions of the display panel 20 in the above embodiments, which will not be described herein again.

[0073] It should be understood that the specific structures of the pixel circuits and the cross-sectional structures of the display panels provided in the drawings of the embodiments of the present application are only some examples, and are not used to limit the present application. In addition, the above embodiments provided in the present application can be combined with each other without contradiction.

[0074] According to the above embodiments of the present application, the embodiments do not describe all the details, and the present application is not limited to the specific embodiments described. Obviously, many modifications and changes can be made according to the above description. The embodiments are selected and specifically described in the present specification in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The present application is limited by the claims and the entire scope and equivalents thereof.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area, the display area and the non-display area are covered by the encapsulation layer of the display panel, the non-display area includes a drive circuit arrangement area and an organic film clearance area, the drive circuit arrangement area is provided with a scan drive circuit, the scan drive circuit includes a transistor, and the organic film clearance area does not contain any other organic film layer except the organic film layer in the encapsulation layer; The organic film clearance area at least partially overlaps with the drive circuit arrangement area, and the drive circuit arrangement area includes a first area overlapping with the organic film clearance area and a second area not overlapping with the organic film clearance area; The scan driving circuit is located in the driving device layer of the display panel; The display panel further includes a first power signal line, the first power signal line including a first sub-power signal line and a second sub-power signal line, the first sub-power signal line is located on the first conductive layer of the display panel, and the second sub-power signal line is located on the second conductive layer of the display panel, and the driving device layer, the first conductive layer, and the second conductive layer are stacked; In the first region, along a direction perpendicular to the plane where the display panel is located, the first sub-power signal line is in contact with the second sub-power signal line.

2. The display panel according to claim 1, wherein: Along a first direction, the second area is located between the first area and the display area, and the first direction is a direction parallel to the plane where the display panel is located.

3. The display panel according to claim 1, wherein: In the second region, a first insulating layer is further provided between the driving device layer and the first conductive layer, and a second insulating layer is further provided between the first conductive layer and the second conductive layer, along a direction perpendicular to the plane where the display panel is located. A first via hole is provided on the second insulating layer, and the first sub-power signal line and the second sub-power signal line are electrically connected through the first via hole.

4. The display panel according to claim 3, wherein: In the first region, along a direction perpendicular to the plane of the display panel, the first insulating layer is not disposed between the driving device layer and the first conductive layer, and the second insulating layer is not disposed between the first conductive layer and the second conductive layer.

5. The display panel according to claim 3, wherein: The first insulating layer and the second insulating layer are both made of organic materials.

6. The display panel according to claim 3, wherein: The display panel further includes a third insulating layer, and the material of the third insulating layer is an inorganic material; Along a direction perpendicular to the plane where the display panel is located, the third insulating layer is located between the driving device layer and the first conductive layer; At least in the first region, the thickness of the third insulating layer is greater than 2000 angstroms, and the thickness is a minimum distance along a direction perpendicular to the plane where the display panel is located.

7. The display panel according to claim 1, wherein: The driving circuit arrangement area includes a first driving circuit arrangement area and a second driving circuit arrangement area, the first driving circuit arrangement area is provided with a light emitting control scanning driving circuit, and the second driving circuit arrangement area is provided with a gate scanning driving circuit; The organic film clearance area is a portion of the driving circuit arrangement area; The first area includes at least a portion of the first driving circuit arrangement area, or the first area includes a portion of the first driving circuit arrangement area and the second driving circuit arrangement area.

8. The display panel according to claim 7, wherein: The organic film clearance area completely overlaps with the first driving circuit arrangement area.

9. The display panel according to claim 1, wherein: The non-display area further includes a retaining wall area, and the retaining wall area is located on a side of the drive circuit arrangement area away from the display area; The retaining wall area is provided with a retaining wall structure, which extends from the center of the display panel to the edge of the display panel, and the organic film layer in the encapsulation layer extends to the retaining wall structure and is terminated.

10. The display panel according to claim 9, wherein: The non-display area also includes an edge packaging area, which is located on the side of the retaining wall area away from the display area. The width of the edge packaging area is greater than the width of the retaining wall area, and the width is the minimum distance along the direction from the center of the display panel to the edge of the display panel.

11. The display panel according to claim 1, wherein In the first area, the display panel includes a substrate, a driving device layer, a third insulating layer, a first conductive layer, a second conductive layer and an encapsulation layer that are stacked; In the display area and the second area, the display panel includes the substrate, the driving device layer, the third insulating layer, the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, the fourth insulating layer and the encapsulation layer, which are stacked; The materials of the first insulating layer, the second insulating layer and the fourth insulating layer are all organic materials.

12. The display panel according to claim 11, wherein: The display panel further includes a second power signal line and a light emitting element. The second power signal line is located in the display area and is disposed on the first conductive layer. The anode of the light emitting element is located in the display area and is disposed on the second conductive layer.

13. The display panel according to claim 11, wherein: The driving device layer includes a first metal layer, a second metal layer, and a third metal layer stacked together, the gate of the transistor is located in the first metal layer, and the source and drain of the transistor are located in the third metal layer; In the display area, the third insulating layer covers the third metal layer, and the fourth insulating layer is provided with a pixel opening, and the pixel opening is used to arrange a light-emitting element.

14. A display device, characterized in that: The display device includes the display panel according to any one of claims 1 to 13.

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