A high-reliability GaN-based HEMT device and a preparation method thereof

Abstract

The application discloses a kind of high reliability GaN base HEMT device and preparation method thereof, the device includes sequentially stacked from bottom to top substrate, AlN nucleation layer, GaN transition layer and barrier layer, wherein, source electrode and drain electrode are respectively arranged on the upper surface of barrier layer, gate electrode is arranged between source electrode and drain electrode, and mesa is formed on the outside of source electrode and drain electrode;Passivation layer is covered on the upper surface of gate electrode, source electrode, drain electrode and the upper surface of barrier layer;Bent-shaped gate field plate is arranged on the upper surface of passivation layer near drain electrode side, one end of gate field plate is located above gate electrode, and the other end extends to above drain electrode;Protective layer is covered on the upper surface of gate field plate and the upper surface of passivation layer.The application utilizes the gate field plate connected with gate electrode and drain electrode to relieve the electric field gathering effect of gate edge, reduces the original electric field peak near gate electrode, avoids the phenomenon that HEMT appears failure degradation under high electric field stress, and improves the breakdown efficiency of device.

Description

Technical Field

[0001] This invention belongs to the field of third-generation semiconductor power device technology, specifically relating to a high-reliability GaN-based HEMT device and its fabrication method. Background Technology

[0002] In recent years, research on traditional Si-based devices has gradually approached physical limits. To further reduce chip area, increase breakdown voltage, and lower on-resistance, GaN materials have attracted much attention due to their advantages such as large bandgap, high breakdown electric field, radiation resistance, and high temperature resistance. However, the breakdown voltage and reliability of GaN-based HEMT devices are often constrained by a variety of factors. One reason is the electric field accumulation effect near the gate, which forms an electric field peak at the gate edge. This can lead to device degradation or even direct breakdown under long-term high field stress.

[0003] To address this issue, many researchers have employed various field plate structures to homogenize the gate-drain electric field, reduce peak electric field, and thus improve the device's breakdown voltage. Existing field plate structures include T-shaped gate field plates, stepped field plates, and inclined field plate structures, among others. These structures each have their limitations, particularly for GaN, a material with high breakdown field strength, where their effect on surface electric field homogenization is relatively limited. Therefore, the long-term reliability of GaN-based HEMT devices remains a pressing issue. Summary of the Invention

[0004] To address the aforementioned problems in existing technologies, this invention provides a high-reliability GaN-based HEMT device and its fabrication method. A bent-shape resistive field plate structure is used to connect the gate and drain electrodes of the GaN-based HEMT device, optimizing the electric field distribution with a very short gate-drain spacing. This results in a more uniform electric field distribution between the gate and drain, thereby significantly improving the long-term reliability and breakdown efficiency of the device. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] One aspect of the present invention provides a high-reliability GaN-based HEMT device, comprising a substrate, an AlN nucleation layer, a GaN transition layer, and a barrier layer stacked sequentially from bottom to top, wherein...

[0006] A source and a drain are respectively disposed on the upper surfaces of the two ends of the barrier layer, and a gate is disposed on the barrier layer between the source and the drain. Mesa extending downward to the upper surface or interior of the AlN nucleation layer is formed on the outer side of the source and the drain, respectively.

[0007] A passivation layer is applied to the upper surfaces of the gate, the source, the drain, and the remaining area of ​​the barrier layer.

[0008] A bent gate field plate is provided on the upper surface of the passivation layer near the drain. The lower surface of the gate field plate extends into the interior of the passivation layer, and the upper surface is flush with the upper surface of the passivation layer. One end of the gate field plate is located above the gate, and the other end extends above the drain.

[0009] A protective layer covers the upper surface of the gate field plate and the remaining upper surface of the passivation layer.

[0010] In one embodiment of the present invention, the gate field plate is formed by a plurality of cuboid structures connected vertically in sequence to form an arc-shaped structure, wherein the cuboid structure at one end of the gate field plate is located vertically above the gate and is separated from the gate by the passivation layer; the cuboid structure at the other end of the gate field plate extends from the upper surface of the passivation layer to vertically above the drain and is separated from the drain by the passivation layer.

[0011] In one embodiment of the present invention, the gate field plate is formed of oxygen-doped semi-insulating polycrystalline silicon material, with an oxygen content between 0.3% and 20%.

[0012] In one embodiment of the present invention, both the source and the drain are made of Ti / Al / Ni / Au metal stack, and the gate is made of Ni / Au metal stack.

[0013] In one embodiment of the present invention, one end of the gate field plate is electrically connected to the gate, and the other end is electrically connected to the drain.

[0014] In one embodiment of the present invention, the depth of the gate field plate is 0.14 μm, the total length is 4.52 μm, and the width of the cuboid structure is 0.47 μm.

[0015] In one embodiment of the present invention, the material of the barrier layer is Al. 0.2 Ga 0.8 N.

[0016] Another aspect of the present invention provides a method for fabricating a high-reliability GaN-based HEMT device, used to fabricate the high-reliability GaN-based HEMT device described in any of the above embodiments, the fabrication method comprising:

[0017] An AlN nucleation layer, a transition layer, and an Al layer are sequentially grown on the substrate. 0.2 Ga 0.8 N-barrier layer;

[0018] In the Al 0.2 Ga 0.8 Metals are deposited at both ends of the N-barrier layer to form the source and drain, respectively;

[0019] In the Al0.2 Ga 0.8 The left and right sides of the N barrier layer are etched to form mesas that extend downward to the upper surface or interior of the AlN nucleation layer;

[0020] In the Al 0.2 Ga 0.8 Metal is deposited at the middle position of the upper surface of the N-barrier layer to form a gate;

[0021] On the upper surfaces of the gate, the source, the drain, and the Al 0.2 Ga 0.8 A passivation layer is formed on the upper surface of the remaining region of the N-barrier layer;

[0022] A bent gate field plate is provided on the upper surface of the passivation layer near the drain.

[0023] A protective layer is deposited on the upper surface of the gate field plate and on the remaining areas of the passivation layer.

[0024] In one embodiment of the present invention, an AlN nucleation layer, a transition layer, and an Al layer are sequentially grown on a substrate. 0.2 Ga 0.8 The N-barrier layer includes:

[0025] A silicon or sapphire substrate is selected and cleaned. A low-temperature AlN nucleation layer is formed on the surface of the substrate. The growth temperature of the low-temperature AlN nucleation layer is about 700℃~800℃, the pressure is 45 Torr, and the aluminum source flow rate is 5 μmol / min. Then, a high-temperature AlN nucleation layer is epitaxially grown on the low-temperature AlN nucleation layer. The growth temperature of the high-temperature AlN nucleation layer is 900℃~1100℃, the pressure is 45 Torr, and the aluminum source flow rate is 5 μmol / min.

[0026] A GaN transition layer with a thickness of 1 μm is formed by epitaxially growing GaN material on the AlN nucleation layer 2;

[0027] Undoped Al with a thickness of 10 nm is deposited on the GaN transition layer 3. 0.2 Ga 0.8 N-barrier layer.

[0028] In one embodiment of the present invention, a bent gate field plate is provided on the upper surface of the passivation layer near the drain, comprising:

[0029] A bent groove is fabricated on the passivation layer using reactive ion etching technology, wherein the depth of the groove is less than the thickness of the passivation layer;

[0030] The gate field plate is formed by depositing oxygen-doped semi-insulating polycrystalline silicon in the groove using electron beam evaporation technology, with an oxygen content between 0.3% and 20%.

[0031] One end of the gate field plate is electrically connected to the gate, and the other end is electrically connected to the drain.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0033] 1. The high-reliability GaN-based HEMT device of the present invention utilizes a bent gate field plate connecting the gate and drain electrodes to alleviate the electric field accumulation effect at the gate edge, reduce the original electric field peak near the gate, modulate the electric field distribution between the gate and drain, avoid the failure and degradation of HEMT under high electric field stress, and at the same time, make full use of the gate-drain spacing to improve the breakdown voltage, greatly improving the breakdown efficiency of the device.

[0034] 2. The gate field plate of this invention is made of semi-insulating polycrystalline silicon material, which can prevent contamination by harmful external impurity ions and mitigate the influence of ion-induced electric fields on the electric field distribution of the device. The gate field plate adopts a bent distribution structure, making full use of the drift region area to further optimize the electric field distribution throughout the channel, resulting in a more uniform electric field distribution and significantly improving the breakdown efficiency of the lateral device. The density and dispersion of the bending of the gate field plate can be modulated according to the actual channel electric field distribution; that is, the bending is denser at the electric field peak and sparser at the electric field flat areas. This maximizes the effect of a uniform channel electric field distribution and improves the device breakdown characteristics.

[0035] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure of a high-reliability GaN-based HEMT device provided in an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of a gate field plate provided in an embodiment of the present invention;

[0038] Figure 3 This is a top view schematic diagram of a passivation layer that can display the shape of a groove (gate field plate) according to an embodiment of the present invention;

[0039] Figure 4 This is a flowchart of a method for fabricating a high-reliability GaN-based HEMT device according to an embodiment of the present invention;

[0040] Figures 5a to 5j This is a schematic diagram illustrating the fabrication process of a high-reliability GaN-based HEMT device provided in an embodiment of the present invention. Detailed Implementation

[0041] To further illustrate the technical means and advantages of this invention in achieving its intended purpose, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a high-reliability GaN-based HEMT device and its fabrication method based on this invention.

[0042] The foregoing and other technical contents, features, and advantages of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and advantages adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0043] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0044] Example 1

[0045] Please see Figures 1 to 3 , Figure 1 This is a schematic diagram of the structure of a high-reliability GaN-based HEMT device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a gate field plate provided in an embodiment of the present invention; Figure 3This is a top view schematic diagram of a passivation layer that can display the shape of a groove (gate field plate) according to an embodiment of the present invention. The high-reliability GaN-based HEMT device of this embodiment includes a substrate 1, an AlN nucleation layer 2, a GaN transition layer 3, and a barrier layer 4 stacked sequentially from bottom to top. A source 5 and a drain 6 are respectively disposed on the upper surfaces of the two ends of the barrier layer 4. A gate 8 is disposed on the barrier layer 4 between the source 5 and the drain 6. Mesa 7 extending downward to the upper surface or interior of the AlN nucleation layer 2 are formed on the outer sides of the source 5 and the drain 6. A passivation layer 9 is covered on the upper surfaces of the gate 8, the source 5, the drain 6, and the remaining area of ​​the barrier layer 4. A bent gate field plate 11 is disposed on the upper surface of the passivation layer 9 near the drain 6. The lower surface of the gate field plate 11 extends into the interior of the passivation layer 9, and the upper surface is flush with the upper surface of the passivation layer 9. One end of the gate field plate 11 is located above the gate 8, and the other end extends above the drain 6. A protective layer 12 is covered on the upper surface of the gate field plate 11 and the remaining area of ​​the passivation layer 9.

[0046] In this embodiment, the AlN nucleation layer 2 includes a low-temperature AlN nucleation layer disposed on the surface of the substrate 1, and a high-temperature AlN nucleation layer disposed on the upper surface of the low-temperature AlN nucleation layer. Both the low-temperature and high-temperature AlN nucleation layers are prepared using MOCVD technology. The low-temperature AlN nucleation layer has a thickness of 30 nm, a growth temperature of approximately 700℃~800℃, a pressure of 45 Torr, and an aluminum source flow rate of 5 μmol / min. The high-temperature AlN nucleation layer 2 has a thickness of 170 nm, a growth temperature of 900℃~1100℃, a pressure of 45 Torr, and an aluminum source flow rate of 5 μmol / min. The transition layer 3 has a thickness of 1 μm, and the barrier layer 4 is made of undoped Al. 0.2 Ga 0.8 The N layer has a thickness of 10 nm. Both source 5 and drain 6 use a Ti / Al / Ni / Au metal stack, with thicknesses of 0.018 μm / 0.135 μm / 0.046 μm / 0.052 μm for each layer, respectively. Gate 8 uses a Ni / Au metal stack, with a Ni metal layer (0.026 μm thick) and an Au metal layer (0.11 μm thick). The passivation layer 9 is made of SiN and has a thickness of 2.0 μm.

[0047] In this embodiment, as Figure 3As shown, the gate field plate 11 is formed by a series of cuboid structures connected vertically to form an arc-shaped structure. One cuboid structure at one end of the gate field plate 11 is located vertically above the gate 8 and is separated from the gate 8 by a passivation layer 9. The other cuboid structure at the other end of the gate field plate 11 extends vertically above the drain 6 within the passivation layer 9 and is separated from the drain 6 by the passivation layer 9. One end of the gate field plate 11 is electrically connected to the gate 8, and the other end is electrically connected to the drain 6. In other embodiments, the gate field plate 11 can also be a curved S-shaped structure. Furthermore, it should be noted that the actual bending shape or folding shape of the gate field plate 11 can be appropriately adjusted according to the actual electric field distribution; the bending or folding is denser at the peak of the electric field and sparser at the flatter areas of the electric field.

[0048] Furthermore, the gate field plate 11 is formed of oxygen-doped semi-insulating polycrystalline silicon material, with an oxygen content between 0.3% and 20%. The gate field plate 11 has a depth of 0.14 μm, a total length of 4.52 μm, and a width of 0.47 μm for its cuboid structure.

[0049] The gate field plate employs a bent structure to fully utilize the drift region area and further optimize the electric field distribution throughout the channel, resulting in a more uniform electric field distribution and significantly improving the breakdown efficiency of lateral devices. It should be noted that the density and dispersion of the gate field plate bends can be modulated according to the actual channel electric field distribution; that is, the field plate bends are denser at electric field peaks and sparser at areas where the electric field is flat. This maximizes the effect of a uniform channel electric field distribution and improves the device's breakdown characteristics.

[0050] Example 2

[0051] Based on the above embodiments, this embodiment provides a method for fabricating a high-reliability GaN-based HEMT device. Please refer to [link to relevant documentation]. Figure 4 As shown in Figure 5, the preparation method of this embodiment includes:

[0052] S1: An AlN nucleation layer 2, a transition layer 3, and an Al layer are sequentially grown on substrate 1. 0.2 Ga 0.8 N-barrier layer 4.

[0053] In this embodiment, step S1 includes:

[0054] S1.1: An AlN nucleation layer 2 is formed by epitaxially growing AlN material on substrate 1, such as... Figure 5a As shown.

[0055] A silicon or sapphire substrate is selected as substrate 1 and cleaned. A low-temperature AlN nucleation layer with a thickness of 30 nm is formed on the surface of substrate 1 using MOCVD process. The growth temperature of the low-temperature AlN nucleation layer is about 700℃~800℃, the pressure is 45 Torr, and the aluminum source flow rate is 5 μmol / min. Then, a high-temperature AlN nucleation layer is epitaxially grown on the low-temperature AlN nucleation layer. The thickness of the high-temperature AlN nucleation layer 2 is 170 nm. The growth temperature of the high-temperature AlN nucleation layer is 900℃~1100℃, the pressure is 45 Torr, and the aluminum source flow rate is 5 μmol / min.

[0056] S1.2: A transition layer 3 is formed by epitaxially growing GaN material on the AlN nucleation layer 2, such as... Figure 5b As shown.

[0057] Specifically, using the lateral epitaxial overgrowth technique (ELOG), a GaN transition layer 3 with a thickness of 1 μm is heteroepitaxially grown in a hydrogen (H2) environment at a temperature of 960 °C and a pressure of 45 Torr. The GaN transition layer 3 covers the AlN nucleation layer 2. The advantage of this technique is that it can obtain a GaN transition layer with a low defect density.

[0058] S1.3: Al is deposited on GaN transition layer 3. 0.2 Ga 0.8 N-barrier layer 4.

[0059] Undoped Al with a thickness of 10 nm was deposited on the GaN transition layer 3 using metal-organic chemical vapor deposition (MOCVD). 0.2 Ga 0.8 N-barrier layer 4, such as Figure 5c As shown. The selected process conditions are: temperature 980℃, pressure 45 Torr, nitrogen source ammonia flow rate 4800 sccm, aluminum source flow rate 3 μmol / min, and gallium source flow rate 8 μmol / min.

[0060] S2: In Al 0.2 Ga 0.8 Metals are deposited at both ends of the N-barrier layer 4 to form the source 5 and drain 6, respectively. Figure 5d As shown.

[0061] Specifically, in Al 0.2 Ga 0.8 The first mask was fabricated on the N-barrier layer 4, and electron beam evaporation was used to fabricate the Al. 0.2 Ga 0.8Metal is deposited at both ends of the N-barrier layer 4, followed by rapid thermal annealing under N2 gas conditions to form the source 5 and drain 6. In this embodiment, the source 5 and drain 6 are made of the same metal, and both are Ti / Al / Ni / Au metal stacks from bottom to top, with thicknesses of 0.018μm, 0.135μm, 0.046μm, and 0.052μm, respectively.

[0062] S3: In Al 0.2 Ga 0.8 The left and right sides of the N barrier layer 4 are etched to form mesas 7 extending downward to the upper surface or interior of the AlN nucleation layer 2, such as... Figure 5e As shown.

[0063] In Al 0.2 Ga 0.8 A second mask is fabricated on the N barrier layer 4. Reactive ion etching is used to etch the barrier layer 4 on the left side of the source 5 and the right side of the drain 6 to form a mesa 7 extending downward to the upper surface or interior of the AlN nucleation layer 2. The etching depth in this embodiment is 1.01 μm.

[0064] S4: In Al 0.2 Ga 0.8 Metal is deposited at the middle position of the N-barrier layer 4 to form the gate 8, such as Figure 5f As shown.

[0065] Specifically, in Al 0.2 Ga 0.8 A third mask is fabricated on the N-barrier layer 4. Electron beam evaporation is used to deposit metal as the gate 8 at the middle position of the barrier layer 4 between the source 5 and the drain 6. The deposited metal material is a Ni / Au multilayer metal, wherein the lower layer is Ni metal with a thickness of 0.026μm and the upper layer is Au metal with a thickness of 0.11μm.

[0066] S5: On the upper surfaces of gate 8, source 5, drain 6, and Al 0.2 Ga 0.8 A passivation layer 9 is formed on the upper surface of the remaining region of the N-barrier layer 4, such as Figure 5g As shown.

[0067] Specifically, PECVD technology is used on the upper surfaces of gate 8, source 5, drain 6, and Al. 0.2 Ga 0.8 On the upper surface of the remaining region of the N barrier layer 4, a SiN passivation layer 9 with a thickness of 2.0 μm is deposited to alleviate the surface states caused by lattice defects on the surface of the barrier layer heterojunction. The surface passivation measure can effectively suppress the current collapse phenomenon.

[0068] S6: A bent groove 10 is formed by etching within the passivation layer 9 above the gate 8 and drain 6, such as... Figure 5hAs shown.

[0069] Specifically, a fourth mask is fabricated on the passivation layer 9, and reactive ion etching is used to etch the passivation layer 9 to create a bent or bow-shaped groove 10. The depth of the groove 10 is less than the thickness of the passivation layer 9. In this embodiment, the groove 10 has a depth of 0.14 μm, a width of 0.47 μm, and a length of 4.52 μm. The groove 10 bends and extends from above the gate to above the drain 6. Specifically, one end of the groove 10 is formed inside the mesa 7, and the other end is located above at least a portion of the drain 6.

[0070] In other embodiments, the groove 10 may also be etched into a curved S-shaped structure.

[0071] S7: An oxygen-doped semi-insulating polycrystalline silicon material is deposited in the groove 10 to form a gate field plate 11, and one end of the gate field plate 11 is electrically connected to the gate 8, and the other end is electrically connected to the drain 6, as shown. Figure 5i As shown.

[0072] Specifically, oxygen-doped semi-insulating polysilicon is deposited in the groove 10 using electron beam evaporation technology. The thickness is 0.14 μm, the width is 0.47 μm, and the length is 4.52 μm. It should be noted that the actual bending or folding shape of the gate field plate 11 can be appropriately adjusted according to the actual electric field distribution. The bending or folding is denser at the electric field peak and sparser at the electric field flat areas. The deposited semi-insulating polysilicon should completely fill the groove 10, and one end of the gate field plate 11 should be electrically connected to the gate 8, and the other end to the drain 6. To ensure that the gate field plate has a suitable resistance value, the oxygen doping content of the semi-insulating polysilicon is determined by the actual length of the device. The oxygen content is generally between 0.3% and 20%, preferably 0.5%.

[0073] S8: A protective layer 12 is deposited on the upper surface of the gate field plate 11 and the remaining upper surface of the passivation layer 9, such as... Figure 5j As shown.

[0074] Specifically, a protective layer 12, with a thickness of 3.0 μm, is deposited on the upper surface of the gate field plate 11 and the remaining areas of the passivation layer 9 using PECVD technology to mitigate the influence of the ambient atmosphere on the electrical characteristics of the gate field plate. At this point, the process flow for the high-reliability GaN-based HEMT device in this embodiment is complete.

[0075] The high-reliability GaN-based HEMT device prepared using the method of this invention utilizes a bent gate field plate connecting the gate and drain electrodes to alleviate the electric field accumulation effect at the gate edge, reduce the original electric field peak near the gate, modulate the electric field distribution between the gate and drain, avoid failure and degradation of HEMT under high electric field stress, and at the same time, make full use of the gate-drain spacing to improve the breakdown voltage, greatly improving the breakdown efficiency of the device.

[0076] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-reliability GaN-based HEMT device, characterized in that, It includes a substrate (1), an AlN nucleation layer (2), a GaN transition layer (3), and a barrier layer (4) stacked sequentially from bottom to top, wherein, Source (5) and drain (6) are respectively provided on the upper surfaces of the two ends of the barrier layer (4), and gate (8) is provided on the barrier layer (4) between the source (5) and the drain (6). Mesa (7) extending downward to the upper surface or interior of the AlN nucleation layer (2) are respectively formed on the outer side of the source (5) and the drain (6). A passivation layer (9) is covered on the upper surfaces of the gate (8), the source (5), the drain (6), and the remaining area of ​​the barrier layer (4); A bent gate field plate (11) is provided on the upper surface of the passivation layer (9) near the drain (6). The lower surface of the gate field plate (11) extends into the interior of the passivation layer (9), and the upper surface is flush with the upper surface of the passivation layer (9). The orthographic projection of the gate field plate (11) is a continuous bow-shaped structure along the direction perpendicular to the plane of the substrate (1). One end of the gate field plate (11) is located above the gate (8), and the other end extends above the drain (6). A protective layer (12) is provided on the upper surface of the gate field plate (11) and the remaining area of ​​the passivation layer (9).

2. The high-reliability GaN-based HEMT device according to claim 1, characterized in that, The gate field plate (11) is formed by a series of cuboid structures connected vertically to form an arch-shaped structure. The cuboid structure at one end of the gate field plate (11) is located vertically above the gate (8) and is separated from the gate (8) by the passivation layer (9). The cuboid structure at the other end of the gate field plate (11) extends to the vertically above the drain (6) on the upper surface of the passivation layer (9) and is separated from the drain (6) by the passivation layer (9).

3. The high-reliability GaN-based HEMT device according to claim 1, characterized in that, The gate field plate (11) is formed of oxygen-doped semi-insulating polycrystalline silicon material with an oxygen content between 0.3% and 20%.

4. The high-reliability GaN-based HEMT device according to claim 1, characterized in that, The source (5) and the drain (6) are both made of Ti / Al / Ni / Au metal stack, and the gate (8) is made of Ni / Au metal stack.

5. The high-reliability GaN-based HEMT device according to claim 1, characterized in that, One end of the gate field plate (11) is electrically connected to the gate (8), and the other end is electrically connected to the drain (6).

6. The high-reliability GaN-based HEMT device according to claim 2, characterized in that, The gate field plate (11) has a depth of 0.14 μm and a total length of 4.52 μm, and the cuboid structure has a width of 0.47 μm.

7. The high-reliability GaN-based HEMT device according to claim 1, characterized in that, The material of the barrier layer (4) is Al. 0.2 Ga 0.8 N.

8. A method for fabricating a high-reliability GaN-based HEMT device, characterized in that, The method for fabricating a high-reliability GaN-based HEMT device according to any one of claims 1 to 7 comprises: An AlN nucleation layer, a transition layer, and an Al layer are sequentially grown on the substrate. 0.2 Ga 0.8 N-barrier layer; In the Al 0.2 Ga 0.8 Metals are deposited at both ends of the N-barrier layer to form the source and drain, respectively; In the Al 0.2 Ga 0.8 The left and right sides of the N barrier layer are etched to form mesas that extend downward to the upper surface or interior of the AlN nucleation layer; In the Al 0.2 Ga 0.8 Metal is deposited at the middle position of the upper surface of the N-barrier layer to form a gate; On the upper surfaces of the gate, the source, the drain, and the Al 0.2 Ga 0.8 A passivation layer is formed on the upper surface of the remaining region of the N-barrier layer; A bent gate field plate is provided on the upper surface of the passivation layer near the drain. The orthogonal projection of the gate field plate along the direction perpendicular to the plane of the substrate is a continuous bow-shaped structure. A protective layer is deposited on the upper surface of the gate field plate and on the remaining areas of the passivation layer.

9. The method for fabricating a high-reliability GaN-based HEMT device according to claim 8, characterized in that, An AlN nucleation layer, a transition layer, and an Al layer are sequentially grown on the substrate. 0.2 Ga 0.8 The N-barrier layer includes: A silicon or sapphire substrate is selected and cleaned. A low-temperature AlN nucleation layer is formed on the surface of the substrate. The growth temperature of the low-temperature AlN nucleation layer is 700℃~800℃, the pressure is 45 Torr, and the aluminum source flow rate is 5µmol / min. Then, a high-temperature AlN nucleation layer is epitaxially grown on the low-temperature AlN nucleation layer. The growth temperature of the high-temperature AlN nucleation layer is 900℃~1100℃, the pressure is 45 Torr, and the aluminum source flow rate is 5µmol / min. A GaN transition layer with a thickness of 1 μm is formed by epitaxially growing GaN material on the AlN nucleation layer; Undoped Al with a thickness of 10 nm is deposited on the GaN transition layer. 0.2 Ga 0.8 N-barrier layer.

10. The method for fabricating a high-reliability GaN-based HEMT device according to claim 8, characterized in that, A bent gate field plate is disposed on the upper surface of the passivation layer near the drain, comprising: A bent groove is fabricated on the passivation layer using reactive ion etching technology, wherein the depth of the groove is less than the thickness of the passivation layer; The gate field plate is formed by depositing oxygen-doped semi-insulating polycrystalline silicon in the groove using electron beam evaporation technology, with an oxygen content between 0.3% and 20%. One end of the gate field plate is electrically connected to the gate, and the other end is electrically connected to the drain.

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