A self-recovery over-voltage and under-voltage protection circuit

Abstract

The invention discloses a self-recovery over-voltage and under-voltage protection circuit, which includes a rectifier sampling circuit, a signal comparison circuit, a self-recovery control circuit, an inverse time control circuit, a delay circuit and a power supply circuit; the input end of the rectifier sampling circuit is connected to a low-voltage power distribution line, and the output end of the rectifier sampling circuit is connected to the input end of the signal comparison circuit and the input end of the inverse time control circuit; the output end of the signal comparison circuit is connected to the self-recovery control circuit, the inverse time control circuit and the delay circuit; the output end of the self-recovery control circuit and the inverse time control circuit are connected to the input end of the delay circuit; the output end of the delay circuit is connected to a driving circuit for driving an actuator to act; the input end of the power supply circuit is connected to an external power supply, and the output end is connected to the signal comparison circuit, the self-recovery control circuit, the inverse time control circuit and the delay circuit. The invention can realize the inverse time delay control function and the power supply state self-recovery function.

Description

Technical Field

[0001] The invention relates to a self-recovering over-voltage and under-voltage protection circuit with a time delay adjustable function. Background Art

[0002] With the rapid development of my country's social economy, the number of electrical equipment in low-voltage distribution systems is increasing, requiring low-voltage distribution systems to continuously adopt new technologies to ensure that the power supply network can operate safely, efficiently and economically. In low-voltage distribution lines, when the live wire or neutral wire fails, the potential of the low-voltage distribution line will be offset. If the potential offset is too large, it will not only burn electrical equipment or loads, but also cause fires and property losses, and more seriously, lead to safety accidents that endanger human life. According to the latest "Electrical Design Code for Residential Buildings", each residential building should be equipped with self-recovering over- and under-voltage protection devices. Requirements for over- and under-voltage protection devices: When over-voltage or under-voltage occurs in the low-voltage distribution line, it can automatically detect and cut off the load or line in time; when the voltage of the low-voltage distribution line returns to normal, the over- and under-voltage protection device can detect the normal state and automatically connect the line or load, thereby achieving the purpose of protecting the load or electrical equipment.

[0003] At present, the over-voltage and under-voltage protectors on the market all use discrete devices + general integrated circuits or single-chip solutions to achieve protection functions. The use of discrete devices + general integrated circuits has a complex circuit structure and requires the use of multiple power supply voltage systems. The integration and product consistency are poor, the delay accuracy is low, and it cannot fully meet technical and market requirements; the use of single-chip solutions has high costs, fixed and non-adjustable delay time, and requires hardware design and software program development, which has problems such as program reliability, anti-interference, and electromagnetic compatibility.

[0004] For example, a self-resetting over-voltage and under-voltage protector and its circuit (announcement number CN108471104A) is implemented by MCU single-chip microcomputer + discrete devices, which has many disadvantages such as low integration, large product volume, poor electromagnetic compatibility, and high cost; another example is a self-resetting over-voltage and under-voltage power-limiting protector (announcement number CN208508510U), which is implemented by a variety of op amp IC + discrete devices, and has many problems such as unstable performance consistency, difficult production and debugging, and high manufacturing cost, which is not suitable for wide application; another example is the "Optimization Design of Self-recovery Over-voltage and Under-voltage Protector Circuit" proposed by Yu Cuntai (Electrical Appliances and Energy Efficiency Management Technology 2018 Issue 7), which adopts The single-chip microcomputer (MCU) + discrete devices are used to realize the circuit function. Its implementation method is complex and requires software development and multiple power supplies. It has low product integration, poor consistency, weak anti-electromagnetic interference ability and other disadvantages, which are not conducive to large-scale application and promotion. For example, Yi Xianjun proposed "Design and Implementation of Self-resetting Over- and Under-voltage Protector Based on Analog Circuit" (Electrical Appliances and Energy Efficiency Management Technology, Issue 8, 2017), which uses a variety of standard analog integrated block circuits and a large number of discrete devices to realize its circuit functions. Due to the process fluctuation differences in the electrical parameter characteristics of each standard analog integrated block circuit and discrete device, it is very easy to cause parameter index deviations, which is difficult to meet the needs of large-scale production applications.

[0005] In summary, it is an urgent need to design a self-recovering over- and under-voltage protection circuit or product with high integration, simple structure, high reliability, low cost, good ESD resistance, strong electromagnetic compatibility, and suitable for large-scale production and application. Summary of the invention

[0006] The purpose of the present invention is to provide a self-recovering over- and under-voltage protection circuit to solve the problems of complex structure, non-adjustable delay time, poor consistency, low integration, need for software development, poor anti-interference performance, reliability and electromagnetic compatibility of existing products.

[0007] The present invention solves the above technical problems through the following technical solutions: a self-recovering over-voltage and under-voltage protection circuit, comprising:

[0008] A rectifier sampling circuit, whose input end is connected to the power supply end of the low-voltage distribution line, and whose output end is respectively connected to the signal comparison circuit and the inverse time control circuit, and the rectifier sampling circuit is used to convert the collected AC power frequency voltage into a smooth DC high-voltage signal, and then convert the DC high-voltage signal into an over-voltage or under-voltage signal;

[0009] A signal comparison circuit, whose output ends are respectively connected to the self-recovery control circuit, the inverse time control circuit and the delay circuit, and the signal comparison circuit is used to compare the over-voltage and under-voltage signals with the reference voltage signal and generate a first control signal;

[0010] A self-recovery control circuit, whose output terminal is connected to the delay circuit, and the self-recovery control circuit is used to control the operation of the self-recovery delay device and the second delay device in the delay circuit according to the first control signal;

[0011] An inverse time control circuit, whose output terminal is connected to a delay circuit, wherein the inverse time control circuit is used to start under the action of the first control signal and convert the overvoltage or undervoltage signal into a different second control signal after starting;

[0012] A delay circuit, whose output terminal is connected to a drive circuit of an actuator, the delay circuit is used to control the operation of a self-recovery delay device according to a self-recovery delay enable signal output by the self-recovery control circuit, and to control the actuator to move through the drive circuit after the self-recovery delay device has finished delaying, thereby realizing a self-recovery function; and is also used to control the operation of different second delay devices according to the first control signal, the second control signal and the intermediate signal output by the self-recovery control circuit, and to control the actuator to move through the drive circuit after the second delay device has finished delaying, thereby realizing an inverse time delay control function;

[0013] The power supply circuit is used to provide power to the signal comparison circuit, the self-recovery control circuit, the inverse time control circuit and the delay circuit.

[0014] Furthermore, the rectification sampling circuit includes a full-wave rectifier and a voltage divider circuit composed of a resistor R1 and a resistor R2 connected in series; the input end of the full-wave rectifier is connected to the power supply end of the low-voltage distribution line; the output end of the full-wave rectifier is connected to the first end of the resistor R1, and the second end of the resistor R2 is grounded.

[0015] Furthermore, the signal comparison circuit includes a first comparator COMP1, a second comparator COMP2 and a first OR gate; the positive input terminal of the first comparator COMP1 and the negative input terminal of the second comparator COMP2 are respectively connected to the output terminal of the rectifier sampling circuit; the negative input terminal of the first comparator COMP1 is connected to the reference voltage V REFH The positive input terminal of the second comparator COMP2 is connected to the reference voltage V REFL The output ends of the first comparator COMP1 and the second comparator COMP2 are connected to the input end of the first OR gate, and the output end of the first OR gate outputs a first control signal.

[0016] Furthermore, both the first comparator COMP1 and the second comparator COMP2 are hysteresis voltage comparators.

[0017] Furthermore, the inverse time control circuit includes a voltage divider circuit composed of a resistor RA, a resistor RB, a resistor RC, a resistor RD and a resistor RE connected in series, and comparators COMPA to COMPD; the positive input terminal of the comparator COMPA is connected to the connection point between the resistor RA and the resistor RB, the positive input terminal of the comparator COMPB is connected to the connection point between the resistor RB and the resistor RC, the positive input terminal of the comparator COMPC is connected to the connection point between the resistor RC and the resistor RD, and the positive input terminal of the comparator COMPD is connected to the connection point between the resistor RD and the resistor RE; the negative input terminals of the comparators COMPA to COMPD are all connected to the reference voltage V REF ; The output ends of the comparators COMPA~COMPD are respectively connected to the delay circuit; the output end of the signal comparison circuit is connected to the enable end of the comparators COMPA~COMPD.

[0018] Furthermore, the self-recovery control circuit includes a first delay device and a latch; the input end of the first delay device is connected to the output end of the signal comparison circuit, and the output end of the first delay device is respectively connected to the input end of the latch and the delay circuit; the output end of the latch is connected to the delay circuit.

[0019] Furthermore, the delay circuit includes an oscillator, a self-recovery delay device, a second delay device 1-4, AND gates 1-6, a second OR gate, and NOT gates 1-7; the input end of the self-recovery delay device is connected to the output end of the latch in the self-recovery control circuit, and its output end is connected to the input end of the AND gate 6 through the NOT gate 1; the input end of the AND gate 1 is respectively connected to the output end of the first delay device in the self-recovery control circuit and the output end of the signal comparison circuit, and the output end of the AND gate 1 is respectively connected to the second delay devices 1-4; the output end of the comparator COMPA in the inverse time control circuit is connected to the input end of the AND gate 2, the output end of the comparator COMPB in the inverse time control circuit is connected to the input end of the AND gate 2 through the NOT gate 2, the output end of the comparator COMPC in the inverse time control circuit is connected to the input end of the AND gate 2 through the NOT gate 3, and the output end of the comparator COMPD in the inverse time control circuit is connected to the input end of the AND gate 2 through the NOT gate 4; the comparator COMP in the inverse time control circuit The output end of B is connected to the input end of AND gate 3, the output end of comparator COMPC in the inverse time control circuit is connected to the input end of AND gate 3 through NOT gate 5, and the output end of comparator COMPD in the inverse time control circuit is connected to the input end of AND gate 3 through NOT gate 6; the output end of comparator COMPC in the inverse time control circuit is connected to the input end of AND gate 4, and the output end of comparator COMPD in the inverse time control circuit is connected to the input end of AND gate 5 through NOT gate 7; the output end of comparator COMPD in the inverse time control circuit is connected to the input end of AND gate 5; the output end of AND gate 2 is connected to the second delay device 1, the output end of AND gate 3 is connected to the second delay device 2, the output end of AND gate 4 is connected to the second delay device 3, and the output end of AND gate 5 is connected to the second delay device 4; the output ends of the second delay devices 1 to 4 are respectively connected to the input ends of the second OR gate, and the output end of the second OR gate is connected to the input end of AND gate 6; the oscillator is respectively connected to the second delay devices 1 to 4.

[0020] Further, the delay time of the second delay device 1 is greater than the delay time of the second delay device 2 , and the delay time of the second delay device 3 is greater than the delay time of the second delay device 4 .

[0021] Furthermore, the power supply circuit includes a voltage stabilizing circuit, a reference voltage source circuit, a reference current source circuit, an overvoltage protection circuit and an undervoltage lockout circuit; the input end of the voltage stabilizing circuit is connected to an external power supply, and the output end of the voltage stabilizing circuit is respectively connected to the reference voltage source circuit, the reference current source circuit, the overvoltage protection circuit and the undervoltage lockout circuit; the overvoltage protection circuit is connected to the undervoltage lockout circuit; the output end of the undervoltage lockout circuit serves as an output end of the power supply voltage VDD.

[0022] Furthermore, a filtering circuit is provided between the rectification sampling circuit and the signal comparison circuit.

[0023] Beneficial Effects

[0024] Compared with the prior art, the advantages of the present invention are:

[0025] The present invention provides a self-recovering over-voltage and under-voltage protection circuit. The inverse time control circuit can automatically adjust the delay time of the delay circuit according to the degree of overvoltage or undervoltage, thereby realizing the inverse time delay control function; the self-recovering control circuit can automatically restore the load / power supply to the normal power supply state when the low-voltage distribution line is in a non-over-voltage or under-voltage state, thereby realizing the power supply state self-recovery function;

[0026] The present invention does not require multiple power supply systems and adopts a single power supply working mode, which greatly improves the integration, simplifies the complexity of product application, improves the consistency of product batch production, and reduces product costs; the present invention does not require secondary development / program writing, shortens the development cycle, and improves product reliability and index performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only one embodiment of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 1 is a structural block diagram of a self-recovering over-voltage and under-voltage protection circuit in an embodiment of the present invention;

[0029] Figure 2 is a schematic diagram of a rectifier sampling circuit in an embodiment of the present invention;

[0030] Figure 3 is a schematic diagram of a signal comparison circuit in an embodiment of the present invention;

[0031] Figure 4 is a schematic diagram of an inverse time control circuit in an embodiment of the present invention;

[0032] Figure 5 is a schematic diagram of a self-recovery control circuit in an embodiment of the present invention;

[0033] Figure 6 It is a schematic diagram of a delay circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following is a clear and complete description of the technical solutions in the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0036] like Figure 1 As shown, a self-recovery over- and under-voltage protection circuit provided by an embodiment of the present invention includes a rectifier sampling circuit, a signal comparison circuit, a self-recovery control circuit, an inverse time control circuit, a delay circuit and a power supply circuit; the input end of the rectifier sampling circuit is connected to the live wire and the neutral wire of the low-voltage distribution line, and the output end of the rectifier sampling circuit is connected to the input end of the signal comparison circuit and the input end of the inverse time control circuit; the output end of the signal comparison circuit is connected to the input end of the self-recovery control circuit, the enable end of the inverse time control circuit, and the input end of the delay circuit; the output ends of the self-recovery control circuit and the inverse time control circuit are respectively connected to the input end of the delay circuit; the output end of the delay circuit is connected to a drive circuit for driving the actuator to act; the input end of the power supply circuit is connected to an external power supply, and the output end is connected to the signal comparison circuit, the self-recovery control circuit, the inverse time control circuit and the delay circuit.

[0037] The rectifier sampling circuit is used to convert the collected AC power frequency voltage into a smooth DC high voltage signal, and then convert the DC high voltage signal into an over-voltage or under-voltage signal; the signal comparison circuit is used to compare the over-voltage or under-voltage signal with the reference voltage signal and generate a first control signal; the self-recovery control circuit is used to control the operation of the self-recovery delay device and the second delay device in the delay circuit according to the first control signal; the inverse time control circuit is used to start under the action of the first control signal, and after starting, the over-voltage or under-voltage signal is converted into a different second control signal; the delay circuit is used to control the operation of the self-recovery delay device according to the self-recovery delay enable signal output by the self-recovery control circuit, and after the delay of the self-recovery delay device ends, the actuator is controlled by the drive circuit to realize the self-recovery function; it is also used to control the operation of different second delay devices according to the first control signal, the second control signal and the intermediate signal output by the self-recovery control circuit, and after the delay of the second delay device ends, the actuator is controlled by the drive circuit to realize the inverse time delay control function; the power supply circuit is used to provide power for the signal comparison circuit, the self-recovery control circuit, the inverse time control circuit and the delay circuit.

[0038] In a specific embodiment of the present invention, Figure 2 As shown, the rectifier sampling circuit includes a rectifier part and a sampling part; the rectifier part is a bridge full-wave rectifier or a half-wave rectifier; the sampling part is a voltage divider circuit composed of a resistor R1 and a resistor R2 connected in series, and the connection point between the resistor R1 and the resistor R2 is the over-voltage and under-voltage signal sampling detection point. The low-voltage distribution line is a two-phase or three-phase AC power frequency voltage of 50HZ / 60HZ. The two-phase or three-phase AC power frequency voltage is collected as an input signal by the input end of the full-wave rectifier or the half-wave rectifier (that is, the live wire L end and the neutral wire N end of the low-voltage distribution line are connected to the input end of the rectifier sampling circuit). The full-wave rectifier or the half-wave rectifier converts the two-phase or three-phase AC power frequency voltage into a smooth DC high-voltage signal VDC or an approximately smooth high-voltage signal VDC with a small ripple factor; since the connection point between the resistor R1 and the resistor R2 is used as the over-voltage and under-voltage signal sampling detection point, the DC high-voltage signal VDC is divided by the resistor R1 to obtain the over-voltage and under-voltage signal VIN. As shown Figure 2 As shown, AC+ and AC- are connected to the live wire terminal and neutral wire terminal of the industrial frequency AC respectively.

[0039] Since the self-recovery over- and under-voltage protection circuit adopts an independent DC low-voltage power supply, which is different from the two-phase / three-phase AC industrial frequency power supply and its rectified DC high-voltage signal VDC, it is necessary to limit the voltage range of the over- and under-voltage sampling detection point to the maximum voltage value range of the DC low-voltage power supply of the self-recovery over- and under-voltage protection circuit to ensure that the self-recovery over- and under-voltage protection circuit can safely and effectively receive and process the over- and under-voltage signal VIN of the over- and under-voltage sampling detection point. The over- and under-voltage signal VIN of the over- and under-voltage sampling detection point is obtained through the voltage divider of the resistor R1.

[0040] In order to ensure the sampling accuracy of the over-voltage and under-voltage signal VIN, a filter circuit C1 is set at the over-voltage and under-voltage sampling detection point, which can effectively filter out AC noise and avoid false detection of over-voltage and under-voltage status caused by inaccurate sampling.

[0041] In a specific embodiment of the present invention, Figure 3 As shown, the signal comparison circuit includes a first comparator COMP1, a second comparator COMP2 and a first OR gate; the positive input terminal of the first comparator COMP1 and the negative input terminal of the second comparator COMP2 are respectively connected to the output terminal of the rectifier sampling circuit; the negative input terminal of the first comparator COMP1 is connected to the reference voltage V REFH The positive input terminal of the second comparator COMP2 is connected to the reference voltage V REFL The output ends of the first comparator COMP1 and the second comparator COMP2 are connected to the input end of the first OR gate, and the output end of the first OR gate outputs the first control signal.

[0042] When the undervoltage signal VIN ≥ reference voltage V REFHWhen the over-voltage or under-voltage signal VIN is less than the reference voltage V REFH When , the first comparator COMP1 outputs a low level;

[0043] When the undervoltage signal VIN ≥ reference voltage V REFL When the over-voltage or under-voltage signal VIN is less than the reference voltage V REFL When , the second comparator COMP2 outputs a high level;

[0044] When both the first comparator COMP1 and the second comparator COMP2 output a low level, it indicates that the low-voltage distribution line is in a normal state and there is no over-voltage or under-voltage problem. At this time, the first control signal is a low-level signal; when any one of the first comparator COMP1 and the second comparator COMP2 outputs a high level, it indicates that the low-voltage distribution line is in an overvoltage state or an undervoltage state. At this time, the first control signal is a high-level signal.

[0045] In a specific embodiment of the present invention, Figure 4 As shown, the inverse time control circuit includes a voltage divider circuit composed of a resistor RA, a resistor RB, a resistor RC, a resistor RD and a resistor RE connected in series, and comparators COMPA to COMPD; the positive input terminal of the comparator COMPA is connected to the connection point of the resistor RA and the resistor RB, the positive input terminal of the comparator COMPB is connected to the connection point of the resistor RB and the resistor RC, the positive input terminal of the comparator COMPC is connected to the connection point of the resistor RC and the resistor RD, and the positive input terminal of the comparator COMPD is connected to the connection point of the resistor RD and the resistor RE; the negative input terminals of the comparators COMPA to COMPD are all connected to the reference voltage V REF ; The output ends of the comparators COMPA~COMPD are respectively connected to the delay circuit; the output end of the first OR gate in the signal comparison circuit is connected to the enable end of the comparators COMPA~COMPD.

[0046] When the first control signal output by the first OR gate is at a high level, the comparators COMPA~COMPD are enabled (i.e., start working), and the over-voltage and under-voltage signal VIN is divided into four signals VP0~VP3 by the voltage divider circuit. When VP0≥reference voltage V REF When VP0 < reference voltage V REF When VP1≥reference voltage V REF When VP1 < reference voltage V REF When VP2≥reference voltage V REFWhen VP2 < reference voltage V REF When VP3 ≥ reference voltage V REF When VP3 < reference voltage V REF When , the comparator COMPD outputs a low level A3 signal.

[0047] When the first control signal output by the first OR gate is at a low level, the comparators COMPA-COMPD do not start working, the over-voltage / under-voltage signal VIN is not regarded as a valid input signal, and therefore the comparators COMPA-COMPD do not generate a changed and valid second control signal.

[0048] The level signals A0~A3 are used as the second control signals. The delay time of the delay circuit is adjusted according to the second control signals A0~A3. When the delay timing ends, the delay circuit controls the actuator to move through the drive circuit to achieve inverse time delay control. The inverse time control circuit automatically adjusts the delay time of the delay circuit according to the overvoltage or undervoltage degree. The higher the overvoltage degree or the lower the undervoltage degree, the shorter the delay time of the delay circuit. On the contrary, the lower the overvoltage degree or the higher the undervoltage degree, the longer the delay time of the delay circuit. When the delay timing ends, if the overvoltage or undervoltage state is still valid, the delay circuit outputs a valid signal to control the output of the drive circuit, driving the actuator to disconnect the load / power supply (for example, disconnecting the contacts of the relay to disconnect the load / power supply) to protect the load or power supply.

[0049] In a specific embodiment of the present invention, Figure 5 As shown, the self-recovery control circuit includes a first delay device and a latch; the first delay device is used to achieve a short delay, such as a 1ms delay, to avoid malfunctions caused by interference; the latch is used to latch the switching between overvoltage, undervoltage and normal states and output control instructions.

[0050] When the first control signal output by the signal comparison circuit is a low-level signal, it indicates that the low-voltage distribution line is in a normal state. The first control signal is confirmed as an invalid signal after passing through the first delay device, and the first delay device outputs a low level, that is, the delay enable terminal OU_en is a low level. When OU_en is a low level, the four second delay devices in the delay circuit do not start the delay timing work; when the first control signal output by the signal comparison circuit is a high-level signal, it indicates that the low-voltage distribution line is in an overvoltage state or an undervoltage state. The first control signal is confirmed as a valid signal after passing through the first delay device, and the first delay device outputs a high level, that is, the delay enable terminal OU_en is a high level. When OU_en is a high level, the four second delay devices in the delay circuit are all enabled and effective. Then, the output signals A0~A3 of the inverse time control circuit are used to control the opening of the second delay devices in the delay circuit to achieve the corresponding delay time.

[0051] When the first control signal output by the signal comparison circuit is at a low level, the latch in the self-recovery control circuit maintains the initial reset state after power-on, and the latch outputs a low level (that is, the self-recovery delay enable is at a low level), and the self-recovery delay device in the delay circuit cannot be triggered; when the first control signal output by the signal comparison circuit changes from a high level to a low level (that is, the low-voltage distribution line recovers from an overvoltage state or an undervoltage state to a normal state), if OU_en changes from a high level to a low level, the latch triggers a flip, and the output signal of the latch changes from a low level to a high level (that is, the self-recovery delay enable changes from a low level to a high level), triggering the self-recovery delay device in the delay circuit to start working. After the delay ends, the control drive circuit closes the load / power supply, restores the normal power supply state, and realizes the self-recovery function.

[0052] In a specific embodiment of the present invention, Figure 6As shown, the delay circuit includes an oscillator, a self-recovery delay device, a second delay device 1-4, AND gates 1-6, a second OR gate, and NOT gates 1-7; the input end of the self-recovery delay device is connected to the output end of the latch, and its output end is connected to the input end of the AND gate 6 through the NOT gate 1; the input end of the AND gate 1 is respectively connected to the output end of the first delay device and the output end of the signal comparison circuit, and the output end of the AND gate 1 is respectively connected to the second delay devices 1-4; the second control signal A0 is connected to the input end of the AND gate 2, and the second control signals A1-A3 are respectively connected to the input end of the AND gate 2 through the NOT gates 2-4; the second control signal A1 is connected to the input end of the AND gate 3, and the second control signal A2 is connected to the input end of the AND gate 4. A2~A3 are connected to the input end of AND gate 3 through NOT gates 5~6 respectively; the second control signal A2 is connected to the input end of AND gate 4, and the second control signal A3 is connected to the input end of AND gate 4 through NOT gate 7; the second control signal A3 is connected to the input end of AND gate 5; the output end of AND gate 2 is connected to the second delay device 1, the output end of AND gate 3 is connected to the second delay device 2, the output end of AND gate 4 is connected to the second delay device 3, and the output end of AND gate 5 is connected to the second delay device 4; the output ends of the second delay devices 1~4 are connected to the input ends of the second OR gate respectively, and the output end of the second OR gate is connected to the input end of AND gate 6; the oscillator is connected to the second delay devices 1~4 respectively.

[0053] The oscillator provides a reference clock signal for the delay circuit. The oscillator generates a standard clock square wave inside to provide a reference clock signal CLK for the delay circuit.

[0054] When the first control signal output by the signal comparison circuit is a low-level signal, it indicates that the low-voltage distribution line is in a normal state, the self-recovery control circuit outputs a low level, the comparators COMPA~COMPD in the inverse time control circuit do not work, the second control signal is invalid, the second delay devices 1~4 in the delay circuit do not start working, and the drive circuit also maintains a low level and does not drive the output; when the first control signal output by the signal comparison circuit is a high level, it indicates that the low-voltage distribution line is in an overvoltage or undervoltage state, the enable terminal OU_en of the self-recovery control circuit changes from a low level to a high level, and the second control signal A0~A3 input signal is valid. When A0 is a high level and A1~A3 are low levels, the second delay device 1 in the delay circuit is enabled to start the delay timing, and the second delay devices 2~4 do not start working; when A0 When A0, A1 and A2 are at high level and A2 and A3 are at low level, the second delay device 2 in the delay circuit is enabled to start the delay timing, while the second delay devices 1, 3 and 4 are not started to work; when A0, A1 and A2 are at high level and A3 is at low level, the second delay device 3 in the delay circuit is enabled to start the delay timing, while the second delay devices 1, 2 and 4 are not started to work; when A0, A1, A2 and A3 are all at high level, the second delay device 4 in the delay circuit is enabled to start the delay timing, while the second delay devices 1 to 3 are not started to work; the delay time relationship of the second delay devices 1 to 4 is: the second delay device 1> the second delay device 2> the second delay device 3> the second delay device 4; after the delay of the second delay device ends, the driving circuit is enabled to drive the output high level, and the power supply or load system is cut off, thereby realizing automatic adjustment of the delay time.

[0055] When the first control signal output by the signal comparison circuit changes from a high-level signal to a low-level signal, it indicates that the overvoltage or undervoltage state of the low-voltage distribution line changes to a normal state, the second delay devices 1 to 4 are disabled and reset to the initial state, and the output signal of the self-recovery control circuit changes from a high-level signal to a low-level signal. At this time, the self-recovery delay device in the delay circuit is triggered and started. After completing the self-recovery delay count, the control delay circuit enables the drive circuit to switch from a high-level signal to a low-level signal, so that the power supply and load system are connected or closed to realize the self-recovery function.

[0056] When the first control signal output by the signal comparison circuit is a high-level signal, it indicates that the low-voltage distribution line is in an overvoltage state or an undervoltage state, the self-recovery control circuit outputs a high level, and the comparators COMPA~COMPD in the inverse time control circuit work. When the self-recovery control circuit outputs a high level and the second control signal A0 is a high level, the second delay device 1 in the delay circuit starts the delay timing while the second delay devices 2, 3, and 4 do not work. After the second delay device 1 completes the timing, the drive circuit is enabled to output a high level, cutting off the load or power supply; when the self-recovery control circuit outputs a high level and the second control signals A0 and A1 are both high levels, the second delay device 2 in the delay circuit starts the timing while the second delay devices 1, 3, and 4 do not work. After the second delay device 2 completes the timing, the drive circuit is enabled to output a high level, cutting off the load or power supply; when When the self-recovery control circuit outputs a high level and the second control signals A0~A2 are all high levels, the second delay device 3 in the delay circuit starts timing while the second delay devices 1, 2, and 4 do not work. After the second delay device 3 completes timing, the drive circuit is enabled to output a high level to cut off the load or power supply; when the self-recovery control circuit outputs a high level and the second control signals A0~A3 are all high levels, the second delay device 4 in the delay circuit starts timing while the second delay devices 1, 2, and 3 do not work. After the second delay device 4 completes timing, the drive circuit is enabled to output a high level to cut off the load or power supply.

[0057] In a specific embodiment of the present invention, the power supply circuit includes a voltage stabilizing circuit, a reference voltage source circuit, a reference current source circuit, an overvoltage protection circuit, and an undervoltage lockout circuit; the input end of the voltage stabilizing circuit is connected to an external power supply, and the output end of the voltage stabilizing circuit is respectively connected to the reference voltage source circuit, the reference current source circuit, the overvoltage protection circuit, and the undervoltage lockout circuit; the overvoltage protection circuit and the undervoltage lockout circuit are used to monitor whether the voltage at the power supply end is within the normal voltage working range. When the external power supply voltage is higher than the rated maximum working voltage, the overvoltage protection circuit is turned on to stabilize the voltage at the power supply input end to within the normal working voltage value; when the external power supply voltage is lower than the circuit's minimum working voltage, the undervoltage lockout circuit will reset the circuit, prohibit the circuit from working and make the output low level to prevent malfunction due to too low voltage, and the voltage stabilizing circuit keeps a stable DC voltage at the output end of the power supply voltage VDD. .

[0058] The voltage stabilizing circuit is connected to the external power supply, converts the external power supply into a stable DC power supply voltage VDD, and provides a reference power supply for the signal comparison circuit, the self-recovery control circuit, the inverse time control circuit, the delay circuit, the reference voltage source circuit and the reference current source circuit; the reference voltage source circuit provides a reference voltage V for the first comparator COMP1 REFH The second comparator COMP2 provides a reference voltage V REFL And provide reference voltage V for comparators COMPA~COMPD REF; The reference current source provides current source bias signals for each analog circuit respectively; The overvoltage protection circuit opens the leakage channel when the DC supply voltage VDD is abnormally high, and closes the leakage channel after reducing the DC supply voltage VDD to below the safe voltage to ensure that the supply voltage does not exceed the set maximum threshold; When the DC supply voltage VDD is lower than the set minimum threshold, the undervoltage lockout circuit turns off the power supply of the self-recovery over- and under-voltage protection circuit, avoiding abnormal circuit operation or malfunction due to too low supply voltage. The power supply circuit integrates overvoltage protection circuit, undervoltage lockout circuit, etc., and has over- and undervoltage protection functions.

[0059] The present invention can automatically, in real time and accurately monitor the overvoltage and undervoltage status of the power supply system of the power grid, and has an inverse time delay function and a delay time self-adjustment function. When overvoltage or undervoltage is detected, the inverse time control circuit automatically adjusts the delay time of the delay circuit according to the degree of overvoltage or undervoltage, and realizes the inverse time delay function in an intelligent and adaptive manner. After the delay ends, it is judged whether the overvoltage or undervoltage still exists. If it still exists, the actuator is driven to disconnect the power supply or load to achieve a protective effect; when it is detected that the voltage of the power supply system of the power grid has recovered from the overvoltage or undervoltage state to the normal power supply state, the self-recovery control circuit controls the delay circuit to start timing. When the delay timing ends, it is judged that the power supply voltage has returned to normal, and the actuator is driven to connect the power supply or load to return to the normal power supply use state.

[0060] What is disclosed above is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or modifications within the technical scope disclosed in the present invention, which should be covered within the protection scope of the present invention.

Claims

1. A self-recovering over-voltage and under-voltage protection circuit, characterized in that: include: A rectifier sampling circuit, whose input end is connected to the power supply end of the low-voltage distribution line, and whose output end is respectively connected to the signal comparison circuit and the inverse time control circuit, and the rectifier sampling circuit is used to convert the collected AC power frequency voltage into a smooth DC high-voltage signal, and then convert the DC high-voltage signal into an overvoltage or undervoltage signal; A signal comparison circuit, whose output ends are respectively connected to the self-recovery control circuit, the inverse time control circuit and the delay circuit, and the signal comparison circuit is used to compare the over-voltage and under-voltage signals with the reference voltage signal and generate a first control signal; A self-recovery control circuit, whose output terminal is connected to the delay circuit, and the self-recovery control circuit is used to control the operation of the self-recovery delay device and the second delay device in the delay circuit according to the first control signal; An inverse time control circuit, whose output terminal is connected to a delay circuit, wherein the inverse time control circuit is used to start under the action of the first control signal and convert the overvoltage or undervoltage signal into a different second control signal after starting; A delay circuit, whose output terminal is connected to a drive circuit of an actuator, the delay circuit is used to control the operation of the self-recovery delay device according to the self-recovery delay enable signal output by the self-recovery control circuit, and control the actuator to move through the drive circuit after the self-recovery delay device delay ends; and is also used to control the operation of different second delay devices according to the first control signal, the second control signal and the intermediate signal output by the self-recovery control circuit, and control the actuator to move through the drive circuit after the second delay device delay ends; A power supply circuit, used to provide power to the signal comparison circuit, the self-recovery control circuit, the inverse time control circuit and the delay circuit; The inverse time control circuit includes a voltage divider circuit composed of a resistor RA, a resistor RB, a resistor RC, a resistor RD and a resistor RE connected in series, and comparators COMPA to COMPD; the positive input terminal of the comparator COMPA is connected to the connection point between the resistor RA and the resistor RB, the positive input terminal of the comparator COMPB is connected to the connection point between the resistor RB and the resistor RC, the positive input terminal of the comparator COMPC is connected to the connection point between the resistor RC and the resistor RD, and the positive input terminal of the comparator COMPD is connected to the connection point between the resistor RD and the resistor RE; the negative input terminals of the comparators COMPA to COMPD are all connected to the reference voltage V REF ; The output ends of the comparators COMPA~COMPD are respectively connected to the delay circuit; the output end of the signal comparison circuit is connected to the enable end of the comparators COMPA~COMPD; The self-recovery control circuit includes a first delay device and a latch; the input end of the first delay device is connected to the output end of the signal comparison circuit, and the output end of the first delay device is respectively connected to the input end of the latch and the delay circuit; the output end of the latch is connected to the delay circuit.

2. The self-recovering over-voltage and under-voltage protection circuit according to claim 1, characterized in that: The rectification sampling circuit includes a full-wave rectifier and a voltage divider circuit composed of a resistor R1 and a resistor R2 connected in series; the input end of the full-wave rectifier is connected to the power supply end of the low-voltage distribution line; the output end of the full-wave rectifier is connected to the first end of the resistor R1, and the second end of the resistor R2 is grounded.

3. The self-recovering over-voltage and under-voltage protection circuit according to claim 1, characterized in that: The signal comparison circuit includes a first comparator COMP1, a second comparator COMP2 and a first OR gate; the positive input terminal of the first comparator COMP1 and the negative input terminal of the second comparator COMP2 are respectively connected to the output terminal of the rectifier sampling circuit; the negative input terminal of the first comparator COMP1 is connected to the reference voltage V REFH The positive input terminal of the second comparator COMP2 is connected to the reference voltage V REFL The output ends of the first comparator COMP1 and the second comparator COMP2 are connected to the input end of the first OR gate, and the output end of the first OR gate outputs a first control signal.

4. The self-recovering over-voltage and under-voltage protection circuit according to claim 3, characterized in that: The first comparator COMP1 and the second comparator COMP2 are both hysteresis voltage comparators.

5. The self-recovering over-voltage and under-voltage protection circuit according to claim 1, characterized in that: The delay circuit includes an oscillator, a self-recovery delay device, a second delay device 1-4, an AND gate 1-6, a second OR gate, and an NOT gate 1-7; the input end of the self-recovery delay device is connected to the output end of the latch in the self-recovery control circuit, and its output end is connected to the input end of the AND gate 6 through an NOT gate 1; the input end of the AND gate 1 is respectively connected to the output end of the first delay device in the self-recovery control circuit and the output end of the signal comparison circuit, and the output end of the AND gate 1 is respectively connected to the second delay devices 1-4; the output end of the comparator COMPA in the inverse time control circuit is connected to the input end of the AND gate 2, the output end of the comparator COMPB in the inverse time control circuit is connected to the input end of the AND gate 2 through an NOT gate 2, the output end of the comparator COMPC in the inverse time control circuit is connected to the input end of the AND gate 2 through an NOT gate 3, and the output end of the comparator COMPD in the inverse time control circuit is connected to the input end of the AND gate 2 through an NOT gate 4; the output end of the comparator COMPB in the inverse time control circuit is connected to the input end of the AND gate 2 through an NOT gate 4; The output end of the comparator COMPC in the inverse time control circuit is connected to the input end of the AND gate 3 through the NOT gate 5, and the output end of the comparator COMPD in the inverse time control circuit is connected to the input end of the AND gate 3 through the NOT gate 6; the output end of the comparator COMPC in the inverse time control circuit is connected to the input end of the AND gate 4, and the output end of the comparator COMPD in the inverse time control circuit is connected to the input end of the AND gate 5 through the NOT gate 7; the output end of the comparator COMPD in the inverse time control circuit is connected to the input end of the AND gate 5; the output end of the AND gate 2 is connected to the second delay device 1, the output end of the AND gate 3 is connected to the second delay device 2, the output end of the AND gate 4 is connected to the second delay device 3, and the output end of the AND gate 5 is connected to the second delay device 4; the output ends of the second delay devices 1 to 4 are respectively connected to the input ends of the second OR gate, and the output end of the second OR gate is connected to the input end of the AND gate 6; the oscillator is respectively connected to the second delay devices 1 to 4.

6. The self-recovering over-voltage and under-voltage protection circuit according to claim 5, characterized in that: The delay time of the second delay device 1 is greater than the delay time of the second delay device 2 , and the delay time of the second delay device 3 is greater than the delay time of the second delay device 4 .

7. The self-recovering over-voltage and under-voltage protection circuit according to any one of claims 1 to 6, characterized in that: The power supply circuit includes a voltage stabilizing circuit, a reference voltage source circuit, a reference current source circuit, an overvoltage protection circuit and an undervoltage lockout circuit; the input end of the voltage stabilizing circuit is connected to an external power supply, and the output end of the voltage stabilizing circuit is respectively connected to the reference voltage source circuit, the reference current source circuit, the overvoltage protection circuit and the undervoltage lockout circuit; The overvoltage protection circuit is connected to the undervoltage lockout circuit; the output end of the undervoltage lockout circuit serves as the output end of the power supply voltage VDD.

8. The self-recovering over-voltage and under-voltage protection circuit according to any one of claims 1 to 6, characterized in that: A filter circuit is also provided between the rectification sampling circuit and the signal comparison circuit.

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