A control method and device for a boost circuit and an electronic device

Abstract

The present invention provides a control method, device, and electronic device for a boost circuit. The method includes: calculating the original duty cycle of a first controllable switch and a second controllable switch based on the error between a given value and an actual value of an output bus voltage; calculating a duty cycle offset based on the error between a given value and an actual value of a voltage across a flying capacitor; determining the difference between the original duty cycle of the first controllable switch and the duty cycle offset as the target duty cycle of the first controllable switch; determining the sum of the original duty cycle of the second controllable switch and the duty cycle offset as the target duty cycle of the second controllable switch; adjusting the first controllable switch based on the target duty cycle of the first controllable switch, and adjusting the second controllable switch based on the target duty cycle of the second controllable switch, so that the anode voltage of a third diode is less than or equal to the cathode voltage. The present invention can reduce the probability of overcurrent in the third diode and improve the reliability of the boost circuit.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a control method and device for a boost circuit, and electronic equipment. Background Art

[0002] like Figure 1 The boost circuit shown includes a first branch consisting of a first controllable switch and a second controllable switch connected in series, a second branch consisting of a first output capacitor and a second output capacitor connected in series, a flying capacitor, and a third diode. The first end of the flying capacitor is connected to the common point of the first and second controllable switches in the first branch, and the second end is connected to the first end of the first branch via a first diode. The anode of the first diode is connected to the first end of the first branch, and the cathode of the first diode is connected to the second end of the flying capacitor. The first end of the flying capacitor is connected to the second end of the second branch via a second diode. The anode of the second diode is connected to the second end of the flying capacitor, and the cathode of the second diode is connected to the first end of the second branch. A third diode is connected between the first end of the flying capacitor and the common point of the first and second output capacitors in the second branch. The anode of the third diode is connected to the first end of the flying capacitor, and the cathode is connected to the common point of the first and second output capacitors in the second branch. The first end of the first branch is connected to the positive terminal of the input of the boost circuit via an inductor; the second end is connected to the negative terminal of the input and the negative terminal of the output of the boost circuit, respectively. The second branch is connected in parallel between the positive electrode and the negative electrode of the output terminal.

[0003] During control of the boost circuit, the first controllable switch Q1 and the second controllable switch Q2 are alternately controlled, ensuring that the voltage across the flying capacitor Cfly is approximately equal to half the bus voltage, i.e., the voltage across the first output capacitor C1. However, when the voltage across the flying capacitor Cfly is lower than the voltage across the first output capacitor C1, a large current may flow through the third diode D3, which cannot handle such a large current. Overcurrent in the third diode D3 can easily damage it, impacting the reliability of the boost circuit. Summary of the Invention

[0004] The present invention provides a control method, device and electronic equipment for a boost circuit, which can increase the voltage across a flying capacitor, reduce the probability of overcurrent in a third diode, and improve the reliability of the boost circuit.

[0005] In a first aspect, the present invention provides a control method for a boost circuit, wherein the boost circuit includes a first branch consisting of a first controllable switch and a second controllable switch connected in series, a second branch consisting of a first output capacitor and a second output capacitor connected in series, a flying capacitor and a third diode, wherein the first end of the flying capacitor is connected to the common point of the first controllable switch and the second controllable switch in the first branch, the second end is connected to the first end of the first branch through the first diode, and is connected to the second end of the second branch through the second diode; the anode of the first diode is connected to the first end of the first branch, and the cathode of the first diode is connected to the second end of the flying capacitor; the anode of the second diode is connected to the second end of the flying capacitor, and the cathode of the second diode is connected to the first end of the second branch; the third second diode is connected between the first end of the flying capacitor and the common point of the first output capacitor and the second output capacitor in the second branch. an anode of the third controllable switch connected to the first end of the flying capacitor, and a cathode of the third diode connected to a common point of the first output capacitor and the second output capacitor in the second branch; the control method comprises: calculating original duty cycles of the first controllable switch and the second controllable switch based on an error between a given value and an actual value of the output bus voltage; calculating a duty cycle offset based on an error between a given value and an actual value of the voltage across the flying capacitor; determining a target duty cycle of the first controllable switch as a difference between the original duty cycle of the first controllable switch and the duty cycle offset; determining a target duty cycle of the second controllable switch as a sum of the original duty cycle of the second controllable switch and the duty cycle offset; and adjusting the first controllable switch based on the target duty cycle of the first controllable switch and adjusting the second controllable switch based on the target duty cycle of the second controllable switch, so that an anode voltage of the third diode is less than or equal to a cathode voltage.

[0006] The present invention provides a control method for a boost circuit. The method controls the voltage across a flying capacitor to calculate a duty cycle offset. The duty cycle offset is used to adjust the duty cycles of two controllable switches. The duty cycle of the first controllable switch is reduced, and the duty cycle of the second controllable switch is increased. This increases the voltage across the flying capacitor Cfly, reduces the probability of overcurrent in the third diode D3, and improves the reliability of the boost circuit.

[0007] In one possible implementation, before calculating the duty cycle offset based on the error between the given value and the actual value of the voltage across the flying capacitor, the method further includes: determining a voltage offset of the voltage across the flying capacitor, where the voltage offset is the difference between the maximum value of the output bus voltage of the boost circuit when the output power is greater than the set power and the minimum value of the voltage across the flying capacitor when the output bus voltage of the boost circuit is greater than the set voltage; and determining the sum of half the given value of the output bus voltage and the voltage offset as the given value of the voltage across the flying capacitor.

[0008] In one possible implementation, before calculating the duty cycle offset based on the error between the given value and the actual value of the voltage across the flying capacitor, the method further includes: determining the sum of half the given value of the output bus voltage and the voltage offset as the minimum value of the adjustment interval corresponding to the given value of the voltage across the flying capacitor; wherein the voltage offset is the difference between the maximum value of the output bus voltage of the boost circuit when the output power is greater than the set power and the minimum value of the voltage across the flying capacitor when the output bus voltage of the boost circuit is greater than the set voltage; determining m times the given value of the output bus voltage as the maximum value of the adjustment interval of the given value of the voltage across the flying capacitor, wherein m1<m<1; m1 is the ratio of the minimum value of the adjustment interval to the given value of the output bus voltage; and dynamically adjusting the given value of the voltage across the flying capacitor based on the adjustment interval.

[0009] In one possible implementation, dynamically adjusting a given value of the voltage across the flying capacitor based on the adjustment interval includes: determining the given value of the voltage across the flying capacitor based on the following formula;

[0010]

[0011] Among them, U fl y R e f is the given value of the voltage across the flying capacitor, U fl ymax is the maximum value of the adjustment interval, U fl ym i n is the minimum value of the adjustment interval, t1 is the initial moment when the first controllable switch is turned on in each adjustment cycle, and t 2 is the initial moment when the first controllable switch is turned off in each adjustment cycle.

[0012] In one possible implementation, before calculating the duty cycle offset based on the error between the given value and the actual value of the voltage across the flying capacitor, the method further includes: obtaining the actual value of the output bus voltage and the actual value of the voltage across the third diode; and determining the sum of half the actual value of the output bus voltage and K times the actual value of the voltage across the third diode as the given value of the voltage across the flying capacitor; wherein K>0.

[0013] In one possible implementation, before calculating the duty cycle offset based on the error between the given value and the actual value of the voltage across the flying capacitor, the method further includes: obtaining the actual value of the voltage across the first output capacitor and the actual value of the voltage across the third diode; and determining the sum of the actual value of the voltage across the first output capacitor and K times the actual value of the voltage across the third diode as the given value of the voltage across the flying capacitor; wherein K>0.

[0014] In one possible implementation, the duty cycle offset is calculated based on the error between the given value and the actual value of the voltage across the flying capacitor, including: performing PI calculation based on the error between the given value and the actual value of the voltage across the flying capacitor to obtain a voltage deviation value; and determining the ratio of the voltage deviation value to the actual value of the output bus voltage as the duty cycle offset.

[0015] In a second aspect, an embodiment of the present invention provides a control device for a boost circuit, the boost circuit comprising a first branch consisting of a first controllable switch and a second controllable switch connected in series, a second branch consisting of a first output capacitor and a second output capacitor connected in series, a flying capacitor and a third diode, wherein the first end of the flying capacitor is connected to a common point of the first controllable switch and the second controllable switch in the first branch, the second end is connected to the first end of the first branch through the first diode, and is connected to the second end of the second branch through the second diode; the anode of the first diode is connected to the first end of the first branch, and the cathode of the first diode is connected to the second end of the flying capacitor; the anode of the second diode is connected to the second end of the flying capacitor, and the cathode of the second diode is connected to the first end of the second branch; a third diode is connected between the first end of the flying capacitor and the common point of the first output capacitor and the second output capacitor in the second branch; the anode of the third diode is connected to the first end of the flying capacitor , the cathode of the third diode is connected to the common point of the first output capacitor and the second output capacitor in the second branch; the control device includes: a communication module, used to obtain a given value and an actual value of the output bus voltage, and a given value and an actual value of the voltage across the flying capacitor; a processing module, used to calculate the original duty cycle of the first controllable switch and the second controllable switch based on the error between the given value and the actual value of the output bus voltage; calculate the duty cycle offset based on the error between the given value and the actual value of the voltage across the flying capacitor; determine the difference between the original duty cycle of the first controllable switch and the duty cycle offset as the target duty cycle of the first controllable switch; determine the sum of the original duty cycle of the second controllable switch and the duty cycle offset as the target duty cycle of the second controllable switch; adjust the first controllable switch based on the target duty cycle of the first controllable switch, and adjust the second controllable switch based on the target duty cycle of the second controllable switch, so that the anode voltage of the third diode is less than or equal to the cathode voltage.

[0016] In one possible implementation, the processing module is further used to determine a voltage offset of the voltage across the flying capacitor, where the voltage offset is the difference between the maximum value of the output bus voltage of the boost circuit when the output power is greater than the set power and the minimum value of the voltage across the flying capacitor when the output bus voltage of the boost circuit is greater than the set voltage; and the sum of half the given value of the output bus voltage and the voltage offset is determined as the given value of the voltage across the flying capacitor.

[0017] In one possible implementation, the processing module is further used to determine the sum of half of the given value of the output bus voltage and the voltage offset as the minimum value of the adjustment interval corresponding to the given value of the voltage across the flying capacitor; wherein the voltage offset is the difference between the maximum value of the output bus voltage of the boost circuit when the output power is greater than the set power and the minimum value of the voltage across the flying capacitor when the output bus voltage of the boost circuit is greater than the set voltage; m times the given value of the output bus voltage is determined as the maximum value of the adjustment interval of the given value of the voltage across the flying capacitor, wherein m1<m<1; m1 is the ratio of the minimum value of the adjustment interval to the given value of the output bus voltage; and based on the adjustment interval, dynamically adjust the given value of the voltage across the flying capacitor.

[0018] In a possible implementation, the processing module is specifically configured to determine a given value of the voltage across the flying capacitor based on the following formula:

[0019]

[0020] Among them, U fl y R e f is the given value of the voltage across the flying capacitor, U fl ymax is the maximum value of the adjustment interval, U fl ym i n is the minimum value of the adjustment interval, t1 is the initial moment when the first controllable switch is turned on in each adjustment cycle, and t 2 is the initial moment when the first controllable switch is turned off in each adjustment cycle.

[0021] In one possible implementation, the communication module is further used to obtain the actual value of the output bus voltage and the actual value of the voltage across the third diode; the processing module is further used to determine the sum of half the actual value of the output bus voltage and K times the actual value of the voltage across the third diode as the given value of the voltage across the flying capacitor; wherein K>0.

[0022] In one possible implementation, the communication module is further used to obtain an actual value of the voltage across the first output capacitor and an actual value of the voltage across the third diode; the processing module is further used to determine the sum of the actual value of the voltage across the first output capacitor and K times the actual value of the voltage across the third diode as a given value of the voltage across the flying capacitor; wherein K>0.

[0023] In one possible implementation, the processing module is specifically used to perform PI calculation based on the error between the given value and the actual value of the voltage across the flying capacitor to obtain a voltage deviation value; and the ratio of the voltage deviation value to the actual value of the output bus voltage is determined as the duty cycle offset.

[0024] In a third aspect, an embodiment of the present invention provides an electronic device, characterized in that the electronic device includes a memory and a processor, the memory stores a computer program, and the processor is used to call and run the computer program stored in the memory to perform the steps of the method described in the first aspect and any possible implementation method of the first aspect.

[0025] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores a computer program, and is characterized in that when the computer program is executed by a processor, it implements the steps of the method described in the first aspect and any possible implementation method of the first aspect.

[0026] The technical effects brought about by any implementation method of the above-mentioned second to fourth aspects can refer to the technical effects brought about by the corresponding implementation method of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 1 is a schematic structural diagram of a boost circuit provided by an embodiment of the present invention;

[0029] Figure 2 1 is a flow chart of a control method for a boost circuit provided by an embodiment of the present invention;

[0030] Figure 3 This is a flow chart of the control logic of a boost circuit provided by an embodiment of the present invention;

[0031] Figure 4 1 is a schematic structural diagram of a control device for a boost circuit provided by an embodiment of the present invention;

[0032] Figure 5 It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In the following description, specific details such as particular system structures and techniques are provided for purposes of illustration, not limitation, to facilitate a thorough understanding of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

[0034] In the description of the present invention, unless otherwise specified, “ / ” means “or”. For example, A / B can mean A or B. “And / or” in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, “at least one” and “a plurality of” refer to two or more. Words such as “first” and “second” do not limit the quantity and execution order, and words such as “first” and “second” do not necessarily limit them to be different.

[0035] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner to facilitate understanding.

[0036] Furthermore, the terms "including," "having," and any variations thereof, as used in the description of this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or modules is not limited to the listed steps or modules, but may optionally include other steps or modules not listed, or may optionally include other steps or modules inherent to the process, method, product, or apparatus.

[0037] In order to make the purpose, technical solutions and advantages of the present invention more clear, the following will be described through specific embodiments in conjunction with the accompanying drawings of the present invention.

[0038] Figure 1 A schematic structural diagram of a boost circuit provided by an embodiment of the present invention. Figure 1The boost circuit shown includes a first branch consisting of a first controllable switch and a second controllable switch connected in series, a second branch consisting of a first output capacitor and a second output capacitor connected in series, a flying capacitor, and a third diode. The first end of the flying capacitor is connected to the common point of the first and second controllable switches in the first branch, and the second end is connected to the first end of the first branch via a first diode. The anode of the first diode is connected to the first end of the first branch, and the cathode of the first diode is connected to the second end of the flying capacitor. The first end of the flying capacitor is connected to the second end of the second branch via a second diode. The anode of the second diode is connected to the second end of the flying capacitor, and the cathode of the second diode is connected to the first end of the second branch. A third diode is connected between the first end of the flying capacitor and the common point of the first and second output capacitors in the second branch. The anode of the third diode is connected to the first end of the flying capacitor, and the cathode is connected to the common point of the first and second output capacitors in the second branch. The first end of the first branch is connected to the positive terminal of the boost circuit's input via an inductor; the second end is connected to the negative terminal of the boost circuit's input and the negative terminal of the boost circuit, respectively. The second branch is connected in parallel between the positive electrode and the negative electrode of the output terminal.

[0039] Figure 2 The present invention provides a flow chart of a control method for a boost circuit according to an embodiment of the present invention. The control method is performed by a control device for the boost circuit and includes steps S101-S104.

[0040] S101 : Calculate original duty cycles of the first controllable switch and the second controllable switch based on an error between a given value and an actual value of an output bus voltage.

[0041] In some embodiments, as Figure 3 As shown, the control device can perform PI calculation based on the error between the given value UbusRef and the actual value Ubusfb of the output bus voltage to obtain the given value IboostRef of the boost circuit current. Thereafter, the control device can perform PI calculation based on the error between the given value IboostRef and the actual value Iboostfb of the inductor current to obtain the original duty cycle of the first controllable switch and the second controllable switch.

[0042] S102 : Calculate a duty cycle offset based on an error between a given value and an actual value of the voltage across the flying capacitor.

[0043] It should be noted that, without considering the output ripple of the boost circuit, the voltage across the flying capacitor is approximately equal to half the bus voltage. However, due to the existence of output ripple, the voltage across the flying capacitor must be greater than half the bus voltage to ensure that no current flows through the third diode, that is, the anode voltage of the third diode is less than or equal to the cathode voltage.

[0044] In some embodiments, the given value of the voltage across the flying capacitor can be a pre-set fixed value. That is, taking into account the output ripple, the given value of the voltage across the flying capacitor is greater than half of the maximum value of the output bus voltage. Exemplarily, the given value of the voltage across the flying capacitor can be m times the output bus voltage, where 0.5 < M < 0.6. For example, taking into account the output ripple, the given value of the voltage across the flying capacitor can be 0.52 times the output bus voltage.

[0045] Exemplarily, the control device may determine a voltage offset of the voltage across the flying capacitor, and determine the given value of the voltage across the flying capacitor as the sum of half the given value of the output bus voltage and the voltage offset. The voltage offset is the difference between the maximum value of the output bus voltage when the output power of the boost circuit is greater than the set power and the minimum value of the voltage across the flying capacitor when the output bus voltage of the boost circuit is greater than the set voltage.

[0046] It should be noted that, in extreme cases, when the boost circuit is fully loaded, the output ripple of the output bus is the largest. The maximum value of the output bus voltage of the boost circuit when the output power is greater than the set power can represent the maximum voltage value that the output bus can reach. When the output bus voltage is the highest, the duty cycle of the first controllable switch is the largest, and the ripple of the voltage across the flying capacitor is the largest. The minimum value of the voltage across the flying capacitor when the output bus voltage of the boost circuit is greater than the set voltage can represent the minimum voltage value that can be reached across the flying capacitor. By controlling the minimum voltage value that can be reached across the flying capacitor to be greater than the maximum voltage value that can be reached by the output bus, the anode voltage of the third diode can be less than or equal to the cathode voltage.

[0047] In other embodiments, the control device may dynamically adjust a given value of the voltage across the flying capacitor within a preset adjustment range.

[0048] Exemplarily, the control device can determine the sum of half of the given value of the output bus voltage and the voltage offset as the minimum value of the adjustment interval corresponding to the given value of the voltage across the flying capacitor; determine m times the given value of the output bus voltage as the maximum value of the adjustment interval of the given value of the voltage across the flying capacitor, and dynamically adjust the given value of the voltage across the flying capacitor based on the adjustment interval.

[0049] Among them, the voltage offset is the difference between the maximum value of the output bus voltage of the boost circuit when the output power is greater than the set power and the minimum value of the voltage across the flying capacitor when the output bus voltage of the boost circuit is greater than the set voltage; m1<m<1; m1 is the ratio of the minimum value of the adjustment interval to the given value of the output bus voltage.

[0050] It should be noted that the control device may dynamically adjust the given value of the voltage across the flying capacitor based on a linear function, or the control device may dynamically adjust the given value of the voltage across the flying capacitor based on a parabolic function.

[0051] Exemplarily, the control device may determine a given value of the voltage across the flying capacitor based on the following formula.

[0052]

[0053] Among them, U fl y R e f is the given value of the voltage across the flying capacitor, U fl ymax is the maximum value of the adjustment interval, U fl ym i n is the minimum value of the adjustment interval, t1 is the initial moment when the first controllable switch is turned on in each adjustment cycle, and t 2 is the initial moment when the first controllable switch is turned off in each adjustment cycle.

[0054] In this way, the embodiment of the present invention can realize dynamic adjustment of the given value of the voltage across the flying capacitor, ensure that the voltage across the flying capacitor is higher than the half-bus voltage, ensure that the third diode does not bear the forward voltage, reduce the probability of overcurrent in the third diode, and improve the reliability of the boost circuit. In the initial stage of the first controllable switch being turned on, the voltage across the flying capacitor is adjusted with a larger given value to speed up the boost speed of the voltage across the flying capacitor. After the voltage across the flying capacitor is increased, the voltage across the flying capacitor is adjusted with the minimum value of the adjustment interval as the given value to ensure that the third diode does not bear the forward voltage.

[0055] In other embodiments, the control device may dynamically adjust a given value of the voltage across the flying capacitor based on the voltage across the third diode.

[0056] Exemplarily, the control device can obtain the actual value of the output bus voltage and the actual value of the voltage across the third diode; and determine the sum of half the actual value of the output bus voltage and K times the actual value of the voltage across the third diode as the given value of the voltage across the flying capacitor; wherein K>0.

[0057] In another exemplary embodiment, the control device can obtain the actual value of the voltage across the first output capacitor and the actual value of the voltage across the third diode; and determine the sum of the actual value of the voltage across the first output capacitor and K times the actual value of the voltage across the third diode as the given value of the voltage across the flying capacitor; wherein K>0.

[0058] In this way, the embodiment of the present invention can dynamically adjust the given value of the voltage across the flying capacitor based on the voltage across the third diode. On the one hand, it can ensure that the voltage across the flying capacitor is higher than the half-bus voltage, ensure that the third diode is not subjected to forward voltage, reduce the probability of overcurrent in the third diode, and improve the reliability of the boost circuit. On the other hand, the greater the difference between the voltage across the flying capacitor and the voltage across the first capacitor, the greater the reverse peak of the first controllable switch Q1, resulting in a shortened life of the first controllable switch Q1. Therefore, while ensuring that the third diode is not conducting, the voltage difference across the third diode should be minimized. The embodiment of the present invention dynamically adjusts the given value of the voltage across the flying capacitor based on the voltage across the three diodes, which can take into account the reliability of the third diode and the first controllable switch at the same time, and ensure the reliable operation of the boost circuit.

[0059] As a possible implementation, Figure 3 As shown, the control device can perform PI calculation based on the error between the given value and the actual value of the voltage across the flying capacitor to obtain a voltage deviation value; and determine the ratio of the voltage deviation value to the actual value of the output bus voltage as the duty cycle offset.

[0060] S103 : Determine the difference between the original duty cycle of the first controllable switch and the duty cycle offset as the target duty cycle of the first controllable switch; and determine the sum of the original duty cycle of the second controllable switch and the duty cycle offset as the target duty cycle of the second controllable switch.

[0061] S104 , adjusting the first controllable switch based on the target duty cycle of the first controllable switch, and adjusting the second controllable switch based on the target duty cycle of the second controllable switch, so that the anode voltage of the third diode is less than or equal to the cathode voltage.

[0062] The present invention provides a control method for a boost circuit. The method controls the voltage across a flying capacitor to calculate a duty cycle offset. The duty cycle offset is used to adjust the duty cycles of two controllable switches. The duty cycle of the first controllable switch is reduced, and the duty cycle of the second controllable switch is increased. This increases the voltage across the flying capacitor Cfly, reduces the probability of overcurrent in the third diode D3, and improves the reliability of the boost circuit.

[0063] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0064] The following are device embodiments of the present invention. For details not fully described therein, reference may be made to the corresponding method embodiments described above.

[0065] Figure 4FIG. 3 is a schematic diagram showing the structure of a control device for a voltage boost circuit according to an embodiment of the present invention. The control device 300 for a voltage boost circuit includes a communication module 301 and a processing module 302 .

[0066] The communication module 301 is used to obtain the given value and actual value of the output bus voltage and the given value and actual value of the voltage across the flying capacitor.

[0067] The processing module 302 is configured to calculate the original duty cycles of the first controllable switch and the second controllable switch based on the error between the given value and the actual value of the output bus voltage; calculate the duty cycle offset based on the error between the given value and the actual value of the voltage across the flying capacitor; determine the difference between the original duty cycle of the first controllable switch and the duty cycle offset as the target duty cycle of the first controllable switch; determine the sum of the original duty cycle of the second controllable switch and the duty cycle offset as the target duty cycle of the second controllable switch; and adjust the first controllable switch based on the target duty cycle of the first controllable switch and adjust the second controllable switch based on the target duty cycle of the second controllable switch so that the anode voltage of the third diode is less than or equal to the cathode voltage.

[0068] In one possible implementation, the processing module 302 is further configured to determine a voltage offset of the voltage across the flying capacitor, where the voltage offset is the difference between a maximum value of the output bus voltage of the boost circuit when the output power is greater than a set power and a minimum value of the voltage across the flying capacitor when the output bus voltage of the boost circuit is greater than the set voltage; and the sum of half a given value of the output bus voltage and the voltage offset is determined as the given value of the voltage across the flying capacitor.

[0069] In one possible implementation, the processing module 302 is further used to determine the sum of half of the given value of the output bus voltage and the voltage offset as the minimum value of the adjustment interval corresponding to the given value of the voltage across the flying capacitor; wherein the voltage offset is the difference between the maximum value of the output bus voltage of the boost circuit when the output power is greater than the set power and the minimum value of the voltage across the flying capacitor when the output bus voltage of the boost circuit is greater than the set voltage; m times the given value of the output bus voltage is determined as the maximum value of the adjustment interval of the given value of the voltage across the flying capacitor, wherein m1<m<1; m1 is the ratio of the minimum value of the adjustment interval to the given value of the output bus voltage; and based on the adjustment interval, dynamically adjust the given value of the voltage across the flying capacitor.

[0070] In a possible implementation, the processing module 302 is specifically configured to determine a given value of the voltage across the flying capacitor based on the following formula.

[0071]

[0072] Among them, U fly R e f is the given value of the voltage across the flying capacitor, U fl ymax is the maximum value of the adjustment interval, U fl ym i n is the minimum value of the adjustment interval, t1 is the initial moment when the first controllable switch is turned on in each adjustment cycle, and t 2 is the initial moment when the first controllable switch is turned off in each adjustment cycle.

[0073] In one possible implementation, the communication module 301 is further used to obtain the actual value of the output bus voltage and the actual value of the voltage across the third diode; the processing module 302 is further used to determine the sum of half the actual value of the output bus voltage and K times the actual value of the voltage across the third diode as the given value of the voltage across the flying capacitor; wherein K>0.

[0074] In one possible implementation, the communication module 301 is further used to obtain an actual value of the voltage across the first output capacitor and an actual value of the voltage across the third diode; the processing module 302 is further used to determine the sum of the actual value of the voltage across the first output capacitor and K times the actual value of the voltage across the third diode as a given value of the voltage across the flying capacitor; wherein K>0.

[0075] In one possible implementation, the processing module 302 is further used to perform PI calculation based on the error between the given value and the actual value of the voltage across the flying capacitor to obtain a voltage deviation value; and determine the ratio of the voltage deviation value to the actual value of the output bus voltage as the duty cycle offset.

[0076] Figure 5 Schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 5 As shown, the electronic device 400 of this embodiment includes: a processor 401, a memory 402, and a computer program 403 stored in the memory 402 and executable on the processor 401. When the processor 401 executes the computer program 403, the steps in the above-mentioned method embodiments are implemented, for example Figure 2 Alternatively, when the processor 401 executes the computer program 403, the functions of the modules / units in the above-mentioned device embodiments are realized, for example, Figure 4 The functions of the communication module 301 and the processing module 302 are shown.

[0077] Exemplarily, the computer program 403 may be divided into one or more modules / units, which are stored in the memory 402 and executed by the processor 401 to implement the present invention. The one or more modules / units may be a series of computer program instruction segments capable of implementing specific functions, which are used to describe the execution process of the computer program 403 in the electronic device 400. For example, the computer program 403 may be divided into Figure 4 The communication module 301 and the processing module 302 are shown.

[0078] The processor 401 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0079] The memory 402 may be an internal storage unit of the electronic device 400, such as a hard disk or memory of the electronic device 400. The memory 402 may also be an external storage device of the electronic device 400, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 400. Furthermore, the memory 402 may include both an internal storage unit of the electronic device 400 and an external storage device. The memory 402 is used to store the computer program and other programs and data required by the terminal. The memory 402 may also be used to temporarily store data that has been output or is about to be output.

[0080] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0081] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0082] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0083] In the embodiments provided by the present invention, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of devices or units, and can be electrical, mechanical, or other forms.

[0084] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0085] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0086] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the process in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device that can carry the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc.

[0087] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A control method for a boost circuit, characterized in that: The boost circuit includes a first branch consisting of a first controllable switch and a second controllable switch connected in series, a second branch consisting of a first output capacitor and a second output capacitor connected in series, a flying capacitor and a third diode, wherein the first end of the flying capacitor is connected to the common point of the first controllable switch and the second controllable switch in the first branch, the second end is connected to the first end of the first branch through the first diode, and is connected to the first end of the second branch through the second diode; the anode of the first diode is connected to the first end of the first branch, and the cathode of the first diode is connected to the second end of the flying capacitor; the anode of the second diode is connected to the second end of the flying capacitor, and the cathode of the second diode is connected to the first end of the second branch; the third diode is connected between the first end of the flying capacitor and the common point of the first output capacitor and the second output capacitor in the second branch; the anode of the third diode is connected to the first end of the flying capacitor, and the cathode of the third diode is connected to the common point of the first output capacitor and the second output capacitor in the second branch; the first end of the second branch is the positive output terminal of the boost circuit; The control method includes: Calculating original duty cycles of the first controllable switch and the second controllable switch based on an error between a given value and an actual value of the output bus voltage; Calculating a duty cycle offset based on an error between a given value and an actual value of the voltage across the flying capacitor; Determine the difference between the original duty cycle of the first controllable switch and the duty cycle offset as the target duty cycle of the first controllable switch; determine the sum of the original duty cycle of the second controllable switch and the duty cycle offset as the target duty cycle of the second controllable switch; adjusting the first controllable switch based on a target duty cycle of the first controllable switch, and adjusting the second controllable switch based on a target duty cycle of the second controllable switch, so that an anode voltage of the third diode is less than or equal to a cathode voltage; The step of calculating the duty cycle offset based on the error between the given value and the actual value of the voltage across the flying capacitor comprises: performing a PI calculation based on the error between the given value and the actual value of the voltage across the flying capacitor to obtain a voltage deviation value; and determining the ratio of the voltage deviation value to the actual value of the output bus voltage as the duty cycle offset; Before calculating the duty cycle offset based on the error between the given value and the actual value of the voltage across the flying capacitor, the method further includes: determining the sum of half of the given value of the output bus voltage and the voltage offset as the minimum value of the adjustment interval corresponding to the given value of the voltage across the flying capacitor; the voltage offset is the difference between the maximum value of the output bus voltage when the output power of the boost circuit is greater than the set power and the minimum value of the voltage across the flying capacitor when the output bus voltage of the boost circuit is greater than the set voltage; determining m times the given value of the output bus voltage as the maximum value of the adjustment interval of the given value of the voltage across the flying capacitor, m1<m<1; m1 is the ratio of the minimum value of the adjustment interval to the given value of the output bus voltage; dynamically adjusting the given value of the voltage across the flying capacitor based on the adjustment interval, including: determining the given value of the voltage across the flying capacitor based on the following formula; Among them, U flyRef is the given value of the voltage across the flying capacitor, U flymax is the maximum value of the adjustment interval, U flymin is the minimum value of the adjustment interval, t1 is the initial moment when the first controllable switch is turned on in each adjustment period, and t2 is the initial moment when the first controllable switch is turned off in each adjustment period.

2. The control method of the boost circuit according to claim 1, wherein: Before calculating the duty cycle offset based on the error between the given value and the actual value of the voltage across the flying capacitor, the method further includes: determining a voltage offset of the voltage across the flying capacitor, the voltage offset being a difference between a maximum value of the output bus voltage when the output power of the boost circuit is greater than a set power and a minimum value of the voltage across the flying capacitor when the output bus voltage of the boost circuit is greater than the set voltage; The sum of half of the given value of the output bus voltage and the voltage offset is determined as the given value of the voltage across the flying capacitor.

3. The control method of the boost circuit according to claim 1, wherein: Before calculating the duty cycle offset based on the error between the given value and the actual value of the voltage across the flying capacitor, the method further includes: Obtaining the actual value of the output bus voltage and the actual value of the voltage across the third diode; The sum of half the actual value of the output bus voltage and K times the actual value of the voltage across the third diode is determined as the given value of the voltage across the flying capacitor; wherein K>0.

4. The control method of the boost circuit according to claim 1, wherein: Before calculating the duty cycle offset based on the error between the given value and the actual value of the voltage across the flying capacitor, the method further includes: Obtaining an actual value of a voltage across the first output capacitor and an actual value of a voltage across the third diode; The sum of the actual value of the voltage across the first output capacitor and K times the actual value of the voltage across the third diode is determined as the given value of the voltage across the flying capacitor; wherein K>0.

5. A control device for a boost circuit, characterized in that: The boost circuit includes a first branch consisting of a first controllable switch and a second controllable switch connected in series, a second branch consisting of a first output capacitor and a second output capacitor connected in series, a flying capacitor and a third diode, wherein the first end of the flying capacitor is connected to the common point of the first controllable switch and the second controllable switch in the first branch, the second end is connected to the first end of the first branch through the first diode, and is connected to the first end of the second branch through the second diode; the anode of the first diode is connected to the first end of the first branch, and the cathode of the first diode is connected to the second end of the flying capacitor; the anode of the second diode is connected to the second end of the flying capacitor, and the cathode of the second diode is connected to the first end of the second branch; the third diode is connected between the first end of the flying capacitor and the common point of the first output capacitor and the second output capacitor in the second branch; the anode of the third diode is connected to the first end of the flying capacitor, and the cathode of the third diode is connected to the common point of the first output capacitor and the second output capacitor in the second branch; the first end of the second branch is the positive output terminal of the boost circuit; The control device comprises: A communication module is used to obtain a given value and an actual value of the output bus voltage and a given value and an actual value of the voltage across the flying capacitor; a processing module, configured to calculate original duty cycles of the first controllable switch and the second controllable switch based on an error between a given value and an actual value of the output bus voltage; calculate a duty cycle offset based on an error between a given value and an actual value of the voltage across the flying capacitor; determine a difference between the original duty cycle of the first controllable switch and the duty cycle offset as a target duty cycle of the first controllable switch; determine a sum of the original duty cycle of the second controllable switch and the duty cycle offset as a target duty cycle of the second controllable switch; adjust the first controllable switch based on the target duty cycle of the first controllable switch, and adjust the second controllable switch based on the target duty cycle of the second controllable switch, so that an anode voltage of the third diode is less than or equal to a cathode voltage; The processing module is specifically configured to perform PI calculation based on an error between a given value and an actual value of the voltage across the flying capacitor to obtain a voltage deviation value; and determine a ratio of the voltage deviation value to the actual value of the output bus voltage as the duty cycle offset; The processing module is further configured to determine the sum of half the given value of the output bus voltage and the voltage offset as the minimum value of the adjustment interval corresponding to the given value of the voltage across the flying capacitor; the voltage offset is the difference between the maximum value of the output bus voltage when the output power of the boost circuit is greater than the set power and the minimum value of the voltage across the flying capacitor when the output bus voltage of the boost circuit is greater than the set voltage; m times the given value of the output bus voltage is determined as the maximum value of the adjustment interval of the given value of the voltage across the flying capacitor, m1<m<1; m1 is the ratio of the minimum value of the adjustment interval to the given value of the output bus voltage; based on the adjustment interval, dynamically adjusting the given value of the voltage across the flying capacitor, comprising: determining the given value of the voltage across the flying capacitor based on the following formula; Among them, U flyRef is the given value of the voltage across the flying capacitor, U flymax is the maximum value of the adjustment interval, U flymin is the minimum value of the adjustment interval, t1 is the initial moment when the first controllable switch is turned on in each adjustment period, and t2 is the initial moment when the first controllable switch is turned off in each adjustment period.

6. An electronic device, characterized in that: The electronic device includes a memory and a processor, wherein the memory stores a computer program, and the processor is configured to call and run the computer program stored in the memory to execute the method according to any one of claims 1 to 4.

7. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

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