Constant current limiting chip, secondary side feedback current limiting circuit of QR mode and control method thereof

Abstract

The application provides a constant current limiting chip, a QR mode secondary side feedback current limiting circuit and a control method thereof, and aims to solve the technical problem that the existing QR working mode can only provide different input voltages and overload protection point compensation methods under different working modes, but cannot solve the overload protection point compensation method under different output voltages. The constant current limiting chip comprises a demagnetization detection module, a PWM main control module, a driving module, a parameter operation module and a comparator. The driving module is used for sending the transformer primary side power tube on time ton into the demagnetization detection module and the parameter operation module. The demagnetization detection module is used for sending the transformer demagnetization time tdemg into the parameter operation module. The parameter operation module is used for obtaining the primary side periodic overcurrent protection reference voltage Vth_oc and sending the primary side periodic overcurrent protection reference voltage Vth_oc into the comparator. After comparison, the primary side periodic overcurrent protection reference voltage Vth_oc is input into the PWM main control module for control. The operation formula of Vth_oc is: wherein, Vref is a reference voltage.

Description

Technical Field

[0001] This invention relates to a secondary-side feedback current limiting circuit, and more particularly to a constant current limiting chip, a QR mode secondary-side feedback current limiting circuit, and its control method. Background Technology

[0002] Currently, in the fast charging field, such as adapters and mobile phone chargers, power supply solutions mainly adopt constant current limiting schemes with primary-side feedback and secondary-side feedback, but these constant current limiting are all done in continuous current mode (CCM). With the rapid development of the fast charging field and user demand, there is a need for power supply solutions that are small in size and compatible with multiple voltage outputs. Therefore, many QR operating mode (valley conduction isolation mode, or critical conduction mode) solutions have emerged in the market. The system circuit diagram is shown below. Figure 1 As shown, however, the overload protection points of this solution vary greatly when the input voltage or output voltage is different. Most solutions use fast charging protocol chips to limit the current in the secondary side; while some solutions do not do this at all, resulting in a large difference in the overload protection points when the output voltage is different.

[0003] Chinese patent publication number CN109818507A proposes an "Overcurrent Protection Compensation Circuit and Method and Flyback Circuit," which states that "the compensation method of this invention can adaptively obtain a better OLP compensation curve in DCM and CCM modes; it can make the compensated OLP curve smoother, solving the regulation rate problem of the chip under different inductor applications. In different inductor applications, regardless of the input voltage position of the system's critical mode setting, the system can have a good OLP compensation curve." This patent proposes overload protection point compensation methods for different input voltages and different operating modes, but it does not solve the overload protection point compensation method under different output voltages. Summary of the Invention

[0004] The purpose of this invention is to solve the technical problem that existing QR mode overload protection point compensation methods can only solve the problem of different input voltages and different operating modes, but cannot solve the problem of overload protection point compensation methods under different output voltages. The invention provides a constant current limiting chip, a secondary side feedback current limiting circuit in QR mode and its control method.

[0005] To achieve the above objectives, the technical solution provided by this invention is as follows:

[0006] A constant current limiting chip is provided, equipped with VCC, Gate, CS, Zcd, FB, and GND pins. Its unique feature lies in the inclusion of a demagnetization detection module, a PWM main control module, a drive module, a parameter calculation module, and a comparator CMP. One input of the PWM main control module is connected to the VCC pin, and its output is connected sequentially to the drive module and the Gate pin. The drive module sends the on-time ton of the transformer primary-side power transistor to both the demagnetization detection module and the parameter calculation module. One input of the demagnetization detection module is connected to the Zcd pin, and sends the transformer demagnetization time tdemg to the parameter calculation module. The parameter calculation module calculates the primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc based on the transformer demagnetization time tdemg and the transformer primary-side power transistor on-time ton, and sends it to one input of the comparator CMP. The calculation formula for the primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc by the parameter calculation module is as follows:

[0007]

[0008] In the formula, Vref is the reference voltage;

[0009] The other input of the comparator CMP is connected to the CS pin, and its output is connected to the other input of the PWM main control module.

[0010] Furthermore, the parameter calculation module includes a mirror unit, a pulse signal source unit, and a switched filter capacitor unit;

[0011] The pulse signal source unit is used to generate a pulse signal tsinL by performing logical operations on the on-time ton of the transformer primary power transistor and the demagnetization time tdemg of the transformer, so as to provide a control signal for the mirror unit; at the same time, the transformer demagnetization time tdemg is used to generate pulse signals tsampH and tsampL by performing logical operations, so as to provide a control signal for the switched filter capacitor unit.

[0012] The mirror unit is used to obtain the current within the transformer primary power transistor conduction time ton and the transformer demagnetization time tdemg by passing the reference voltage Vref through the mirror and combining it with the pulse signal tsinL; to obtain the current within the transformer demagnetization time tdemg by passing the feedback primary overcurrent protection reference voltage Vth_oc through the mirror; and to generate the ramp voltage at the same time.

[0013] The switched filter capacitor unit is used to generate the primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc from the ramp voltage according to the pulse signals tsampH and tsampL, and feed it back to the mirror unit.

[0014] Furthermore, the mirror unit includes a first operational amplifier OP1, a first NMOS transistor N1, a first PMOS transistor P1, a second NMOS transistor N2, a second PMOS transistor P2, a first resistor R1, a first capacitor C1, a second operational amplifier OP2, a third NMOS transistor N3, a third PMOS transistor P3, a fourth PMOS transistor P4, a second resistor R2, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6;

[0015] The positive input of the first operational amplifier OP1 is used to receive the reference voltage signal Vref. Its negative input is connected to the source of the first NMOS transistor N1 and one end of the first resistor R1. The output of the first operational amplifier OP1 is connected to the gate of the first NMOS transistor N1. The drain of the first NMOS transistor N1 is connected to the drain and gate of the first PMOS transistor P1. The gate of the first PMOS transistor P1 is connected to the gate of the second PMOS transistor P2. The drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2. The gate of the second NMOS transistor N2 is connected to the pulse signal source unit, and its source is connected to one end of the first capacitor C1, the drain of the sixth NMOS transistor N6, and the switched filter capacitor unit. The positive input of the second operational amplifier OP2 is used to receive the feedback primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc. Its negative input is connected to the third NMOS transistor. The source of N3 and one end of the second resistor R2 are connected to the output of the second operational amplifier OP2, which is connected to the gate of the third NMOS transistor N3. The drain of the third NMOS transistor N3 is connected to the drain and gate of the third PMOS transistor P3 and the gate of the fourth PMOS transistor P4. The drain of the fourth PMOS transistor P4 is connected to the drain and gate of the fourth NMOS transistor N4 and the gate of the fifth NMOS transistor N5. The drain of the fifth NMOS transistor N5 is connected to the source of the sixth NMOS transistor N6. The gate of the sixth NMOS transistor N6 is used to receive the transformer demagnetization time tdemg. The sources of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, and the fourth PMOS transistor P4 are all connected to the internal power supply. The other ends of the first capacitor C1, the first resistor R1, the second resistor R2, and the sources of the fourth NMOS transistor N4 and the fifth NMOS transistor N5 are all grounded.

[0016] Furthermore, the pulse signal source unit is used to provide control signals to the switched capacitor, and includes a logic OR gate NOR1, a first logic NOT gate INV1, a second logic NOT gate INV2, a third logic NOT gate INV3, a fourth logic NOT gate INV4, a fifth logic NOT gate INV5, a logic AND gate AND1, a third resistor R3, and a second capacitor C2.

[0017] The two inputs of the logic OR gate NOR1 are used to receive the on-time ton of the transformer primary power transistor and the demagnetization time tdemg of the transformer, respectively. Its output is connected to the input of the first logic NOT gate inv1, and the output of the first logic NOT gate inv1 is connected to the gate of the second NMOS transistor N2.

[0018] The input of the second NOT gate inv2 is used to receive the transformer demagnetization time tdemg. Its output is connected to the input of the third NOT gate inv3 and one input of the AND gate and1. The output of the third NOT gate inv3 is connected to one end of the third resistor R3. The other end of the third resistor is connected to one end of the second capacitor C2 and the input of the fourth NOT gate inv4. The output of the fourth NOT gate inv4 is connected to the other input of the AND gate and1. The output of the AND gate and1 is connected to the input of the fifth NOT gate inv5 and the switched filter capacitor unit. The output of the fifth NOT gate inv5 is connected to the switched filter capacitor unit. The other end of the second capacitor C2 is grounded.

[0019] Furthermore, the switched filter capacitor unit includes a fifth PMOS transistor P5, a seventh NMOS transistor N7, a sixth PMOS transistor P6, an eighth NMOS transistor N8, a third capacitor C3, and a fourth capacitor C4.

[0020] The gates of the seventh NMOS transistor N7 and the sixth PMOS transistor P6 are both connected to the output of the AND gate AND1. The gates of the fifth PMOS transistor P5 and the eighth NMOS transistor N8 are both connected to the output of the fifth NOT gate INV5. The drain of the seventh NMOS transistor N7 is connected to the drain of the fifth PMOS transistor P5, the source of the second NMOS transistor N2, and the drain of the sixth NMOS transistor N6. Its source is connected to the source of the fifth PMOS transistor P5, the drain of the sixth PMOS transistor P6, the drain of the eighth NMOS transistor N8, and one end of the third capacitor C3. The source of the sixth PMOS transistor P6 is connected to the source of the eighth NMOS transistor N8, one end of the fourth capacitor C4, and the output. The other ends of the third capacitor C3 and the fourth capacitor C4 are both grounded.

[0021] The present invention also provides a secondary-side feedback current limiting circuit in QR mode, which is characterized in that it includes the above-mentioned constant current limiting chip, detection circuit, rectifier circuit, transformer unit, output module, ninth NMOS transistor N9 and primary-side current limiting resistor Rcs; the transformer unit includes a primary-side winding disposed on the primary side, a secondary-side winding disposed on the secondary side and an auxiliary winding.

[0022] The detection circuit includes a fourth resistor R4, a fifth resistor R5, and a diode D1;

[0023] One end of the auxiliary winding is grounded, and the other end is connected in sequence to diode D1 and the VCC pin of the constant current limiting chip, which is used to send the auxiliary voltage Vaux into the PWM main control module 2 to provide power; the fourth resistor R4 and the fifth resistor R5 are connected in series to the two ends of the auxiliary winding, and the connection point of the fourth resistor R4 and the fifth resistor R5 is connected to the Zcd pin of the constant current limiting chip. The demagnetization detection module 1 samples the transformer demagnetization signal according to the voltage division signal of the fifth resistor R5.

[0024] The rectifier circuit is connected in sequence to the primary winding of the transformer, the ninth NMOS transistor N9, and the primary current limiting resistor Rcs; the gate of the ninth NMOS transistor N9 is connected to the Gate pin of the constant current limiting chip to control the primary current conduction and cutoff. When the primary side is on, the transformer is magnetized; one end of the primary current limiting resistor Rcs is connected to the source of the ninth NMOS transistor N9 and the CS pin of the constant current limiting chip, and the other end is grounded to detect the primary current.

[0025] The output terminal of the secondary winding is connected to the input terminal of the output module, and one of the output terminals of the output module is connected to the FB pin of the constant current limiting chip to provide feedback on the output voltage and load status of the output module.

[0026] Based on the aforementioned QR mode secondary-side feedback current limiting circuit, this invention also provides a control method for the QR mode secondary-side feedback current limiting circuit, characterized by the following steps:

[0027] 1. Calculate the primary side cycle-by-cycle overcurrent protection reference voltage Vth_oc based on the transformer demagnetization time tdemg and the transformer primary power transistor conduction time ton;

[0028] 2. Based on the obtained primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc, control the output current overload protection point Io_olp to remain constant.

[0029] Further, in step 2], based on the obtained primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc, the output current overload protection point Io_olp is controlled to remain constant as follows:

[0030] A reference voltage Vref is set inside the constant current limiting chip, so that...

[0031]

[0032] The output current overload protection point Io_olp is kept constant by the following formula:

[0033]

[0034] Where Rcs is the primary current-limiting resistor and n is the primary-secondary turns ratio of the transformer.

[0035] The advantages of this invention compared to the prior art are as follows:

[0036] 1. The present invention provides a constant current limiting chip, which is equipped with a parameter calculation module. After inputting the conduction time ton of the power transistor on the primary side of the transformer and the demagnetization time tdemg of the transformer into the parameter calculation module for relevant calculation, the chip outputs the primary side cycle-by-cycle overcurrent protection reference voltage Vth_oc. This can control the output current overload protection point Io_olp to remain constant, and it can be applied to various different working conditions, thus having a wider range of applications.

[0037] 2. The present invention provides a secondary-side feedback current limiting circuit in QR mode, which uses a constant current limiting chip of the present invention to perform constant current limiting in QR mode. Compared with the traditional overload protection point compensation method that only targets different input voltage operating modes, the present invention, in addition to compensating for the output current overload protection point Io_olp under different input voltages and different operating modes, also ensures that the output current overload protection point Io_olp remains constant under different output voltage operating modes, thus achieving the purpose of constant current limiting.

[0038] 3. The QR mode secondary feedback current limiting circuit control method provided by this invention ensures that the output current overload protection point Io_olp remains constant under different input voltages, different inductance values ​​and different output voltages, and has high constant current limiting efficiency and good effect. Attached Figure Description

[0039] Figure 1 A schematic diagram of the secondary-side feedback current limiting circuit in the existing QR mode;

[0040] Figure 2 This is a schematic diagram of an embodiment of a QR mode secondary-side feedback current limiting circuit according to the present invention;

[0041] Figure 3 This is a circuit diagram of the parameter calculation module in an embodiment of the present invention;

[0042] Figure 4 This is a waveform diagram of the operation in an embodiment of the present invention.

[0043] The specific labeling in the attached diagram is as follows:

[0044] 1-Demagnetization detection module; 2-PWM main control module; 3-Drive module; 4-Parameter calculation module. Detailed Implementation

[0045] To make the advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] The design concept of this invention is as follows: Based on the critical conduction (QR) mode, the primary side overcurrent protection reference voltage Vth_oc is calculated by utilizing the transformer demagnetization time tdemg and the primary power transistor conduction time (transformer magnetization time) ton. This voltage limits the output current overload protection point Io_olp to remain constant, ensuring that the output current overload protection point Io_olp does not change with variations in inductance, input voltage, and output voltage. This guarantees that the output current overload protection point Io_olp remains consistent under different conditions, achieving the purpose of constant current limiting.

[0047] The present invention provides a constant current limiting chip, which is provided with VCC pin, Gate pin, CS pin, Zcd pin, FB pin and GND pin; the constant current limiting chip includes a demagnetization detection module 1, a PWM main control module 2, a drive module 3, a parameter calculation module 4 and a comparator CMP. One input terminal of the PWM main control module 2 is connected to the VCC pin, and its output terminal is connected to the drive module 3 and the Gate pin in sequence. The other output terminal of the drive module 3 is connected to one input terminal of the demagnetization detection module 1 and one input terminal of the parameter calculation module 4, respectively, to send the on-time ton of the transformer primary power transistor to the demagnetization detection module 1 and the parameter calculation module 4, respectively. The other input terminal of the demagnetization detection module 1 is connected to the Zcd pin, and its output terminal is connected to the other input terminal of the parameter calculation module 4, to send the transformer demagnetization time tdemg to the parameter calculation module 4. The output terminal of the parameter calculation module 4 is connected to one input terminal of the comparator CMP, to send the output primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc to the comparator CMP. The other input terminal of the comparator CMP is connected to the CS pin, and its output terminal is connected to the other input terminal of the PWM main control module 2.

[0048] Among them, the demagnetization detection module 1, the PWM main control module 2, and the drive module 3 are all implemented using relevant modules from existing technologies. The parameter calculation module 4 is the core module of this invention, such as... Figure 3 As shown, it includes a mirror unit, a pulse signal source unit, and a switched filter capacitor unit.

[0049] The mirror unit is used to obtain the current during the on-time ton and demagnetization time tdemg of the transformer primary power transistor by mirroring the reference voltage Vref and combining it with the pulse signal tsinL; to obtain the current during the demagnetization time tdemg of the transformer by mirroring the feedback primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc; and to generate a ramp voltage. It includes a first operational amplifier OP1, a first NMOS transistor N1, a first PMOS transistor P1, a second NMOS transistor N2, a second PMOS transistor P2, a first resistor R1, a first capacitor C1, a second operational amplifier OP2, a third NMOS transistor N3, a third PMOS transistor P3, a fourth PMOS transistor P4, a second resistor R2, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6, where r is the resistance value of the first resistor R1 and the second resistor R2. The pulse signal source unit is used to generate a pulse signal tsinL by performing logical operations on the on-time ton of the transformer primary-side power transistor and the transformer demagnetization time tdemg, providing a control signal for the mirror unit; simultaneously, it generates pulse signals tsampH and tsampL by performing logical operations on the transformer demagnetization time tdemg, providing a control signal for the switched filter capacitor unit; it includes a logic OR gate nor1, a first logic NOT gate inv1, a second logic NOT gate inv2, a third logic NOT gate inv3, a fourth logic NOT gate inv4, a fifth logic NOT gate inv5, a logic AND gate and1, a third resistor R3, and a second capacitor C2; the switched filter capacitor unit is used to generate a primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc based on the pulse signals tsampH and tsampL, and feeds it back to the mirror unit; it includes a fifth PMOS transistor P5, a seventh NMOS transistor N7, a sixth PMOS transistor P6, an eighth NMOS transistor N8, a third capacitor C3, and a fourth capacitor C4.

[0050] Specifically, the two inputs of the NOR gate NOR1 are used to receive the on-time ton of the primary power transistor of the transformer and the demagnetization time tdemg of the transformer, respectively. Its output is connected to the input of the first NOT gate inv1, and the tsinH signal generated by the NOR gate NOR1 is sent to the first NOT gate inv1. The output of the first NOT gate inv1 is connected to the gate of the second NMOS transistor N2, and the tsinL signal generated by the first NOT gate inv1 is sent to the second NMOS transistor N2. The input of the second NOT gate inv2 is used to receive the demagnetization time tdemg of the transformer, and its output is connected to the input of the third NOT gate inv3 and one input of the AND gate AND1, respectively. The output of the third NOT gate inv3 is connected to one end of the third resistor R3, and the other end of the third resistor is connected to... One end of the second capacitor C2 is connected to the input of the fourth NOT gate inv4; the output of the fourth NOT gate inv4 is connected to the other input of the AND gate and1; the output of the AND gate and1 is connected to the input of the fifth NOT gate inv5, the gate of the seventh NMOS transistor N7, and the gate of the sixth PMOS transistor P6, respectively, and the tsampH signal generated by the AND gate and1 is sent to the fifth NOT gate inv5, the seventh NMOS transistor N7, and the sixth PMOS transistor P6, respectively; the output of the fifth NOT gate inv5 is connected to the gate of the fifth PMOS transistor P5 and the gate of the eighth NMOS transistor N8, respectively, and the tsampL signal generated by the fifth NOT gate inv5 is sent to the fifth PMOS transistor P5 and the eighth NMOS transistor N8, respectively; the other end of the second capacitor C2 is grounded.

[0051] The positive input of the first operational amplifier OP1 is used to receive the reference voltage signal Vref. Its negative input is connected to the source of the first NMOS transistor N1 and one end of the first resistor R1. The output of the first operational amplifier OP1 is connected to the gate of the first NMOS transistor N1. The drain of the first NMOS transistor N1 is connected to the drain and gate of the first PMOS transistor P1. The gate of the first PMOS transistor P1 is connected to the gate of the second PMOS transistor P2. The drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2. The source of the second NMOS transistor N2 is connected to one end of the first capacitor C1, the drain of the sixth NMOS transistor N6, the drain of the fifth PMOS transistor P5, and the drain of the seventh NMOS transistor N7. The positive input of the second operational amplifier OP2 is used to receive the feedback primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc. Its negative input is connected to the third NMOS transistor. The source of S-MOSFET N3 and one end of the second resistor R2 are connected to the output of the second operational amplifier OP2, which is connected to the gate of the third NMOS transistor N3. The drain of the third NMOS transistor N3 is connected to the drain and gate of the third PMOS transistor P3 and the gate of the fourth PMOS transistor P4. The drain of the fourth PMOS transistor P4 is connected to the drain and gate of the fourth NMOS transistor N4 and the gate of the fifth NMOS transistor N5. The drain of the fifth NMOS transistor N5 is connected to the source of the sixth NMOS transistor N6. The gate of the sixth NMOS transistor N6 is used to receive the transformer demagnetization time tdemg. The sources of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, and the fourth PMOS transistor P4 are all connected to the internal power supply. The other ends of the first capacitor C1, the first resistor R1, the second resistor R2, and the sources of the fourth NMOS transistor N4 and the fifth NMOS transistor N5 are all grounded. A ramp voltage is generated across the first capacitor C1.

[0052] The source of the seventh NMOS transistor N7 is connected to the source of the fifth PMOS transistor P5, the drain of the sixth PMOS transistor P6, the drain of the eighth NMOS transistor N8, and one end of the third capacitor C3, respectively; the source of the sixth PMOS transistor P6 is connected to the source of the eighth NMOS transistor N8, one end of the fourth capacitor C4, and the output terminal, so that the output terminal generates the primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc; the other ends of the third capacitor C3 and the fourth capacitor C4 are both grounded.

[0053] The derivation process of the calculation formula for the primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc in parameter calculation module 4 is as follows:

[0054] Based on QR mode (critical conduction mode), the duty cycle T = ton + tdemg.

[0055] The output current overload protection point Io_olp is expressed by the following formula:

[0056]

[0057] Where n is the turns ratio of the primary and secondary sides of the transformer; Ipk is the peak current of the primary side; Vth_oc is the reference voltage for the primary side cycle-by-cycle overcurrent protection set by the constant current limiting chip; and Rcs is the primary side current limiting resistor.

[0058] A reference voltage Vref is set inside the constant current limiting chip, such that:

[0059]

[0060] Combining formulas (1) and (2), we can see that:

[0061]

[0062] As can be seen from formula (3), the overload protection point Io_olp of the output current is only related to the turns ratio n of the primary and secondary sides of the transformer, the reference voltage Vref, and the current limiting resistor Rcs of the primary side, and is not related to the input voltage, output voltage, and inductance.

[0063] Therefore, the calculation formula for the primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc of parameter calculation module 4 is as follows:

[0064]

[0065] The working principle of the parameter calculation module 4 circuit:

[0066] The reference voltage Vref is applied across the first resistor R1 via the first operational amplifier OP1, yielding the current of the first PMOS transistor P1. Since the second PMOS transistor P2 is a mirror image of the first PMOS transistor P1, the current of the second PMOS transistor P2 is equal to the current of the first PMOS transistor P1, i.e., Vref / R1. Similarly, the primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc is applied across the second resistor R2 via the second operational amplifier OP2, yielding the current of the third PMOS transistor P3. Since the fourth PMOS transistor P4 is a mirror image of the third PMOS transistor P3, and the fifth NMOS transistor N5 is a mirror image of the fourth NMOS transistor N4, the final current of the fifth NMOS transistor N5 is Vth_oc / R2. Since the conduction time of the second NMOS transistor N2 is ton + tdemg, and the conduction time of the sixth NMOS transistor N6 is tdemg, the change in ramp voltage per cycle is equal to Vref*(ton + tdemg) / R1 - Vth_oc*tdemg / R2. With R1 = R2, the ramp voltage, through the switched capacitor filter unit, forms negative feedback to the primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc. After several cycles, it reaches stability, and finally, the change in ramp voltage per cycle is 0, i.e., Vref*(ton + tdemg) / R1 - Vth_oc*tdemg / R2 = 0. Since R1 = R2, the primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc = Vref*(ton + tdemg) / tdemg. Figure 4 The figure shows the working waveforms of the drain voltage Vds of the ninth NMOS transistor N9, the transformer demagnetization time tdemg, the on-time ton of the transformer primary power transistor, the tsampL signal, the ramp voltage, and the cycle-by-cycle overcurrent protection reference voltage Vth_oc.

[0067] This invention also provides a secondary-side feedback current limiting circuit based on QR mode, such as... Figure 2 As shown, the circuit includes the aforementioned constant current limiting chip, detection circuit, rectifier circuit, transformer unit, output module, ninth NMOS transistor N9, and primary-side current limiting resistor Rcs. The transformer unit includes a primary winding on the primary side, a secondary winding on the secondary side, and an auxiliary winding. The detection circuit includes a fourth resistor R4, a fifth resistor R5, and a diode D1.

[0068] One end of the auxiliary winding is grounded, and the other end is connected in sequence to diode D1 and the VCC pin of the constant current limiting chip, which is used to send the auxiliary voltage Vaux into the PWM main control module 2 to provide power.

[0069] The fourth resistor R4 and the fifth resistor R5 are connected in series across the two ends of the auxiliary winding. The connection point of the fourth resistor R4 and the fifth resistor R5 is connected to the Zcd pin of the constant current limiting chip. The demagnetization detection module 1 samples the transformer demagnetization signal based on the voltage divider signal of the fifth resistor R5.

[0070] The rectifier circuit is connected in sequence to the primary winding of the transformer, the ninth NMOS transistor N9, and the primary current limiting resistor Rcs. The gate of the ninth NMOS transistor N9 is connected to the Gate pin of the constant current limiting chip to control the primary current on and off. When the primary side is on, the transformer is magnetized. One end of the primary current limiting resistor Rcs is connected to the source of the ninth NMOS transistor N9 and the CS pin of the constant current limiting chip, and the other end is grounded to detect the primary current.

[0071] The output terminal of the secondary winding is connected to the input terminal of the output module. One of the output terminals of the output module is connected to the FB pin of the constant current limiting chip to provide feedback on the output voltage and load status of the output module.

[0072] Based on the above-mentioned QR mode secondary-side feedback current limiting circuit, the present invention provides a control method for a QR mode secondary-side feedback current limiting circuit, which specifically includes the following steps:

[0073] 1】The transformer demagnetization time tdemg collected by the demagnetization detection module 1 and the transformer primary power tube conduction time ton output by the drive module 3 are sent to the parameter calculation module 4 for calculation to obtain the primary side cycle-by-cycle overcurrent protection reference voltage Vth_oc.

[0074] 2】The obtained primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc and overcurrent voltage CS are respectively sent to the PWM main control module 2 through comparator CMP. The PWM main control module 2 controls the output current overload protection point Io_olp to remain constant.

[0075] The above description is only used to illustrate the technical solutions of the present invention, and is not intended to limit them. For those skilled in the art, modifications can be made to the specific technical solutions described in the above embodiments, or equivalent substitutions can be made to some of the technical features. However, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions protected by the present invention.

Claims

1. A constant current limiting chip, comprising a VCC pin, a Gate pin, a CS pin, a Zcd pin, an FB pin, and a GND pin, characterized in that: It includes a demagnetization detection module (1), a PWM main control module (2), a drive module (3), a parameter calculation module (4), and a comparator (CMP); One input terminal of the PWM main control module (2) is connected to the VCC pin, and its output terminal is connected to the drive module (3) and the Gate pin in sequence. The drive module (3) is used to send the conduction time ton of the primary power tube of the transformer to the demagnetization detection module (1) and the parameter calculation module (4) respectively; One of the input terminals of the demagnetization detection module (1) is connected to the Zcd pin, which is used to send the transformer demagnetization time tdemg into the parameter calculation module (4); The parameter calculation module (4) includes a mirror unit, a pulse signal source unit, and a switched filter capacitor unit; The pulse signal source unit is used to generate a pulse signal tsinL by performing logical operations on the on-time ton of the transformer primary power transistor and the demagnetization time tdemg of the transformer, so as to provide a control signal for the mirror unit; at the same time, the transformer demagnetization time tdemg is used to generate pulse signals tsampH and tsampL by performing logical operations, so as to provide a control signal for the switched filter capacitor unit. The mirror unit is used to obtain the current during the on-time ton and demagnetization time tdemg of the transformer primary power transistor by mirroring the reference voltage Vref; to obtain the current during the demagnetization time tdemg of the transformer by mirroring the feedback primary overcurrent protection reference voltage Vth_oc; and to generate ramp voltage. The switched filter capacitor unit is used to generate the primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc from the ramp voltage according to the control signal, and feed it back to the mirror unit; wherein, the calculation formula of the primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc of the parameter calculation module (4) is: In the formula, Vref is the reference voltage; One input of the comparator (CMP) is connected to the output of the switched filter capacitor unit, and the other input is connected to the CS pin. Its output is connected to the other input of the PWM main control module (2).

2. A constant current limiting chip according to claim 1, characterized in that: The mirror unit includes a first operational amplifier (OP1), a first NMOS transistor (N1), a first PMOS transistor (P1), a second NMOS transistor (N2), a second PMOS transistor (P2), a first resistor (R1), a first capacitor (C1), a second operational amplifier (OP2), a third NMOS transistor (N3), a third PMOS transistor (P3), a fourth PMOS transistor (P4), a second resistor (R2), a fourth NMOS transistor (N4), a fifth NMOS transistor (N5), and a sixth NMOS transistor (N6); The positive input of the first operational amplifier (OP1) is used to receive the reference voltage signal Vref. Its negative input is connected to the source of the first NMOS transistor (N1) and one end of the first resistor (R1). The output of the first operational amplifier (OP1) is connected to the gate of the first NMOS transistor (N1). The drain of the first NMOS transistor (N1) is connected to the drain and gate of the first PMOS transistor (P1) and the gate of the second PMOS transistor (P2). The drain of the second PMOS transistor (P2) is connected to the drain of the second NMOS transistor (N2). The gate of the second NMOS transistor (N2) is connected to the pulse signal source unit, and its source is connected to one end of the first capacitor (C1), the drain of the sixth NMOS transistor (N6), and the switched filter capacitor unit. The positive input of the second operational amplifier (OP2) is used to receive the feedback primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc. Its negative input is connected to the source of the third NMOS transistor (N3) and one end of the second resistor (R2). The output of the operational amplifier (OP2) is connected to the gate of the third NMOS transistor (N3); the drain of the third NMOS transistor (N3) is connected to the drain and gate of the third PMOS transistor (P3) and the gate of the fourth PMOS transistor (P4); the drain of the fourth PMOS transistor (P4) is connected to the drain and gate of the fourth NMOS transistor (N4); the gate of the fourth NMOS transistor (N4) is connected to the gate of the fifth NMOS transistor (N5); the drain of the fifth NMOS transistor (N5) is connected to the source of the sixth NMOS transistor (N6); the gate of the sixth NMOS transistor (N6) is used to receive the transformer demagnetization time tdemg; the sources of the first PMOS transistor (P1), the second PMOS transistor (P2), the third PMOS transistor (P3), and the fourth PMOS transistor (P4) are all connected to the internal power supply; the other ends of the first capacitor (C1), the first resistor (R1), the second resistor (R2), and the sources of the fourth NMOS transistor (N4) and the fifth NMOS transistor (N5) are all grounded.

3. A constant current limiting chip according to claim 2, characterized in that: The pulse signal source unit includes a logic OR gate (nor1), a first logic NOT gate (inv1), a second logic NOT gate (inv2), a third logic NOT gate (inv3), a fourth logic NOT gate (inv4), a fifth logic NOT gate (inv5), a logic AND gate (and1), a third resistor (R3), and a second capacitor (C2). The two inputs of the OR gate (nor1) are used to receive the on-time ton of the primary power transistor of the transformer and the demagnetization time tdemg of the transformer, respectively. Its output is connected to the input of the first NOT gate (inv1), and the output of the first NOT gate (inv1) is connected to the gate of the second NMOS transistor (N2). The input of the second NOT gate (inv2) is used to receive the transformer demagnetization time tdemg. Its output is connected to the input of the third NOT gate (inv3) and one input of the AND gate (and1). The output of the third NOT gate (inv3) is connected to one end of the third resistor (R3). The other end of the third resistor is connected to one end of the second capacitor (C2) and the input of the fourth NOT gate (inv4). The output of the fourth NOT gate (inv4) is connected to the other input of the AND gate (and1). The output of the AND gate (and1) is connected to the input of the fifth NOT gate (inv5) and the switched filter capacitor unit. The output of the fifth NOT gate (inv5) is connected to the switched filter capacitor unit. The other end of the second capacitor (C2) is grounded.

4. A constant current limiting chip according to claim 3, characterized in that: The switched filter capacitor unit includes a fifth PMOS transistor (P5), a seventh NMOS transistor (N7), a sixth PMOS transistor (P6), an eighth NMOS transistor (N8), a third capacitor (C3), and a fourth capacitor (C4). The gates of the seventh NMOS transistor (N7) and the sixth PMOS transistor (P6) are both connected to the output of an AND gate (AND1), and the gates of the fifth PMOS transistor (P5) and the eighth NMOS transistor (N8) are both connected to the output of a fifth NOT gate (INV5). The drain of the seventh NMOS transistor (N7) is connected to the drain of the fifth PMOS transistor (P5), the source of the second NMOS transistor (N2), and the drain of the sixth NMOS transistor (N6), respectively. Its source is connected to the source of the fifth PMOS transistor (P5), the drain of the sixth PMOS transistor (P6), the drain of the eighth NMOS transistor (N8), and one end of the third capacitor (C3), respectively. The source of the sixth PMOS transistor (P6) is connected to the source of the eighth NMOS transistor (N8), one end of the fourth capacitor (C4), and the output terminal, respectively. The other ends of the third capacitor (C3) and the fourth capacitor (C4) are both grounded.

5. A QR-mode secondary-side feedback current limiting circuit, characterized in that: Includes the constant current limiting chip, detection circuit, rectifier circuit, transformer unit, output module, ninth NMOS transistor (N9) and primary side current limiting resistor Rcs as described in any one of claims 1-4; the transformer unit includes a primary side winding disposed on the primary side, a secondary side winding disposed on the secondary side and an auxiliary winding. The detection circuit includes a fourth resistor (R4), a fifth resistor (R5), and a diode (D1); One end of the auxiliary winding is grounded, and the other end is connected in sequence to the diode (D1) and the VCC pin of the constant current limiting chip to supply power to the PWM main control module (2); the fourth resistor (R4) and the fifth resistor (R5) are connected in series to the two ends of the auxiliary winding, and the connection point of the fourth resistor (R4) and the fifth resistor (R5) is connected to the Zcd pin of the constant current limiting chip; the demagnetization detection module (1) samples the transformer demagnetization signal according to the voltage division signal of the fifth resistor (R5); The rectifier circuit is connected in sequence to the primary winding of the transformer, the ninth NMOS transistor (N9), and the primary current limiting resistor Rcs; the gate of the ninth NMOS transistor (N9) is connected to the Gate pin of the constant current limiting chip; one end of the primary current limiting resistor Rcs is connected to the source of the ninth NMOS transistor (N9) and the CS pin of the constant current limiting chip, and the other end is grounded to detect the primary current. The output terminal of the secondary winding is connected to the input terminal of the output module, and one of the output terminals of the output module is connected to the FB pin of the constant current limiting chip to provide feedback on the output voltage and load status of the output module.

6. A control method for a secondary-side feedback current limiting circuit based on the QR mode described in claim 5, characterized in that, Includes the following steps:

1. Calculate the primary side cycle-by-cycle overcurrent protection reference voltage Vth_oc based on the transformer demagnetization time tdemg and the transformer primary power transistor conduction time ton; 2. Based on the obtained primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc, control the output current overload protection point Io_olp to remain constant.

7. The control method for the secondary-side feedback current limiting circuit according to claim 6, characterized in that: In step 2, based on the obtained primary-side cycle-by-cycle overcurrent protection reference voltage Vth_oc, the output current overload protection point Io_olp is controlled to remain constant as follows: A reference voltage Vref is set inside the constant current limiting chip, so that... Where T represents the work cycle; The output current overload protection point Io_olp is kept constant by the following formula: Where Rcs is the primary current-limiting resistor and n is the primary-secondary turns ratio of the transformer.

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