An aircraft engine speed acquisition circuit with fault detection

Abstract

The present invention provides an aero-engine speed acquisition circuit with fault detection, comprising: a BIT on-line detection circuit, a filtering and limiting circuit, a signal superposition and amplification circuit, a voltage biasing circuit, a comparison and buffering circuit, a processor or a logic unit; the filtering and limiting circuit is used for filtering and limiting the differential signal output by the speed acquisition sensor, the BIT on-line detection circuit is used for generating and conditioning the line detection signal, the signal superposition and amplification circuit amplifies the quasi-sine wave signal and superposes it with the detection square wave signal, the voltage biasing circuit performs a positive bias on the superposed wave signal, the comparison and buffering circuit compares and isolates the superposed wave signal, and outputs a square wave signal with the same frequency to the processor or the logic unit, and the processor or the logic unit performs operations and judgments according to the frequency of the input square wave signal to complete on-line fault detection. The present invention can perform BIT on-line detection on the acquisition circuit at the rear end of the sensor, achieving the purpose of fault detection and isolation.

Description

Technical Field

[0001] The present invention relates to the technical field of aero-engine testing, and particularly to a circuit for collecting the rotational speed of an aero-engine with fault detection. Background Art

[0002] In the design of aero-engines, the collection of rotational speed signals is very important. The rotational speed signal is one of the important monitoring parameters for evaluating the operating performance of aero-engines. The collection of the rotational speed of an aero-engine mainly consists of a sensor and a backend collection circuit. When a fault occurs during the rotational speed collection process, the traditional collection scheme has the problem that it cannot isolate and locate the fault in the first time when the engine is in the starting state. Therefore, it is necessary to propose a method for collecting the rotational speed of an aero-engine that can perform fault detection. Summary of the Invention

[0003] In view of this, the embodiments of the present application provide a circuit for collecting the rotational speed of an aero-engine with fault detection to improve the fault detection rate of the rotational speed collection circuit. By means of the BIT online circuit to detect the rotational speed collection circuit, the problem that the fault isolation between the sensor output and the backend rotational speed signal collection circuit cannot be achieved when a rotational speed collection fault occurs in the engine starting state is solved. At the same time, the time required for fault isolation can be reduced, and the reliability and stability of the rotational speed signal collection circuit can be enhanced.

[0004] The embodiments of the present application provide the following technical solutions: A circuit for collecting the rotational speed of an aero-engine with fault detection, comprising: a BIT online detection circuit, a filtering and amplitude limiting circuit, a signal superposition and amplification circuit, a voltage biasing circuit, a comparison and buffering circuit, a processor or a logic unit;

[0005] The filtering and amplitude limiting circuit is used for performing filtering and amplitude limiting processing on the differential signal output by the rotational speed sensor of the engine, and generating a quasi-sine wave signal to output to the signal superposition and amplification circuit;

[0006] The BIT online detection circuit is used for realizing the generation and conditioning of the BIT online detection signal, and outputting a detection square wave signal to the signal superposition and amplification circuit;

[0007] The signal superposition and amplification circuit amplifies the quasi-sine wave signal, and superposes it with the detection square wave signal and then outputs to the voltage biasing circuit;

[0008] The voltage biasing circuit performs positive biasing on the superposed wave signal, and outputs the positively biased superposed wave signal to the comparison and buffering circuit;

[0009] The comparison buffer circuit compares and isolates the forward-biased superimposed wave signal, and outputs a square wave signal with the same frequency as the output signal of the BIT online detection circuit to the processor or logic unit. The processor or logic unit performs operations and judgments based on the frequency of the input square wave signal to complete online fault detection.

[0010] Further, the process of the processor or logic unit performing operations and judgments based on the frequency of the input square wave signal to complete online fault detection specifically includes:

[0011] The processor or logic unit compares the frequency of the input square wave signal with the frequency of the detection square wave signal output by the BIT online detection circuit, calculates the accuracy. If the accuracy is within the threshold range, the engine speed acquisition circuit is normal; otherwise, the engine speed acquisition circuit fails.

[0012] Further, the BIT online detection circuit includes a waveform generation circuit, a saturation comparison circuit, and a detection gating circuit. The waveform generation circuit is used to generate a detection square wave signal through the processor or logic unit and output it to the saturation comparison circuit. The saturation comparison circuit performs amplitude saturation conditioning on the detection square wave signal. The detection gating circuit is connected to the processor or logic unit for control. The processor or logic unit generates a gating signal to control the detection gating circuit to output the saturated detection square wave signal to the signal superposition and amplification circuit.

[0013] Further, the frequency of the detection square wave signal generated by the processor or logic unit is configurable, and the frequency of the detection square wave signal is greater than twice the highest acquisition frequency range of the engine speed acquisition sensor excitation.

[0014] Further, the signal superposition and amplification circuit includes an operational amplifier. The negative terminal of the operational amplifier is connected to a diode to protect the superimposed square wave from exceeding the input threshold of the operational amplifier.

[0015] Further, the comparison buffer circuit includes a hysteresis comparator. The negative terminal of the hysteresis comparator is connected to a diode to attenuate the negative value of the input waveform and ensure that the input waveform conforms to the comparison characteristics.

[0016] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the embodiments of this specification at least include: The embodiments of the present invention can effectively improve the fault detection rate of the rotational speed acquisition circuit. By utilizing the saturated output and signal superposition characteristics of the amplifier, and through the method of BIT online circuit to detect the rotational speed acquisition circuit, when a rotational speed acquisition fault occurs during the engine startup state, the problem that the isolation between the sensor output and the rear-end rotational speed signal acquisition circuit cannot be achieved is solved, and the BIT online detection of the acquisition circuit behind the sensor is realized, achieving the purpose of fault detection and isolation. At the same time, it can reduce the time required for fault isolation, enhance the reliability and stability of the rotational speed signal acquisition circuit, and is used for the measurement of rotational speed and the online test of BIT (built-in self-test) of the rotational speed acquisition circuit itself during engine control and engine commissioning. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0018] Figure 1 is the functional principle block diagram of an aeroengine rotational speed acquisition circuit with fault detection of the present invention;

[0019] Figure 2 is the composition diagram of the BIT online detection circuit of the embodiment of the present invention;

[0020] Figure 3 is the hardware schematic diagram of the filter and amplitude limiting circuit of the embodiment of the present invention;

[0021] Figure 4 is the hardware schematic diagram of the signal superposition and amplification circuit of the embodiment of the present invention;

[0022] Among them, A1 - amplifier;

[0023] Figure 5 is the hardware schematic diagram of the voltage bias circuit of the embodiment of the present invention;

[0024] Among them, A2 - amplifier;

[0025] Figure 6 is the hardware schematic diagram of the comparison and buffer circuit of the embodiment of the present invention;

[0026] Among them, B1 - comparator;

[0027] Figure 7 is the hardware schematic diagram of the BIT online detection circuit of the embodiment of the present invention;

[0028] Among them, B2 - comparator;

[0029] Figure 8 It is a schematic diagram of signal transmission in the rotational speed acquisition and BIT online detection process of an embodiment of the present invention. Specific embodiments

[0030] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0031] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments. The technical solutions of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0032] As Figures 1-8 shown, an embodiment of the present invention provides an aeroengine rotational speed acquisition circuit with fault detection, including: a BIT online detection circuit, a filtering and limiting circuit, a signal superposition and amplification circuit, a voltage biasing circuit, a comparison and buffering circuit, a processor or a logic unit;

[0033] The filtering and limiting circuit is used to perform filtering and limiting processing on the differential signal output by the engine rotational speed acquisition sensor. After the input signal is limited, a quasi-sine wave with an amplitude of the diode voltage drop (amplitude approximately -0.7V to +0.7V) is output, and a quasi-sine wave signal is generated and output to the signal superposition and amplification circuit;

[0034] The BIT online detection circuit is used to generate and condition the BIT online detection signal, and output a detection square wave signal to the signal superposition and amplification circuit;

[0035] The signal superposition and amplification circuit amplifies the quasi-sine wave from the filtering and limiting circuit, and superposes it with the detection square wave signal and then outputs it to the voltage biasing circuit;

[0036] The voltage biasing circuit performs a positive shift on the superimposed wave signal to ensure that the amplitude of the amplified acquisition signal is positive, and outputs the generated positively biased superimposed wave signal to the comparison and buffering circuit;

[0037] The comparison and buffering circuit compares and isolates the positively biased superimposed wave signal, and outputs a square wave signal with the same frequency as the output signal of the BIT online detection circuit to the processor or the logic unit. The processor or the logic unit performs operations and judgments based on the frequency of the input square wave signal to complete online fault detection.

[0038] Specifically, the processor or logic unit compares the frequency of the input square wave signal with the frequency of the detection square wave signal output by the BIT on-line detection circuit, calculates the accuracy. If the accuracy is within the threshold range, the engine speed acquisition circuit is normal; otherwise, the engine speed acquisition circuit fails.

[0039] Among them, the frequency of the detection square wave signal generated by the processor or logic unit is configurable, and the frequency of the detection square wave signal is greater than twice the highest acquisition frequency range of the engine speed acquisition sensor excitation, so as to detect the accuracy of the backend acquisition circuit.

[0040] In the embodiment of the present invention, by using the amplifier saturation output and signal superposition characteristics, a detection square wave signal is generated by the BIT on-line detection circuit and superposed with the speed signal output by the sensor, and is collected and processed by the processor or logic chip. The processing result is used to judge the acquisition fault and acquisition accuracy, and the on-line fault detection of the sensor acquisition circuit is completed. This detection method can perform acquisition fault isolation and detection in the engine running state, and can also detect the backend acquisition circuit in the sensor open circuit state.

[0041] In this embodiment, as Figure 2 shown, the BIT on-line detection circuit includes a waveform generation circuit, a saturation comparison circuit and a detection gating circuit. The waveform generation circuit is used to generate a detection square wave signal through the processor or logic unit and output it to the saturation comparison circuit. The saturation comparison circuit performs amplitude saturation conditioning on the detection square wave signal and outputs a saturated square wave signal (the signal amplitude depends on the positive and negative power rails of the comparator). The detection gating circuit is controlled and connected to the processor or logic unit, and the processor or logic unit generates a control signal to control the operation of the detection gating circuit, thereby determining whether the BIT on-line detection circuit works. Specifically, the processor or logic unit generates a gating signal to control the detection gating circuit to output the saturated detection square wave signal to the signal superposition and amplification circuit.

[0042] As Figure 3 shown, Figure 3 is the schematic diagram of the filter limiting circuit. The rotational speed differential signal collected by the sensor is filtered by the band-pass filter composed of C1, C2, R1, R2 and C3, and then the signal amplitude is limited within the effective acquisition range by the diode limiting circuit composed of V1 and V2.

[0043] In the embodiment of the present invention, by utilizing the signal superposition characteristic, the acquired signal is superimposed by the saturated square-wave detection signal output by the BIT on-line detection circuit. In the signal superposition and amplification circuit, the negative terminal of the amplifier is protected by a diode to ensure that the superimposed waveform does not exceed the input threshold of the amplifier. The superimposed waveform is conditioned by using the saturated output characteristic of the operational amplifier, and the acquired waveform is attenuated to finally generate a square-wave signal with the same frequency as the BIT on-line detection circuit and enter the processor or logic for processing. The processing result is used as an index for judging the fault of the acquisition circuit and the acquisition accuracy. As Figure 4 shown Figure 4 Figure 4 is a schematic diagram of the signal superposition and amplification circuit. The square-wave signal generated by the BIT on-line detection circuit and the rotational speed acquisition signal are subjected to an addition operation. At the same time, the amplification function is completed by the ratio of R6 to other resistors. Diode V3 is a protection diode to prevent the input signal from exceeding the maximum input voltage limit of operational amplifier A1.

[0044] As Figure 5 shown Figure 5 Figure 5 is a schematic diagram of the voltage biasing circuit. The superimposed signal is biased on the Vcc / 2 voltage reference. Set R9 = R8 to prepare for subsequent entry into the comparison circuit.

[0045] In the embodiment of the present invention, the comparison buffer circuit is implemented by a hysteresis comparator. The negative terminal of the comparator is protected by a diode to attenuate the negative value of the input waveform and ensure that the input waveform conforms to the comparison characteristic. As Figure 6 shown Figure 6 Figure 6 is a schematic diagram of the comparison buffer circuit. The biased superimposed signal is compared with the Vcc / 2 voltage reference to separate the signal generated by the BIT on-line detection circuit from the superimposed waveform. The purpose of setting V4 is to eliminate the negative voltage signal from entering the comparator. R10 - R13 and B1 form a hysteresis comparison circuit.

[0046] As Figure 7 shown Figure 7 Figure 7 is a schematic diagram of the BIT on-line detection circuit, which is used to generate an on-line detection test waveform. The square-wave signal generated by the processor or logic is compared with the Vcc / 2 voltage reference to generate a saturated square-wave signal. The detection circuit is controlled to work or not by gating through the processor or logic. R16 is the open-circuit output configuration resistor of the comparator to ensure that it can output a signal near the positive power supply rail.

[0047] The working process of the aero-engine rotational speed acquisition circuit with fault detection according to the present invention is as follows:

[0048] Step 1: The rotational speed differential signal output by the sensor is conditioned by the filter and amplitude-limiting circuit and then outputs an unbiased, approximately 0.7V sinusoidal-like differential signal.

[0049] Step 2: The conditioned differential signal enters the signal superposition and amplification circuit and the voltage biasing circuit for processing. After proportional amplification and forward biasing, a forward-biased quasi-sine wave signal is output to the comparison buffer circuit;

[0050] Step 3: The quasi-sine wave signal enters the comparison buffer circuit. After passing through the comparison buffer circuit, a square wave signal with the same frequency as the input signal is output and sent to the processor or logic unit for operation;

[0051] Step 4: During on-line BIT detection, a gating signal is generated by the processor or logic unit. At the same time, the waveform generation circuit generates a logic square wave signal with a configurable frequency. After passing through the saturation comparison circuit and the detection gating circuit, a saturation square wave detection signal with the same frequency as the waveform generation circuit is output and superimposed on the sensor input signal to form a mixed waveform;

[0052] Step 5: After passing through the signal superposition and amplification circuit and the voltage biasing circuit, a forward-biased mixed waveform is output;

[0053] Step 6: The mixed waveform is sent to the comparison buffer circuit for comparison and isolation, and a square wave signal with the same frequency as the output signal of the BIT on-line detection circuit is generated and sent to the processor or logic chip for processing. The processing result judges the acquisition fault and acquisition accuracy, and completes the on-line fault detection.

[0054] In this embodiment, during the normal acquisition process of the engine speed acquisition circuit, the control signal sets the detection gating circuit to an open state, and the BIT on-line detection circuit is in a high-impedance state, which does not affect the operation of the acquisition circuit and realizes the normal measurement of the engine speed signal; when performing fault detection, a control signal is generated by the processor or logic chip to control the gating of the detection gating circuit, and the detection signal generated by the BIT on-line detection circuit is injected into the engine speed acquisition circuit to check whether the subsequent acquisition circuit works properly.

[0055] In a specific embodiment, the working process of an aero-engine speed acquisition circuit with fault detection in this embodiment is as follows:

[0056] Step 1: The rotational speed differential signal (N1+ and N1-) output by the sensor is conditioned by a filter-limiting circuit composed of a band-pass filter (formed by C1, C2, R1, R2, and C3) and diodes (V1 and V2), and a non-biased quasi-sine wave differential signal (N1_IN+ and N1_IN-) with an amplitude of about 0.7V is output;

[0057] Step 2: The conditioned differential signal enters the signal superposition and amplification circuit. After proportional amplification (amplification factor G = R6 / R4), a non-biased quasi-sine wave signal with an amplitude of 0.7*G is output to the shaping circuit;

[0058] Step 3: The conditioned quasi-sine wave signal is output, after passing through a voltage biasing circuit (with an amplification factor set to 1), a quasi-sine wave signal with a positive bias of Vcc / 2 and an amplitude of 0.7*G to the comparison buffer circuit;

[0059] Step 4: The quasi-sine wave signal with a positive bias enters the comparison buffer circuit. After hysteresis comparison by comparator B1, a square wave signal with the same frequency as the input signal is output and sent to a processor or logic chip for calculation and processing to obtain the rotational speed value;

[0060] Step 4: During on-line BIT detection, a waveform generation circuit in the BIT on-line detection circuit generates a logic square wave signal (generated by a processor or logic chip) with a configurable frequency, a peak-to-peak value of Vcc, and a bias of Vcc / 2. After passing through comparator B2 (with a comparison reference voltage value of Vcc / 2) in the saturation comparison circuit and the detection gating circuit, a saturation square wave signal (detection square wave signal) with the same frequency, no bias, and an amplitude of approximately Vss is output and superimposed on the acquisition signal to form a mixed waveform.

[0061] Step 5: Set Vss >= 3*Vcc. According to the signal superposition principle, the detection square wave signal will attenuate the acquisition signal to a negative value at the moment when its amplitude is negative, and add it to the sensor input signal at the moment when its amplitude is positive. Since VSS is the saturation output voltage rail, and considering the presence of diode V3, after superposition, the detection square wave signal conditions the input rotational speed signal into a mixed waveform from -Vss + 0.7*G to Vss. Therefore, an appropriate reference voltage can be used for comparison so that the frequency of the detection square wave can be detected, thereby realizing the detection function of rotational speed acquisition.

[0062] Step 6: To ensure the normal operation of comparator B1 in the comparison buffer circuit under the power supply conditions, diode V4 is set as a protection device for the negative input terminal of comparator B1. The mixed waveform is adjusted to a mixed waveform with an output voltage range of approximately -0.7V to +Vss and sent to comparator B1 for comparison. The signal output can detect the signal frequency through a frequency detection circuit at the back end (such as a processor with frequency capture or a logic device using the pulse filling method for frequency detection). If the frequency is the same as that of the detection square wave signal, the rotational speed acquisition circuit is normal; otherwise, the rotational speed acquisition circuit is faulty.

[0063] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An aircraft engine speed acquisition circuit with fault detection, characterized in that, Including: BIT on-line detection circuit, filter-limiting circuit, signal superposition and amplification circuit, voltage biasing circuit, comparison buffer circuit, processor or logic unit; The filter-limiting circuit is used to perform filter-limiting processing on the differential signal output by the engine speed acquisition sensor, and generate a quasi-sine wave signal to output to the signal superposition and amplification circuit; The BIT on-line detection circuit is used to generate and condition the BIT on-line detection signal, and output a detection square wave signal to the signal superposition and amplification circuit; The signal superposition and amplification circuit amplifies the quasi-sine wave signal, and superposes it with the detection square wave signal and then outputs to the voltage biasing circuit; The voltage biasing circuit performs positive biasing on the superimposed wave signal, and outputs the generated positively biased superimposed wave signal to the comparison buffer circuit; The comparison buffer circuit compares and isolates the positively biased superimposed wave signal, and outputs a square wave signal with the same frequency as the output signal of the BIT on-line detection circuit to the processor or logic unit, and the processor or logic unit performs operations and judgments according to the frequency of the input square wave signal to complete on-line fault detection; The process that the processor or logic unit performs operations and judgments according to the frequency of the input square wave signal to complete on-line fault detection specifically includes: The processor or logic unit compares the frequency of the input square wave signal with the frequency of the detection square wave signal output by the BIT on-line detection circuit, calculates the accuracy. If the accuracy is within the threshold range, the engine speed acquisition circuit is normal; if not, the engine speed acquisition circuit has a fault; The BIT on-line detection circuit includes a waveform generation circuit, a saturation comparison circuit and a detection gating circuit. The waveform generation circuit is used to generate a detection square wave signal through the processor or logic unit and output it to the saturation comparison circuit. The saturation comparison circuit performs amplitude saturation conditioning on the detection square wave signal. The detection gating circuit is connected to the processor or logic unit for control. The processor or logic unit generates a gating signal to control the detection gating circuit to output the saturated detection square wave signal to the signal superposition and amplification circuit; Among them, during the normal acquisition process of the engine speed acquisition circuit, the control signal sets the detection gating circuit to an open state, and the BIT on-line detection circuit is in a high-impedance state, which does not affect the operation of the acquisition circuit, and realizes the normal measurement of the engine speed signal; when performing fault detection, the processor or logic chip generates a control signal to control the detection gating circuit to be gated, and the detection signal generated by the BIT on-line detection circuit is injected into the engine speed acquisition circuit to check whether the backend acquisition circuit works normally.

2. The aero-engine speed acquisition circuit with fault detection according to claim 1, wherein The frequency of the detection square wave signal generated by the processor or logic unit is configurable, and the frequency of the detection square wave signal is greater than twice the highest acquisition frequency range of the engine speed acquisition sensor excitation.

3. The aero-engine speed acquisition circuit with fault detection according to claim 1, characterized in that, The signal superposition and amplification circuit includes an operational amplifier, and the negative terminal of the operational amplifier is connected to a diode to protect the superimposed square wave from exceeding the input threshold of the operational amplifier.

4. The aero-engine speed acquisition circuit with fault detection according to claim 1, characterized in that, The comparison buffer circuit includes a hysteresis comparator. The negative terminal of the hysteresis comparator is connected to a diode, which is used to attenuate the negative value of the input waveform to ensure that the input waveform meets the comparison characteristics.

Images