A processor-stored link management method and apparatus
By using a processor-stored link management method to parse and differentiate signaling messages and service data, the lack of unified management in existing technologies is solved, achieving efficient data transmission and management and improving system performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 刘学
- Filing Date
- 2022-08-09
- Publication Date
- 2026-06-26
AI Technical Summary
Existing technologies fail to effectively distinguish between signaling messages and service data, resulting in a lack of unified management solutions for processor-based storage link management.
The message packets are parsed by the Demux module, and signaling messages and service messages are processed separately. The DMA_Manage module reads the descriptor, determines the data migration type based on the source end, and sends the DMA migration data through the Dest_Manage module, forming a unified chain management scheme.
It increases transmission bandwidth, reduces transmission latency, enhances system and interface utilization, supports multiple ports, multiple users, and multiple tasks, and features high efficiency and standardized operation.
Smart Images
Figure CN115309338B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, and more specifically, to a processor-based storage link management method and apparatus. Background Technology
[0002] Current technology does not separate signaling messages and service data at the source, resulting in design redundancy at the front end. Therefore, there is currently no unified and effective management solution for processor-based storage link management. Summary of the Invention
[0003] The purpose of this invention is to provide a processor storage link management method and apparatus to improve the problem that there is no unified and effective management scheme for processor storage link management in the prior art.
[0004] The embodiments of the present invention are implemented as follows:
[0005] In a first aspect, embodiments of this application provide a processor-based memory link management method, which includes the following steps:
[0006] When responding to a data transfer task between the master device and an external device, the message packet is obtained and parsed through the Demux module;
[0007] If the message packet is a signaling message, the Demux module will send the parsed message packet to the message execution module. The message execution module is used to receive and parse the signaling message, and then assemble and send the signaling message into packets.
[0008] If the message packet is a business message packet, the Demux module will transmit the parsed message packet to the DMA_Manage module via the Tag_Manage module, and at the same time the DMA_Manage module will obtain the DMA task start message;
[0009] Based on the message packet, the DMA_Manage module reads the descriptor back to the TLP, and reads the source and destination descriptors at the same time;
[0010] The data transfer task type is determined based on the source end. If the data transfer task type is downlink, the Dest_Manage module adds an address field to the downlink DMA transfer data and sends it to the external device. If the data transfer task type is uplink, the Dest_Manage module adds an address field to the uplink DMA transfer data and sends it to the master device.
[0011] In some embodiments of the present invention, if the data transfer task type is downlink, the Dest_Manage module adds an address field to the downlink DMA transfer data and sends it to the external device. If the data transfer task type is uplink, the Dest_Manage module adds an address field to the uplink DMA transfer data and sends it to the master device. At the same time, the Tx_arbiter module receives the DMA transfer data and the address field, judges the address field, and transmits the DMA transfer data sequentially according to the address field.
[0012] In some embodiments of the present invention, if the message packet is a service message packet, the step of the Demux module transmitting the parsed message packet to the DMA_Manage module via the Tag_Manage module includes:
[0013] The parsed business message packets are marked using the Tag_Manage module.
[0014] In some embodiments of the present invention, the steps described above, whereby the DMA_Manage module reads the descriptor back to the TLP based on message packets, and simultaneously reads the source and destination descriptors, include:
[0015] All descriptors are read back to the TLP sequentially using the DMA_Manage module;
[0016] Once all descriptors have been read, the data packet is obtained, and the data in the data packet is written into the corresponding descriptor table.
[0017] In some embodiments of the present invention, the step of determining the data migration task type based on the source end includes:
[0018] If the source is the master device, then the data migration task type is data downlink;
[0019] If the source is an external device, the data migration task type is data uplink.
[0020] In some embodiments of the present invention, the above-mentioned data migration task includes at least one or more of the following: from a single source to a single destination address, from a single source to multiple destination addresses, from multiple sources to a single destination address, and from data from multiple source addresses to multiple destination addresses.
[0021] Secondly, embodiments of this application provide a processor-based memory link management device, which includes a bus interface, a Demux module, a message execution module, a Tag_Manage module, a DMA_Manage module, and a Dest_Manage module:
[0022] The bus interface is used to connect the master device and the external device.
[0023] The Demux module is used to acquire and parse message packets. If the message packet is a signaling message, the parsed message packet is sent to the message execution module. If the message packet is a service message packet, the parsed message packet is transmitted to the DMA_Manage module via the Tag_Manage module.
[0024] The message execution module is used to receive and parse signaling messages, and to assemble and send the signaling messages into packets.
[0025] The DMA_Manage module is used to read descriptors back to the TLP, and read both the source and destination descriptors.
[0026] The Dest_Manage module is used to send downlink DMA transfer data to the external device with an address field added if the data transfer task type is downlink, and to send uplink DMA transfer data to the master device with an address field added if the data transfer task type is uplink.
[0027] In some embodiments of the present invention, the bus interface includes a PCIe interface and an AXI interface.
[0028] Thirdly, embodiments of this application provide an electronic device including a memory for storing one or more programs; and a processor. When the one or more programs are executed by the processor, they implement the methods described in any of the first aspects above.
[0029] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method as described in any of the first aspects above.
[0030] Compared with the prior art, the embodiments of the present invention have at least the following advantages or beneficial effects:
[0031] This invention provides a processor-based storage link management method and apparatus, comprising the following steps: When responding to a data transfer task between a master device and an external device, a message packet is acquired and parsed via a Demux module. If the message packet is a signaling message, the Demux module sends the parsed message packet to a message execution module, which receives and parses the signaling message and assembles and sends the signaling message into packets. If the message packet is a service message packet, the Demux module transmits the parsed message packet to a DMA_Manage module via a Tag_Manage module, while the DMA_Manage module acquires a DMA task start message. Based on the message packet, the DMA_Manage module reads the descriptor back to the TLP, and reads the source and destination descriptors. The data transfer task type is determined based on the source. If the data transfer task type is downlink, the downlink DMA transfer data is sent to the external device with an address field added via a Dest_Manage module. If the data transfer task type is uplink, the uplink DMA transfer data is sent to the master device with an address field added via a Dest_Manage module. This method and apparatus parse and decompose signaling and service messages at the source, forming a unified and effective chain-like management scheme, including message mechanisms, data migration mechanisms, and related components, thereby improving transmission bandwidth and reducing transmission latency. The mechanism formed by this method and apparatus can cooperate with host software and flexibly adapt to most buses, improving the overall system and interface utilization. It features high transmission efficiency, multi-port and multi-user support, multi-task support, and multi-message ring support, and is characterized by high efficiency, standardized operation, and independence from bus type. Attached Figure Description
[0032] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1 A flowchart illustrating a processor-based memory link management method provided in an embodiment of the present invention;
[0034] Figure 2 A flowchart of another processor-based storage link management method provided in an embodiment of the present invention;
[0035] Figure 3 This is a schematic diagram of the processing flow of a processor-based storage link management device provided in an embodiment of the present invention;
[0036] Figure 4A structural block diagram of a processor-based storage link management device provided in an embodiment of the present invention;
[0037] Figure 5 This is a schematic structural block diagram of an electronic device provided in an embodiment of the present invention.
[0038] Icons: 110 - Bus interface; 120 - Demux module; 130 - Message execution module; 140 - Tag_Manage module; 150 - DMA_Manage module; 160 - Dest_Manage module; 101 - Memory; 102 - Processor; 103 - Communication interface. Detailed Implementation
[0039] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0040] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0041] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0042] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the use of the terms "comprising," "including," or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, the presence of an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0043] In the description of this application, it should be noted that if the terms "upper", "lower", "inner", "outer", etc. appear to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0044] In the description of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0045] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the various embodiments and features described below can be combined with each other.
[0046] Example
[0047] Please refer to Figures 1 to 3 , Figure 1 The diagram shown is a flowchart of a processor-based memory link management method provided in an embodiment of this application. Figure 2 The diagram shown is a flowchart of another processor-based storage link management method provided by an embodiment of the present invention. Figure 3 The diagram shown is a schematic representation of the processing flow of a processor-based memory link management device according to an embodiment of the present invention. This application embodiment provides a processor-based memory link management method, which includes the following steps:
[0048] S110: When responding to a data transfer task between the master device and the external device, the message packet is obtained and parsed through the Demux module 120;
[0049] Specifically, the aforementioned data migration task typically refers to moving data between the master device and the external device. The operation of moving data from the master device's memory to the slave device (i.e., the external device) is called data downlink, while the operation of moving data from the slave device to the master device's memory is called data uplink.
[0050] Before data migration, a buffer needs to be set up in memory on the host side, and the source and destination descriptors for this data migration need to be prepared. The content of the descriptors is set according to the specific migration task. For example, in a downlink data migration task, the master device is the source, the memory address where the data is stored is the data source address, the total number of bytes to be migrated is the length of the source data, and the slave device is the destination, with the slave device's memory address being the destination address. Conversely, in an uplink data migration task, the master device is the destination and the slave device is the source. A single migration task can complete various types of migrations, including migrations from a single source to a single destination address, from a single source to multiple destination addresses, from multiple sources to a single destination address, or from multiple source addresses to multiple destination addresses.
[0051] In the above implementation process, when the master device and the external device perform data transfer tasks, the Demux module 120 receives and parses message packets through the PCIE interface or AXI interface, and sends the parsed message packets to different modules according to the type of message packets.
[0052] S120: If the message packet is a signaling message, the Demux module 120 sends the parsed message packet to the message execution module 130. The message execution module 130 is used to receive and parse the signaling message and assemble and send the signaling message.
[0053] S130: If the message packet is a business message packet, the Demux module 120 will transmit the parsed message packet to the DMA_Manage module 150 via the Tag_Manage module 140, and at the same time the DMA_Manage module 150 will obtain the DMA task start message.
[0054] S140: Based on the message packet, the DMA_Manage module 150 reads the descriptor back to the TLP, and reads the source and destination descriptors at the same time;
[0055] Specifically, the current data flow includes two types: one is the data flow of signaling messages, and the other is the data flow of business messages.
[0056] When the message packet type is a signaling message, the Demux module 120 sends the parsed message packet to the message execution module 130 (Msg-Resolve and Response). After the message ring in the message execution module 130 parses the signaling message, the message execution module 130 then reassembles and sends the signaling message. The message ring supports multiple message ring address configurations and supports multi-message ring reply messages. When the message packet is a service message packet, the Demux module 120 transmits the parsed message packet to the Tag_Manage module 140. After the Tag_Manage module 140 marks the parsed service message packet, it transmits it to the DMA_Manage module 150. At this time, the DMA_Manage module 150 obtains the DMA task start message to start the task. The DMA_Manage module 150 reads all descriptors back to the TLP sequentially, and after all descriptors have been read, it obtains the data packet and writes the data in the data packet into the corresponding descriptor table. The read address and length fields in the memory read packet are obtained from the task start message.
[0057] S150: Determine the data transfer task type based on the source end. If the data transfer task type is downlink, the Dest_Manage module 160 adds the address field to the downlink DMA transfer data and sends it to the external device. If the data transfer task type is uplink, the Dest_Manage module 160 adds the address field to the uplink DMA transfer data and sends it to the master device.
[0058] Among them, DMA (Direct Memory Access) does not involve register relocation, which can greatly improve transmission bandwidth and reduce transmission latency.
[0059] Specifically, since the sources of uplink and downlink data are different, the data migration task type can be determined based on the source. After the DMA_Manage module 150 finishes execution, the Dest_Manage module 160, based on the data migration task type, adds an address field to the downlink DMA migration data and sends it to the external device, and adds an address field to the uplink DMA migration data and sends it to the master device. This method parses and decomposes signaling messages and service messages at the source, forming a unified and effective chain management scheme, including message mechanisms, data migration mechanisms, and related components, thereby improving transmission bandwidth and reducing transmission latency. The mechanism formed by this method can cooperate with the host software and flexibly adapt to most buses, improving the overall system and interface utilization. It features high transmission efficiency, multi-port and multi-user support, multi-task support, and multi-message ring support, and is characterized by high efficiency, standardized operation, and independence from bus type.
[0060] In some implementations of this embodiment, if the data transfer task type is downlink, the Dest_Manage module 160 adds an address field to the downlink DMA transfer data and sends it to the external device. If the data transfer task type is uplink, the Dest_Manage module 160 adds an address field to the uplink DMA transfer data and sends it to the master device. Simultaneously, the Tx_arbiter module receives the DMA transfer data and the address field, determines the address field, and transmits the DMA transfer data sequentially according to the address field. This further improves the accuracy of DMA transfer data transmission.
[0061] In some embodiments of this example, if the message packet is a service message packet, the step of the Demux module 120 transmitting the parsed message packet to the DMA_Manage module 150 via the Tag_Manage module 140 includes:
[0062] The parsed business message packets are marked using the Tag_Manage module 140.
[0063] In some embodiments of this example, the steps of the DMA_Manage module 150 reading the descriptor back to the TLP based on message packets, and simultaneously reading the source and destination descriptors, include:
[0064] All descriptors are read back to the TLP sequentially via the DMA_Manage module 150;
[0065] Once all descriptors have been read, the data packet is obtained, and the data in the data packet is written into the corresponding descriptor table.
[0066] In some embodiments of this example, the step of determining the data migration task type based on the source end includes:
[0067] If the source is the master device, then the data migration task type is data downlink;
[0068] If the source is an external device, the data migration task type is data uplink.
[0069] In some embodiments of this example, the data migration task described above includes at least one or more of the following: from a single source to a single destination address, from a single source to multiple destination addresses, from multiple sources to a single destination address, and from data from multiple source addresses to multiple destination addresses.
[0070] Please refer to Figure 4 , Figure 4The diagram shown is a structural block diagram of a processor-based memory link management device provided in an embodiment of the present invention. This application provides a processor-based memory link management device, which includes a bus interface 110, a Demux module 120, a message execution module 130, a Tag_Manage module 140, a DMA_Manage module 150, and a Dest_Manage module 160.
[0071] Bus interface 110 is used to connect the master device and the external device.
[0072] Demux module 120 is used to acquire and parse message packets. If the message packet is a signaling message, the parsed message packet is sent to message execution module 130. If the message packet is a service message packet, the parsed message packet is transmitted to DMA_Manage module 150 via Tag_Manage module 140.
[0073] The message execution module 130 is used to receive and parse signaling messages, and to assemble and send the signaling messages into packets;
[0074] DMA_Manage module 150 is used to read descriptors back to TLP, while reading source and destination descriptors;
[0075] The Dest_Manage module 160 is used to send downlink DMA transfer data with an address field to the external device if the data transfer task type is downlink, and to send uplink DMA transfer data with an address field to the master device if the data transfer task type is uplink.
[0076] In the aforementioned implementation process, this device parses and decomposes signaling messages and service messages at the source, forming a unified and effective chain-like management scheme, including message mechanisms, data migration mechanisms, and related components, thereby improving transmission bandwidth and reducing transmission latency. The mechanism formed by this device can cooperate with host software and flexibly adapt to most buses, improving the overall system and interface utilization. It features high transmission efficiency, multi-port and multi-user support, multi-task support, and multi-message ring support, and is characterized by high efficiency, standardized operation, and independence from bus type.
[0077] In some embodiments of this example, the bus interface 110 includes a PCIe interface and an AXI interface. Specifically, this processor memory link management device can be flexibly applied to both PCIe and AXI interfaces, exhibiting high adaptability.
[0078] It should be noted that PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard with wide applications. PCIe is a high-speed serial point-to-point dual-channel high-bandwidth transmission, where each connected device is allocated its own dedicated channel bandwidth and does not share the bus bandwidth. It primarily supports active power management, error reporting, end-to-end reliable transmission, hot-plugging, and Quality of Service (QoS) functions. AXI (Advanced eXtensible Interface) is a widely used bus protocol, designed for high performance, high bandwidth, and low latency on-chip buses.
[0079] Please refer to Figure 5 , Figure 5 This is a schematic structural block diagram of an electronic device provided in an embodiment of this application. The electronic device includes a memory 101, a processor 102, and a communication interface 103. The memory 101, processor 102, and communication interface 103 are electrically connected to each other directly or indirectly to realize data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The memory 101 can be used to store software programs and modules, such as the program instructions / modules corresponding to the processor-stored link management device provided in an embodiment of this application. The processor 102 executes various functional applications and data processing by executing the software programs and modules stored in the memory 101. The communication interface 103 can be used for signaling or data communication with other node devices.
[0080] The memory 101 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.
[0081] The processor 102 can be an integrated circuit chip with signal processing capabilities. The processor 102 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
[0082] Understandable. Figure 5 The structure shown is for illustrative purposes only; the electronic device may also include components that are more advanced than those shown. Figure 5 The more or fewer components shown, or having the same Figure 5 The different configurations shown. Figure 5 The components shown can be implemented using hardware, software, or a combination thereof.
[0083] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0084] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0085] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0086] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
[0087] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.
Claims
1. A processor-based memory-based link management method, characterized in that, Includes the following steps: When responding to a data transfer task between the master device and an external device, the message packet is obtained and parsed through the Demux module; If the message packet is a signaling message, the Demux module sends the parsed message packet to the message execution module. The message execution module is used to receive and parse the signaling message, and to assemble and send the signaling message into packets. If the message packet is a business message packet, the Demux module will transmit the parsed message packet to the DMA_Manage module via the Tag_Manage module, and at the same time the DMA_Manage module will obtain the DMA task start message. Based on the message packet, the DMA_Manage module reads the descriptor back to the TLP, and reads out the source and target descriptors at the same time; Based on the source end, the data migration task type is determined. If the data migration task type is downlink, the Dest_Manage module adds an address field to the downlink DMA migration data and sends it to the external device. If the data migration task type is uplink, the Dest_Manage module adds an address field to the uplink DMA migration data and sends it to the master device.
2. The processor-based memory link management method according to claim 1, characterized in that, If the data transfer task type is downlink, the Dest_Manage module adds an address field to the downlink DMA transfer data and sends it to the external device. If the data transfer task type is uplink, the Dest_Manage module adds an address field to the uplink DMA transfer data and sends it to the master device. At the same time, the Tx_arbiter module receives the DMA transfer data and the address field, judges the address field, and transmits the DMA transfer data sequentially according to the address field.
3. The processor-based memory link management method according to claim 1, characterized in that, If the message packet is a business message packet, the step of the Demux module transmitting the parsed message packet to the DMA_Manage module via the Tag_Manage module includes: The parsed business message packets are marked using the Tag_Manage module.
4. The processor-based memory link management method according to claim 1, characterized in that, Based on the message packet, the DMA_Manage module reads the descriptor back to the TLP, and the steps of reading the source and destination descriptors simultaneously include: The DMA_Manage module sequentially reads all descriptors back to the TLP; Once all descriptors have been read, the data packet is obtained, and the data in the data packet is written into the corresponding descriptor table.
5. The processor-based memory link management method according to claim 1, characterized in that, The steps for determining the data migration task type based on the source end include: If the source end is the master device end, then the data migration task type is data downlink; If the source is the external device, then the data migration task type is data uplink.
6. The processor-based memory link management method according to claim 1, characterized in that, The data migration task includes at least one or more of the following: from a single source to a single destination address, from a single source to multiple destination addresses, from multiple sources to a single destination address, and from data from multiple source addresses to multiple destination addresses.
7. A processor-based memory link management device, characterized in that, This includes the bus interface, Demux module, message execution module, Tag_Manage module, DMA_Manage module, and Dest_Manage module: The bus interface is used to connect the master device and the external device. The Demux module is used to acquire and parse message packets. If the message packet is a signaling message, the parsed message packet is sent to the message execution module. If the message packet is a service message, the parsed message packet is transmitted to the DMA_Manage module via the Tag_Manage module. The message execution module is used to receive and parse the signaling message, and to assemble and send the signaling message into packets; The DMA_Manage module is used to read the descriptor back to the TLP, and at the same time read the source and target descriptors; The Dest_Manage module is used to send downlink DMA transfer data with an address field added to the external device if the data transfer task type is downlink, and to send uplink DMA transfer data with an address field added to the master device if the data transfer task type is uplink.
8. The processor-based memory link management device according to claim 7, characterized in that, The bus interfaces include PCIe and AXI interfaces.
9. An electronic device, characterized in that, include: Memory, used to store one or more programs; processor; When the one or more programs are executed by the processor, the method as described in any one of claims 1-6 is implemented.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-6.