Integrated pivot table in logical-to-physical mapping

Abstract

This disclosure relates to integrated pivot tables in logical to physical mappings. A memory system can receive a read command and read a first entry of a first subset of a mapping and a second entry of a second subset of the mapping. The second entry can include at least a portion of a pivot table associated with a physical address of a non-volatile memory device. Rather than accessing a different portion of the logical to physical mapping, the memory system can retrieve data from the physical address identified in the pivot table. The memory system can transmit the data retrieved from the physical address identified in the pivot table to a host system.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 17 / 315,015, filed on May 7, 2021, by D'Eliseo et al., entitled "INTEGRATED PIVOT TABLE IN ALOGICAL-TO-PHYSICALMAPPING," which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to integrated pivot tables in logical to physical mapping. Background Art

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically corresponding to a logical 1 or a logical 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any of these possible states. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D cross-point), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Unless periodically refreshed by an external power source, volatile memory cells (e.g., DRAM cells) may lose their programmed state over time. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods of time even in the absence of an external power source. Summary of the Invention

[0006] An apparatus is described. The apparatus may include a memory device and a controller coupled to the memory device. The controller may be configured to cause the apparatus to: receive a read command including a logical block address of a non-volatile memory device; read a first entry in a first subset of a map defining a relationship between the logical block address and a physical address based on the logical block address; read a second entry in a second subset of the map based on reading the first entry of the first subset, the second entry including at least a portion of a pivot table associated with the physical address of the non-volatile memory device; and transmit data retrieved from the physical address identified in the pivot table of the second subset of the map to a host system based on reading the second entry of the second subset of the map.

[0007] An apparatus is described. The apparatus may include a memory device and a controller coupled to the memory device. The controller may be configured to cause the apparatus to: receive a plurality of write commands for a set of physical addresses of a non-volatile memory device; determine, based on receiving the plurality of write commands, whether the set of physical addresses is contiguously indexed; set a flag in entries of a second subset of a mapping comprising a first subset, a second subset, and a third subset, based on the set of physical addresses being contiguously indexed, the entries of the second subset including at least a portion of a pivot table associated with the set of physical addresses; and write data to the set of physical addresses based, at least in part, on setting the flag.

[0008] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a read command including a logical block address of a non-volatile memory device; read a first entry in a first subset of a map defining a relationship between the logical block address and a physical address based on the logical block address; read a second entry in a second subset of the map based on reading the first entry of the first subset, the second entry including at least a portion of a pivot table associated with the physical address of the non-volatile memory device; and transmit data retrieved from the physical address identified in the pivot table of the second subset of the map to a host system based on reading the second entry of the second subset of the map.

[0009] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a plurality of write commands for a set of physical addresses of a non-volatile memory device; determine, based on receiving the plurality of write commands, whether the set of physical addresses is contiguously indexed; set a flag in entries of a second subset of a mapping comprising a first subset, a second subset, and a third subset based on the set of physical addresses being contiguously indexed, the entries of the second subset including at least a portion of a pivot table associated with the set of physical addresses; and write data to the set of physical addresses based, at least in part, on setting the flag. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a system supporting integrated pivot tables in logical to physical mapping according to examples as disclosed herein is described.

[0011] Figure 2 An example of an entry diagram supporting integrated pivot tables in logical to physical mapping according to examples as disclosed herein is illustrated.

[0012] Figure 3 An example of a pivot table structure supporting integrated pivot tables in logical to physical mapping according to examples as disclosed herein is illustrated.

[0013] Figure 4 An example of a read graph supporting integrated pivot tables in logical to physical mapping according to examples as disclosed herein is illustrated.

[0014] Figure 5 An example of a flow diagram illustrating integrated pivot tables in support of logical to physical mapping according to examples as disclosed herein.

[0015] Figure 6 An example of a flow diagram illustrating integrated pivot tables in support of logical to physical mapping according to examples as disclosed herein.

[0016] Figure 7 A block diagram showing a memory system supporting integrated pivot tables in logical to physical mapping according to examples as disclosed herein.

[0017] Figure 8 and 9 A flowchart illustrating one or more methods of supporting integrated pivot tables in logical to physical mapping according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0018] Some memory systems may use an addressing scheme that differs from that of an associated host system. For example, a host system may use logical addresses (e.g., logical block addresses (LBAs), virtual addresses, system addresses, or other logical addresses) to identify data, and the memory system may store the data at physical addresses that are independent of the logical addresses used by the host system. A physical address may identify the physical location of a corresponding memory cell (e.g., or page of memory cells) within a memory device. The physical location of data within a memory device may change over time due to the memory device accommodating the writing of additional data, maintenance operations performed by the memory device (e.g., garbage collection operations), or for other reasons. A host system coupled to the memory system may use the logical addresses to reference the data (e.g., when issuing read, write, or other commands associated with the data), and the memory system may generate and maintain a logical-to-physical (L2P) mapping between the logical addresses used for communication with the host system and the physical addresses of the memory cells storing the data.

[0019] A memory system may use a hierarchical L2P map divided into multiple subsets (or levels) to map logical addresses to corresponding physical addresses. The memory system may use the hierarchical L2P map to gradually convert logical block addresses to corresponding physical addresses. For example, a three-level L2P map may be divided into a relatively small first subset (e.g., or level), which may include entries pointing to different locations in a second subset (e.g., or level). The entries of the second subset may point to different locations in a third subset (e.g., or level), and the entries of the third subset may point to physical addresses of data pages stored in a memory device of the memory system. Thus, to access data stored in the memory device, the memory system may navigate through the three subsets to identify the location of the requested data page. This approach may allow the relatively small first subset to be stored in a volatile memory device of the memory system for fast access and updating, but may increase read latency by introducing additional operations such as two additional reads (e.g., to read entries in different subsets of the map) to identify the physical address of the data.

[0020] Described herein are techniques, systems, and devices for increasing performance and reducing latency associated with using an L2P map by embedding a pivot table in entries of a second subset of an L2P map to identify the physical address of data, thereby skipping reading entries of a third subset of the L2P map. For example, a memory system may receive a write command for a set of addresses and determine whether the set of addresses is consecutively indexed. The memory system may set a flag in the pivot table in entries of the second subset based on the fact that the set of addresses is consecutively indexed, and write data to the set of addresses in response to setting the flag. A flag in the entries of the second subset may be set to indicate that the entries of the second subset indicate a starting physical address.

[0021] In response to receiving a read command that includes an LBA corresponding to data, the memory system may traverse the first and second subsets of the L2P map to locate and read the data without accessing the third subset. For example, the memory system may read entries of the first subset corresponding to the LBAs and may identify entries of the second subset based on the first subset and the LBAs. The memory system may read entries of the second subset, which may include a pivot table. Using the pivot table, the memory system may identify the physical address associated with the LBA and access the data stored at the physical address. The memory system may then transmit the data to a host system coupled to the memory system. In this manner, the memory system can reduce the latency associated with using the L2P map to locate data stored at consecutively indexed physical addresses by including the pivot table in the second subset and eliminating the need to read the third subset to locate the data.

[0022] First, in reference Figure 1 The features of the present disclosure are described in the context of a system. Figures 2 to 6 The features of the present disclosure are described in the context of the drawings and structures of FIG. Figures 7 to 9 These and other features of the present disclosure are further illustrated and described in the context of device diagrams and flow charts involving integrated pivot tables in logical to physical mapping.

[0023] Figure 1 An example of a system 100 supporting integrated pivot tables in logical to physical mapping according to examples as disclosed herein is illustrated. The system 100 includes a host system 105 coupled to a memory system 110.

[0024] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0025] The computing system 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0026] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 can be coupled to any number of memory systems 110 .

[0027] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM socket interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more of these interfaces can be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, host system 105 may be coupled to memory system 110 via a respective physical host interface for each memory device 130 included in memory system 110, or via a respective physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0028] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but memory system 110 may include any number of memory devices 130. Furthermore, if memory system 110 includes more than one memory device 130, different memory devices 130 within memory system 110 may include the same or different types of memory cells.

[0029] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory devices 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory devices 130—as well as other such operations—which can generally be referred to as access operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0030] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0031] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuits with dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuit.

[0032] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or operations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may serve as a cache for the memory system controller 115. For example, data may be stored in the local memory 120 when read from or written to the memory device 130, and the data may be available within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a cache policy (e.g., reduced latency relative to the memory device 130).

[0033] although Figure 1 The example of the memory system 110 in FIG. 1 has been described as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, which may each be internal to the memory device 130, to perform the functions attributed herein to the memory system controller 115. In general, one or more functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof in some cases. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0035] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As illustrated, memory device 130-a may include a local controller 135-a, and memory device 130-b may include a local controller 135-b.

[0036] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, where each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0037] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as a multi-level cell (MLC) if configured to each store two bits of information, a triple-level cell (TLC) if configured to each store three bits of information, a quad-level cell (QLC) if configured to each store four bits of information, or more generally, a multi-level cell. Multi-level cells may provide higher storage density relative to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0038] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0039] In some cases, block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share (e.g., be coupled to) a common word line, and memory cells in the same string can share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0040] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level), but can be erased at a second level of granularity (e.g., at a block granularity level). That is, a page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single program or read operation), and a block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., erased in parallel as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 has been erased.

[0041] In some cases, to update some data within a block 170 while retaining other data within the block 170, the memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. The memory device 130 (e.g., the local controller 135) or the memory system controller 115 may mark or otherwise indicate the data remaining in the old block 170 as invalid or outdated and may update a logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 rather than the old invalid block 170. For example, in some cases, due to latency or wear considerations, this copying and remapping may be performed rather than erasing and rewriting the entire old block 170. In some cases, one or more copies of the L2P mapping table may be stored within a memory location of the memory device 130 (e.g., within one or more blocks 170 or planes 165) for use (e.g., reference and updating) by the local controller 135 or the memory system controller 115.

[0042] In some cases, an L2P mapping table may be maintained and data may be marked as valid or invalid at a page-level granularity, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be data that is outdated because the latest or updated version of the data is stored in a different page 175 of the memory device 130. Invalid data may have been previously programmed to an invalid page 175 but may no longer be associated with a valid logical address, such as a logical address referenced by the host system 105. Valid data may be the latest version of such data stored on the memory device 130. A page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0043] In some cases, the memory system controller 115 or the local controller 135 may perform operations for the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background flushing, garbage collection, scrubbing, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in a block 170 to have invalid data so that the block 170 can be erased and reused, an algorithm known as "garbage collection" may be invoked to allow the block 170 to be erased and freed as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that includes, for example, selecting a block 170 containing both valid and invalid data, selecting a page 175 in the block containing valid data, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected page 175 as invalid, and erasing the selected block 170. Thus, the number of erased blocks 170 may be increased so that more blocks 170 may be used to store subsequent data (eg, data subsequently received from the host system 105 ).

[0044] The system 100 may include any number of non-transitory computer-readable media that support integrated pivot tables in logical-to-physical mapping. For example, the host system 105, the memory system controller 115, or the memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), such instructions may cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0045] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0046] In some cases, during a read operation, the memory system 110 may receive a read command, read entries of a first subset of a mapping (e.g., a root mapping of a logical-to-physical mapping), read entries of a second subset of the mapping (e.g., a global mapping of a logical-to-physical mapping), and transfer the data to the host system 105. In such cases, the memory system 110 may read from the pivot table included in the entries of the second subset of the mapping. In some examples, during a write operation, the memory system 110 may receive a write command to write data to consecutive physical addresses, write the data to the physical addresses, and set a consecutive flag in the entry of the pivot table included in the second subset of the mapping (e.g., the global mapping).

[0047] Figure 2 An example of an item diagram 200 supporting an integrated pivot table in a logical to physical mapping according to an example disclosed herein is illustrated. The item diagram 200 may implement a reference Figure 1 For example, the item map 200 may be configured as shown in FIG. Figure 1 The described controller (such as memory system controller 115 or local controller 135) or memory device (such as memory device 130), or both, may implement the entry map 200 to reduce latency and power consumption, and increase performance of a memory system, among other benefits.

[0048] Entries map 200 depicts a map 205 that may correspond to an L2P map as described herein. For example, map 205 may be an example of a hierarchical L2P map that is divided into a plurality of subsets 210. Map 205 may include at least subset 210-a, subset 210-b, and subset 210-c. A controller may maintain map 205 to map LBAs generated by a host system coupled to a memory system to physical addresses 235 (e.g., page addresses) of a non-volatile memory device 215 (e.g., a memory device 130 including non-volatile memory cells, such as a NAND device) of the memory system.

[0049] Subset 210-a may be an instance of a root hierarchy or root map (e.g., a first subset of map 205). Subset 210-a may include entries 220-a through 220-w, where w is some positive integer. In some cases, subset 210-a may include a relatively small number of entries 220 (e.g., w may be a relatively small positive integer), so that a controller may store subset 210-a in a volatile memory device of a memory system (e.g., local memory 120, memory device 130 including volatile memory cells, an SRAM device) to allow for faster access and updates.

[0050] Subset 210-b may be an instance of a global hierarchy or global map (e.g., a second subset of map 205). Subset 210-b may include entries 225-a through 225-x, where x is some positive integer. In some examples, subset 210-b may include a relatively large number of entries 225 (e.g., x may be a relatively large positive integer), such that a controller may store subset 210-b in non-volatile memory device 215 (e.g., at physical address 235, not shown). Therefore, to read entries 225 of subset 210-b, the controller may transfer a portion of subset 210-b, including entries 225, from non-volatile memory device 215 to a volatile memory device. After reading entries 225, the controller may transfer a portion of subset 210-b back to non-volatile memory device 215.

[0051] Subset 210-c may be an instance of an L2P hierarchy or L2P map (e.g., the third subset of map 205). In some examples, subset 210-c may be an instance of a physical page table (PPT) hierarchy or PPT map. Subset 210-c may include entries 230-a through 230-y, where y is some positive integer. In some examples, subset 210-c may include a relatively large number of entries 230 (e.g., y may be a relatively large positive integer), such that a controller may store subset 210-c in non-volatile memory device 215 (e.g., at physical address 235, not shown). Therefore, to read entries 230 of subset 210-c, the controller may transfer a portion of subset 210-c, including entries 230, from non-volatile memory device 215 to a volatile memory device. After reading entries 230, the controller may transfer a portion of subset 210-c back to non-volatile memory device 215.

[0052] In some examples, each subset 210 may be a separate L2P mapping table stored in the memory system. For example, subset 210-a may be a first-level L2P mapping table stored in a volatile memory device. Here, each entry 220 may point to a different second-level L2P table. For example, subset 210-b may include multiple second-level L2P tables, each of which includes a corresponding set of entries 225. Here, the controller can use the entry 220 and an offset (e.g., indicated by an LBA) to determine the corresponding entry 225 within the second-level L2P table pointed to by the entry 220. Furthermore, in some cases, each entry 225 may point to a different third-level L2P table. For example, subset 210-c may include multiple third-level L2P tables, each of which includes a corresponding set of entries 230. Here, the controller can use the entry 225 and a second offset (e.g., indicated by an LBA) to determine the corresponding entry 230 within the third-level L2P table pointed to by the entry 225.

[0053] For example, the controller may use the LBA to identify entry 220 of subset 210-a, use entry 220 to identify entry 225 of subset 210-b, use entry 225 to identify entry 230 of subset 210-c, and use entry 230 to identify physical address 235 corresponding to the LBA. That is, to identify corresponding physical address 235, the controller may, in some cases, traverse the first, second, and third levels of map 205. However, traversing the three levels of map 205 may include transferring portions of subsets 210-a, 210-b, and 210-c to the volatile memory device to read the various entries. Each entry of map 205 read and the portion of subset 210 transferred may increase the latency associated with using map 205 (e.g., identifying corresponding physical address 235). Therefore, techniques for reducing the number of entries of map 205 read and the portion of subset 210 transferred may reduce the latency associated with using map 205.

[0054] The controller can reduce the number of entries of map 205 that are read and (by extension) the number of portions of subset 210 that are transferred to the volatile memory device by setting entry 225 to indicate physical address 235 instead of entry 230. For example, if the data stored in the set of physical addresses 235 is indexed consecutively, the controller can set entry 225 to indicate a starting physical address 235a in the set of consecutively indexed physical addresses 235. For example, data corresponding to a first LBA can be stored at a consecutively indexed set of physical addresses 235 that includes at least physical address 235-a, physical address 235-b, and physical address 235-c, where physical address 235-a is the starting physical address in the set of consecutively indexed physical addresses 235.

[0055] The controller may set entry 225-a to indicate physical address 235-a. For example, entry 225-a may include flag 240 and at least a portion of pivot table 250. Flag 240 may indicate whether entry 225 is associated with entry 230 of subset 210-c or with starting physical address 235a in a set of consecutively indexed physical addresses 235. Pivot table 250 may include multiple entries, where entries in the multiple entries represent a plurality of consecutively indexed logical block addresses and instructions for identifying starting physical address 235a in the plurality of consecutively indexed physical addresses 235. To address increasing amounts of data associated with a host system (e.g., user data) that can fit within map 205 (e.g., 1 MB), the controller may determine whether the data comprises sequential data. For example, the controller may determine whether blocks can be logically and physically written in sequential order (e.g., consecutively indexed).

[0056] Based on flags 240 and pivot table 250, the physical address of entry 225-a may correspond to the physical address of entry 230 or the starting physical address 235-a. Figure 2 In the example of , the controller may set flag 240 of entry 225-a to indicate that entry 225-a corresponds to a consecutively indexed set of physical addresses 235. Additionally, the controller may read entry 225-a (e.g., an entry including pivot table 250) to indicate starting physical address 235-a. In this way, the controller may set entry 225-a to avoid (e.g., skip) reading and transferring a portion of subset 210-c including entry 230. For example, the controller may receive a read command including a first LBA (e.g., from a host system). The controller may use the first LBA to identify and read entry 220-a, and the controller may use entry 220-a to identify and read entry 225-a. Based on flag 240, the controller may determine that pivot table 250 indicates starting physical address 235-a and may read data corresponding to the first LBA starting at physical address 235-a. The controller may then transmit the data to the host system.

[0057] In some cases, the LBA used to identify entry 220 of subset 210-a (e.g., and subsequently entry 225 of subset 210-b) may not correspond to a physical address in pivot table 250. In such cases, pivot table 250 may indicate a starting physical address 235a corresponding to a starting LBA. For example, the controller may determine the difference between the LBA in the command and the starting LBA. The controller may then use the determined difference between the LBA and the starting LBA to identify physical address 235. For example, the controller may combine the difference between the LBA and the starting physical address stored in the pivot table to determine the desired physical address. In some examples, the controller may use entry 220 and an offset (e.g., the difference between the LBA and the starting LBA) to determine a corresponding entry 225 within the second-level L2P table pointed to by entry 220. The controller may use entry 225 and a second offset (e.g., the difference between the LBA and the starting LBA) to determine a corresponding entry 230 within the third-level L2P table pointed to by entry 225.

[0058] To increase the range of LBAs addressable by map 205, the system may integrate pivot table 250 into map 205. For example, pivot table 250 may be generated and integrated into subset 210-b of map 205. In such cases, by embedding pivot table 250 into subset 210-b, the range of LBAs addressable by the controller without accessing the NAND can be increased, thereby improving overall system performance and reducing latency. In some instances, a pivot table may be an example of a data structure or map that summarizes or compresses information associated with a broader data structure or map. In some cases, a pivot table may be an example of a compressed version of the physical addresses associated with the memory system.

[0059] Alternatively, data may be stored at a set of physical addresses 235 that includes one or more physical addresses 235 that are non-contiguous with respect to other sets of physical addresses 235. For example, data corresponding to a second LBA may be stored at a set of physical addresses 235 that includes at least non-contiguous physical address 235-d. Consequently, the controller may identify pointer 245 to indicate that entry 225-b is associated with entry 230 (e.g., entry 230-a) (indicating the physical address of entry 230). Additionally, the controller may identify pointer 245 for entry 225-b to indicate entry 230-a (e.g., to include the physical address of entry 230-a) and may set entry 230-a to indicate physical address 235-d. In such cases, the controller may avoid setting flag 240. The controller may read a second entry (e.g., entry 225-b), which includes pointer 245 and represents a logical block address that is non-contiguously indexed with respect to other logical block addresses.

[0060] Thus, in response to receiving a read command including the second LBA, the controller can use the second LBA to identify and read entry 220-b. The controller can then use entry 220-b to identify and read entry 225-b. The controller can determine that pointer 245 indicates the physical address of entry 230-a. Therefore, the controller can identify and read entry 230-a, identify physical address 235-d, and read the data corresponding to the second LBA stored at physical address 235-d. The controller can then transmit the data to the host system.

[0061] In some cases, the range of LBAs that can be addressed from the controller without having to fetch (e.g., retrieve) the L2P map from the NAND to determine where data can be stored can be increased. In some systems, a one (1) GB addressing range can utilize one (1) MB of embedded SRAM to store a certain number of L2P maps (e.g., 1024 KB divided by 4B times 4KB). To scale (e.g., increase the addressing range), the system can increase the map data size from 4KB to 512KB.

[0062] In some examples, entries 230 of subset 210 - c may be 4B in size and managed as 4KB units on a 2048GB device, as illustrated in Table 1.

[0063] Mapping Subsets Physical table size Cache size type Record size Mapping Area Subset 210-a 2KB 2KB Static 4B 4GB Subset 210-b 2MB 8-32KB Static 4B 4MB Subset 210-c 2GB 256-1024KB dynamic 4B 4KB

[0064] Table 1

[0065] The physical table size supporting a 2048GB drive may include a subset 210-a of 2KB (e.g., 512 entries (e.g., entry 220) multiplied by 4B (e.g., record size)). The physical table size supporting a 2048GB drive may include a subset 210-b of 2MB (e.g., 512 entries multiplied by 1024 entries (e.g., entry 225) multiplied by 4B). The physical table size supporting a 2048GB drive may include a subset 210-c of 2GB (e.g., 512 entries multiplied by 1024 entries (e.g., entry 230) multiplied by 4B). The L2P cache (e.g., subset 210-c) addressing range may be 1GB (e.g., 1024KB divided by 4B entries multiplied by 4KB). In other examples, entries 230 of subset 210 - c may be 4B in size and managed as 4KB units on a 2048GB device, as illustrated in Table 2.

[0066]

[0067]

[0068] Table 2

[0069] In some instances, the size of subset 210-c may be 1024KB (e.g., LBA), the range of the pivot table 250 included in subset 210-b may be 128 (e.g., LBA), and the pivots of each PPT may be 8 (e.g., 1024 entries (the size of subset 210-c) divided by 128 pivot ranges (e.g., the ranges of the pivot table 250)). The physical table size to support a 2048GB drive may include a subset 210-a of 16KB (e.g., 512 entries 220 multiplied by 8 (e.g., the pivots of each table) multiplied by 4B (e.g., the record size)). The physical table size to support a 2048GB drive may include a subset 210-b of 16MB (e.g., 512 entries 220 multiplied by 8 (e.g., the pivots of each table) multiplied by 1024 entries 225 multiplied by 4B (e.g., the record size)). The physical table size supporting a 2048GB drive may include a subset 210c of 2048MB (e.g., 512 entries 220 multiplied by 1024 entries 225 multiplied by 1024 entries 230 multiplied by 4B (e.g., record size)). The global cache (e.g., subset 210-b) (e.g., for direct data) may have an addressing range of 128GB (e.g., 1MB divided by 4B entries 225 multiplied by 128 (e.g., the range of pivot table 250) multiplied by 4KB). The L2P cache (e.g., subset 210-c) may have an addressing range of 1GB (e.g., 1MB divided by 4B entries 225 multiplied by 4KB).

[0070] By integrating pivot table 250 into subset 210-b, the size of the mapping for subset 210-b can be increased from 2MB to 16MB. In this case, subset 210-b can store an increased number of pointers. The granularity of the mapping area for subset 210-b can be updated from 4MB to 0.5MB (e.g., 512KB). By increasing the size of subset 210-b, the system can handle an increased amount of data. Instead of addressing 1GB of address space, if the controller determines that the physical addresses are sequential (e.g., continuously indexed), the controller can address 128GB of address space.

[0071] Figure 3 An example of a pivot table structure 300 supporting integrated pivot tables in logical to physical mapping according to an example disclosed herein is illustrated. The pivot table structure 300 may be implemented as shown in FIG. Figure 1 and 2 The system 100 and item graph 200 described herein are described in detail. For example, the pivot table structure 300 may be configured as shown in FIG. Figure 1The described controller (such as memory system controller 115 or local controller 135) or memory device (such as memory device 130), or both, may implement the pivot table structure 300 to reduce latency and power consumption, and increase performance of a memory system, among other benefits.

[0072] The pivot table structure 300 may include an L2P table 305 and a pivot table 310. The L2P table 305 may include entries 315-a through 315-w, where w is some positive integer. For example, w may be 1024, where the L2P table 305 may include 1024 entries 315. Each entry 315 of the L2P table 305 may include a physical address and point to a 4K entry. The L2P table 305 may include intervals 325, where each interval 325 includes a certain number of entries 315. For example, each interval 325 may include 128 entries 315. In such a case, entries 315 (e.g., sampled physical address values) may be selected per 128 intervals 325. The number of entries 315 in an interval 325 (e.g., 128) may be an example of a pivot range. In some cases, the L2P table 305 may be an example of a PPT.

[0073] In some cases, the physical addresses in each of the 128 blocks (e.g., interval 325) may contain sequential data and may be invalid or valid data. For example, entry 315-a of interval 325-a may contain sequential valid data. Entry 315-b of interval 325-b may contain sequential invalid data. The memory system may store the first entry 315 (e.g., physical address) of each interval 325 in pivot table 310, which may enable the memory system to retrieve relevant information from the map.

[0074] The pivot table 310 may include a plurality of entries 320-a through 320-x, where x is some positive integer. For example, x may be 8, in which case the pivot table 310 may include eight entries 320. The number of entries 320 in the pivot table 310 may be an instance of a pivot for each physical page table. To generate the pivot table 310, the memory system may include a first entry 315 for each interval 325 of the L2P table 305. For example, the pivot table 310 may include at least a first entry 315-a for the first interval 325-a, a first entry 315-b for the second interval 325-b, and a first entry 315-c for the third interval 325-c. In such a case, the pivot table 310 may include a first entry 315 for each of the eight intervals 325 of the L2P table 305. In some cases, the memory system may include a pivot table 310 for each L2P table 305 or a fragment of an L2P table 305.

[0075] In some cases, entry 320-a (e.g., first entry 315-a including first interval 325-a) may represent a plurality of logical block addresses indexed consecutively and an instruction to identify a starting physical address of the plurality of physical addresses indexed consecutively. The physical address may correspond to the logical block address. In some instances, entry 320-b (e.g., first entry 315-b including second interval 325-b) may represent a plurality of logical block addresses including invalid data. Pivot table 310 may summarize information about the physical addresses in a 128-entry block (e.g., interval 325).

[0076] The memory system may receive a request to perform a read or write operation and generate pivot table 310. To generate pivot table 310, the memory system may replace an entry of a second subset of the mapping (e.g., a global hierarchy or a global map) with pivot table 310. In some systems, the first entry of the second subset of the mapping may include a pointer. In such cases, the memory system may replace the pointer with at least a portion of pivot table 310. In response to receiving the write command, the memory system may store the pivot table in the entry of the second subset of the mapping.

[0077] For example, pivot table 310 may be embedded within the second subset of the mapping. In this case, the memory system may receive a read command associated with the first logical block address. The memory system may read an entry (e.g., entry 320-a) of pivot table 310 included in the second subset of the mapping, and entry 320-a may indicate whether the address is consecutively indexed or the starting physical address of a plurality of physical addresses associated with the third subset of the mapping. The memory system may retrieve and transfer data based on entry 320-a of pivot table 310.

[0078] The memory system may use L2P table 305 to convert logical block addresses to physical addresses. The size of L2P table 305 may be larger than what can be maintained in system-on-chip (SoC) memory. In such cases, a subset of L2P table 305 may be stored in memory, and the remaining subset of L2P table 305 may be stored in NAND. The subset of L2P table 305 may include LBAs that are written sequentially. In such cases, the memory system may generate a compressed representation of L2P table 305 based on the sequentially written data. Pivot table 310 may include a compressed subset of L2P table 305 and may be stored in SoC memory. In some cases, a bitmap pivot table may be used to verify that the logical block addresses were written to the physical addresses in a sequential order or that they were written out of order through random writes.

[0079] A bitmap pivot table can be generated starting with the value of pivot table 310 as the basis for the second "expected physical address" and using that value to compare with the range of corresponding values ​​in L2P table 305. If the value from L2P table 305 can be kept in sync with the sequence of the "expected physical addresses" of pivot table 310, then the associated bit in the bitmap pivot table can be set. If the L2P table 305 value fails to follow that sequence, then the bitmap pivot table can be cleared to 0. In some cases, entry 320-b of pivot table 310 may contain invalid data. In such cases, the bitmap pivot table for the sequence of 128 logical block addresses (e.g., interval 325-b) can be cleared to 0. The bitmap pivot table may include a bit for each of the 128 logical block addresses represented by entry 320 of pivot table 310.

[0080] Each entry 320 of the pivot table 310 may represent a set of 128 logical block addresses, where the value of the first physical address (e.g., entry 315-a) may be recorded as entry 320-a of the pivot table 310. The first entry 320-a of the pivot table 310 may include a set of physical addresses written sequentially. In such a case, the bitmap pivot table may be written with 1's. The second entry 320-b of the pivot table 310 may include invalid data. In such a case, the bitmap pivot table may be written with 0's. The third entry 320-c may include a combination of physical addresses written sequentially and random physical addresses. In such a case, the bitmap pivot table may be written with a combination of 1's and 0's.

[0081] In some examples, the memory system can identify entry 320 (e.g., PBA(n)) from LBA(n) by using the starting LBA (e.g., LBA(0)) and the starting physical address (e.g., entry 320-a) stored in pivot table 310. Entry 320-a can be an instance of PBA(0). For example, the memory system can determine the difference between LBA(n) and the starting LBA (e.g., LBA(0)). The difference can be used to identify entry 320 (e.g., PBA(n)). In such cases, by compressing the data, the memory system can execute an algorithm to determine the physical address of entry 320.

[0082] Figure 4 An example of a read graph 400 supporting an integrated pivot table in a logical to physical mapping according to an example disclosed herein is illustrated. The read graph 400 may be implemented as described in reference Figures 1 to 3 For example, the reading diagram 400 may be obtained by referring to Figure 1 The described embodiments are implemented by a controller (such as memory system controller 115 or local controller 135) or a memory device (such as memory device 130), or both.

[0083] The read map 400 depicts operations that may correspond to read operations as described herein. The read map 400 may include at least a subset 410-a, a subset 410-b, and a non-volatile memory device 415, which may be as described in reference Figure 2 The examples of the described subset 210-b, subset 210-c and non-volatile memory device 215. The subset 410-a may be as shown in FIG. Figure 3 An example of a pivot table 310 is depicted.

[0084] Subset 410-a may be an instance of a global hierarchy or global map (e.g., a second subset of a map). Subset 410-a may include entries 425-a through 425-x, where x is some positive integer. For example, subset 410-a may include eight entries 425. Subset 410-b may be an instance of an L2P / PPT hierarchy or map (e.g., a third subset of a map). Subset 410-b may include entries 430-a through 430-y, where y is some positive integer. Non-volatile memory device 415 may include physical addresses 435-a through 435-z, where z is some positive integer.

[0085] In some cases, each entry 425 may point to subset 410-b or non-volatile memory device 415. For example, entry 425 may point to non-volatile memory device 415. Data corresponding to a first LBA may be stored at a set of consecutively indexed physical addresses 435, the set of consecutively indexed physical addresses 435 including at least physical address 435-a and physical address 435-b, where physical address 435-a is the starting physical address in the set of consecutively indexed physical addresses 435. The memory system may set entry 425-a to indicate physical address 435-a. For example, entry 425-a may indicate the starting physical address 435 in the set of consecutively indexed physical addresses 435. In such a case, entry 425-a may correspond to the set of consecutively indexed physical addresses 435.

[0086] The memory system may perform a sequential read 405 to read entry 425-a (e.g., an entry containing a pivot table) to indicate a starting physical address 435-a. In this manner, the memory system may set entry 425-a to avoid (e.g., skip) reading and transferring a portion of subset 410-b containing entry 430. For example, the memory system may receive a read command containing a first LBA (e.g., from a host system). The memory system may use the first LBA to identify (e.g., read) entry 425-a. The memory system may determine that entry 425-a indicates a starting physical address 435-a and may read data corresponding to the first LBA starting at physical address 435-a. The memory system may then transfer the data to the host system.

[0087] In other examples, the memory system may use the LBA to identify (e.g., read) entry 425, where entry 425 may not be a starting physical address (e.g., may not indicate starting physical address 435-a). For example, if the LBA in the read command is LBA(n) where n is greater than zero (0) (e.g., not a starting LBA), the memory system may use PBA(0) and LBA(n) to identify PBA(n). The memory system may read data corresponding to the LBA starting at physical address 435 (e.g., PBA(n)). In such cases, the physical address may correspond to a logical block address.

[0088] In some examples, entry 425 may point to non-volatile memory device 415. In such cases, data may be stored at a set of physical addresses 435 that includes one or more physical addresses 435 that are non-contiguous from other sets of physical addresses 435. For example, data corresponding to a second LBA may be stored at a set of physical addresses 435 that includes at least non-contiguous physical address 435-z. The memory system may recognize that entry 425-b is associated with entry 430 (e.g., entry 430-a) (indicating the physical address of entry 430). The memory system may set entry 430-a to indicate physical address 435-z.

[0089] In some examples, the memory system may use entry 425-b and an offset (e.g., indicated by an LBA) to determine the corresponding entry 230 within subset 410-b pointed to by entry 425-b. In such cases, the memory system may use entry 425-b to identify entry 430 of subset 410-b and use entry 430 to identify a physical address 435 corresponding to the LBA. The physical address of entry 425-b may correspond to the physical address of entry 430 (e.g., entry 430-a). The memory system may read a second entry (e.g., entry 425-b) representing a logical block address that is not indexed consecutively with the other logical block addresses. The memory system may identify and perform a random read 420 to read entry 430-a to identify physical address 435-z, and then perform a read 440 to read data corresponding to the second LBA stored at physical address 235-z. The memory system may then transfer the data to the host system.

[0090] In some systems, subset 410-a may include a single pointer. By embedding the pivot table within subset 410-a, the number of pointers can be increased from a single pointer to eight pointers (e.g., eight entries 425). For example, entry 425-a may point to non-volatile memory device 415, and entry 425-b may point to subset 410-b. In such cases, subset 410-a may include a mix of pointers that may point to subset 410-b or non-volatile memory device 415. The granularity of subset 410-a can be reduced from each entry 425 pointing to 4MB to each entry 425 pointing to 512KB, thereby increasing the overall performance of the memory system. In such cases, each of the eight entries 425 points to 512KB, which is equal to the total 4MB pointed to by subset 410-a.

[0091] To expand the addressable range of logical block addresses, each 4MB pointer in subset 410-a can be replaced with a pivot table segment. The pivot table entries defined by the pivot table range can divide each 4MB physical address in subset 410-a into multiple entries 425, which can point directly to sequential data in the NAND or, if the data is random, to the L2P mapping level (e.g., subset 410-b). For example, the size of the PPT (e.g., 1024 entries) divided by the pivot range (e.g., 128 entries per interval) equals the number of entries 425 in subset 410-a (e.g., 8 entries 425).

[0092] Data can be compressed by each 4B entry in subset 410-a that directly points to sequential data in the NAND (e.g., non-volatile memory device 415), while similar L2P mapping entries may be unused. For example, if each entry 425 in subset 410-a represents 512KB, the compression ratio is 128:1. Data compression can be expressed by the number of mapped logical block addresses in a 1MB controller SRAM buffer. The lower limit of the size of the mapped logical block address can be equal to 1MB divided by the 4B physical address multiplied by the data pivot range (e.g., 128) multiplied by 4KB. In such a case, the lower limit of the size of the mapped logical block address can be 128GB. For example, each 4B physical address can point to 512KB of sequential data. The number of mapped logical block addresses can depend on the data.

[0093] If the order of logical block addresses can be written out of sequence into the NAND, entry 425 of subset 410-a may point to subset 410-b, and the memory system may extract the L2P from the NAND (e.g., nonvolatile memory device 415). In some cases, a 512KB pivot range may be used to track sequential data.

[0094] A read command associated with sequential read 405 may directly address the NAND, and sequential physical addresses stored in subset 410-a may be incremented one by one to read the associated data. A read command associated with random read 420 may be associated with a non-sequential physical address, and the memory system may extract (e.g., retrieve) the associated L2P level map (e.g., subset 410-b) to directly address data of the non-volatile memory device 415 associated with the host system.

[0095] Figure 5 An example of a flowchart 500 illustrating an integrated pivot table in support of logical to physical mapping according to an example disclosed herein. The operations of the flowchart 500 may be implemented by any device or component thereof as described herein. For example, the operations of the flowchart 500 may be implemented by any device or component thereof as described herein. Figure 1 The memory system described herein performs the following steps. Alternative examples of the following may be implemented, wherein some steps are performed in a different order or not performed at all. Some steps may also include additional features not described below. Flowchart 500 illustrates a technique by which a memory system may perform read operations using an integrated pivot table in a logical-to-physical mapping.

[0096] Aspects of flowchart 500 may be implemented by a controller and other components. Additionally or alternatively, aspects of flowchart 500 may be implemented as instructions stored in a controller (e.g., a controller coupled to a memory system). For example, when executed by a controller (e.g., memory system controller 115), the instructions may cause the controller to perform the operations of flowchart 500.

[0097] At 505, a read command may be received. For example, the memory system may receive the read command. The read command may include a logical block address of the non-volatile memory device. At 510, a first entry may be read. For example, the memory system may read a first entry of a first subset of a map based at least in part on the logical block address. In some cases, the first entry may define a relationship between the logical block address and a physical address. The first subset of the map may be an instance of a root map or root hierarchy.

[0098] At 515, a second entry can be read. For example, the memory system can read a second entry of a second subset of the mapping based at least in part on reading the first entry of the first subset. In some cases, the second entry can include at least a portion of a pivot table associated with a physical address of the non-volatile memory device. The second subset of the mapping can be an instance of a global mapping or global hierarchy.

[0099] In some examples, the second entry of the second subset may include a flag indicating whether the second entry is associated with a third subset of the mapping or is associated with a starting physical address in a set of physical addresses associated with the read command. The third subset of the mapping may be an instance of an L2P mapping or an L2P hierarchy. In other examples, the third subset of the mapping may be an instance of a PPT mapping or a PPT hierarchy. In some cases, the pivot table for the second subset of the mapping may include a flag indicating whether the physical addresses are indexed consecutively (e.g., continuously).

[0100] The pivot table may include multiple entries, where an entry in the multiple entries may represent multiple logical block addresses indexed consecutively. In such cases, an entry in the pivot table may identify a starting physical address in the multiple physical addresses indexed consecutively. The multiple physical addresses may correspond to multiple logical block addresses. In some examples, the memory system may read a second entry of a second subset of the mapping by reading an entry in the multiple entries. For example, the memory system may read a first entry (e.g., a fragment of the pivot table). In some cases, an entry in the pivot table may point to a third level of the mapping (e.g., an L2P table or a PPT).

[0101] At 520, a determination can be made. For example, the memory system can determine whether the physical addresses in the set of physical addresses are consecutively indexed in response to reading the second entry of the second subset of the map. In such cases, the memory system can determine whether the physical addresses associated with the read command are consecutive and determine whether to set a flag based on the physical addresses being consecutive. In some examples, the memory system can determine that the physical addresses are consecutively indexed.

[0102] At 525, the user data may be retrieved. For example, the memory system may retrieve data from the non-volatile memory device at the physical address identified using the pivot table of the second entry directly in response to determining that the physical address is indexed consecutively. The data may be retrieved from the physical address without reading the third subset of the mapping. In some examples, the data may correspond to user data from the non-volatile memory device.

[0103] In some cases, the memory system may avoid reading a third entry of a third subset of the mapping based on a flag indicating that the second entry of the second subset of the mapping is associated with a physical address of the non-volatile memory device. The memory system may avoid transferring at least a portion of the third subset of the mapping from the non-volatile memory device to the volatile memory device based on a flag indicating that the second entry of the second subset of the mapping is associated with the physical address of the non-volatile memory device. In such cases, the memory system may avoid reading the third subset of the mapping or avoid loading the third subset of the mapping, or both, in response to determining that the physical addresses are consecutively indexed.

[0104] At 530, a starting physical address may be identified. For example, the memory system may identify a starting physical address from a plurality of physical addresses indexed consecutively using the pivot table of the second entry. The memory system may identify the physical address to be accessed based on the starting logical block address and the difference between the starting logical block address and the logical block address. In such cases, the memory system may identify the starting address and determine the offset.

[0105] At 535, data can be transferred. For example, the memory system can transfer data retrieved from the physical address identified in the pivot table of the second subset of the mapping to the host system in response to reading the second entry of the second subset of the mapping. In some cases, transferring the data can be in direct response to determining that the physical address is continuously indexed and retrieving the data.

[0106] In some examples, the memory system may determine that the physical addresses are not indexed consecutively (e.g., randomly). In this case, at 540, a portion of the third subset may be transferred. For example, the memory system may transfer at least a portion of the third subset of the mapping from the non-volatile memory device to the volatile memory device based on a flag indicating that the second entry of the second subset of the mapping is associated with the physical address of the non-volatile memory device. In such cases, the memory system may transfer at least the portion of the third subset of the mapping to the volatile memory device directly in response to determining that the physical addresses are not indexed consecutively.

[0107] At 545, the third entry can be read. For example, the memory system can read the third entry of the third subset of the mapping based on a flag indicating that the second entry of the second subset of the mapping is associated with a physical address of the non-volatile memory device. The memory system can read the third entry of the third subset in response to transferring the portion of the third subset of the mapping.

[0108] The data can be transferred at 550. For example, the memory system can transfer data retrieved from the physical address identified in the pivot table of the second subset of the map to the host system in response to reading the third entry of the third subset of the map.

[0109] Figure 6 An example of a flowchart 600 illustrating an integrated pivot table in support of logical to physical mapping according to an example disclosed herein. The operations of the flowchart 600 may be implemented by any device or component thereof as described herein. For example, the operations of the flowchart 600 may be implemented by any device or component thereof as described herein. Figure 1 The memory system described herein performs the following steps. Alternative examples of the following may be implemented, wherein some steps are performed in a different order or not performed at all. Some steps may also include additional features not described below. Flowchart 600 illustrates a technique by which a memory system may perform write operations using an integrated pivot table in a logical-to-physical mapping.

[0110] Aspects of flowchart 600 may be implemented by a controller and other components. Additionally or alternatively, aspects of flowchart 600 may be implemented as instructions stored in a controller (e.g., a controller coupled to a memory system). For example, when executed by a controller (e.g., memory system controller 115), the instructions may cause the controller to perform the operations of flowchart 600.

[0111] At 605, a write command may be received. For example, the memory system may receive multiple write commands for a set of physical addresses of a non-volatile memory device. At 610, a pivot table may be identified. For example, in response to receiving the multiple write commands, the memory system may identify that the pivot table is included in the second subset of the mapping. In such cases, the pivot table may be identified in a global mapping or a global hierarchy. The memory system may generate the pivot table to be included in the second subset of the mapping directly in response to receiving the multiple write commands. In some cases, the memory system may replace an entry in the second subset of the mapping containing a pointer with at least a portion of the pivot table. For example, the pointer of the second subset of the mapping may be replaced with the pivot table.

[0112] The pivot table may include a plurality of entries, wherein a first entry of the plurality of entries may represent a plurality of consecutively indexed logical block addresses. The pivot table may identify a starting physical address of the consecutively indexed plurality of physical addresses, wherein the plurality of physical addresses correspond to the plurality of logical block addresses.

[0113] At 615, the pivot table can be stored. For example, the memory system can store at least a portion of the pivot table in entries of the second subset of the mapping in response to receiving the plurality of write commands. In some examples, the memory system can store the portion of the pivot table in response to generating the pivot table, identifying the pivot table, replacing the pointer with the pivot table, or a combination thereof.

[0114] At 620, a determination can be made. For example, the memory system can determine whether the set of physical addresses are consecutively indexed in response to receiving the plurality of write commands. In some cases, the memory system can determine that the set of physical addresses are consecutively indexed.

[0115] At 625, a flag may be set. For example, the memory system may set a flag in an entry of a second subset of the mapping based on the set of physical addresses being indexed consecutively. The mapping may include a first subset (e.g., a root map or root hierarchy), a second subset, and a third subset (e.g., an L2P table or L2P hierarchy). The memory system may set the flag in the entry directly in response to determining that the physical addresses are indexed consecutively. The entry of the second subset includes at least a portion of a pivot table associated with the set of physical addresses. In some cases, the flag may indicate that the entry is associated with a starting physical address of a set of physical addresses associated with multiple write commands. The memory system may set the flag in response to identifying the pivot table, generating the pivot table, replacing the entry, storing at least a portion of the pivot table, or a combination thereof.

[0116] At 630, an entry may be set. For example, the memory system may set an entry of the second subset of the mapping to indicate a starting physical address in response to determining that the set of physical addresses is consecutively indexed. In such a case, the memory system may set the entry of the second subset of the mapping to include the starting physical address of the data located in the NAND. At 635, data may be written. For example, the memory system may write data to the set of physical addresses in response to setting the flag.

[0117] The memory system may determine that the set of physical addresses is not indexed consecutively (e.g., randomly). In such a case, a flag may be set at 640. For example, the memory system may set a flag in an entry of the third subset of the mapping based on the set of physical addresses not being indexed consecutively. The flag may indicate that the entry is associated with the third subset of the mapping. In such a case, the memory system may determine that the physical addresses are randomly indexed and set the flag directly in response to such determination.

[0118] At 645, the entry may be set. For example, the memory system may set the entry of the third subset of the mapping in response to determining that the set of physical addresses is not consecutively indexed. In such cases, the memory system may determine that the physical addresses are randomly indexed and set the entry directly in response to that determination. At 650, the data may be written. For example, the memory system may write the data to the set of physical addresses in response to setting the flag.

[0119] Figure 7 A block diagram 700 is shown of a memory system 720 that supports integrated pivot tables in logical to physical mapping according to examples as disclosed herein. The memory system 720 may be a memory system 720 as described in reference to FIG. Figures 1 to 6 7. Memory system 720 or its various components may be examples of means for performing various aspects of the integrated pivot table in the logical-to-physical mapping as described herein. For example, memory system 720 may include a command receiver 725, a root component 730, a global component 735, a data transfer 740, an index component 745, a flag component 750, a write component 755, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0120] The command receiver 725 may be configured as or otherwise support means for receiving a read command comprising a logical block address of a non-volatile memory device. The root component 730 may be configured as or otherwise support means for reading a first entry in a first subset of a mapping that defines a relationship between a logical block address and a physical address based at least in part on the logical block address. The global component 735 may be configured as or otherwise support means for reading a second entry in a second subset of the mapping based at least in part on reading the first entry in the first subset, the second entry comprising at least a portion of a pivot table associated with a physical address of the non-volatile memory device. The data transmitter 740 may be configured as or otherwise support means for transmitting data retrieved from the pivot table of the second subset of the mapping for the physical address identified therein to a host system based at least in part on reading the second entry in the second subset of the mapping.

[0121] In some examples, data transmitter 740 may be configured or otherwise support means for retrieving data from a non-volatile memory device from a physical address identified using the pivot table of the second entry, wherein transmitting the data is based at least in part on retrieving the data.

[0122] In some examples, data is retrieved from the physical address without reading the third subset of the mapping.

[0123] In some examples, the second entry of the second subset includes a flag indicating whether the second entry is associated with the third subset of the mapping or is associated with a starting physical address in the set of physical addresses associated with the read command.

[0124] In some examples, the global component 735 may be configured to or otherwise support means for determining whether the physical addresses in the set of physical addresses are consecutively indexed based at least in part on reading a second entry of a second subset of the mapping, wherein transferring data is based at least in part on determining that the physical addresses are consecutively indexed.

[0125] In some examples, the global component 735 can be configured to or otherwise support means for identifying a starting physical address among a plurality of physical addresses indexed consecutively using the pivot table of the second entry. In some examples, the global component 735 can be configured to or otherwise support means for identifying a physical address to be accessed based at least in part on a starting logical block address and a difference between the starting logical block address and the logical block address.

[0126] In some examples, the flag component 750 may be configured as or otherwise support means for avoiding reading a third entry of a third subset of the mapping based at least in part on a flag indicating that the second entry of the second subset of the mapping is associated with a physical address of the non-volatile memory device.

[0127] In some examples, the flag component 750 may be configured to or otherwise support means for avoiding transferring at least a portion of the third subset of the mapping from the non-volatile memory device to the volatile memory device based at least in part on a flag indicating that the second entry of the second subset of the mapping is associated with a physical address of the non-volatile memory device.

[0128] In some examples, the pivot table includes a plurality of entries, entries in the plurality of entries representing a plurality of logical block addresses indexed consecutively, and to support identifying a starting physical address in the plurality of physical addresses indexed consecutively, the plurality of physical addresses corresponding to the plurality of logical block addresses, and in the case of reading a second entry of a second subset of the mapping, the global component 735 may be configured to or otherwise support means for reading an entry in the plurality of entries, wherein data is transferred to the host system based at least in part on reading the entry.

[0129] In some examples, a third entry of the plurality of entries represents a logical block address that is non-contiguously indexed from other logical block addresses and identifies a fourth entry of a third subset of the mapping, the fourth entry of the third subset including a physical address associated with the logical block address.

[0130] In some examples, command receiver 725 may be configured to or otherwise support means for receiving a plurality of write commands for a set of physical addresses of a non-volatile memory device. Index component 745 may be configured to or otherwise support means for determining whether the set of physical addresses is consecutively indexed based at least in part on receiving the plurality of write commands. Flag component 750 may be configured to or otherwise support means for setting a flag in entries of a second subset of a mapping comprising a first subset, a second subset, and a third subset based at least in part on the set of physical addresses being consecutively indexed, the entries of the second subset comprising at least a portion of a pivot table associated with the set of physical addresses. Write component 755 may be configured to or otherwise support means for writing data to the set of physical addresses based at least in part on setting the flag.

[0131] In some examples, the flag indicates whether the entry is associated with the third subset of the mapping or is associated with a starting physical address in the set of physical addresses associated with the plurality of write commands.

[0132] In some examples, index component 745 can be configured to or otherwise support means for setting entries of the second subset of the mapping to indicate a starting physical address based at least in part on determining that the set of physical addresses are consecutively indexed.

[0133] In some examples, the global component 735 can be configured or otherwise support means for identifying that the pivot table is included in the second subset of the mapping based at least in part on receiving the plurality of write commands, wherein setting the flag is based at least in part on identifying the pivot table.

[0134] In some examples, the global component 735 can be configured to or otherwise support means for generating a pivot table to be included in the second subset of the mapping based at least in part on receiving the plurality of write commands, wherein setting the flag is based at least in part on generating the pivot table.

[0135] In some examples, the global component 735 can be configured to or otherwise support means for replacing entries containing pointers in the second subset of the map with at least a portion of the pivot table, wherein setting the flag is based at least in part on replacing the entry.

[0136] In some examples, the global component 735 may be configured to or otherwise support means for storing at least a portion of the pivot table in entries of the second subset of the mapping based at least in part on receiving the plurality of write commands, wherein setting the flag is based at least in part on storing at least a portion of the pivot table.

[0137] In some examples, the pivot table includes a plurality of entries, a first entry of the plurality of entries representing a consecutively indexed plurality of logical block addresses and identifying a starting physical address of a consecutively indexed plurality of physical addresses, the plurality of physical addresses corresponding to the plurality of logical block addresses.

[0138] Figure 8 A flowchart illustrating a method 800 for supporting integrated pivot tables in logical to physical mapping according to an example disclosed herein is shown. The operations of the method 800 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 800 may be implemented by a memory system or components thereof as described herein. Figures 1 to 7 The memory system described herein performs. In some examples, the memory system may execute an instruction set to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0139] At 805, a read command may be received. For example, the method may include receiving a read command including a logical block address of a non-volatile memory device. The operations of 805 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 805 may be as described in reference to Figure 7 The command receiver 725 described here performs.

[0140] At 810, a first entry may be read. For example, the method may include reading a first entry in a first subset of a mapping that defines a relationship between a logical block address and a physical address based at least in part on the logical block address. The operations of 810 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 810 may be described in detail with reference to Figure 7 The root component 730 is described as executing.

[0141] At 815, a second entry may be read. For example, the method may include reading a second entry of a second subset of the mapping based at least in part on reading the first entry of the first subset, the second entry including at least a portion of a pivot table associated with a physical address of the non-volatile memory device. The operation of 815 may be performed according to examples as disclosed herein. In some examples, aspects of the operation of 815 may be described by reference to Figure 7 The described global component 735 performs.

[0142] At 820, data may be transferred. For example, the method may include transferring data retrieved from a physical address identified in a pivot table of a second subset of the mapping to a host system based at least in part on reading a second entry of a second subset of the mapping. The operations of 820 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 820 may be described in detail with reference to Figure 7 The data transmitter 740 is described as performing.

[0143] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) may include features, circuitry, logic, means, or instructions for: receiving a read command including a logical block address of a non-volatile memory device; reading a first entry in a first subset of a map defining a relationship between the logical block address and a physical address based at least in part on the logical block address; reading a second entry in a second subset of the map based at least in part on reading the first entry of the first subset, the second entry including at least a portion of a pivot table associated with the physical address of the non-volatile memory device; and transmitting data retrieved from the physical address identified in the pivot table of the second subset of the map to a host system based at least in part on reading the second entry of the second subset of the map.

[0144] Some examples of the method 800 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for retrieving data from a non-volatile memory device from a physical address identified using the pivot table of the second entry, wherein transferring the data may be based at least in part on retrieving the data.

[0145] In some examples of the method 800 and apparatus described herein, data may be retrieved from the physical address without reading the third subset of the mapping.

[0146] In some examples of the method 800 and apparatus described herein, the second entry of the second subset includes a flag indicating whether the second entry is associable with a third subset of the mapping or with a starting physical address in a set of physical addresses associated with the read command.

[0147] Some instances of the method 800 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for determining whether physical addresses in a set of physical addresses are contiguously indexable based at least in part on reading a second entry of a second subset of a mapping, wherein transmitting data may be based at least in part on determining that the physical addresses are contiguously indexable.

[0148] Some examples of the method 800 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for identifying a starting physical address among a plurality of physical addresses that may be indexed consecutively using a pivot table of second entries, and identifying a physical address to be accessed based at least in part on the starting logical block address and a difference between the starting logical block address and the logical block address.

[0149] Some examples of the method 800 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for avoiding reading a third entry of a third subset of the mapping based at least in part on a flag indicating that a second entry of the second subset of the mapping may be associated with a physical address of the non-volatile memory device.

[0150] Some examples of the method 800 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for avoiding transferring at least a portion of a third subset of the mapping from the non-volatile memory device to the volatile memory device based at least in part on a flag indicating that a second entry of the second subset of the mapping may be associated with a physical address of the non-volatile memory device.

[0151] In some examples of the method 800 and apparatus described herein, the pivot table includes a plurality of entries, entries of the plurality of entries representing a plurality of logical block addresses that can be consecutively indexed and identifying a starting physical address of a plurality of physical addresses that can be consecutively indexed, the plurality of physical addresses corresponding to the plurality of logical block addresses, and wherein reading a second entry of a second subset of the mapping may include operations, features, circuitry, logic, means, or instructions of a means for reading an entry of the plurality of entries, wherein data may be transferred to a host system based at least in part on reading the entry.

[0152] In some instances of the method 800 and apparatus described herein, a third entry in the plurality of entries represents a logical block address that may be indexed discontinuously with other logical block addresses and identifies the logical block address of a fourth entry of a third subset of the mapping, the fourth entry of the third subset containing a physical address associated with the logical block address.

[0153] Figure 9 A flowchart illustrating a method 900 for supporting integrated pivot tables in logical to physical mapping according to an example disclosed herein is shown. The operations of the method 900 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 900 may be implemented by a memory system or components thereof as described herein. Figures 1 to 7 The memory system described herein performs. In some examples, the memory system may execute an instruction set to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0154] At 905, a plurality of commands may be received. For example, the method may include receiving a plurality of write commands for a set of physical addresses of a non-volatile memory device. The operations of 905 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 905 may be as described with reference to Figure 7 The command receiver 725 is described as executing.

[0155] At 910, a determination may be made. For example, the method may include determining whether the set of physical addresses are indexed consecutively based at least on receiving a plurality of write commands. The operations of 910 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 910 may be as described in reference to Figure 7 The described indexing component 745 performs.

[0156] At 915, a flag may be set. For example, the method may include setting a flag in an entry of a second subset of a mapping that includes a first subset, a second subset, and a third subset based at least in part on the physical address sets being consecutively indexed, the entries of the second subset including at least a portion of a pivot table associated with the physical address sets. The operations of 915 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 915 may be described by reference to Figure 7 The flag component 750 is described as performing.

[0157] At 920, data may be written. For example, the method may include writing data to a set of physical addresses based at least in part on setting a flag. The operations of 920 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 920 may be described in detail with reference to FIG. Figure 7 The write component 755 performs as described.

[0158] In some examples, an apparatus as described herein may perform one or more methods, such as method 900. The apparatus (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) may include features, circuitry, logic, means, or instructions for: receiving a plurality of write commands for a set of physical addresses of a non-volatile memory device; determining whether the set of physical addresses is contiguously indexed based on receiving at least the plurality of write commands; setting a flag in entries of a second subset of a mapping that includes a first subset, a second subset, and a third subset based at least in part on the set of physical addresses being contiguously indexed, the entries of the second subset including at least a portion of a pivot table associated with the set of physical addresses; and writing data to the set of physical addresses based at least in part on setting the flag.

[0159] In some examples of the method 900 and apparatus described herein, the flag indicates whether the entry is associated with a third subset of the mapping or with a starting physical address in a set of physical addresses associated with the plurality of write commands.

[0160] Some examples of the method 900 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for setting entries of a second subset of the mapping to indicate a starting physical address based at least in part on determining that the set of physical addresses may be indexed consecutively.

[0161] Some examples of the method 900 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for identifying that a pivot table may be included in a second subset of the mapping based at least in part on receiving a plurality of write commands, wherein setting the flag may be based at least in part on identifying the pivot table.

[0162] Some examples of the method 900 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for generating a pivot table to be included in the second subset of the mapping based at least in part on receiving a plurality of write commands, wherein setting the flag may be based at least in part on generating the pivot table.

[0163] Some examples of the method 900 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for replacing entries including pointers in a second subset of the map with at least a portion of the pivot table, wherein setting the flag may be based at least in part on the replacement entry.

[0164] Some instances of the method 900 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for storing at least a portion of the pivot table in entries of a second subset of the mapping based at least in part on receiving a plurality of write commands, wherein setting the flag may be based at least in part on storing at least a portion of the pivot table.

[0165] In some examples of the method 900 and apparatus described herein, the pivot table includes a plurality of entries, a first entry of the plurality of entries representing a plurality of logical block addresses that can be indexed consecutively and identifying a starting physical address of a plurality of physical addresses that can be indexed consecutively, the plurality of physical addresses corresponding to the plurality of logical block addresses.

[0166] It should be noted that the methods described above describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and that other embodiments are possible. Furthermore, portions from two or more of the described methods may be combined.

[0167] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, the signal may represent a bus of signals, where the bus may have various bit widths.

[0168] The terms "electrical communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are said to be in electrical communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electrical communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component such as a switch, transistor, or other component. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as a switch or transistor.

[0169] The term "coupling" refers to a condition in which a signal is moved from an open-circuit relationship between components, in which signals are currently unable to communicate between the components via a conductive path, to a closed-circuit relationship in which signals are able to communicate between the components via a conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via a conductive path that previously did not permit signal flow.

[0170] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. Components are isolated from one another if an open circuit exists between them. For example, two components separated by a switch positioned between them are isolated from one another when the switch is open. If a controller isolates two components, it implements a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0171] The terms "if," "when," "based on," or "based at least in part on" are used interchangeably. In some instances, if the terms "if," "when," "based on," or "based at least in part on" are used to describe a conditional action, a conditional process, or a connection between parts of a process, the terms are interchangeable.

[0172] The term "in response to" may refer to a condition or action that occurs at least in part (if not entirely) as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least in part as a result of the preceding condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occur after the first condition or action).

[0173] In addition, the term "directly in response to" or "directly in response to" may refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being "based on," "at least partially based on," or "in response to" some other step, action, event, or condition may be performed additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly in response to" this other condition or action.

[0174] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0175] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials such as metals. The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority of carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority of carriers are holes), the FET can be referred to as a p-type FET. The channel can be terminated by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "switched on" or "activated." When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "off" or "deactivated."

[0176] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. As used herein, the term "exemplary" means "serving as an example, instance, or illustration" and is not intended to be "preferred" or "advantageous over other examples." The detailed description includes specific details to provide an understanding of the described technology. However, these technologies may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0177] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label regardless of the second reference label.

[0178] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0179] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0180] As used herein (including in the claims), "or" as used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C, or AB, or AC, or BC, or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be understood to refer to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0181] Computer-readable media include both non-transitory computer storage media and communication media, and communication media include any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disc storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. In addition, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, then the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CDs, laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs. Disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0182] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: memory device; a controller coupled to the memory device and configured to cause the apparatus to: receiving a read command including a logical block address of a nonvolatile memory device; reading a first entry in a first subset of a map that defines a relationship between the logical block address and a physical address based at least in part on the logical block address; reading a second entry of a second subset of the mapping based at least in part on reading the first entry of the first subset, the second entry comprising at least a portion of a pivot table associated with a physical address of the non-volatile memory device; and Data retrieved from the physical address identified in the pivot table of the second subset of the mapping is transmitted to a host system based at least in part on reading the second entry of the second subset of the mapping.

2. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: The data from the physical address identified using the pivot table of the second entry is retrieved from the non-volatile memory device, wherein transmitting the data is based at least in part on retrieving the data.

3. The apparatus of claim 2, wherein the data is retrieved from the physical address without reading a third subset of the mapping.

4. The apparatus of claim 1 , wherein the second entry of the second subset comprises a flag indicating whether the second entry is associated with a third subset of the mapping or with a starting physical address in a set of physical addresses associated with the read command.

5. The apparatus of claim 4, wherein the controller is further configured to cause the apparatus to: A determination is made based at least in part on reading the second entry of the second subset of the mapping whether the physical addresses in the set of physical addresses are consecutively indexed, wherein transmitting the data is based at least in part on determining that the physical addresses are consecutively indexed.

6. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: identifying a starting physical address of a plurality of physical addresses indexed consecutively using the pivot table of the second entry; and The physical address to be accessed is identified based at least in part on a starting logical block address and a difference between the starting logical block address and the logical block address.

7. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: Reading a third entry of a third subset of the mapping is avoided based at least in part on a flag indicating that the second entry of the second subset of the mapping is associated with the physical address of the non-volatile memory device.

8. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: Transferring at least a portion of a third subset of the mapping from the nonvolatile memory device to a volatile memory device is avoided based at least in part on a flag indicating that the second entry of the second subset of the mapping is associated with the physical address of the nonvolatile memory device.

9. The apparatus of claim 1 , wherein the pivot table comprises a plurality of entries, entries of the plurality of entries representing a plurality of consecutively indexed logical block addresses and instructions for identifying a starting physical address of a plurality of consecutively indexed physical addresses, the plurality of physical addresses corresponding to the plurality of logical block addresses, and wherein To read the second entry of the second subset of the mapping, the controller is configured to cause the device to: The entry of the plurality of entries is read, wherein transferring the data to the host system is based at least in part on reading the entry.

10. The apparatus of claim 9, wherein a third entry of the plurality of entries represents the logical block address that is non-contiguously indexed from other logical block addresses and identifies a fourth entry of a third subset of the mapping, the fourth entry of the third subset comprising the physical address associated with the logical block address.

11. A device comprising: memory device; a controller coupled to the memory device and configured to cause the apparatus to: receiving a plurality of write commands for a set of physical addresses of a non-volatile memory device; determining whether the set of physical addresses are consecutively indexed based at least in part on receiving the plurality of write commands; setting a flag in an entry of a second subset comprising mappings of a first subset, a second subset, and a third subset based at least in part on the set of physical addresses being consecutively indexed, the entry of the second subset comprising at least a portion of a pivot table associated with the set of physical addresses; and Data is written to the set of physical addresses based at least in part on setting the flag.

12. The apparatus of claim 11, wherein the flag indicates whether the entry is associated with the third subset of the mapping or a starting physical address in the set of physical addresses associated with the plurality of write commands.

13. The apparatus of claim 11 , wherein the controller is further configured to cause the apparatus to: The entries of the second subset of the mapping are set to indicate a starting physical address based at least in part on determining that the set of physical addresses are consecutively indexed.

14. The apparatus of claim 11 , wherein the controller is further configured to cause the apparatus to: The pivot table is identified as being included in the second subset of the mapping based at least in part on receiving the plurality of write commands, wherein setting the flag is based at least in part on identifying the pivot table.

15. The apparatus of claim 11, wherein the controller is further configured to cause the apparatus to: The pivot table is generated to be included in the second subset of the mapping based at least in part on receiving the plurality of write commands, wherein setting the flag is based at least in part on generating the pivot table.

16. The apparatus of claim 11, wherein the controller is further configured to cause the apparatus to: The entry in the second subset of the map that includes a pointer is replaced with at least the portion of the pivot table, wherein setting the flag is based at least in part on replacing the entry.

17. The apparatus of claim 11, wherein the controller is further configured to cause the apparatus to: The at least the portion of the pivot table is stored in the entries of the second subset of the mapping based at least in part on receiving the plurality of write commands, wherein setting the flag is based at least in part on storing at least the portion of the pivot table.

18. The apparatus of claim 11, wherein the pivot table comprises a plurality of entries, a first entry of the plurality of entries representing a plurality of consecutively indexed logical block addresses and identifying a starting physical address of a plurality of consecutively indexed physical addresses corresponding to the plurality of logical block addresses.

19. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a read command including a logical block address of a nonvolatile memory device; reading a first entry in a first subset of a map that defines a relationship between the logical block address and a physical address based at least in part on the logical block address; reading a second entry of a second subset of the mapping based at least in part on reading the first entry of the first subset, the second entry comprising at least a portion of a pivot table associated with a physical address of the non-volatile memory device; and Data retrieved from the physical address identified in the pivot table of the second subset of the mapping is transmitted to a host system based at least in part on reading the second entry of the second subset of the mapping.

20. The non-transitory computer-readable medium of claim 19, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The data from the physical address identified using the pivot table of the second entry is retrieved from the non-volatile memory device, wherein transmitting the data is based at least in part on retrieving the data.

21. The non-transitory computer-readable medium of claim 20, wherein the data is retrieved from the physical address without reading a third subset of the mapping.

22. The non-transitory computer-readable medium of claim 19, wherein the second entry of the second subset comprises a flag indicating whether the second entry is associated with a third subset of the mapping or with a starting physical address in a set of physical addresses associated with the read command.

23. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a plurality of write commands for a set of physical addresses of a non-volatile memory device; determining whether the set of physical addresses are consecutively indexed based at least in part on receiving the plurality of write commands; setting a flag in an entry of a second subset comprising mappings of a first subset, a second subset, and a third subset based at least in part on the set of physical addresses being consecutively indexed, the entry of the second subset comprising at least a portion of a pivot table associated with the set of physical addresses; and Data is written to the set of physical addresses based at least in part on setting the flag.

24. The non-transitory computer-readable medium of claim 23, wherein the flag indicates whether the entry is associated with the third subset of the mapping or a starting physical address in the set of physical addresses associated with the plurality of write commands.

25. The non-transitory computer-readable medium of claim 23, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The entries of the second subset of the mapping are set to indicate a starting physical address based at least in part on determining that the set of physical addresses are consecutively indexed.

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