Storage device for generating identification code and identification code generation method

Abstract

The present disclosure provides a storage device for generating an identification code and a method for generating an identification code, wherein the storage device includes a first storage circuit, a second storage circuit, and a read circuit. The first storage circuit stores a plurality of first data, each of which has a plurality of bits. The second storage circuit stores a plurality of second data, each of which has a plurality of bits. The read circuit reads the second data from the second storage circuit into a first sequence, selects a first portion of the first data based on the first sequence, reads the first portion of the first data from the first storage circuit into a target sequence, and outputs the target sequence as an identification code.

Description

Technical Field

[0001] The present disclosure relates to a storage device and an operating method thereof, and more particularly to a storage device for generating a unique identification code and a method for generating a unique identification code. Background Art

[0002] With the advancement of technology, various types of electronic devices have been widely used in daily life, such as personal computers, mobile phones, head-mounted devices, etc. Among them, personal computers or mobile phones usually store important personal data related to personal privacy, and personal computers or mobile phones also often conduct financial transactions. Therefore, strict security mechanisms are needed to ensure the confidentiality of personal data and the security of transactions. In common security mechanisms, each electronic device is given a unique identification code (ID code), and the legitimacy of each electronic device can be confirmed based on the identification code.

[0003] The application of unique identification codes is not limited to terminal devices such as personal computers and mobile phones. It can also be applied to semiconductor chips within terminal devices. A unique identification code can be stored in each chip to identify the chip. In other words, the unique identification code is like a fingerprint of the chip.

[0004] To ensure that the identification code is unique and does not duplicate the identification codes of other devices or chips, the identification code can be generated by leveraging the physically unclonable properties of hardware components. This type of identification code is called a physically unclonable function code (PUF code).

[0005] However, factors in the manufacturing process or operating environment of hardware components (such as ambient temperature) often cause defects or parameter variations in the hardware components, which in turn causes erroneous bits in the identification code stored in the hardware components, destroying the accuracy and uniqueness of the identification code. This is a technical problem faced by the existing physical non-cloneable function code.

[0006] Public content

[0007] In order to overcome the above technical problems of the physical unclonable function code in the prior art, the present disclosure proposes a technical solution to store two sets of data (first data and second data) in a memory respectively, and select the first part of the first data according to the second data to generate an identification code.

[0008] The technical solution disclosed in the present invention provides a storage device for generating an identification code, comprising a first storage circuit, a second storage circuit, and a reading circuit. The first storage circuit is used to store a plurality of first data, each of which has a plurality of bits. The second storage circuit is used to store a plurality of second data, each of which has a plurality of bits. The reading circuit is used to read the second data from the second storage circuit into a first sequence, select a first part of the first data according to the first sequence, read the first part of the first data from the first storage circuit into a target sequence, and output the target sequence as an identification code. The logical values of the bits of the first data are randomly distributed, and the logical values of the bits of the second data are pre-defined by the user or randomly distributed.

[0009] The technical solution disclosed in the present invention provides an identification code generation method, which is applied to a first storage circuit and a second storage circuit, wherein the first storage circuit stores a plurality of first data, and the second storage circuit stores a plurality of second data. The identification code generation method includes the following steps. Reading these second data from the second storage circuit becomes a first sequence, wherein these second data have a plurality of bits, and the logical values of these bits are predefined by the user or randomly distributed. Selecting a first part of these first data according to the first sequence, wherein these first data have a plurality of bits, and the logical values of these bits are randomly distributed. Reading the first part of these first data from the first storage circuit becomes a target sequence. And, outputting the target sequence as an identification code

[0010] Other aspects and advantages of the present invention will become apparent from a review of the following drawings, detailed description, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A FIG. 4 is a block diagram of a storage device for generating an identification code according to a first embodiment of the present disclosure.

[0012] Figure 1B FIG. 4 is a circuit diagram of a memory array of a first storage circuit and a memory array of a second storage circuit according to a first embodiment of the present disclosure.

[0013] Figure 1C and Figure 1D Schematic diagram of the operation of generating an identification code for a storage device according to the first embodiment of the present disclosure.

[0014] Figure 2A and Figure 2B FIG. 1 is a schematic diagram of characteristic analysis of an identification code generated by a simulation according to the first embodiment of the present disclosure.

[0015] Figure 3 FIG. 4 is a block diagram of a storage device for generating an identification code according to a second embodiment of the present disclosure.

[0016] Figure 4A FIG. 4 is a block diagram of a storage device for generating an identification code according to a third embodiment of the present disclosure.

[0017] Figure 4B Schematic diagram of the operation of generating an identification code for a storage device according to the third embodiment of the present disclosure.

[0018] Figure 4C 、 4D 2 are circuit diagrams of two types of processing circuits of a storage device according to a third embodiment of the present disclosure.

[0019] Figure 5 Schematic diagram of the operation of generating an identification code for a storage device according to the fourth embodiment of the present disclosure.

[0020] Figure 6 Schematic diagram of the operation of generating an identification code for a storage device according to the fifth embodiment of the present disclosure.

[0021] Figure 7 4 is a flowchart of a method for generating an identification code according to the first embodiment of the present disclosure.

[0022] Figure 8 4 is a flowchart of a method for generating an identification code according to a third embodiment of the present disclosure.

[0023] Description of Reference Numerals

[0024] 10A, 10B, 10C: Storage devices

[0025] 102: Identification code

[0026] 104: First Data

[0027] 106: Second Data

[0028] 20: First storage circuit

[0029] 30: Second storage circuit

[0030] 21: Memory array

[0031] 31: Memory array

[0032] 201: First storage area

[0033] 202: Second storage area

[0034] 40: Read circuit

[0035] 41, 41A, 41B: Processing circuit

[0036] A: First Sequence

[0037] a: first sequence of bits

[0038] a': the complement of the first sequence of bits

[0039] a1~a16: bits of the first sequence

[0040] B: Second sequence

[0041] b1~b16: bits of the second sequence

[0042] b': the complement of the second sequence of bits

[0043] P: target sequence

[0044] p: the bit of the target sequence

[0045] 702-714: Steps

[0046] 802-808: Steps DETAILED DESCRIPTION

[0047] The technical terms in this specification refer to the customary terms in this technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, technicians in this technical field may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0048] Figure 1A FIG is a block diagram of a storage device 10A for generating an identification code 102 according to a first embodiment of the present disclosure. Figure 1A The storage device 10A of the first embodiment includes a first storage circuit 20, a second storage circuit 30, and a readout circuit 40. In the storage device 10A of the first embodiment, the first storage circuit 20 and the second storage circuit 30 are physically separate storage circuits. The readout circuit 40 reads data from the first storage circuit 20 and the second storage circuit 30, respectively, and processes the data to generate an identification code 102.

[0049] More specifically, Figure 1B FIG1 is a circuit diagram of the memory array 21 of the first storage circuit 20 and the memory array 31 of the second storage circuit 30 according to the first embodiment of the present disclosure. Figure 1BThe memory array 21 of the first storage circuit 20 is, for example, a random access memory (RAM) array of one transistor and two resistors (1T2R, 1Transistor + 2Re). Resistors Ra and Rb determine the voltage at the transistor gates, which in turn determines the logic value stored in the memory cells of the memory array 21: "1" or "0." Meanwhile, the memory array 31 of the second storage circuit 30 is a programmable memory array, allowing the logic values stored in the memory cells of the memory array 31 to be programmed according to user specifications. The memory array 31 of the second storage circuit 30 is, for example, a random access memory array of one transistor and one resistor (1T1R, 1Transistor + 1Re).

[0050] The memory form of the first storage circuit 20 and the second storage circuit 30 may also include static random access memory (SRAM) or random access memory (ROM), such as mask ROM, fuse ROM, anti-fuse ROM, etc. Alternatively, it may include high-precision non-volatile memory (NVM), charge storage memory, floating gate memory (FG), charge trapping memory, silicon-oxide-nitride-oxide-silicon memory (SONOS), resistive random access memory (ReRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), ferroelectric tunneling interface memory (FTJ), and ferroelectric random access memory (FeRAM).

[0051] Figure 1C and Figure 1D FIG. 1 is a schematic diagram of an operation of generating an identification code 102 by the storage device 10A according to the first embodiment of the present disclosure. Figure 7 FIG is a flow chart of the identification code generation method 700 according to the first embodiment of the present disclosure. Figure 1C (See also Figure 1A), the first storage circuit 20 is used to store a plurality of first data 104. These first data 104, for example, include sixteen bits {1, 0, 1, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0} (binary logic values). The first data 104 are sequentially stored in sixteen (four by four) memory cells of the memory array 21 of the first storage circuit 20. The first data 104 is used as information, that is, the first data 104 serves as the content of the subsequently generated identification code 102. However, in the technical solution of the present disclosure, the sixteen bits {1, 0, 1, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 1} of the original first data 104 have not yet become the final identification code 102. The bits of the first portion of the first data 104 must be selected via the second data 106, and the selected bits of the first data 104 become the final identification code 102.

[0052] While the first data 104 is used as information, the second data 106 is used as an address. Based on the address provided by the second data 106, the first portion of the bits of the first data 104 can be selected to form the final identification code 102. In the storage device 10A of the first embodiment, the first data 104 is stored in the first storage circuit 20, and the second data 106 is stored in the second storage circuit 30. In other words, the first data 104 and the second data 106 are physically stored in different storage circuits. The number of second data 106 is equal to the number of first data 104, and the second data 106 also includes sixteen bits of binary logic value. The sixteen bits of the second data 106 are: {1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0}. Similarly, the second data 106 is also sequentially stored in the four by four memory cells of the memory array 31 of the second storage circuit 30. The sixteen bits of the second data 106 have a one-to-one correspondence with the sixteen bits of the first data 104. A logical "1" bit of the second data 106 corresponds to a selected bit of the first data 104. Conversely, bits of the first data 104 corresponding to a logical "0" bit of the second data 106 are not selected. The selected portion of the first data 104 is referred to as the first portion, and the unselected portion of the first data 104 is referred to as the second portion.

[0053] In the operation of the storage device 10A of the first embodiment, the read circuit 40 first reads the second data 106 from the second storage circuit 30. The read second data 106 forms a first sequence A, which can be represented as {1, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0}. The logical value "1" bit of the first sequence A is used as the selected address. See also Figure 7This corresponds to step 706 of the identification code generation method 700 of the first embodiment: reading the second data 106 from the second storage circuit 30 to form a first sequence A.

[0054] Next, based on the addresses of the bits with a logic value of "1" in the first sequence A, the bits of the first portion of the first data 104 are selected. Conversely, for the addresses of the bits with a logic value of "0" in the first sequence A, the bits of the second portion of the first data 104 are discarded and not selected. For example, the bits with a logic value of "1" in the first sequence A are bits a1, a4, a6, a11, a13, and a14. Furthermore, for the addresses of the bits a1, a4, a6, a11, a13, and a14, the bits b1, b4, b6, b11, b13, and b14 of the first portion of the first data 104 are selected. See also Figure 7 , which corresponds to step 708 of the identification code generation method 700 : selecting bits of the first part of the first data 104 according to the address of the logic value “1” bit of the first sequence A.

[0055] Next, the read circuit 40 reads the bits b1, b4, b6, b11, b13, and b14 of the selected first portion of the first data 104 from the first storage circuit 20 to form a target sequence P. The target sequence P can be represented as {1, 1, 0, 1, 0, 1}, and the target sequence P serves as the final identification code 102. Figure 7 , which corresponds to step 710 of the identification code generation method 700 : reading the first portion of the bits of the first data 104 from the first storage circuit 20 to form a target sequence P, and step 712 : outputting the target sequence P as the final identification code 102 .

[0056] Compared to the selected bits b1, b4, b6, b11, b13, and b14 of the first part of the first data 104, the bits b2, b3, b5, b7, b8, b9, b10, b12, b15, and b16 of the second part of the first data 104 are discarded and not selected.

[0057] For the storage device 10A of the first embodiment, the user pre-programs the logic value stored in the second storage circuit 30 to pre-define the logic value "1" bit of the second data 106. In other words, the user pre-defines the address to select which bits of the first data 104 are used as the final identification code 102.

[0058] The physical characteristics of the hardware components of the first storage circuit 20 typically exhibit variability. For example, if the hardware component of the first storage circuit 20 is a static random access memory (SRAM), there is mismatch variability between the N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS) transistors within the memory. If the hardware component of the first storage circuit 20 is a non-volatile memory (e.g., a variable resistance memory, phase change memory, or floating gate memory), the programming state of the memory is unpredictable. Due to the variability of the hardware components of the first storage circuit 20, the logical value of each bit of the first data 104 stored in the first storage circuit 20 is randomly distributed. Therefore, it is highly unlikely that the logical value of each bit of the first data 104 will be the same in another storage device. Therefore, the first portion of the first data 104 is selected as the target sequence P = {1, 1, 0, 1, 0, 1}, which is unique and can serve as the identification code 102. The identification code 102 can also be represented as {1, 1, 0, 1, 0, 1}.

[0059] In another example, Figure 1D As shown, hardware components of the first storage circuit 20 may experience defects (e.g., component parameter variations caused by temperature fluctuations), resulting in certain bits of the first data 104 being error bits or insufficient margin bits. For example, memory cells at addresses (1, 3), (2, 1), (3, 3), and (4, 4) of the memory array 21 of the first storage circuit 20 may experience defects, resulting in the first data 104 stored at addresses (1, 3), (2, 1), and (4, 4) of the memory array 21 being error bits "x." The disclosed technical solution uses the address provided by the second data 106 to select the first portion of the first data 104 as the final identification code 102, while the second portion of the first data 104 is discarded. The erroneous bit "x" of the first data 104 corresponds to the addresses (1, 3), (2, 1), and (4, 4) of the memory array 31 of the second storage circuit 30. The logical values of the bits of the second data 106 stored at the addresses (1, 3), (2, 1), and (4, 4) of the memory array 31 are all "0." Therefore, the erroneous bit "x" of the first data 104 belongs to the second portion and is discarded and not selected. It does not affect the target sequence P = {1, 1, 0, 1, 0, 1} and the final identification code 102. In other words, the address provided by the second data 106 can filter out the erroneous bit "x" in the first data 104. Therefore, the generation mechanism of the identification code 102 of the present disclosure has error tolerance to tolerate the erroneous bit "x" of the first data 104.

[0060] Figure 2Aand Figure 2B This figure illustrates the characteristics of the identification code 102 generated by simulation according to the first embodiment of the present disclosure. The first data 104 stored in the first storage circuit 20 consists of 500 bits (500 bits / chip). The second data 106 stored in the second storage circuit 30 contains 100 bits of logic "1" (100 bits / chip). Therefore, using the address provided by the second data 106, 100 bits can be selected from the 500 bits of the first data 104 to form the target sequence P, which serves as the final identification code 102.

[0061] like Figure 2A As shown in FIG. 1 , the intra-hamming-distance (intra-HD) can show the correlation between the five hundred bits of the first data 104, wherein the correlation coefficient μ is 11.62%. Figure 2B As shown, the correlation coefficient μ between the 100 bits of the first data 104 selected via the address of the second data 106 (forming the identification code 102 of the target sequence P) is significantly reduced to 0.53%. The above simulation results show that the selection of the address provided by the second data 106 can increase the randomness of the logical value of each bit of the target sequence P, thereby further ensuring the uniqueness of the identification code 102.

[0062] On the other hand, Figure 2A As shown, the external Hamming distance (inter-HD) can show the correlation between the logic value of each bit of the first data 104 stored in the first storage circuit 20 and other storage devices, wherein the correlation coefficient μ is 49.88%. Figure 2B As shown, after selecting one hundred bits of the first data 104 through the address of the second data 106 , the correlation coefficient μ of the external Hamming distance is 50.01%, which can still be maintained at a value close to 50%.

[0063] exist Figure 2A and Figure 2B In the simulation setting, 100 bits are selected from 500 bits of the first data 104 as the identification code 102, with a selection ratio of one-fifth. In different examples, different selection ratios may be used, such as one-tenth or one-twentieth. A lower selection ratio can filter out more error bits in the first data 104, resulting in a higher error tolerance.

[0064] Figure 3 FIG is a block diagram of a storage device 10B for generating an identification code 102 according to a second embodiment of the present disclosure. Figure 3The storage device 10B of the second embodiment includes a first storage circuit 20 and a read circuit 40. The storage device 10B of the second embodiment includes only one physical storage circuit (the first storage circuit 20) and simultaneously stores the first data 104 and the second data 106. The first storage circuit 20 is divided into a first storage area 201 and a second storage area 202 to store the first data 104 and the second data 106, respectively.

[0065] Figure 4A is a block diagram of a storage device 10C for generating an identification code 102 according to a third embodiment of the present disclosure. Figure 4B FIG. 1 is a schematic diagram of an operation of generating an identification code 102 by a storage device 10C according to a third embodiment of the present disclosure. Figure 8 FIG is a flow chart of an identification code generating method 800 according to the third embodiment of the present disclosure. Figure 4A The storage device 10C of the third embodiment differs from the storage device 10A of the first embodiment in that the read circuit 40 of the third embodiment simultaneously reads the first data 104 from the first storage circuit 20 and the second data 106 from the second storage circuit 30 in parallel. Furthermore, the read circuit 40 of the third embodiment further includes a processing circuit 41. The simultaneously read first data 104 and second data 106 are simultaneously transmitted to the processing circuit 41 for processing.

[0066] See next Figure 4B More specifically, in the operation of the storage device 10C of the third embodiment, the read circuit 40 reads the second data 106 from the second storage circuit 30 to form a first sequence A and simultaneously reads the first data 104 from the first storage circuit 20 to form a second sequence B. The first sequence A can be represented as {1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0}, and the second sequence B can be represented as {1, 0, 1, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0}. See also Figure 8 This corresponds to step 802 of the identification code generation method 800 of the third embodiment: reading the second data 106 from the second storage circuit 30 and simultaneously reading the first data 104 from the first storage circuit 20. The second data 106 form a first sequence A, and the first data 104 form a second sequence B.

[0067] Next, the first sequence A and the second sequence B are simultaneously transmitted to the processing circuit 41 for operation, which corresponds to step 804 of the identification code generation method 800 : transmitting the first sequence A and the second sequence B to the processing circuit 41 simultaneously.

[0068] In the processing circuit 41, the bits of the first part of the second sequence B are selected according to the address of the logical value "1" bit of the first sequence A. On the other hand, the bits of the second part of the second sequence B correspond to the logical value "0" bits of the first sequence A, and the processing circuit 41 discards the bits of the second part of the second sequence B. Figure 4B As shown, corresponding to the addresses of bits a1, a4, a6, a11, a13, and a14 of the first sequence A, the processing circuit 41 selects bits b1, b4, b6, b11, b13, and b14 of the first portion of the second sequence B. Furthermore, the processing circuit 41 masks the bits of the second portion of the second sequence B and does not select them. Figure 8 , which corresponds to step 806 of the identification code generation method 800 : selecting the first part of the bits of the second sequence B according to the address of the logic value “1” bit of the first sequence A.

[0069] Next, the processing circuit 41 outputs the bits b1, b4, b6, b11, b13, and b14 of the selected first portion of the second sequence B to form the target sequence P. The target sequence P can be represented as {1, 1, 0, 1, 0, 1} and serves as the final identification code 102. This corresponds to step 808 of the identification code generation method 800: outputting the bits b1, b4, b6, b11, b13, and b14 of the selected first portion of the second sequence B to form the target sequence P, which serves as the final identification code 102.

[0070] As described above, the difference between the operation of the storage device 10C of the third embodiment (corresponding to the identification code generation method 800 of the third embodiment) and the operation of the storage device 10A of the first embodiment (corresponding to the identification code generation method 700 of the first embodiment) is that the identification code generation method 700 of the first embodiment first reads the second data 106 from the second storage circuit 30 to form a first sequence A, then selects the first portion of the bits of the first data 104 according to the address of the logical value "1" bit of the first sequence A. Then, only the selected first portion of the bits of the first data 104 is read from the first storage circuit 20 to form the final identification code 102. Conversely, the identification code generation method 800 of the third embodiment simultaneously reads the second data 106 and the first data 104 from the second storage circuit 30 and the first storage circuit 20 to form the first sequence A and the second sequence B. Then, the first portion is selected from the second sequence B to form the final identification code 102.

[0071] Figure 4C 、 4DCircuit diagrams of two processing circuits 41A and 41B of a storage device 10C according to a third embodiment of the present disclosure are provided. Processing circuits 41A and 41B can be logic circuits, such as latches or flip-flops. Processing circuits 41A and 41B select bit b of a second sequence B using bit a of a first sequence A and its complement a', which becomes bit p of a target sequence P.

[0072] Figure 5 FIG. 1 is a schematic diagram of an operation of generating an identification code 102 by a storage device according to a fourth embodiment of the present disclosure. Figure 5 The difference between the fourth embodiment and the first embodiment is that the logic values of each bit of the second data 106 of the first embodiment are pre-programmed and defined by the user; while the logic values of each bit of the second data 106 of the fourth embodiment are randomly distributed and not defined by the user. In other words, the logic values of each bit of the first data 104 and the second data 106 of the fourth embodiment are randomly distributed. By using the randomly distributed address provided by the second data 106 to select the randomly distributed information of the first data 104, the fourth embodiment increases the randomness of the random distribution to two dimensions, which can better ensure the uniqueness of the identification code 102 formed by selecting the first part of the bits from the first data 104. For example, the first sequence A read from the randomly distributed second data 106 is {0, 1, 0, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 1, 0}. According to the address provided by the first sequence A, the first part is selected from the first data 104 to become the target sequence P = {0, 1, 0, 0, 1, 0, 0} to obtain the final identification code 102. In operation, Figure 7 In step 702, it is first determined whether the logic values of each bit of the second data 106 must be user-programmed. If not, random logic values for each bit of the second data 106 are directly generated randomly based on the physical properties of the second storage circuit 30, without programming the bits of the second data 106. Therefore, step 704 can be skipped and step 706 can be executed directly, directly reading the randomly distributed second data 106 from the second storage circuit 30 to form the first sequence A.

[0073] Figure 6 FIG. 1 is a schematic diagram of an operation of generating an identification code 102 by a storage device according to a fifth embodiment of the present disclosure. Figure 6In the fifth embodiment, the user can reprogram the second data 106 during the process to redefine the logic value of each bit of the second data 106, thereby redefining the address provided by the first sequence A, and then reselecting other bits of the first data 104 as the new target sequence P to generate a new identification code 102. In other words, the fifth embodiment can change the identification code 102 again during use. In operation, Figure 7 Step 714 determines whether the user needs to reprogram the second data 106 during the process. If so, step 704 is executed to program the logic values of each bit of the second data 106. Next, step 706 reads the reprogrammed second data 106 to produce a new first sequence A = {0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 1, 0, 0}. Furthermore, step 708 reselects five bits b6, b7, b10, b12, and b14 from the first data 104 based on the new first sequence A to obtain a new target sequence P = {0, 0, 0, 0, 1}, which becomes the modified identification code 102.

[0074] Through the technical solutions of the above-mentioned embodiments of the present disclosure, the address provided by the first sequence A formed by the second data 106 is used to select the first part of the first data 104 to generate the final identification code 102. In addition, the second part of the first data 104 is discarded, and the error bits in the second part of the first data 104 can be tolerated, thereby further ensuring the uniqueness of the final generated identification code 102. The first sequence A formed by the second data 106 can be pre-defined by the user, randomly distributed, or reprogrammed and redefined by the user during use, making the encoding mechanism of the identification code 102 more flexible and better ensuring its uniqueness. The above is the technical effect achieved by the technical solution of the present disclosure.

[0075] Although the present invention has been disclosed in detail above with reference to preferred embodiments and examples, it is to be understood that these examples are intended to be illustrative rather than restrictive. It is anticipated that those skilled in the art will be able to devise various modifications and combinations that fall within the spirit of the present invention and the scope of the appended claims.

Claims

1. A storage device for generating an identification code, comprising: a first storage circuit for storing a plurality of first data, wherein the first data has a plurality of bits; a second storage circuit for storing a plurality of second data, wherein the second data has a plurality of bits; and a read circuit for reading the second data from the second storage circuit to form a first sequence, using a switch circuit to select a first portion of the first data according to the address of a bit with a logic value of "1" in the first sequence, reading the first portion of the first data from the first storage circuit to form a target sequence, and outputting the target sequence as an identification code; The logic values of the bits of the first data are randomly distributed, and the logic values of the bits of the second data are predefined by a user or randomly distributed.

2. The storage device according to claim 1, wherein The first data further includes a second portion, and the read circuit discards error bits in the second portion of the first data.

3. The storage device according to claim 1, wherein The logic values of these bits of the second data are predefined by the user, and the bits of the first sequence with logic values of “1” are predefined by the user.

4. The storage device according to claim 1, wherein The logic values of these bits of the second data are reprogrammed, and the reading circuit reads the second data from the second storage circuit into a reprogrammed first sequence, reselects a first part of the first data according to the first sequence, and reads the reselected first part of the first data into the target sequence.

5. The storage device according to claim 1, wherein The logic values of the bits of the second data are randomly distributed, and the bits of the logic value “1” of the first sequence are randomly distributed.

6. A storage device for generating an identification code, comprising: a first storage circuit for storing a plurality of first data, wherein the first data has a plurality of bits; a second storage circuit for storing a plurality of second data, wherein the second data has a plurality of bits; as well as a read circuit for reading the second data from the second storage circuit into a first sequence and simultaneously reading the first data from the first storage circuit into a second sequence, the read circuit comprising: a processing circuit for simultaneously receiving the first sequence and the second sequence, and using a switch circuit to select a first portion of the second sequence as a target sequence according to the address of the bit with a logic value of "1" in the first sequence, and outputting the target sequence as an identification code; The logic values of the bits of the first data are randomly distributed, and the logic values of the bits of the second data are predefined by a user or randomly distributed.

7. The storage device according to claim 6, wherein: The second sequence further includes a second portion, and the processing circuit discards erroneous bits in the second portion of the second sequence.

8. The storage device according to claim 6, wherein The logical values of these bits of the second data are predefined by the user, and the bits of the logical value "1" of the first sequence are predefined by the user. The processing circuit selects the first part of the second sequence according to the addresses of the bits of the logical value "1" of the first sequence.

9. The storage device according to claim 6, wherein: The logic values of these bits of these second data are reprogrammed, the reading circuit reads these second data from the second storage circuit into a reprogrammed first sequence, and the processing circuit reselects a first part of the second sequence according to the first sequence, and the reselected first part of the second sequence becomes the target sequence.

10. The storage device according to claim 6, wherein The logic values of these bits of the second data are randomly distributed, and the bits of the logic value "1" of the first sequence are randomly distributed. The processing circuit selects the first part of the second sequence according to the addresses of the bits of the logic value "1" of the first sequence.

11. A method for generating an identification code, applied to a first storage circuit and a second storage circuit, wherein the first storage circuit stores a plurality of first data and the second storage circuit stores a plurality of second data, the method comprising: Reading the second data from the second storage circuit into a first sequence, wherein the second data has a plurality of bits, and the logic values of the bits are predefined by a user or randomly distributed; Selecting a first portion of the first data according to addresses of bits of the first sequence having a logic value of “1”, wherein the first data has a plurality of bits, and the logic values of the bits are randomly distributed; Reading the first portion of the first data from the first storage circuit into a target sequence; and The target sequence is output as an identification code.

12. The identification code generation method according to claim 11, wherein: The first data also includes a second part, and the identification code generation method further includes: Error bits in the second portion of the first data are discarded.

13. The identification code generation method according to claim 11, further comprising: pre-defining the logic values of the bits of the second data so that the bits of the logic value "1" of the first sequence are pre-defined; as well as The first portion of the first data is selected according to the address of the bit of the first sequence with a logic value of “1”.

14. The identification code generation method according to claim 11, further comprising: reprogramming logic values of the bits of the second data; Reading the second data from the second storage circuit into a reprogrammed first sequence; reselecting a first portion of the first data according to the first sequence; as well as The reselected first portion of the first data is read to become the target sequence.

15. The identification code generation method according to claim 11, wherein: The logical values of the bits of the second data are randomly distributed, and the identification code generation method further includes: The first portion of the first data is selected according to addresses of bits of the first sequence having a logic value of “1”, wherein the bits of the first sequence having a logic value of “1” are randomly distributed.

16. A method for generating an identification code, applied to a first storage circuit and a second storage circuit, wherein the first storage circuit stores a plurality of first data and the second storage circuit stores a plurality of second data, the method comprising: Reading the second data from the second storage circuit into a first sequence, wherein the second data has a plurality of bits, and the logic values of the bits are predefined by a user or randomly distributed; Reading the first data from the first storage circuit into a second sequence, wherein the first data has a plurality of bits, and the logic values of the bits are randomly distributed; transmitting the first sequence and the second sequence to a processing circuit simultaneously; Selecting, by the processing circuit, a first portion of the second sequence as a target sequence according to the addresses of the bits of the first sequence having a logic value of “1”; and The target sequence is output as an identification code.

17. The identification code generation method according to claim 16, wherein: The second sequence further includes a second part, and the identification code generation method further includes: Error bits in the second portion of the second sequence are discarded.

18. The identification code generation method according to claim 16, further comprising: pre-defining the logic values of the bits of the second data so that the bits of the logic value "1" of the first sequence are pre-defined; as well as The first part of the second sequence is selected according to the address of the bit with the logic value "1" of the first sequence.

19. The identification code generation method according to claim 16, further comprising: reprogramming logic values of the bits of the second data; Reading the second data from the second storage circuit into a reprogrammed first sequence; reselecting, by the processing circuit, a first portion of the second sequence according to the first sequence; as well as The reselected first portion of the second sequence becomes the target sequence.

20. The identification code generation method according to claim 16, wherein: The logical values of the bits of the second data are randomly distributed, and the identification code generation method further includes: The first part of the second sequence is selected by the processing circuit according to the addresses of the bits of the logic value “1” of the first sequence, wherein the bits of the logic value “1” of the first sequence are randomly distributed.

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